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Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
4ac13294 | 20 | #include <linux/module.h> |
241771ef IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/sched.h> | |
d7d59fb3 | 23 | #include <linux/uaccess.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
30dd568c | 25 | #include <linux/cpu.h> |
272d30be | 26 | #include <linux/bitops.h> |
0c9d42ed | 27 | #include <linux/device.h> |
241771ef | 28 | |
241771ef | 29 | #include <asm/apic.h> |
d7d59fb3 | 30 | #include <asm/stacktrace.h> |
4e935e47 | 31 | #include <asm/nmi.h> |
257ef9d2 | 32 | #include <asm/compat.h> |
69092624 | 33 | #include <asm/smp.h> |
c8e5910e | 34 | #include <asm/alternative.h> |
e3f3541c | 35 | #include <asm/timer.h> |
241771ef | 36 | |
de0428a7 KW |
37 | #include "perf_event.h" |
38 | ||
7645a24c PZ |
39 | #if 0 |
40 | #undef wrmsrl | |
41 | #define wrmsrl(msr, val) \ | |
42 | do { \ | |
43 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | |
44 | (unsigned long)(val)); \ | |
45 | native_write_msr((msr), (u32)((u64)(val)), \ | |
46 | (u32)((u64)(val) >> 32)); \ | |
47 | } while (0) | |
48 | #endif | |
49 | ||
de0428a7 | 50 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 51 | |
de0428a7 | 52 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
53 | .enabled = 1, |
54 | }; | |
241771ef | 55 | |
de0428a7 | 56 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
57 | [PERF_COUNT_HW_CACHE_MAX] |
58 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
59 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 60 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
61 | [PERF_COUNT_HW_CACHE_MAX] |
62 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
63 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 64 | |
ee06094f | 65 | /* |
cdd6c482 IM |
66 | * Propagate event elapsed time into the generic event. |
67 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
68 | * Returns the delta events processed. |
69 | */ | |
de0428a7 | 70 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 71 | { |
cc2ad4ba | 72 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 73 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 74 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 75 | int idx = hwc->idx; |
ec3232bd | 76 | s64 delta; |
ee06094f | 77 | |
30dd568c MM |
78 | if (idx == X86_PMC_IDX_FIXED_BTS) |
79 | return 0; | |
80 | ||
ee06094f | 81 | /* |
cdd6c482 | 82 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
83 | * |
84 | * Our tactic to handle this is to first atomically read and | |
85 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 86 | * count to the generic event atomically: |
ee06094f IM |
87 | */ |
88 | again: | |
e7850595 | 89 | prev_raw_count = local64_read(&hwc->prev_count); |
73d6e522 | 90 | rdmsrl(hwc->event_base, new_raw_count); |
ee06094f | 91 | |
e7850595 | 92 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
93 | new_raw_count) != prev_raw_count) |
94 | goto again; | |
95 | ||
96 | /* | |
97 | * Now we have the new raw value and have updated the prev | |
98 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 99 | * (event-)time and add that to the generic event. |
ee06094f IM |
100 | * |
101 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 102 | * of the count. |
ee06094f | 103 | */ |
ec3232bd PZ |
104 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
105 | delta >>= shift; | |
ee06094f | 106 | |
e7850595 PZ |
107 | local64_add(delta, &event->count); |
108 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
109 | |
110 | return new_raw_count; | |
ee06094f IM |
111 | } |
112 | ||
a7e3ed1e AK |
113 | /* |
114 | * Find and validate any extra registers to set up. | |
115 | */ | |
116 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
117 | { | |
efc9f05d | 118 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
119 | struct extra_reg *er; |
120 | ||
efc9f05d | 121 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
122 | |
123 | if (!x86_pmu.extra_regs) | |
124 | return 0; | |
125 | ||
126 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
127 | if (er->event != (config & er->config_mask)) | |
128 | continue; | |
129 | if (event->attr.config1 & ~er->valid_mask) | |
130 | return -EINVAL; | |
efc9f05d SE |
131 | |
132 | reg->idx = er->idx; | |
133 | reg->config = event->attr.config1; | |
134 | reg->reg = er->msr; | |
a7e3ed1e AK |
135 | break; |
136 | } | |
137 | return 0; | |
138 | } | |
139 | ||
cdd6c482 | 140 | static atomic_t active_events; |
4e935e47 PZ |
141 | static DEFINE_MUTEX(pmc_reserve_mutex); |
142 | ||
b27ea29c RR |
143 | #ifdef CONFIG_X86_LOCAL_APIC |
144 | ||
4e935e47 PZ |
145 | static bool reserve_pmc_hardware(void) |
146 | { | |
147 | int i; | |
148 | ||
948b1bb8 | 149 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 150 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
151 | goto perfctr_fail; |
152 | } | |
153 | ||
948b1bb8 | 154 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 155 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
156 | goto eventsel_fail; |
157 | } | |
158 | ||
159 | return true; | |
160 | ||
161 | eventsel_fail: | |
162 | for (i--; i >= 0; i--) | |
41bf4989 | 163 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 164 | |
948b1bb8 | 165 | i = x86_pmu.num_counters; |
4e935e47 PZ |
166 | |
167 | perfctr_fail: | |
168 | for (i--; i >= 0; i--) | |
41bf4989 | 169 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 170 | |
4e935e47 PZ |
171 | return false; |
172 | } | |
173 | ||
174 | static void release_pmc_hardware(void) | |
175 | { | |
176 | int i; | |
177 | ||
948b1bb8 | 178 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
179 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
180 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 181 | } |
4e935e47 PZ |
182 | } |
183 | ||
b27ea29c RR |
184 | #else |
185 | ||
186 | static bool reserve_pmc_hardware(void) { return true; } | |
187 | static void release_pmc_hardware(void) {} | |
188 | ||
189 | #endif | |
190 | ||
33c6d6a7 DZ |
191 | static bool check_hw_exists(void) |
192 | { | |
193 | u64 val, val_new = 0; | |
4407204c | 194 | int i, reg, ret = 0; |
33c6d6a7 | 195 | |
4407204c PZ |
196 | /* |
197 | * Check to see if the BIOS enabled any of the counters, if so | |
198 | * complain and bail. | |
199 | */ | |
200 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 201 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
202 | ret = rdmsrl_safe(reg, &val); |
203 | if (ret) | |
204 | goto msr_fail; | |
205 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) | |
206 | goto bios_fail; | |
207 | } | |
208 | ||
209 | if (x86_pmu.num_counters_fixed) { | |
210 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
211 | ret = rdmsrl_safe(reg, &val); | |
212 | if (ret) | |
213 | goto msr_fail; | |
214 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
215 | if (val & (0x03 << i*4)) | |
216 | goto bios_fail; | |
217 | } | |
218 | } | |
219 | ||
220 | /* | |
221 | * Now write a value and read it back to see if it matches, | |
222 | * this is needed to detect certain hardware emulators (qemu/kvm) | |
223 | * that don't trap on the MSR access and always return 0s. | |
224 | */ | |
33c6d6a7 | 225 | val = 0xabcdUL; |
41bf4989 RR |
226 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); |
227 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | |
33c6d6a7 | 228 | if (ret || val != val_new) |
4407204c | 229 | goto msr_fail; |
33c6d6a7 DZ |
230 | |
231 | return true; | |
4407204c PZ |
232 | |
233 | bios_fail: | |
45daae57 IM |
234 | /* |
235 | * We still allow the PMU driver to operate: | |
236 | */ | |
237 | printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n"); | |
4407204c | 238 | printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val); |
45daae57 IM |
239 | |
240 | return true; | |
4407204c PZ |
241 | |
242 | msr_fail: | |
243 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | |
45daae57 | 244 | |
4407204c | 245 | return false; |
33c6d6a7 DZ |
246 | } |
247 | ||
cdd6c482 | 248 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 249 | { |
cdd6c482 | 250 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) { |
4e935e47 | 251 | release_pmc_hardware(); |
ca037701 | 252 | release_ds_buffers(); |
4e935e47 PZ |
253 | mutex_unlock(&pmc_reserve_mutex); |
254 | } | |
255 | } | |
256 | ||
85cf9dba RR |
257 | static inline int x86_pmu_initialized(void) |
258 | { | |
259 | return x86_pmu.handle_irq != NULL; | |
260 | } | |
261 | ||
8326f44d | 262 | static inline int |
e994d7d2 | 263 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 264 | { |
e994d7d2 | 265 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
266 | unsigned int cache_type, cache_op, cache_result; |
267 | u64 config, val; | |
268 | ||
269 | config = attr->config; | |
270 | ||
271 | cache_type = (config >> 0) & 0xff; | |
272 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
273 | return -EINVAL; | |
274 | ||
275 | cache_op = (config >> 8) & 0xff; | |
276 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
277 | return -EINVAL; | |
278 | ||
279 | cache_result = (config >> 16) & 0xff; | |
280 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
281 | return -EINVAL; | |
282 | ||
283 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
284 | ||
285 | if (val == 0) | |
286 | return -ENOENT; | |
287 | ||
288 | if (val == -1) | |
289 | return -EINVAL; | |
290 | ||
291 | hwc->config |= val; | |
e994d7d2 AK |
292 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
293 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
294 | } |
295 | ||
de0428a7 | 296 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
297 | { |
298 | struct perf_event_attr *attr = &event->attr; | |
299 | struct hw_perf_event *hwc = &event->hw; | |
300 | u64 config; | |
301 | ||
6c7e550f | 302 | if (!is_sampling_event(event)) { |
c1726f34 RR |
303 | hwc->sample_period = x86_pmu.max_period; |
304 | hwc->last_period = hwc->sample_period; | |
e7850595 | 305 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
306 | } else { |
307 | /* | |
308 | * If we have a PMU initialized but no APIC | |
309 | * interrupts, we cannot sample hardware | |
310 | * events (user-space has to fall back and | |
311 | * sample via a hrtimer based software event): | |
312 | */ | |
313 | if (!x86_pmu.apic) | |
314 | return -EOPNOTSUPP; | |
315 | } | |
316 | ||
317 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 318 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
319 | |
320 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 321 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
322 | |
323 | if (attr->config >= x86_pmu.max_events) | |
324 | return -EINVAL; | |
325 | ||
326 | /* | |
327 | * The generic map: | |
328 | */ | |
329 | config = x86_pmu.event_map(attr->config); | |
330 | ||
331 | if (config == 0) | |
332 | return -ENOENT; | |
333 | ||
334 | if (config == -1LL) | |
335 | return -EINVAL; | |
336 | ||
337 | /* | |
338 | * Branch tracing: | |
339 | */ | |
18a073a3 PZ |
340 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
341 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 342 | /* BTS is not supported by this architecture. */ |
6809b6ea | 343 | if (!x86_pmu.bts_active) |
c1726f34 RR |
344 | return -EOPNOTSUPP; |
345 | ||
346 | /* BTS is currently only allowed for user-mode. */ | |
347 | if (!attr->exclude_kernel) | |
348 | return -EOPNOTSUPP; | |
349 | } | |
350 | ||
351 | hwc->config |= config; | |
352 | ||
353 | return 0; | |
354 | } | |
4261e0e0 | 355 | |
de0428a7 | 356 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 357 | { |
ab608344 PZ |
358 | if (event->attr.precise_ip) { |
359 | int precise = 0; | |
360 | ||
361 | /* Support for constant skid */ | |
6809b6ea | 362 | if (x86_pmu.pebs_active) { |
ab608344 PZ |
363 | precise++; |
364 | ||
5553be26 PZ |
365 | /* Support for IP fixup */ |
366 | if (x86_pmu.lbr_nr) | |
367 | precise++; | |
368 | } | |
ab608344 PZ |
369 | |
370 | if (event->attr.precise_ip > precise) | |
371 | return -EOPNOTSUPP; | |
372 | } | |
373 | ||
a072738e CG |
374 | /* |
375 | * Generate PMC IRQs: | |
376 | * (keep 'enabled' bit clear for now) | |
377 | */ | |
b4cdc5c2 | 378 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
379 | |
380 | /* | |
381 | * Count user and OS events unless requested not to | |
382 | */ | |
b4cdc5c2 PZ |
383 | if (!event->attr.exclude_user) |
384 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
385 | if (!event->attr.exclude_kernel) | |
386 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 387 | |
b4cdc5c2 PZ |
388 | if (event->attr.type == PERF_TYPE_RAW) |
389 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 390 | |
9d0fcba6 | 391 | return x86_setup_perfctr(event); |
a098f448 RR |
392 | } |
393 | ||
241771ef | 394 | /* |
0d48696f | 395 | * Setup the hardware configuration for a given attr_type |
241771ef | 396 | */ |
b0a873eb | 397 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 398 | { |
4e935e47 | 399 | int err; |
241771ef | 400 | |
85cf9dba RR |
401 | if (!x86_pmu_initialized()) |
402 | return -ENODEV; | |
241771ef | 403 | |
4e935e47 | 404 | err = 0; |
cdd6c482 | 405 | if (!atomic_inc_not_zero(&active_events)) { |
4e935e47 | 406 | mutex_lock(&pmc_reserve_mutex); |
cdd6c482 | 407 | if (atomic_read(&active_events) == 0) { |
30dd568c MM |
408 | if (!reserve_pmc_hardware()) |
409 | err = -EBUSY; | |
f80c9e30 PZ |
410 | else |
411 | reserve_ds_buffers(); | |
30dd568c MM |
412 | } |
413 | if (!err) | |
cdd6c482 | 414 | atomic_inc(&active_events); |
4e935e47 PZ |
415 | mutex_unlock(&pmc_reserve_mutex); |
416 | } | |
417 | if (err) | |
418 | return err; | |
419 | ||
cdd6c482 | 420 | event->destroy = hw_perf_event_destroy; |
a1792cda | 421 | |
4261e0e0 RR |
422 | event->hw.idx = -1; |
423 | event->hw.last_cpu = -1; | |
424 | event->hw.last_tag = ~0ULL; | |
b690081d | 425 | |
efc9f05d SE |
426 | /* mark unused */ |
427 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
428 | ||
9d0fcba6 | 429 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
430 | } |
431 | ||
de0428a7 | 432 | void x86_pmu_disable_all(void) |
f87ad35d | 433 | { |
cdd6c482 | 434 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
9e35ad38 PZ |
435 | int idx; |
436 | ||
948b1bb8 | 437 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
438 | u64 val; |
439 | ||
43f6201a | 440 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 441 | continue; |
41bf4989 | 442 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 443 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 444 | continue; |
bb1165d6 | 445 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 446 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 447 | } |
f87ad35d JSR |
448 | } |
449 | ||
a4eaf7f1 | 450 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 451 | { |
1da53e02 SE |
452 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
453 | ||
85cf9dba | 454 | if (!x86_pmu_initialized()) |
9e35ad38 | 455 | return; |
1da53e02 | 456 | |
1a6e21f7 PZ |
457 | if (!cpuc->enabled) |
458 | return; | |
459 | ||
460 | cpuc->n_added = 0; | |
461 | cpuc->enabled = 0; | |
462 | barrier(); | |
1da53e02 SE |
463 | |
464 | x86_pmu.disable_all(); | |
b56a3802 | 465 | } |
241771ef | 466 | |
de0428a7 | 467 | void x86_pmu_enable_all(int added) |
f87ad35d | 468 | { |
cdd6c482 | 469 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
f87ad35d JSR |
470 | int idx; |
471 | ||
948b1bb8 | 472 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 473 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 474 | |
43f6201a | 475 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 476 | continue; |
984b838c | 477 | |
d45dd923 | 478 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
479 | } |
480 | } | |
481 | ||
51b0fe39 | 482 | static struct pmu pmu; |
1da53e02 SE |
483 | |
484 | static inline int is_x86_event(struct perf_event *event) | |
485 | { | |
486 | return event->pmu == &pmu; | |
487 | } | |
488 | ||
1e2ad28f RR |
489 | /* |
490 | * Event scheduler state: | |
491 | * | |
492 | * Assign events iterating over all events and counters, beginning | |
493 | * with events with least weights first. Keep the current iterator | |
494 | * state in struct sched_state. | |
495 | */ | |
496 | struct sched_state { | |
497 | int weight; | |
498 | int event; /* event index */ | |
499 | int counter; /* counter index */ | |
500 | int unassigned; /* number of events to be assigned left */ | |
501 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; | |
502 | }; | |
503 | ||
bc1738f6 RR |
504 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
505 | #define SCHED_STATES_MAX 2 | |
506 | ||
1e2ad28f RR |
507 | struct perf_sched { |
508 | int max_weight; | |
509 | int max_events; | |
510 | struct event_constraint **constraints; | |
511 | struct sched_state state; | |
bc1738f6 RR |
512 | int saved_states; |
513 | struct sched_state saved[SCHED_STATES_MAX]; | |
1e2ad28f RR |
514 | }; |
515 | ||
516 | /* | |
517 | * Initialize interator that runs through all events and counters. | |
518 | */ | |
519 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c, | |
520 | int num, int wmin, int wmax) | |
521 | { | |
522 | int idx; | |
523 | ||
524 | memset(sched, 0, sizeof(*sched)); | |
525 | sched->max_events = num; | |
526 | sched->max_weight = wmax; | |
527 | sched->constraints = c; | |
528 | ||
529 | for (idx = 0; idx < num; idx++) { | |
530 | if (c[idx]->weight == wmin) | |
531 | break; | |
532 | } | |
533 | ||
534 | sched->state.event = idx; /* start with min weight */ | |
535 | sched->state.weight = wmin; | |
536 | sched->state.unassigned = num; | |
537 | } | |
538 | ||
bc1738f6 RR |
539 | static void perf_sched_save_state(struct perf_sched *sched) |
540 | { | |
541 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
542 | return; | |
543 | ||
544 | sched->saved[sched->saved_states] = sched->state; | |
545 | sched->saved_states++; | |
546 | } | |
547 | ||
548 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
549 | { | |
550 | if (!sched->saved_states) | |
551 | return false; | |
552 | ||
553 | sched->saved_states--; | |
554 | sched->state = sched->saved[sched->saved_states]; | |
555 | ||
556 | /* continue with next counter: */ | |
557 | clear_bit(sched->state.counter++, sched->state.used); | |
558 | ||
559 | return true; | |
560 | } | |
561 | ||
1e2ad28f RR |
562 | /* |
563 | * Select a counter for the current event to schedule. Return true on | |
564 | * success. | |
565 | */ | |
bc1738f6 | 566 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
567 | { |
568 | struct event_constraint *c; | |
569 | int idx; | |
570 | ||
571 | if (!sched->state.unassigned) | |
572 | return false; | |
573 | ||
574 | if (sched->state.event >= sched->max_events) | |
575 | return false; | |
576 | ||
577 | c = sched->constraints[sched->state.event]; | |
578 | ||
4defea85 PZ |
579 | /* Prefer fixed purpose counters */ |
580 | if (x86_pmu.num_counters_fixed) { | |
581 | idx = X86_PMC_IDX_FIXED; | |
582 | for_each_set_bit_cont(idx, c->idxmsk, X86_PMC_IDX_MAX) { | |
583 | if (!__test_and_set_bit(idx, sched->state.used)) | |
584 | goto done; | |
585 | } | |
586 | } | |
1e2ad28f RR |
587 | /* Grab the first unused counter starting with idx */ |
588 | idx = sched->state.counter; | |
4defea85 | 589 | for_each_set_bit_cont(idx, c->idxmsk, X86_PMC_IDX_FIXED) { |
1e2ad28f | 590 | if (!__test_and_set_bit(idx, sched->state.used)) |
4defea85 | 591 | goto done; |
1e2ad28f | 592 | } |
1e2ad28f | 593 | |
4defea85 PZ |
594 | return false; |
595 | ||
596 | done: | |
597 | sched->state.counter = idx; | |
1e2ad28f | 598 | |
bc1738f6 RR |
599 | if (c->overlap) |
600 | perf_sched_save_state(sched); | |
601 | ||
602 | return true; | |
603 | } | |
604 | ||
605 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
606 | { | |
607 | while (!__perf_sched_find_counter(sched)) { | |
608 | if (!perf_sched_restore_state(sched)) | |
609 | return false; | |
610 | } | |
611 | ||
1e2ad28f RR |
612 | return true; |
613 | } | |
614 | ||
615 | /* | |
616 | * Go through all unassigned events and find the next one to schedule. | |
617 | * Take events with the least weight first. Return true on success. | |
618 | */ | |
619 | static bool perf_sched_next_event(struct perf_sched *sched) | |
620 | { | |
621 | struct event_constraint *c; | |
622 | ||
623 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
624 | return false; | |
625 | ||
626 | do { | |
627 | /* next event */ | |
628 | sched->state.event++; | |
629 | if (sched->state.event >= sched->max_events) { | |
630 | /* next weight */ | |
631 | sched->state.event = 0; | |
632 | sched->state.weight++; | |
633 | if (sched->state.weight > sched->max_weight) | |
634 | return false; | |
635 | } | |
636 | c = sched->constraints[sched->state.event]; | |
637 | } while (c->weight != sched->state.weight); | |
638 | ||
639 | sched->state.counter = 0; /* start with first counter */ | |
640 | ||
641 | return true; | |
642 | } | |
643 | ||
644 | /* | |
645 | * Assign a counter for each event. | |
646 | */ | |
647 | static int perf_assign_events(struct event_constraint **constraints, int n, | |
648 | int wmin, int wmax, int *assign) | |
649 | { | |
650 | struct perf_sched sched; | |
651 | ||
652 | perf_sched_init(&sched, constraints, n, wmin, wmax); | |
653 | ||
654 | do { | |
655 | if (!perf_sched_find_counter(&sched)) | |
656 | break; /* failed */ | |
657 | if (assign) | |
658 | assign[sched.state.event] = sched.state.counter; | |
659 | } while (perf_sched_next_event(&sched)); | |
660 | ||
661 | return sched.state.unassigned; | |
662 | } | |
663 | ||
de0428a7 | 664 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 665 | { |
63b14649 | 666 | struct event_constraint *c, *constraints[X86_PMC_IDX_MAX]; |
1da53e02 | 667 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
1e2ad28f | 668 | int i, wmin, wmax, num = 0; |
1da53e02 SE |
669 | struct hw_perf_event *hwc; |
670 | ||
671 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
672 | ||
1e2ad28f | 673 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b622d644 PZ |
674 | c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]); |
675 | constraints[i] = c; | |
1e2ad28f RR |
676 | wmin = min(wmin, c->weight); |
677 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
678 | } |
679 | ||
8113070d SE |
680 | /* |
681 | * fastpath, try to reuse previous register | |
682 | */ | |
c933c1a6 | 683 | for (i = 0; i < n; i++) { |
8113070d | 684 | hwc = &cpuc->event_list[i]->hw; |
81269a08 | 685 | c = constraints[i]; |
8113070d SE |
686 | |
687 | /* never assigned */ | |
688 | if (hwc->idx == -1) | |
689 | break; | |
690 | ||
691 | /* constraint still honored */ | |
63b14649 | 692 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
693 | break; |
694 | ||
695 | /* not already used */ | |
696 | if (test_bit(hwc->idx, used_mask)) | |
697 | break; | |
698 | ||
34538ee7 | 699 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
700 | if (assign) |
701 | assign[i] = hwc->idx; | |
702 | } | |
8113070d | 703 | |
1e2ad28f RR |
704 | /* slow path */ |
705 | if (i != n) | |
706 | num = perf_assign_events(constraints, n, wmin, wmax, assign); | |
8113070d | 707 | |
1da53e02 SE |
708 | /* |
709 | * scheduling failed or is just a simulation, | |
710 | * free resources if necessary | |
711 | */ | |
712 | if (!assign || num) { | |
713 | for (i = 0; i < n; i++) { | |
714 | if (x86_pmu.put_event_constraints) | |
715 | x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]); | |
716 | } | |
717 | } | |
aa2bc1ad | 718 | return num ? -EINVAL : 0; |
1da53e02 SE |
719 | } |
720 | ||
721 | /* | |
722 | * dogrp: true if must collect siblings events (group) | |
723 | * returns total number of events and error code | |
724 | */ | |
725 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
726 | { | |
727 | struct perf_event *event; | |
728 | int n, max_count; | |
729 | ||
948b1bb8 | 730 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
731 | |
732 | /* current number of events already accepted */ | |
733 | n = cpuc->n_events; | |
734 | ||
735 | if (is_x86_event(leader)) { | |
736 | if (n >= max_count) | |
aa2bc1ad | 737 | return -EINVAL; |
1da53e02 SE |
738 | cpuc->event_list[n] = leader; |
739 | n++; | |
740 | } | |
741 | if (!dogrp) | |
742 | return n; | |
743 | ||
744 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
745 | if (!is_x86_event(event) || | |
8113070d | 746 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
747 | continue; |
748 | ||
749 | if (n >= max_count) | |
aa2bc1ad | 750 | return -EINVAL; |
1da53e02 SE |
751 | |
752 | cpuc->event_list[n] = event; | |
753 | n++; | |
754 | } | |
755 | return n; | |
756 | } | |
757 | ||
1da53e02 | 758 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 759 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 760 | { |
447a194b SE |
761 | struct hw_perf_event *hwc = &event->hw; |
762 | ||
763 | hwc->idx = cpuc->assign[i]; | |
764 | hwc->last_cpu = smp_processor_id(); | |
765 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 SE |
766 | |
767 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | |
768 | hwc->config_base = 0; | |
769 | hwc->event_base = 0; | |
770 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | |
771 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
fc66c521 | 772 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED); |
1da53e02 | 773 | } else { |
73d6e522 RR |
774 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
775 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
1da53e02 SE |
776 | } |
777 | } | |
778 | ||
447a194b SE |
779 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
780 | struct cpu_hw_events *cpuc, | |
781 | int i) | |
782 | { | |
783 | return hwc->idx == cpuc->assign[i] && | |
784 | hwc->last_cpu == smp_processor_id() && | |
785 | hwc->last_tag == cpuc->tags[i]; | |
786 | } | |
787 | ||
a4eaf7f1 | 788 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 789 | |
a4eaf7f1 | 790 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 791 | { |
1da53e02 SE |
792 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
793 | struct perf_event *event; | |
794 | struct hw_perf_event *hwc; | |
11164cd4 | 795 | int i, added = cpuc->n_added; |
1da53e02 | 796 | |
85cf9dba | 797 | if (!x86_pmu_initialized()) |
2b9ff0db | 798 | return; |
1a6e21f7 PZ |
799 | |
800 | if (cpuc->enabled) | |
801 | return; | |
802 | ||
1da53e02 | 803 | if (cpuc->n_added) { |
19925ce7 | 804 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
805 | /* |
806 | * apply assignment obtained either from | |
807 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
808 | * | |
809 | * step1: save events moving to new counters | |
810 | * step2: reprogram moved events into new counters | |
811 | */ | |
19925ce7 | 812 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
813 | event = cpuc->event_list[i]; |
814 | hwc = &event->hw; | |
815 | ||
447a194b SE |
816 | /* |
817 | * we can avoid reprogramming counter if: | |
818 | * - assigned same counter as last time | |
819 | * - running on same CPU as last time | |
820 | * - no other event has used the counter since | |
821 | */ | |
822 | if (hwc->idx == -1 || | |
823 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
824 | continue; |
825 | ||
a4eaf7f1 PZ |
826 | /* |
827 | * Ensure we don't accidentally enable a stopped | |
828 | * counter simply because we rescheduled. | |
829 | */ | |
830 | if (hwc->state & PERF_HES_STOPPED) | |
831 | hwc->state |= PERF_HES_ARCH; | |
832 | ||
833 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
834 | } |
835 | ||
836 | for (i = 0; i < cpuc->n_events; i++) { | |
1da53e02 SE |
837 | event = cpuc->event_list[i]; |
838 | hwc = &event->hw; | |
839 | ||
45e16a68 | 840 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 841 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
842 | else if (i < n_running) |
843 | continue; | |
1da53e02 | 844 | |
a4eaf7f1 PZ |
845 | if (hwc->state & PERF_HES_ARCH) |
846 | continue; | |
847 | ||
848 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
849 | } |
850 | cpuc->n_added = 0; | |
851 | perf_events_lapic_init(); | |
852 | } | |
1a6e21f7 PZ |
853 | |
854 | cpuc->enabled = 1; | |
855 | barrier(); | |
856 | ||
11164cd4 | 857 | x86_pmu.enable_all(added); |
ee06094f | 858 | } |
ee06094f | 859 | |
245b2e70 | 860 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 861 | |
ee06094f IM |
862 | /* |
863 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 864 | * To be called with the event disabled in hw: |
ee06094f | 865 | */ |
de0428a7 | 866 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 867 | { |
07088edb | 868 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 869 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 870 | s64 period = hwc->sample_period; |
7645a24c | 871 | int ret = 0, idx = hwc->idx; |
ee06094f | 872 | |
30dd568c MM |
873 | if (idx == X86_PMC_IDX_FIXED_BTS) |
874 | return 0; | |
875 | ||
ee06094f | 876 | /* |
af901ca1 | 877 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
878 | */ |
879 | if (unlikely(left <= -period)) { | |
880 | left = period; | |
e7850595 | 881 | local64_set(&hwc->period_left, left); |
9e350de3 | 882 | hwc->last_period = period; |
e4abb5d4 | 883 | ret = 1; |
ee06094f IM |
884 | } |
885 | ||
886 | if (unlikely(left <= 0)) { | |
887 | left += period; | |
e7850595 | 888 | local64_set(&hwc->period_left, left); |
9e350de3 | 889 | hwc->last_period = period; |
e4abb5d4 | 890 | ret = 1; |
ee06094f | 891 | } |
1c80f4b5 | 892 | /* |
dfc65094 | 893 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
894 | */ |
895 | if (unlikely(left < 2)) | |
896 | left = 2; | |
241771ef | 897 | |
e4abb5d4 PZ |
898 | if (left > x86_pmu.max_period) |
899 | left = x86_pmu.max_period; | |
900 | ||
245b2e70 | 901 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f IM |
902 | |
903 | /* | |
cdd6c482 | 904 | * The hw event starts counting from this event offset, |
ee06094f IM |
905 | * mark it to be able to extra future deltas: |
906 | */ | |
e7850595 | 907 | local64_set(&hwc->prev_count, (u64)-left); |
ee06094f | 908 | |
73d6e522 | 909 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac CG |
910 | |
911 | /* | |
912 | * Due to erratum on certan cpu we need | |
913 | * a second write to be sure the register | |
914 | * is updated properly | |
915 | */ | |
916 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 917 | wrmsrl(hwc->event_base, |
948b1bb8 | 918 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 919 | } |
e4abb5d4 | 920 | |
cdd6c482 | 921 | perf_event_update_userpage(event); |
194002b2 | 922 | |
e4abb5d4 | 923 | return ret; |
2f18d1e8 IM |
924 | } |
925 | ||
de0428a7 | 926 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 927 | { |
0a3aee0d | 928 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
929 | __x86_pmu_enable_event(&event->hw, |
930 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
931 | } |
932 | ||
b690081d | 933 | /* |
a4eaf7f1 | 934 | * Add a single event to the PMU. |
1da53e02 SE |
935 | * |
936 | * The event is added to the group of enabled events | |
937 | * but only if it can be scehduled with existing events. | |
fe9081cc | 938 | */ |
a4eaf7f1 | 939 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc PZ |
940 | { |
941 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1da53e02 SE |
942 | struct hw_perf_event *hwc; |
943 | int assign[X86_PMC_IDX_MAX]; | |
944 | int n, n0, ret; | |
fe9081cc | 945 | |
1da53e02 | 946 | hwc = &event->hw; |
fe9081cc | 947 | |
33696fc0 | 948 | perf_pmu_disable(event->pmu); |
1da53e02 | 949 | n0 = cpuc->n_events; |
24cd7f54 PZ |
950 | ret = n = collect_events(cpuc, event, false); |
951 | if (ret < 0) | |
952 | goto out; | |
53b441a5 | 953 | |
a4eaf7f1 PZ |
954 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
955 | if (!(flags & PERF_EF_START)) | |
956 | hwc->state |= PERF_HES_ARCH; | |
957 | ||
4d1c52b0 LM |
958 | /* |
959 | * If group events scheduling transaction was started, | |
0d2eb44f | 960 | * skip the schedulability test here, it will be performed |
a4eaf7f1 | 961 | * at commit time (->commit_txn) as a whole |
4d1c52b0 | 962 | */ |
8d2cacbb | 963 | if (cpuc->group_flag & PERF_EVENT_TXN) |
24cd7f54 | 964 | goto done_collect; |
4d1c52b0 | 965 | |
a072738e | 966 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 967 | if (ret) |
24cd7f54 | 968 | goto out; |
1da53e02 SE |
969 | /* |
970 | * copy new assignment, now we know it is possible | |
971 | * will be used by hw_perf_enable() | |
972 | */ | |
973 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 974 | |
24cd7f54 | 975 | done_collect: |
1da53e02 | 976 | cpuc->n_events = n; |
356e1f2e | 977 | cpuc->n_added += n - n0; |
90151c35 | 978 | cpuc->n_txn += n - n0; |
95cdd2e7 | 979 | |
24cd7f54 PZ |
980 | ret = 0; |
981 | out: | |
33696fc0 | 982 | perf_pmu_enable(event->pmu); |
24cd7f54 | 983 | return ret; |
241771ef IM |
984 | } |
985 | ||
a4eaf7f1 | 986 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 987 | { |
c08053e6 PZ |
988 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
989 | int idx = event->hw.idx; | |
990 | ||
a4eaf7f1 PZ |
991 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
992 | return; | |
993 | ||
994 | if (WARN_ON_ONCE(idx == -1)) | |
995 | return; | |
996 | ||
997 | if (flags & PERF_EF_RELOAD) { | |
998 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
999 | x86_perf_event_set_period(event); | |
1000 | } | |
1001 | ||
1002 | event->hw.state = 0; | |
d76a0812 | 1003 | |
c08053e6 PZ |
1004 | cpuc->events[idx] = event; |
1005 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1006 | __set_bit(idx, cpuc->running); |
aff3d91a | 1007 | x86_pmu.enable(event); |
c08053e6 | 1008 | perf_event_update_userpage(event); |
a78ac325 PZ |
1009 | } |
1010 | ||
cdd6c482 | 1011 | void perf_event_print_debug(void) |
241771ef | 1012 | { |
2f18d1e8 | 1013 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
ca037701 | 1014 | u64 pebs; |
cdd6c482 | 1015 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1016 | unsigned long flags; |
1e125676 IM |
1017 | int cpu, idx; |
1018 | ||
948b1bb8 | 1019 | if (!x86_pmu.num_counters) |
1e125676 | 1020 | return; |
241771ef | 1021 | |
5bb9efe3 | 1022 | local_irq_save(flags); |
241771ef IM |
1023 | |
1024 | cpu = smp_processor_id(); | |
cdd6c482 | 1025 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1026 | |
faa28ae0 | 1027 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1028 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1029 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1030 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1031 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
ca037701 | 1032 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
a1ef58f4 JSR |
1033 | |
1034 | pr_info("\n"); | |
1035 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1036 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1037 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1038 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
ca037701 | 1039 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); |
f87ad35d | 1040 | } |
7645a24c | 1041 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1042 | |
948b1bb8 | 1043 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1044 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1045 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1046 | |
245b2e70 | 1047 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1048 | |
a1ef58f4 | 1049 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1050 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1051 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1052 | cpu, idx, pmc_count); |
a1ef58f4 | 1053 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1054 | cpu, idx, prev_left); |
241771ef | 1055 | } |
948b1bb8 | 1056 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1057 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1058 | ||
a1ef58f4 | 1059 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1060 | cpu, idx, pmc_count); |
1061 | } | |
5bb9efe3 | 1062 | local_irq_restore(flags); |
241771ef IM |
1063 | } |
1064 | ||
de0428a7 | 1065 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1066 | { |
d76a0812 | 1067 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
cdd6c482 | 1068 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1069 | |
a4eaf7f1 PZ |
1070 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1071 | x86_pmu.disable(event); | |
1072 | cpuc->events[hwc->idx] = NULL; | |
1073 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1074 | hwc->state |= PERF_HES_STOPPED; | |
1075 | } | |
30dd568c | 1076 | |
a4eaf7f1 PZ |
1077 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1078 | /* | |
1079 | * Drain the remaining delta count out of a event | |
1080 | * that we are disabling: | |
1081 | */ | |
1082 | x86_perf_event_update(event); | |
1083 | hwc->state |= PERF_HES_UPTODATE; | |
1084 | } | |
2e841873 PZ |
1085 | } |
1086 | ||
a4eaf7f1 | 1087 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 PZ |
1088 | { |
1089 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1090 | int i; | |
1091 | ||
90151c35 SE |
1092 | /* |
1093 | * If we're called during a txn, we don't need to do anything. | |
1094 | * The events never got scheduled and ->cancel_txn will truncate | |
1095 | * the event_list. | |
1096 | */ | |
8d2cacbb | 1097 | if (cpuc->group_flag & PERF_EVENT_TXN) |
90151c35 SE |
1098 | return; |
1099 | ||
a4eaf7f1 | 1100 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1101 | |
1da53e02 SE |
1102 | for (i = 0; i < cpuc->n_events; i++) { |
1103 | if (event == cpuc->event_list[i]) { | |
1104 | ||
1105 | if (x86_pmu.put_event_constraints) | |
1106 | x86_pmu.put_event_constraints(cpuc, event); | |
1107 | ||
1108 | while (++i < cpuc->n_events) | |
1109 | cpuc->event_list[i-1] = cpuc->event_list[i]; | |
1110 | ||
1111 | --cpuc->n_events; | |
6c9687ab | 1112 | break; |
1da53e02 SE |
1113 | } |
1114 | } | |
cdd6c482 | 1115 | perf_event_update_userpage(event); |
241771ef IM |
1116 | } |
1117 | ||
de0428a7 | 1118 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1119 | { |
df1a132b | 1120 | struct perf_sample_data data; |
cdd6c482 IM |
1121 | struct cpu_hw_events *cpuc; |
1122 | struct perf_event *event; | |
11d1578f | 1123 | int idx, handled = 0; |
9029a5e3 IM |
1124 | u64 val; |
1125 | ||
dc1d628a | 1126 | perf_sample_data_init(&data, 0); |
df1a132b | 1127 | |
cdd6c482 | 1128 | cpuc = &__get_cpu_var(cpu_hw_events); |
962bf7a6 | 1129 | |
2bce5dac DZ |
1130 | /* |
1131 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1132 | * inside the nmi handler. As a result, the unmasking was pushed | |
1133 | * into all the nmi handlers. | |
1134 | * | |
1135 | * This generic handler doesn't seem to have any issues where the | |
1136 | * unmasking occurs so it was left at the top. | |
1137 | */ | |
1138 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1139 | ||
948b1bb8 | 1140 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1141 | if (!test_bit(idx, cpuc->active_mask)) { |
1142 | /* | |
1143 | * Though we deactivated the counter some cpus | |
1144 | * might still deliver spurious interrupts still | |
1145 | * in flight. Catch them: | |
1146 | */ | |
1147 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1148 | handled++; | |
a29aa8a7 | 1149 | continue; |
63e6be6d | 1150 | } |
962bf7a6 | 1151 | |
cdd6c482 | 1152 | event = cpuc->events[idx]; |
a4016a79 | 1153 | |
cc2ad4ba | 1154 | val = x86_perf_event_update(event); |
948b1bb8 | 1155 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1156 | continue; |
962bf7a6 | 1157 | |
9e350de3 | 1158 | /* |
cdd6c482 | 1159 | * event overflow |
9e350de3 | 1160 | */ |
4177c42a | 1161 | handled++; |
cdd6c482 | 1162 | data.period = event->hw.last_period; |
9e350de3 | 1163 | |
07088edb | 1164 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1165 | continue; |
1166 | ||
a8b0ca17 | 1167 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1168 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1169 | } |
962bf7a6 | 1170 | |
9e350de3 PZ |
1171 | if (handled) |
1172 | inc_irq_stat(apic_perf_irqs); | |
1173 | ||
a29aa8a7 RR |
1174 | return handled; |
1175 | } | |
39d81eab | 1176 | |
cdd6c482 | 1177 | void perf_events_lapic_init(void) |
241771ef | 1178 | { |
04da8a43 | 1179 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1180 | return; |
85cf9dba | 1181 | |
241771ef | 1182 | /* |
c323d95f | 1183 | * Always use NMI for PMU |
241771ef | 1184 | */ |
c323d95f | 1185 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1186 | } |
1187 | ||
1188 | static int __kprobes | |
9c48f1c6 | 1189 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1190 | { |
cdd6c482 | 1191 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1192 | return NMI_DONE; |
4177c42a | 1193 | |
9c48f1c6 | 1194 | return x86_pmu.handle_irq(regs); |
241771ef IM |
1195 | } |
1196 | ||
de0428a7 KW |
1197 | struct event_constraint emptyconstraint; |
1198 | struct event_constraint unconstrained; | |
f87ad35d | 1199 | |
3f6da390 PZ |
1200 | static int __cpuinit |
1201 | x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) | |
1202 | { | |
1203 | unsigned int cpu = (long)hcpu; | |
7fdba1ca | 1204 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
b38b24ea | 1205 | int ret = NOTIFY_OK; |
3f6da390 PZ |
1206 | |
1207 | switch (action & ~CPU_TASKS_FROZEN) { | |
1208 | case CPU_UP_PREPARE: | |
7fdba1ca | 1209 | cpuc->kfree_on_online = NULL; |
3f6da390 | 1210 | if (x86_pmu.cpu_prepare) |
b38b24ea | 1211 | ret = x86_pmu.cpu_prepare(cpu); |
3f6da390 PZ |
1212 | break; |
1213 | ||
1214 | case CPU_STARTING: | |
0c9d42ed PZ |
1215 | if (x86_pmu.attr_rdpmc) |
1216 | set_in_cr4(X86_CR4_PCE); | |
3f6da390 PZ |
1217 | if (x86_pmu.cpu_starting) |
1218 | x86_pmu.cpu_starting(cpu); | |
1219 | break; | |
1220 | ||
7fdba1ca PZ |
1221 | case CPU_ONLINE: |
1222 | kfree(cpuc->kfree_on_online); | |
1223 | break; | |
1224 | ||
3f6da390 PZ |
1225 | case CPU_DYING: |
1226 | if (x86_pmu.cpu_dying) | |
1227 | x86_pmu.cpu_dying(cpu); | |
1228 | break; | |
1229 | ||
b38b24ea | 1230 | case CPU_UP_CANCELED: |
3f6da390 PZ |
1231 | case CPU_DEAD: |
1232 | if (x86_pmu.cpu_dead) | |
1233 | x86_pmu.cpu_dead(cpu); | |
1234 | break; | |
1235 | ||
1236 | default: | |
1237 | break; | |
1238 | } | |
1239 | ||
b38b24ea | 1240 | return ret; |
3f6da390 PZ |
1241 | } |
1242 | ||
12558038 CG |
1243 | static void __init pmu_check_apic(void) |
1244 | { | |
1245 | if (cpu_has_apic) | |
1246 | return; | |
1247 | ||
1248 | x86_pmu.apic = 0; | |
1249 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1250 | pr_info("no hardware sampling interrupt available.\n"); | |
1251 | } | |
1252 | ||
dda99116 | 1253 | static int __init init_hw_perf_events(void) |
b56a3802 | 1254 | { |
c1d6f42f | 1255 | struct x86_pmu_quirk *quirk; |
b622d644 | 1256 | struct event_constraint *c; |
72eae04d RR |
1257 | int err; |
1258 | ||
cdd6c482 | 1259 | pr_info("Performance Events: "); |
1123e3ad | 1260 | |
b56a3802 JSR |
1261 | switch (boot_cpu_data.x86_vendor) { |
1262 | case X86_VENDOR_INTEL: | |
72eae04d | 1263 | err = intel_pmu_init(); |
b56a3802 | 1264 | break; |
f87ad35d | 1265 | case X86_VENDOR_AMD: |
72eae04d | 1266 | err = amd_pmu_init(); |
f87ad35d | 1267 | break; |
4138960a | 1268 | default: |
004417a6 | 1269 | return 0; |
b56a3802 | 1270 | } |
1123e3ad | 1271 | if (err != 0) { |
cdd6c482 | 1272 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1273 | return 0; |
1123e3ad | 1274 | } |
b56a3802 | 1275 | |
12558038 CG |
1276 | pmu_check_apic(); |
1277 | ||
33c6d6a7 | 1278 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1279 | if (!check_hw_exists()) |
004417a6 | 1280 | return 0; |
33c6d6a7 | 1281 | |
1123e3ad | 1282 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1283 | |
c1d6f42f PZ |
1284 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1285 | quirk->func(); | |
3c44780b | 1286 | |
948b1bb8 | 1287 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
cdd6c482 | 1288 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", |
948b1bb8 RR |
1289 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1290 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | |
241771ef | 1291 | } |
948b1bb8 | 1292 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
241771ef | 1293 | |
948b1bb8 | 1294 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
cdd6c482 | 1295 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", |
948b1bb8 RR |
1296 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1297 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | |
703e937c | 1298 | } |
862a1a5f | 1299 | |
d6dc0b4e | 1300 | x86_pmu.intel_ctrl |= |
948b1bb8 | 1301 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
241771ef | 1302 | |
cdd6c482 | 1303 | perf_events_lapic_init(); |
9c48f1c6 | 1304 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1305 | |
63b14649 | 1306 | unconstrained = (struct event_constraint) |
948b1bb8 | 1307 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
bc1738f6 | 1308 | 0, x86_pmu.num_counters, 0); |
63b14649 | 1309 | |
b622d644 | 1310 | if (x86_pmu.event_constraints) { |
cd09c0c4 SE |
1311 | /* |
1312 | * event on fixed counter2 (REF_CYCLES) only works on this | |
1313 | * counter, so do not extend mask to generic counters | |
1314 | */ | |
b622d644 | 1315 | for_each_event_constraint(c, x86_pmu.event_constraints) { |
cd09c0c4 SE |
1316 | if (c->cmask != X86_RAW_EVENT_MASK |
1317 | || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) { | |
b622d644 | 1318 | continue; |
cd09c0c4 | 1319 | } |
b622d644 | 1320 | |
948b1bb8 RR |
1321 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; |
1322 | c->weight += x86_pmu.num_counters; | |
b622d644 PZ |
1323 | } |
1324 | } | |
1325 | ||
0c9d42ed PZ |
1326 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1327 | ||
57c0c15b | 1328 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1329 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1330 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1331 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1332 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1333 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1334 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1335 | |
2e80a82a | 1336 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
3f6da390 | 1337 | perf_cpu_notifier(x86_pmu_notifier); |
004417a6 PZ |
1338 | |
1339 | return 0; | |
241771ef | 1340 | } |
004417a6 | 1341 | early_initcall(init_hw_perf_events); |
621a01ea | 1342 | |
cdd6c482 | 1343 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1344 | { |
cc2ad4ba | 1345 | x86_perf_event_update(event); |
ee06094f IM |
1346 | } |
1347 | ||
4d1c52b0 LM |
1348 | /* |
1349 | * Start group events scheduling transaction | |
1350 | * Set the flag to make pmu::enable() not perform the | |
1351 | * schedulability test, it will be performed at commit time | |
1352 | */ | |
51b0fe39 | 1353 | static void x86_pmu_start_txn(struct pmu *pmu) |
4d1c52b0 | 1354 | { |
33696fc0 | 1355 | perf_pmu_disable(pmu); |
0a3aee0d TH |
1356 | __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN); |
1357 | __this_cpu_write(cpu_hw_events.n_txn, 0); | |
4d1c52b0 LM |
1358 | } |
1359 | ||
1360 | /* | |
1361 | * Stop group events scheduling transaction | |
1362 | * Clear the flag and pmu::enable() will perform the | |
1363 | * schedulability test. | |
1364 | */ | |
51b0fe39 | 1365 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1366 | { |
0a3aee0d | 1367 | __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN); |
90151c35 SE |
1368 | /* |
1369 | * Truncate the collected events. | |
1370 | */ | |
0a3aee0d TH |
1371 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1372 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1373 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1374 | } |
1375 | ||
1376 | /* | |
1377 | * Commit group events scheduling transaction | |
1378 | * Perform the group schedulability test as a whole | |
1379 | * Return 0 if success | |
1380 | */ | |
51b0fe39 | 1381 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 LM |
1382 | { |
1383 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1384 | int assign[X86_PMC_IDX_MAX]; | |
1385 | int n, ret; | |
1386 | ||
1387 | n = cpuc->n_events; | |
1388 | ||
1389 | if (!x86_pmu_initialized()) | |
1390 | return -EAGAIN; | |
1391 | ||
1392 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1393 | if (ret) | |
1394 | return ret; | |
1395 | ||
1396 | /* | |
1397 | * copy new assignment, now we know it is possible | |
1398 | * will be used by hw_perf_enable() | |
1399 | */ | |
1400 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1401 | ||
8d2cacbb | 1402 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1403 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1404 | return 0; |
1405 | } | |
cd8a38d3 SE |
1406 | /* |
1407 | * a fake_cpuc is used to validate event groups. Due to | |
1408 | * the extra reg logic, we need to also allocate a fake | |
1409 | * per_core and per_cpu structure. Otherwise, group events | |
1410 | * using extra reg may conflict without the kernel being | |
1411 | * able to catch this when the last event gets added to | |
1412 | * the group. | |
1413 | */ | |
1414 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1415 | { | |
1416 | kfree(cpuc->shared_regs); | |
1417 | kfree(cpuc); | |
1418 | } | |
1419 | ||
1420 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1421 | { | |
1422 | struct cpu_hw_events *cpuc; | |
1423 | int cpu = raw_smp_processor_id(); | |
1424 | ||
1425 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1426 | if (!cpuc) | |
1427 | return ERR_PTR(-ENOMEM); | |
1428 | ||
1429 | /* only needed, if we have extra_regs */ | |
1430 | if (x86_pmu.extra_regs) { | |
1431 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1432 | if (!cpuc->shared_regs) | |
1433 | goto error; | |
1434 | } | |
1435 | return cpuc; | |
1436 | error: | |
1437 | free_fake_cpuc(cpuc); | |
1438 | return ERR_PTR(-ENOMEM); | |
1439 | } | |
4d1c52b0 | 1440 | |
ca037701 PZ |
1441 | /* |
1442 | * validate that we can schedule this event | |
1443 | */ | |
1444 | static int validate_event(struct perf_event *event) | |
1445 | { | |
1446 | struct cpu_hw_events *fake_cpuc; | |
1447 | struct event_constraint *c; | |
1448 | int ret = 0; | |
1449 | ||
cd8a38d3 SE |
1450 | fake_cpuc = allocate_fake_cpuc(); |
1451 | if (IS_ERR(fake_cpuc)) | |
1452 | return PTR_ERR(fake_cpuc); | |
ca037701 PZ |
1453 | |
1454 | c = x86_pmu.get_event_constraints(fake_cpuc, event); | |
1455 | ||
1456 | if (!c || !c->weight) | |
aa2bc1ad | 1457 | ret = -EINVAL; |
ca037701 PZ |
1458 | |
1459 | if (x86_pmu.put_event_constraints) | |
1460 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
1461 | ||
cd8a38d3 | 1462 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
1463 | |
1464 | return ret; | |
1465 | } | |
1466 | ||
1da53e02 SE |
1467 | /* |
1468 | * validate a single event group | |
1469 | * | |
1470 | * validation include: | |
184f412c IM |
1471 | * - check events are compatible which each other |
1472 | * - events do not compete for the same counter | |
1473 | * - number of events <= number of counters | |
1da53e02 SE |
1474 | * |
1475 | * validation ensures the group can be loaded onto the | |
1476 | * PMU if it was the only group available. | |
1477 | */ | |
fe9081cc PZ |
1478 | static int validate_group(struct perf_event *event) |
1479 | { | |
1da53e02 | 1480 | struct perf_event *leader = event->group_leader; |
502568d5 | 1481 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 1482 | int ret = -EINVAL, n; |
fe9081cc | 1483 | |
cd8a38d3 SE |
1484 | fake_cpuc = allocate_fake_cpuc(); |
1485 | if (IS_ERR(fake_cpuc)) | |
1486 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
1487 | /* |
1488 | * the event is not yet connected with its | |
1489 | * siblings therefore we must first collect | |
1490 | * existing siblings, then add the new event | |
1491 | * before we can simulate the scheduling | |
1492 | */ | |
502568d5 | 1493 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 1494 | if (n < 0) |
cd8a38d3 | 1495 | goto out; |
fe9081cc | 1496 | |
502568d5 PZ |
1497 | fake_cpuc->n_events = n; |
1498 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 1499 | if (n < 0) |
cd8a38d3 | 1500 | goto out; |
fe9081cc | 1501 | |
502568d5 | 1502 | fake_cpuc->n_events = n; |
1da53e02 | 1503 | |
a072738e | 1504 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 1505 | |
502568d5 | 1506 | out: |
cd8a38d3 | 1507 | free_fake_cpuc(fake_cpuc); |
502568d5 | 1508 | return ret; |
fe9081cc PZ |
1509 | } |
1510 | ||
dda99116 | 1511 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 1512 | { |
51b0fe39 | 1513 | struct pmu *tmp; |
621a01ea IM |
1514 | int err; |
1515 | ||
b0a873eb PZ |
1516 | switch (event->attr.type) { |
1517 | case PERF_TYPE_RAW: | |
1518 | case PERF_TYPE_HARDWARE: | |
1519 | case PERF_TYPE_HW_CACHE: | |
1520 | break; | |
1521 | ||
1522 | default: | |
1523 | return -ENOENT; | |
1524 | } | |
1525 | ||
1526 | err = __x86_pmu_event_init(event); | |
fe9081cc | 1527 | if (!err) { |
8113070d SE |
1528 | /* |
1529 | * we temporarily connect event to its pmu | |
1530 | * such that validate_group() can classify | |
1531 | * it as an x86 event using is_x86_event() | |
1532 | */ | |
1533 | tmp = event->pmu; | |
1534 | event->pmu = &pmu; | |
1535 | ||
fe9081cc PZ |
1536 | if (event->group_leader != event) |
1537 | err = validate_group(event); | |
ca037701 PZ |
1538 | else |
1539 | err = validate_event(event); | |
8113070d SE |
1540 | |
1541 | event->pmu = tmp; | |
fe9081cc | 1542 | } |
a1792cda | 1543 | if (err) { |
cdd6c482 IM |
1544 | if (event->destroy) |
1545 | event->destroy(event); | |
a1792cda | 1546 | } |
621a01ea | 1547 | |
b0a873eb | 1548 | return err; |
621a01ea | 1549 | } |
d7d59fb3 | 1550 | |
fe4a3308 PZ |
1551 | static int x86_pmu_event_idx(struct perf_event *event) |
1552 | { | |
1553 | int idx = event->hw.idx; | |
1554 | ||
1555 | if (x86_pmu.num_counters_fixed && idx >= X86_PMC_IDX_FIXED) { | |
1556 | idx -= X86_PMC_IDX_FIXED; | |
1557 | idx |= 1 << 30; | |
1558 | } | |
1559 | ||
1560 | return idx + 1; | |
1561 | } | |
1562 | ||
0c9d42ed PZ |
1563 | static ssize_t get_attr_rdpmc(struct device *cdev, |
1564 | struct device_attribute *attr, | |
1565 | char *buf) | |
1566 | { | |
1567 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
1568 | } | |
1569 | ||
1570 | static void change_rdpmc(void *info) | |
1571 | { | |
1572 | bool enable = !!(unsigned long)info; | |
1573 | ||
1574 | if (enable) | |
1575 | set_in_cr4(X86_CR4_PCE); | |
1576 | else | |
1577 | clear_in_cr4(X86_CR4_PCE); | |
1578 | } | |
1579 | ||
1580 | static ssize_t set_attr_rdpmc(struct device *cdev, | |
1581 | struct device_attribute *attr, | |
1582 | const char *buf, size_t count) | |
1583 | { | |
1584 | unsigned long val = simple_strtoul(buf, NULL, 0); | |
1585 | ||
1586 | if (!!val != !!x86_pmu.attr_rdpmc) { | |
1587 | x86_pmu.attr_rdpmc = !!val; | |
1588 | smp_call_function(change_rdpmc, (void *)val, 1); | |
1589 | } | |
1590 | ||
1591 | return count; | |
1592 | } | |
1593 | ||
1594 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
1595 | ||
1596 | static struct attribute *x86_pmu_attrs[] = { | |
1597 | &dev_attr_rdpmc.attr, | |
1598 | NULL, | |
1599 | }; | |
1600 | ||
1601 | static struct attribute_group x86_pmu_attr_group = { | |
1602 | .attrs = x86_pmu_attrs, | |
1603 | }; | |
1604 | ||
1605 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
1606 | &x86_pmu_attr_group, | |
1607 | NULL, | |
1608 | }; | |
1609 | ||
b0a873eb | 1610 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1611 | .pmu_enable = x86_pmu_enable, |
1612 | .pmu_disable = x86_pmu_disable, | |
1613 | ||
0c9d42ed PZ |
1614 | .attr_groups = x86_pmu_attr_groups, |
1615 | ||
b0a873eb | 1616 | .event_init = x86_pmu_event_init, |
a4eaf7f1 PZ |
1617 | |
1618 | .add = x86_pmu_add, | |
1619 | .del = x86_pmu_del, | |
b0a873eb PZ |
1620 | .start = x86_pmu_start, |
1621 | .stop = x86_pmu_stop, | |
1622 | .read = x86_pmu_read, | |
a4eaf7f1 | 1623 | |
b0a873eb PZ |
1624 | .start_txn = x86_pmu_start_txn, |
1625 | .cancel_txn = x86_pmu_cancel_txn, | |
1626 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 PZ |
1627 | |
1628 | .event_idx = x86_pmu_event_idx, | |
b0a873eb PZ |
1629 | }; |
1630 | ||
e3f3541c PZ |
1631 | void perf_update_user_clock(struct perf_event_mmap_page *userpg, u64 now) |
1632 | { | |
1633 | if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
1634 | return; | |
1635 | ||
1636 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | |
1637 | return; | |
1638 | ||
1639 | userpg->time_mult = this_cpu_read(cyc2ns); | |
1640 | userpg->time_shift = CYC2NS_SCALE_FACTOR; | |
1641 | userpg->time_offset = this_cpu_read(cyc2ns_offset) - now; | |
1642 | } | |
1643 | ||
d7d59fb3 PZ |
1644 | /* |
1645 | * callchain support | |
1646 | */ | |
1647 | ||
d7d59fb3 PZ |
1648 | static int backtrace_stack(void *data, char *name) |
1649 | { | |
038e836e | 1650 | return 0; |
d7d59fb3 PZ |
1651 | } |
1652 | ||
1653 | static void backtrace_address(void *data, unsigned long addr, int reliable) | |
1654 | { | |
1655 | struct perf_callchain_entry *entry = data; | |
1656 | ||
70791ce9 | 1657 | perf_callchain_store(entry, addr); |
d7d59fb3 PZ |
1658 | } |
1659 | ||
1660 | static const struct stacktrace_ops backtrace_ops = { | |
d7d59fb3 PZ |
1661 | .stack = backtrace_stack, |
1662 | .address = backtrace_address, | |
06d65bda | 1663 | .walk_stack = print_context_stack_bp, |
d7d59fb3 PZ |
1664 | }; |
1665 | ||
56962b44 FW |
1666 | void |
1667 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 | 1668 | { |
927c7a9e FW |
1669 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1670 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1671 | return; |
927c7a9e FW |
1672 | } |
1673 | ||
70791ce9 | 1674 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1675 | |
e8e999cf | 1676 | dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry); |
d7d59fb3 PZ |
1677 | } |
1678 | ||
257ef9d2 TE |
1679 | #ifdef CONFIG_COMPAT |
1680 | static inline int | |
1681 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
74193ef0 | 1682 | { |
257ef9d2 TE |
1683 | /* 32-bit process in 64-bit kernel. */ |
1684 | struct stack_frame_ia32 frame; | |
1685 | const void __user *fp; | |
74193ef0 | 1686 | |
257ef9d2 TE |
1687 | if (!test_thread_flag(TIF_IA32)) |
1688 | return 0; | |
1689 | ||
1690 | fp = compat_ptr(regs->bp); | |
1691 | while (entry->nr < PERF_MAX_STACK_DEPTH) { | |
1692 | unsigned long bytes; | |
1693 | frame.next_frame = 0; | |
1694 | frame.return_address = 0; | |
1695 | ||
1696 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); | |
1697 | if (bytes != sizeof(frame)) | |
1698 | break; | |
74193ef0 | 1699 | |
257ef9d2 TE |
1700 | if (fp < compat_ptr(regs->sp)) |
1701 | break; | |
74193ef0 | 1702 | |
70791ce9 | 1703 | perf_callchain_store(entry, frame.return_address); |
257ef9d2 TE |
1704 | fp = compat_ptr(frame.next_frame); |
1705 | } | |
1706 | return 1; | |
d7d59fb3 | 1707 | } |
257ef9d2 TE |
1708 | #else |
1709 | static inline int | |
1710 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry) | |
1711 | { | |
1712 | return 0; | |
1713 | } | |
1714 | #endif | |
d7d59fb3 | 1715 | |
56962b44 FW |
1716 | void |
1717 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
d7d59fb3 PZ |
1718 | { |
1719 | struct stack_frame frame; | |
1720 | const void __user *fp; | |
1721 | ||
927c7a9e FW |
1722 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
1723 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 1724 | return; |
927c7a9e | 1725 | } |
5a6cec3a | 1726 | |
74193ef0 | 1727 | fp = (void __user *)regs->bp; |
d7d59fb3 | 1728 | |
70791ce9 | 1729 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 1730 | |
20afc60f AV |
1731 | if (!current->mm) |
1732 | return; | |
1733 | ||
257ef9d2 TE |
1734 | if (perf_callchain_user32(regs, entry)) |
1735 | return; | |
1736 | ||
f9188e02 | 1737 | while (entry->nr < PERF_MAX_STACK_DEPTH) { |
257ef9d2 | 1738 | unsigned long bytes; |
038e836e | 1739 | frame.next_frame = NULL; |
d7d59fb3 PZ |
1740 | frame.return_address = 0; |
1741 | ||
257ef9d2 TE |
1742 | bytes = copy_from_user_nmi(&frame, fp, sizeof(frame)); |
1743 | if (bytes != sizeof(frame)) | |
d7d59fb3 PZ |
1744 | break; |
1745 | ||
5a6cec3a | 1746 | if ((unsigned long)fp < regs->sp) |
d7d59fb3 PZ |
1747 | break; |
1748 | ||
70791ce9 | 1749 | perf_callchain_store(entry, frame.return_address); |
038e836e | 1750 | fp = frame.next_frame; |
d7d59fb3 PZ |
1751 | } |
1752 | } | |
1753 | ||
39447b38 ZY |
1754 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
1755 | { | |
1756 | unsigned long ip; | |
dcf46b94 | 1757 | |
39447b38 ZY |
1758 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
1759 | ip = perf_guest_cbs->get_guest_ip(); | |
1760 | else | |
1761 | ip = instruction_pointer(regs); | |
dcf46b94 | 1762 | |
39447b38 ZY |
1763 | return ip; |
1764 | } | |
1765 | ||
1766 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
1767 | { | |
1768 | int misc = 0; | |
dcf46b94 | 1769 | |
39447b38 | 1770 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
1771 | if (perf_guest_cbs->is_user_mode()) |
1772 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
1773 | else | |
1774 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
1775 | } else { | |
1776 | if (user_mode(regs)) | |
1777 | misc |= PERF_RECORD_MISC_USER; | |
1778 | else | |
1779 | misc |= PERF_RECORD_MISC_KERNEL; | |
1780 | } | |
1781 | ||
39447b38 | 1782 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 1783 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
1784 | |
1785 | return misc; | |
1786 | } | |
b3d9468a GN |
1787 | |
1788 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
1789 | { | |
1790 | cap->version = x86_pmu.version; | |
1791 | cap->num_counters_gp = x86_pmu.num_counters; | |
1792 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
1793 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
1794 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
1795 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
1796 | cap->events_mask_len = x86_pmu.events_mask_len; | |
1797 | } | |
1798 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |