[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / perf_event.h

/*
 * Performance events x86 architecture header
 *
 *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
 *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
 *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
 *  Copyright (C) 2009 Google, Inc., Stephane Eranian
 *
 *  For licencing details see kernel-base/COPYING
 */

#include <linux/perf_event.h>

/*
 *          |   NHM/WSM    |      SNB     |
 * register -------------------------------
 *          |  HT  | no HT |  HT  | no HT |
 *-----------------------------------------
 * offcore  | core | core  | cpu  | core  |
 * lbr_sel  | core | core  | cpu  | core  |
 * ld_lat   | cpu  | core  | cpu  | core  |
 *-----------------------------------------
 *
 * Given that there is a small number of shared regs,
 * we can pre-allocate their slot in the per-cpu
 * per-core reg tables.
 */
enum extra_reg_type {
	EXTRA_REG_NONE  = -1,	/* not used */

	EXTRA_REG_RSP_0 = 0,	/* offcore_response_0 */
	EXTRA_REG_RSP_1 = 1,	/* offcore_response_1 */
	EXTRA_REG_LBR   = 2,	/* lbr_select */

	EXTRA_REG_MAX		/* number of entries needed */
};

struct event_constraint {
	union {
		unsigned long	idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
		u64		idxmsk64;
	};
	u64	code;
	u64	cmask;
	int	weight;
	int	overlap;
};

struct amd_nb {
	int nb_id;  /* NorthBridge id */
	int refcnt; /* reference count */
	struct perf_event *owners[X86_PMC_IDX_MAX];
	struct event_constraint event_constraints[X86_PMC_IDX_MAX];
};

/* The maximal number of PEBS events: */
#define MAX_PEBS_EVENTS		4

/*
 * A debug store configuration.
 *
 * We only support architectures that use 64bit fields.
 */
struct debug_store {
	u64	bts_buffer_base;
	u64	bts_index;
	u64	bts_absolute_maximum;
	u64	bts_interrupt_threshold;
	u64	pebs_buffer_base;
	u64	pebs_index;
	u64	pebs_absolute_maximum;
	u64	pebs_interrupt_threshold;
	u64	pebs_event_reset[MAX_PEBS_EVENTS];
};

/*
 * Per register state.
 */
struct er_account {
	raw_spinlock_t		lock;	/* per-core: protect structure */
	u64                 config;	/* extra MSR config */
	u64                 reg;	/* extra MSR number */
	atomic_t            ref;	/* reference count */
};

/*
 * Per core/cpu state
 *
 * Used to coordinate shared registers between HT threads or
 * among events on a single PMU.
 */
struct intel_shared_regs {
	struct er_account       regs[EXTRA_REG_MAX];
	int                     refcnt;		/* per-core: #HT threads */
	unsigned                core_id;	/* per-core: core id */
};

#define MAX_LBR_ENTRIES		16

struct cpu_hw_events {
	/*
	 * Generic x86 PMC bits
	 */
	struct perf_event	*events[X86_PMC_IDX_MAX]; /* in counter order */
	unsigned long		active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	unsigned long		running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	int			enabled;

	int			n_events;
	int			n_added;
	int			n_txn;
	int			assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
	u64			tags[X86_PMC_IDX_MAX];
	struct perf_event	*event_list[X86_PMC_IDX_MAX]; /* in enabled order */

	unsigned int		group_flag;

	/*
	 * Intel DebugStore bits
	 */
	struct debug_store	*ds;
	u64			pebs_enabled;

	/*
	 * Intel LBR bits
	 */
	int				lbr_users;
	void				*lbr_context;
	struct perf_branch_stack	lbr_stack;
	struct perf_branch_entry	lbr_entries[MAX_LBR_ENTRIES];
	struct er_account		*lbr_sel;
	u64				br_sel;

	/*
	 * Intel host/guest exclude bits
	 */
	u64				intel_ctrl_guest_mask;
	u64				intel_ctrl_host_mask;
	struct perf_guest_switch_msr	guest_switch_msrs[X86_PMC_IDX_MAX];

	/*
	 * manage shared (per-core, per-cpu) registers
	 * used on Intel NHM/WSM/SNB
	 */
	struct intel_shared_regs	*shared_regs;

	/*
	 * AMD specific bits
	 */
	struct amd_nb			*amd_nb;
	/* Inverted mask of bits to clear in the perf_ctr ctrl registers */
	u64				perf_ctr_virt_mask;

	void				*kfree_on_online;
};

#define __EVENT_CONSTRAINT(c, n, m, w, o) {\
	{ .idxmsk64 = (n) },		\
	.code = (c),			\
	.cmask = (m),			\
	.weight = (w),			\
	.overlap = (o),			\
}

#define EVENT_CONSTRAINT(c, n, m)	\
	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)

/*
 * The overlap flag marks event constraints with overlapping counter
 * masks. This is the case if the counter mask of such an event is not
 * a subset of any other counter mask of a constraint with an equal or
 * higher weight, e.g.:
 *
 *  c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
 *  c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
 *  c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
 *
 * The event scheduler may not select the correct counter in the first
 * cycle because it needs to know which subsequent events will be
 * scheduled. It may fail to schedule the events then. So we set the
 * overlap flag for such constraints to give the scheduler a hint which
 * events to select for counter rescheduling.
 *
 * Care must be taken as the rescheduling algorithm is O(n!) which
 * will increase scheduling cycles for an over-commited system
 * dramatically.  The number of such EVENT_CONSTRAINT_OVERLAP() macros
 * and its counter masks must be kept at a minimum.
 */
#define EVENT_CONSTRAINT_OVERLAP(c, n, m)	\
	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)

/*
 * Constraint on the Event code.
 */
#define INTEL_EVENT_CONSTRAINT(c, n)	\
	EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)

/*
 * Constraint on the Event code + UMask + fixed-mask
 *
 * filter mask to validate fixed counter events.
 * the following filters disqualify for fixed counters:
 *  - inv
 *  - edge
 *  - cnt-mask
 *  The other filters are supported by fixed counters.
 *  The any-thread option is supported starting with v3.
 */
#define FIXED_EVENT_CONSTRAINT(c, n)	\
	EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)

/*
 * Constraint on the Event code + UMask
 */
#define INTEL_UEVENT_CONSTRAINT(c, n)	\
	EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)

#define EVENT_CONSTRAINT_END		\
	EVENT_CONSTRAINT(0, 0, 0)

#define for_each_event_constraint(e, c)	\
	for ((e) = (c); (e)->weight; (e)++)

/*
 * Extra registers for specific events.
 *
 * Some events need large masks and require external MSRs.
 * Those extra MSRs end up being shared for all events on
 * a PMU and sometimes between PMU of sibling HT threads.
 * In either case, the kernel needs to handle conflicting
 * accesses to those extra, shared, regs. The data structure
 * to manage those registers is stored in cpu_hw_event.
 */
struct extra_reg {
	unsigned int		event;
	unsigned int		msr;
	u64			config_mask;
	u64			valid_mask;
	int			idx;  /* per_xxx->regs[] reg index */
};

#define EVENT_EXTRA_REG(e, ms, m, vm, i) {	\
	.event = (e),		\
	.msr = (ms),		\
	.config_mask = (m),	\
	.valid_mask = (vm),	\
	.idx = EXTRA_REG_##i	\
	}

#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx)	\
	EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)

#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)

union perf_capabilities {
	struct {
		u64	lbr_format:6;
		u64	pebs_trap:1;
		u64	pebs_arch_reg:1;
		u64	pebs_format:4;
		u64	smm_freeze:1;
	};
	u64	capabilities;
};

struct x86_pmu_quirk {
	struct x86_pmu_quirk *next;
	void (*func)(void);
};

/*
 * struct x86_pmu - generic x86 pmu
 */
struct x86_pmu {
	/*
	 * Generic x86 PMC bits
	 */
	const char	*name;
	int		version;
	int		(*handle_irq)(struct pt_regs *);
	void		(*disable_all)(void);
	void		(*enable_all)(int added);
	void		(*enable)(struct perf_event *);
	void		(*disable)(struct perf_event *);
	int		(*hw_config)(struct perf_event *event);
	int		(*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
	unsigned	eventsel;
	unsigned	perfctr;
	u64		(*event_map)(int);
	int		max_events;
	int		num_counters;
	int		num_counters_fixed;
	int		cntval_bits;
	u64		cntval_mask;
	union {
			unsigned long events_maskl;
			unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
	};
	int		events_mask_len;
	int		apic;
	u64		max_period;
	struct event_constraint *
			(*get_event_constraints)(struct cpu_hw_events *cpuc,
						 struct perf_event *event);

	void		(*put_event_constraints)(struct cpu_hw_events *cpuc,
						 struct perf_event *event);
	struct event_constraint *event_constraints;
	struct x86_pmu_quirk *quirks;
	int		perfctr_second_write;

	/*
	 * sysfs attrs
	 */
	int		attr_rdpmc;

	/*
	 * CPU Hotplug hooks
	 */
	int		(*cpu_prepare)(int cpu);
	void		(*cpu_starting)(int cpu);
	void		(*cpu_dying)(int cpu);
	void		(*cpu_dead)(int cpu);

	/*
	 * Intel Arch Perfmon v2+
	 */
	u64			intel_ctrl;
	union perf_capabilities intel_cap;

	/*
	 * Intel DebugStore bits
	 */
	int		bts, pebs;
	int		bts_active, pebs_active;
	int		pebs_record_size;
	void		(*drain_pebs)(struct pt_regs *regs);
	struct event_constraint *pebs_constraints;

	/*
	 * Intel LBR
	 */
	unsigned long	lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
	int		lbr_nr;			   /* hardware stack size */
	u64		lbr_sel_mask;		   /* LBR_SELECT valid bits */
	const int	*lbr_sel_map;		   /* lbr_select mappings */

	/*
	 * Extra registers for events
	 */
	struct extra_reg *extra_regs;
	unsigned int er_flags;

	/*
	 * Intel host/guest support (KVM)
	 */
	struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
};

#define x86_add_quirk(func_)						\
do {									\
	static struct x86_pmu_quirk __quirk __initdata = {		\
		.func = func_,						\
	};								\
	__quirk.next = x86_pmu.quirks;					\
	x86_pmu.quirks = &__quirk;					\
} while (0)

#define ERF_NO_HT_SHARING	1
#define ERF_HAS_RSP_1		2

extern struct x86_pmu x86_pmu __read_mostly;

DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);

int x86_perf_event_set_period(struct perf_event *event);

/*
 * Generalized hw caching related hw_event table, filled
 * in on a per model basis. A value of 0 means
 * 'not supported', -1 means 'hw_event makes no sense on
 * this CPU', any other value means the raw hw_event
 * ID.
 */

#define C(x) PERF_COUNT_HW_CACHE_##x

extern u64 __read_mostly hw_cache_event_ids
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];
extern u64 __read_mostly hw_cache_extra_regs
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX];

u64 x86_perf_event_update(struct perf_event *event);

static inline int x86_pmu_addr_offset(int index)
{
	int offset;

	/* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
	alternative_io(ASM_NOP2,
		       "shll $1, %%eax",
		       X86_FEATURE_PERFCTR_CORE,
		       "=a" (offset),
		       "a"  (index));

	return offset;
}

static inline unsigned int x86_pmu_config_addr(int index)
{
	return x86_pmu.eventsel + x86_pmu_addr_offset(index);
}

static inline unsigned int x86_pmu_event_addr(int index)
{
	return x86_pmu.perfctr + x86_pmu_addr_offset(index);
}

int x86_setup_perfctr(struct perf_event *event);

int x86_pmu_hw_config(struct perf_event *event);

void x86_pmu_disable_all(void);

static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
					  u64 enable_mask)
{
	u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);

	if (hwc->extra_reg.reg)
		wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
	wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
}

void x86_pmu_enable_all(int added);

int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);

void x86_pmu_stop(struct perf_event *event, int flags);

static inline void x86_pmu_disable_event(struct perf_event *event)
{
	struct hw_perf_event *hwc = &event->hw;

	wrmsrl(hwc->config_base, hwc->config);
}

void x86_pmu_enable_event(struct perf_event *event);

int x86_pmu_handle_irq(struct pt_regs *regs);

extern struct event_constraint emptyconstraint;

extern struct event_constraint unconstrained;

static inline bool kernel_ip(unsigned long ip)
{
#ifdef CONFIG_X86_32
	return ip > PAGE_OFFSET;
#else
	return (long)ip < 0;
#endif
}

#ifdef CONFIG_CPU_SUP_AMD

int amd_pmu_init(void);

#else /* CONFIG_CPU_SUP_AMD */

static inline int amd_pmu_init(void)
{
	return 0;
}

#endif /* CONFIG_CPU_SUP_AMD */

#ifdef CONFIG_CPU_SUP_INTEL

int intel_pmu_save_and_restart(struct perf_event *event);

struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);

struct intel_shared_regs *allocate_shared_regs(int cpu);

int intel_pmu_init(void);

void init_debug_store_on_cpu(int cpu);

void fini_debug_store_on_cpu(int cpu);

void release_ds_buffers(void);

void reserve_ds_buffers(void);

extern struct event_constraint bts_constraint;

void intel_pmu_enable_bts(u64 config);

void intel_pmu_disable_bts(void);

int intel_pmu_drain_bts_buffer(void);

extern struct event_constraint intel_core2_pebs_event_constraints[];

extern struct event_constraint intel_atom_pebs_event_constraints[];

extern struct event_constraint intel_nehalem_pebs_event_constraints[];

extern struct event_constraint intel_westmere_pebs_event_constraints[];

extern struct event_constraint intel_snb_pebs_event_constraints[];

struct event_constraint *intel_pebs_constraints(struct perf_event *event);

void intel_pmu_pebs_enable(struct perf_event *event);

void intel_pmu_pebs_disable(struct perf_event *event);

void intel_pmu_pebs_enable_all(void);

void intel_pmu_pebs_disable_all(void);

void intel_ds_init(void);

void intel_pmu_lbr_reset(void);

void intel_pmu_lbr_enable(struct perf_event *event);

void intel_pmu_lbr_disable(struct perf_event *event);

void intel_pmu_lbr_enable_all(void);

void intel_pmu_lbr_disable_all(void);

void intel_pmu_lbr_read(void);

void intel_pmu_lbr_init_core(void);

void intel_pmu_lbr_init_nhm(void);

void intel_pmu_lbr_init_atom(void);

void intel_pmu_lbr_init_snb(void);

int intel_pmu_setup_lbr_filter(struct perf_event *event);

int p4_pmu_init(void);

int p6_pmu_init(void);

#else /* CONFIG_CPU_SUP_INTEL */

static inline void reserve_ds_buffers(void)
{
}

static inline void release_ds_buffers(void)
{
}

static inline int intel_pmu_init(void)
{
	return 0;
}

static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
{
	return NULL;
}

#endif /* CONFIG_CPU_SUP_INTEL */
Commit	Line	Data
de0428a7 KW	1	/*
	2	* Performance events x86 architecture header
	3	*
	4	* Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
	5	* Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
	6	* Copyright (C) 2009 Jaswinder Singh Rajput
	7	* Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
	8	* Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
	9	* Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
	10	* Copyright (C) 2009 Google, Inc., Stephane Eranian
	11	*
	12	* For licencing details see kernel-base/COPYING
	13	*/
	14
	15	#include <linux/perf_event.h>
	16
	17	/*
	18	* \| NHM/WSM \| SNB \|
	19	* register -------------------------------
	20	* \| HT \| no HT \| HT \| no HT \|
	21	*-----------------------------------------
	22	* offcore \| core \| core \| cpu \| core \|
	23	* lbr_sel \| core \| core \| cpu \| core \|
	24	* ld_lat \| cpu \| core \| cpu \| core \|
	25	*-----------------------------------------
	26	*
	27	* Given that there is a small number of shared regs,
	28	* we can pre-allocate their slot in the per-cpu
	29	* per-core reg tables.
	30	*/
	31	enum extra_reg_type {
	32	EXTRA_REG_NONE = -1, /* not used */
	33
	34	EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
	35	EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
b36817e8	36	EXTRA_REG_LBR = 2, /* lbr_select */
de0428a7 KW	37
	38	EXTRA_REG_MAX /* number of entries needed */
	39	};
	40
	41	struct event_constraint {
	42	union {
	43	unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	44	u64 idxmsk64;
	45	};
	46	u64 code;
	47	u64 cmask;
	48	int weight;
bc1738f6	49	int overlap;
de0428a7 KW	50	};
	51
	52	struct amd_nb {
	53	int nb_id; /* NorthBridge id */
	54	int refcnt; /* reference count */
	55	struct perf_event *owners[X86_PMC_IDX_MAX];
	56	struct event_constraint event_constraints[X86_PMC_IDX_MAX];
	57	};
	58
	59	/* The maximal number of PEBS events: */
	60	#define MAX_PEBS_EVENTS 4
	61
	62	/*
	63	* A debug store configuration.
	64	*
	65	* We only support architectures that use 64bit fields.
	66	*/
	67	struct debug_store {
	68	u64 bts_buffer_base;
	69	u64 bts_index;
	70	u64 bts_absolute_maximum;
	71	u64 bts_interrupt_threshold;
	72	u64 pebs_buffer_base;
	73	u64 pebs_index;
	74	u64 pebs_absolute_maximum;
	75	u64 pebs_interrupt_threshold;
	76	u64 pebs_event_reset[MAX_PEBS_EVENTS];
	77	};
	78
	79	/*
	80	* Per register state.
	81	*/
	82	struct er_account {
	83	raw_spinlock_t lock; /* per-core: protect structure */
	84	u64 config; /* extra MSR config */
	85	u64 reg; /* extra MSR number */
	86	atomic_t ref; /* reference count */
	87	};
	88
	89	/*
	90	* Per core/cpu state
	91	*
	92	* Used to coordinate shared registers between HT threads or
	93	* among events on a single PMU.
	94	*/
	95	struct intel_shared_regs {
	96	struct er_account regs[EXTRA_REG_MAX];
	97	int refcnt; /* per-core: #HT threads */
	98	unsigned core_id; /* per-core: core id */
	99	};
	100
	101	#define MAX_LBR_ENTRIES 16
	102
	103	struct cpu_hw_events {
	104	/*
	105	* Generic x86 PMC bits
	106	*/
	107	struct perf_event events[X86_PMC_IDX_MAX]; / in counter order */
	108	unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	109	unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
	110	int enabled;
	111
	112	int n_events;
	113	int n_added;
114	int n_txn;
115	int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
116	u64 tags[X86_PMC_IDX_MAX];
117	struct perf_event event_list[X86_PMC_IDX_MAX]; / in enabled order */
118
119	unsigned int group_flag;
120
121	/*
122	* Intel DebugStore bits
123	*/
124	struct debug_store *ds;
125	u64 pebs_enabled;
126
127	/*
128	* Intel LBR bits
129	*/
130	int lbr_users;
131	void *lbr_context;
132	struct perf_branch_stack lbr_stack;
133	struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
b36817e8	134	struct er_account *lbr_sel;
3e702ff6	135	u64 br_sel;
de0428a7	136
144d31e6 GN	137	/*
	138	* Intel host/guest exclude bits
	139	*/
	140	u64 intel_ctrl_guest_mask;
	141	u64 intel_ctrl_host_mask;
	142	struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
	143
de0428a7 KW	144	/*
	145	* manage shared (per-core, per-cpu) registers
	146	* used on Intel NHM/WSM/SNB
	147	*/
	148	struct intel_shared_regs *shared_regs;
	149
	150	/*
	151	* AMD specific bits
	152	*/
1018faa6 JR	153	struct amd_nb *amd_nb;
	154	/* Inverted mask of bits to clear in the perf_ctr ctrl registers */
	155	u64 perf_ctr_virt_mask;
de0428a7 KW	156
	157	void *kfree_on_online;
	158	};
	159
bc1738f6	160	#define __EVENT_CONSTRAINT(c, n, m, w, o) {\
de0428a7 KW	161	{ .idxmsk64 = (n) }, \
	162	.code = (c), \
	163	.cmask = (m), \
	164	.weight = (w), \
bc1738f6	165	.overlap = (o), \
de0428a7 KW	166	}
	167
	168	#define EVENT_CONSTRAINT(c, n, m) \
bc1738f6 RR	169	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0)
	170
	171	/*
	172	* The overlap flag marks event constraints with overlapping counter
	173	* masks. This is the case if the counter mask of such an event is not
	174	* a subset of any other counter mask of a constraint with an equal or
	175	* higher weight, e.g.:
	176	*
	177	* c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
	178	* c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
	179	* c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
	180	*
	181	* The event scheduler may not select the correct counter in the first
	182	* cycle because it needs to know which subsequent events will be
	183	* scheduled. It may fail to schedule the events then. So we set the
	184	* overlap flag for such constraints to give the scheduler a hint which
	185	* events to select for counter rescheduling.
	186	*
	187	* Care must be taken as the rescheduling algorithm is O(n!) which
	188	* will increase scheduling cycles for an over-commited system
	189	* dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
	190	* and its counter masks must be kept at a minimum.
	191	*/
	192	#define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
	193	__EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1)
de0428a7 KW	194
	195	/*
	196	* Constraint on the Event code.
	197	*/
	198	#define INTEL_EVENT_CONSTRAINT(c, n) \
	199	EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
	200
	201	/*
	202	* Constraint on the Event code + UMask + fixed-mask
	203	*
	204	* filter mask to validate fixed counter events.
	205	* the following filters disqualify for fixed counters:
	206	* - inv
	207	* - edge
	208	* - cnt-mask
	209	* The other filters are supported by fixed counters.
	210	* The any-thread option is supported starting with v3.
	211	*/
	212	#define FIXED_EVENT_CONSTRAINT(c, n) \
	213	EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
	214
	215	/*
	216	* Constraint on the Event code + UMask
	217	*/
	218	#define INTEL_UEVENT_CONSTRAINT(c, n) \
	219	EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
	220
	221	#define EVENT_CONSTRAINT_END \
	222	EVENT_CONSTRAINT(0, 0, 0)
	223
	224	#define for_each_event_constraint(e, c) \
	225	for ((e) = (c); (e)->weight; (e)++)
	226
	227	/*
	228	* Extra registers for specific events.
	229	*
	230	* Some events need large masks and require external MSRs.
	231	* Those extra MSRs end up being shared for all events on
	232	* a PMU and sometimes between PMU of sibling HT threads.
	233	* In either case, the kernel needs to handle conflicting
	234	* accesses to those extra, shared, regs. The data structure
	235	* to manage those registers is stored in cpu_hw_event.
	236	*/
	237	struct extra_reg {
	238	unsigned int event;
	239	unsigned int msr;
	240	u64 config_mask;
	241	u64 valid_mask;
	242	int idx; /* per_xxx->regs[] reg index */
	243	};
	244
	245	#define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
	246	.event = (e), \
	247	.msr = (ms), \
	248	.config_mask = (m), \
	249	.valid_mask = (vm), \
	250	.idx = EXTRA_REG_##i \
	251	}
	252
	253	#define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
	254	EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
	255
	256	#define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
	257
258	union perf_capabilities {
259	struct {
260	u64 lbr_format:6;
261	u64 pebs_trap:1;
262	u64 pebs_arch_reg:1;
263	u64 pebs_format:4;
264	u64 smm_freeze:1;
265	};
266	u64 capabilities;
267	};
268
c1d6f42f PZ	269	struct x86_pmu_quirk {
	270	struct x86_pmu_quirk *next;
	271	void (*func)(void);
	272	};
	273
de0428a7 KW	274	/*
	275	* struct x86_pmu - generic x86 pmu
	276	*/
	277	struct x86_pmu {
	278	/*
	279	* Generic x86 PMC bits
	280	*/
	281	const char *name;
	282	int version;
	283	int (handle_irq)(struct pt_regs );
	284	void (*disable_all)(void);
	285	void (*enable_all)(int added);
	286	void (enable)(struct perf_event );
	287	void (disable)(struct perf_event );
	288	int (hw_config)(struct perf_event event);
	289	int (schedule_events)(struct cpu_hw_events cpuc, int n, int *assign);
	290	unsigned eventsel;
	291	unsigned perfctr;
	292	u64 (*event_map)(int);
	293	int max_events;
	294	int num_counters;
	295	int num_counters_fixed;
	296	int cntval_bits;
	297	u64 cntval_mask;
ffb871bc GN	298	union {
	299	unsigned long events_maskl;
	300	unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
	301	};
	302	int events_mask_len;
de0428a7 KW	303	int apic;
	304	u64 max_period;
	305	struct event_constraint *
	306	(get_event_constraints)(struct cpu_hw_events cpuc,
	307	struct perf_event *event);
	308
	309	void (put_event_constraints)(struct cpu_hw_events cpuc,
	310	struct perf_event *event);
	311	struct event_constraint *event_constraints;
c1d6f42f	312	struct x86_pmu_quirk *quirks;
de0428a7 KW	313	int perfctr_second_write;
de0428a7 KW	314
0c9d42ed PZ	315	/*
	316	* sysfs attrs
	317	*/
	318	int attr_rdpmc;
	319
	320	/*
	321	* CPU Hotplug hooks
	322	*/
de0428a7 KW	323	int (*cpu_prepare)(int cpu);
	324	void (*cpu_starting)(int cpu);
	325	void (*cpu_dying)(int cpu);
	326	void (*cpu_dead)(int cpu);
	327
	328	/*
	329	* Intel Arch Perfmon v2+
	330	*/
	331	u64 intel_ctrl;
	332	union perf_capabilities intel_cap;
	333
	334	/*
	335	* Intel DebugStore bits
	336	*/
	337	int bts, pebs;
	338	int bts_active, pebs_active;
	339	int pebs_record_size;
	340	void (drain_pebs)(struct pt_regs regs);
	341	struct event_constraint *pebs_constraints;
	342
	343	/*
	344	* Intel LBR
	345	*/
	346	unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
	347	int lbr_nr; /* hardware stack size */
b36817e8 SE	348	u64 lbr_sel_mask; /* LBR_SELECT valid bits */
b36817e8 SE	349	const int lbr_sel_map; / lbr_select mappings */
de0428a7 KW	350
	351	/*
	352	* Extra registers for events
	353	*/
	354	struct extra_reg *extra_regs;
	355	unsigned int er_flags;
144d31e6 GN	356
	357	/*
	358	* Intel host/guest support (KVM)
	359	*/
	360	struct perf_guest_switch_msr (guest_get_msrs)(int *nr);
de0428a7 KW	361	};
de0428a7 KW	362
c1d6f42f PZ	363	#define x86_add_quirk(func_) \
	364	do { \
	365	static struct x86_pmu_quirk __quirk __initdata = { \
	366	.func = func_, \
	367	}; \
	368	__quirk.next = x86_pmu.quirks; \
	369	x86_pmu.quirks = &__quirk; \
	370	} while (0)
	371
de0428a7 KW	372	#define ERF_NO_HT_SHARING 1
	373	#define ERF_HAS_RSP_1 2
	374
	375	extern struct x86_pmu x86_pmu __read_mostly;
	376
	377	DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
	378
	379	int x86_perf_event_set_period(struct perf_event *event);
	380
	381	/*
	382	* Generalized hw caching related hw_event table, filled
	383	* in on a per model basis. A value of 0 means
	384	* 'not supported', -1 means 'hw_event makes no sense on
	385	* this CPU', any other value means the raw hw_event
	386	* ID.
	387	*/
	388
	389	#define C(x) PERF_COUNT_HW_CACHE_##x
	390
	391	extern u64 __read_mostly hw_cache_event_ids
	392	[PERF_COUNT_HW_CACHE_MAX]
	393	[PERF_COUNT_HW_CACHE_OP_MAX]
	394	[PERF_COUNT_HW_CACHE_RESULT_MAX];
	395	extern u64 __read_mostly hw_cache_extra_regs
	396	[PERF_COUNT_HW_CACHE_MAX]
	397	[PERF_COUNT_HW_CACHE_OP_MAX]
	398	[PERF_COUNT_HW_CACHE_RESULT_MAX];
	399
	400	u64 x86_perf_event_update(struct perf_event *event);
	401
	402	static inline int x86_pmu_addr_offset(int index)
	403	{
	404	int offset;
	405
	406	/* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
	407	alternative_io(ASM_NOP2,
	408	"shll $1, %%eax",
	409	X86_FEATURE_PERFCTR_CORE,
	410	"=a" (offset),
	411	"a" (index));
	412
	413	return offset;
	414	}
	415
	416	static inline unsigned int x86_pmu_config_addr(int index)
	417	{
	418	return x86_pmu.eventsel + x86_pmu_addr_offset(index);
	419	}
	420
	421	static inline unsigned int x86_pmu_event_addr(int index)
	422	{
	423	return x86_pmu.perfctr + x86_pmu_addr_offset(index);
	424	}
	425
	426	int x86_setup_perfctr(struct perf_event *event);
	427
	428	int x86_pmu_hw_config(struct perf_event *event);
	429
	430	void x86_pmu_disable_all(void);
	431
	432	static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
	433	u64 enable_mask)
	434	{
1018faa6 JR	435	u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
1018faa6 JR	436
de0428a7 KW	437	if (hwc->extra_reg.reg)
de0428a7 KW	438	wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
1018faa6	439	wrmsrl(hwc->config_base, (hwc->config \| enable_mask) & ~disable_mask);
de0428a7 KW	440	}
	441
	442	void x86_pmu_enable_all(int added);
	443
	444	int x86_schedule_events(struct cpu_hw_events cpuc, int n, int assign);
	445
	446	void x86_pmu_stop(struct perf_event *event, int flags);
	447
	448	static inline void x86_pmu_disable_event(struct perf_event *event)
	449	{
	450	struct hw_perf_event *hwc = &event->hw;
	451
	452	wrmsrl(hwc->config_base, hwc->config);
	453	}
	454
	455	void x86_pmu_enable_event(struct perf_event *event);
	456
	457	int x86_pmu_handle_irq(struct pt_regs *regs);
	458
	459	extern struct event_constraint emptyconstraint;
	460
	461	extern struct event_constraint unconstrained;
	462
3e702ff6 SE	463	static inline bool kernel_ip(unsigned long ip)
	464	{
	465	#ifdef CONFIG_X86_32
	466	return ip > PAGE_OFFSET;
	467	#else
	468	return (long)ip < 0;
	469	#endif
	470	}
	471
de0428a7 KW	472	#ifdef CONFIG_CPU_SUP_AMD
	473
	474	int amd_pmu_init(void);
	475
	476	#else /* CONFIG_CPU_SUP_AMD */
	477
	478	static inline int amd_pmu_init(void)
	479	{
	480	return 0;
	481	}
	482
	483	#endif /* CONFIG_CPU_SUP_AMD */
	484
	485	#ifdef CONFIG_CPU_SUP_INTEL
	486
	487	int intel_pmu_save_and_restart(struct perf_event *event);
	488
	489	struct event_constraint *
	490	x86_get_event_constraints(struct cpu_hw_events cpuc, struct perf_event event);
	491
	492	struct intel_shared_regs *allocate_shared_regs(int cpu);
	493
	494	int intel_pmu_init(void);
	495
	496	void init_debug_store_on_cpu(int cpu);
	497
	498	void fini_debug_store_on_cpu(int cpu);
	499
	500	void release_ds_buffers(void);
	501
	502	void reserve_ds_buffers(void);
	503
	504	extern struct event_constraint bts_constraint;
	505
	506	void intel_pmu_enable_bts(u64 config);
	507
	508	void intel_pmu_disable_bts(void);
	509
	510	int intel_pmu_drain_bts_buffer(void);
	511
	512	extern struct event_constraint intel_core2_pebs_event_constraints[];
	513
	514	extern struct event_constraint intel_atom_pebs_event_constraints[];
	515
	516	extern struct event_constraint intel_nehalem_pebs_event_constraints[];
	517
	518	extern struct event_constraint intel_westmere_pebs_event_constraints[];
	519
	520	extern struct event_constraint intel_snb_pebs_event_constraints[];
	521
	522	struct event_constraint intel_pebs_constraints(struct perf_event event);
	523
	524	void intel_pmu_pebs_enable(struct perf_event *event);
	525
	526	void intel_pmu_pebs_disable(struct perf_event *event);
	527
	528	void intel_pmu_pebs_enable_all(void);
	529
	530	void intel_pmu_pebs_disable_all(void);
	531
	532	void intel_ds_init(void);
	533
	534	void intel_pmu_lbr_reset(void);
	535
536	void intel_pmu_lbr_enable(struct perf_event *event);
537
538	void intel_pmu_lbr_disable(struct perf_event *event);
539
540	void intel_pmu_lbr_enable_all(void);
541
542	void intel_pmu_lbr_disable_all(void);
543
544	void intel_pmu_lbr_read(void);
545
546	void intel_pmu_lbr_init_core(void);
547
548	void intel_pmu_lbr_init_nhm(void);
549
550	void intel_pmu_lbr_init_atom(void);
551
c5cc2cd9 SE	552	void intel_pmu_lbr_init_snb(void);
c5cc2cd9 SE	553
60ce0fbd SE	554	int intel_pmu_setup_lbr_filter(struct perf_event *event);
60ce0fbd SE	555
de0428a7 KW	556	int p4_pmu_init(void);
	557
	558	int p6_pmu_init(void);
	559
	560	#else /* CONFIG_CPU_SUP_INTEL */
	561
	562	static inline void reserve_ds_buffers(void)
	563	{
	564	}
	565
	566	static inline void release_ds_buffers(void)
	567	{
	568	}
	569
	570	static inline int intel_pmu_init(void)
	571	{
	572	return 0;
	573	}
	574
	575	static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
	576	{
	577	return NULL;
	578	}
	579
	580	#endif /* CONFIG_CPU_SUP_INTEL */