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Commit | Line | Data |
---|---|---|
a7e3ed1e | 1 | /* |
efc9f05d SE |
2 | * Per core/cpu state |
3 | * | |
4 | * Used to coordinate shared registers between HT threads or | |
5 | * among events on a single PMU. | |
a7e3ed1e | 6 | */ |
de0428a7 KW |
7 | |
8 | #include <linux/stddef.h> | |
9 | #include <linux/types.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/slab.h> | |
69c60c88 | 12 | #include <linux/export.h> |
de0428a7 KW |
13 | |
14 | #include <asm/hardirq.h> | |
15 | #include <asm/apic.h> | |
16 | ||
17 | #include "perf_event.h" | |
a7e3ed1e | 18 | |
f22f54f4 | 19 | /* |
b622d644 | 20 | * Intel PerfMon, used on Core and later. |
f22f54f4 | 21 | */ |
ec75a716 | 22 | static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = |
f22f54f4 PZ |
23 | { |
24 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, | |
25 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
26 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
27 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
28 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
29 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
30 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
9c1497ea | 31 | [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ |
f22f54f4 PZ |
32 | }; |
33 | ||
5c543e3c | 34 | static struct event_constraint intel_core_event_constraints[] __read_mostly = |
f22f54f4 PZ |
35 | { |
36 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
37 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
38 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
39 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
40 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
41 | INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ | |
42 | EVENT_CONSTRAINT_END | |
43 | }; | |
44 | ||
5c543e3c | 45 | static struct event_constraint intel_core2_event_constraints[] __read_mostly = |
f22f54f4 | 46 | { |
b622d644 PZ |
47 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
48 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 49 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
50 | INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ |
51 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
52 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
53 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
54 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
55 | INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ | |
56 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
57 | INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ | |
b622d644 | 58 | INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ |
f22f54f4 PZ |
59 | INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ |
60 | EVENT_CONSTRAINT_END | |
61 | }; | |
62 | ||
5c543e3c | 63 | static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = |
f22f54f4 | 64 | { |
b622d644 PZ |
65 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
66 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 67 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
68 | INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ |
69 | INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ | |
70 | INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ | |
71 | INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ | |
72 | INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ | |
73 | INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ | |
74 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ | |
75 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
76 | EVENT_CONSTRAINT_END | |
77 | }; | |
78 | ||
5c543e3c | 79 | static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = |
a7e3ed1e | 80 | { |
efc9f05d | 81 | INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), |
a7e3ed1e AK |
82 | EVENT_EXTRA_END |
83 | }; | |
84 | ||
5c543e3c | 85 | static struct event_constraint intel_westmere_event_constraints[] __read_mostly = |
f22f54f4 | 86 | { |
b622d644 PZ |
87 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
88 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 89 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
90 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ |
91 | INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ | |
92 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
d1100770 | 93 | INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ |
f22f54f4 PZ |
94 | EVENT_CONSTRAINT_END |
95 | }; | |
96 | ||
5c543e3c | 97 | static struct event_constraint intel_snb_event_constraints[] __read_mostly = |
b06b3d49 LM |
98 | { |
99 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
100 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 101 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
b06b3d49 | 102 | INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ |
b06b3d49 LM |
103 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ |
104 | INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ | |
105 | EVENT_CONSTRAINT_END | |
106 | }; | |
107 | ||
5c543e3c | 108 | static struct extra_reg intel_westmere_extra_regs[] __read_mostly = |
a7e3ed1e | 109 | { |
efc9f05d SE |
110 | INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), |
111 | INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), | |
a7e3ed1e AK |
112 | EVENT_EXTRA_END |
113 | }; | |
114 | ||
0af3ac1f AK |
115 | static struct event_constraint intel_v1_event_constraints[] __read_mostly = |
116 | { | |
117 | EVENT_CONSTRAINT_END | |
118 | }; | |
119 | ||
5c543e3c | 120 | static struct event_constraint intel_gen_event_constraints[] __read_mostly = |
f22f54f4 | 121 | { |
b622d644 PZ |
122 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
123 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 124 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
125 | EVENT_CONSTRAINT_END |
126 | }; | |
127 | ||
ee89cbc2 SE |
128 | static struct extra_reg intel_snb_extra_regs[] __read_mostly = { |
129 | INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), | |
130 | INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), | |
131 | EVENT_EXTRA_END | |
132 | }; | |
133 | ||
f22f54f4 PZ |
134 | static u64 intel_pmu_event_map(int hw_event) |
135 | { | |
136 | return intel_perfmon_event_map[hw_event]; | |
137 | } | |
138 | ||
b06b3d49 LM |
139 | static __initconst const u64 snb_hw_cache_event_ids |
140 | [PERF_COUNT_HW_CACHE_MAX] | |
141 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
142 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
143 | { | |
144 | [ C(L1D) ] = { | |
145 | [ C(OP_READ) ] = { | |
146 | [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ | |
147 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ | |
148 | }, | |
149 | [ C(OP_WRITE) ] = { | |
150 | [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ | |
151 | [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ | |
152 | }, | |
153 | [ C(OP_PREFETCH) ] = { | |
154 | [ C(RESULT_ACCESS) ] = 0x0, | |
155 | [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ | |
156 | }, | |
157 | }, | |
158 | [ C(L1I ) ] = { | |
159 | [ C(OP_READ) ] = { | |
160 | [ C(RESULT_ACCESS) ] = 0x0, | |
161 | [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ | |
162 | }, | |
163 | [ C(OP_WRITE) ] = { | |
164 | [ C(RESULT_ACCESS) ] = -1, | |
165 | [ C(RESULT_MISS) ] = -1, | |
166 | }, | |
167 | [ C(OP_PREFETCH) ] = { | |
168 | [ C(RESULT_ACCESS) ] = 0x0, | |
169 | [ C(RESULT_MISS) ] = 0x0, | |
170 | }, | |
171 | }, | |
172 | [ C(LL ) ] = { | |
b06b3d49 | 173 | [ C(OP_READ) ] = { |
63b6a675 | 174 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
b06b3d49 | 175 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
176 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ |
177 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
178 | }, |
179 | [ C(OP_WRITE) ] = { | |
63b6a675 | 180 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
b06b3d49 | 181 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
182 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ |
183 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
184 | }, |
185 | [ C(OP_PREFETCH) ] = { | |
63b6a675 | 186 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
b06b3d49 | 187 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
188 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ |
189 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
190 | }, |
191 | }, | |
192 | [ C(DTLB) ] = { | |
193 | [ C(OP_READ) ] = { | |
194 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ | |
195 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ | |
196 | }, | |
197 | [ C(OP_WRITE) ] = { | |
198 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ | |
199 | [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ | |
200 | }, | |
201 | [ C(OP_PREFETCH) ] = { | |
202 | [ C(RESULT_ACCESS) ] = 0x0, | |
203 | [ C(RESULT_MISS) ] = 0x0, | |
204 | }, | |
205 | }, | |
206 | [ C(ITLB) ] = { | |
207 | [ C(OP_READ) ] = { | |
208 | [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ | |
209 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ | |
210 | }, | |
211 | [ C(OP_WRITE) ] = { | |
212 | [ C(RESULT_ACCESS) ] = -1, | |
213 | [ C(RESULT_MISS) ] = -1, | |
214 | }, | |
215 | [ C(OP_PREFETCH) ] = { | |
216 | [ C(RESULT_ACCESS) ] = -1, | |
217 | [ C(RESULT_MISS) ] = -1, | |
218 | }, | |
219 | }, | |
220 | [ C(BPU ) ] = { | |
221 | [ C(OP_READ) ] = { | |
222 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
223 | [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
224 | }, | |
225 | [ C(OP_WRITE) ] = { | |
226 | [ C(RESULT_ACCESS) ] = -1, | |
227 | [ C(RESULT_MISS) ] = -1, | |
228 | }, | |
229 | [ C(OP_PREFETCH) ] = { | |
230 | [ C(RESULT_ACCESS) ] = -1, | |
231 | [ C(RESULT_MISS) ] = -1, | |
232 | }, | |
233 | }, | |
89d6c0b5 PZ |
234 | [ C(NODE) ] = { |
235 | [ C(OP_READ) ] = { | |
236 | [ C(RESULT_ACCESS) ] = -1, | |
237 | [ C(RESULT_MISS) ] = -1, | |
238 | }, | |
239 | [ C(OP_WRITE) ] = { | |
240 | [ C(RESULT_ACCESS) ] = -1, | |
241 | [ C(RESULT_MISS) ] = -1, | |
242 | }, | |
243 | [ C(OP_PREFETCH) ] = { | |
244 | [ C(RESULT_ACCESS) ] = -1, | |
245 | [ C(RESULT_MISS) ] = -1, | |
246 | }, | |
247 | }, | |
248 | ||
b06b3d49 LM |
249 | }; |
250 | ||
caaa8be3 | 251 | static __initconst const u64 westmere_hw_cache_event_ids |
f22f54f4 PZ |
252 | [PERF_COUNT_HW_CACHE_MAX] |
253 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
254 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
255 | { | |
256 | [ C(L1D) ] = { | |
257 | [ C(OP_READ) ] = { | |
258 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
259 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
260 | }, | |
261 | [ C(OP_WRITE) ] = { | |
262 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
263 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
264 | }, | |
265 | [ C(OP_PREFETCH) ] = { | |
266 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
267 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
268 | }, | |
269 | }, | |
270 | [ C(L1I ) ] = { | |
271 | [ C(OP_READ) ] = { | |
272 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
273 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
274 | }, | |
275 | [ C(OP_WRITE) ] = { | |
276 | [ C(RESULT_ACCESS) ] = -1, | |
277 | [ C(RESULT_MISS) ] = -1, | |
278 | }, | |
279 | [ C(OP_PREFETCH) ] = { | |
280 | [ C(RESULT_ACCESS) ] = 0x0, | |
281 | [ C(RESULT_MISS) ] = 0x0, | |
282 | }, | |
283 | }, | |
284 | [ C(LL ) ] = { | |
285 | [ C(OP_READ) ] = { | |
63b6a675 | 286 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
e994d7d2 | 287 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
288 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ |
289 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 | 290 | }, |
e994d7d2 AK |
291 | /* |
292 | * Use RFO, not WRITEBACK, because a write miss would typically occur | |
293 | * on RFO. | |
294 | */ | |
f22f54f4 | 295 | [ C(OP_WRITE) ] = { |
63b6a675 PZ |
296 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
297 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
298 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
e994d7d2 | 299 | [ C(RESULT_MISS) ] = 0x01b7, |
f22f54f4 PZ |
300 | }, |
301 | [ C(OP_PREFETCH) ] = { | |
63b6a675 | 302 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
e994d7d2 | 303 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
304 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ |
305 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
306 | }, |
307 | }, | |
308 | [ C(DTLB) ] = { | |
309 | [ C(OP_READ) ] = { | |
310 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
311 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
312 | }, | |
313 | [ C(OP_WRITE) ] = { | |
314 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
315 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
316 | }, | |
317 | [ C(OP_PREFETCH) ] = { | |
318 | [ C(RESULT_ACCESS) ] = 0x0, | |
319 | [ C(RESULT_MISS) ] = 0x0, | |
320 | }, | |
321 | }, | |
322 | [ C(ITLB) ] = { | |
323 | [ C(OP_READ) ] = { | |
324 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
325 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ | |
326 | }, | |
327 | [ C(OP_WRITE) ] = { | |
328 | [ C(RESULT_ACCESS) ] = -1, | |
329 | [ C(RESULT_MISS) ] = -1, | |
330 | }, | |
331 | [ C(OP_PREFETCH) ] = { | |
332 | [ C(RESULT_ACCESS) ] = -1, | |
333 | [ C(RESULT_MISS) ] = -1, | |
334 | }, | |
335 | }, | |
336 | [ C(BPU ) ] = { | |
337 | [ C(OP_READ) ] = { | |
338 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
339 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
340 | }, | |
341 | [ C(OP_WRITE) ] = { | |
342 | [ C(RESULT_ACCESS) ] = -1, | |
343 | [ C(RESULT_MISS) ] = -1, | |
344 | }, | |
345 | [ C(OP_PREFETCH) ] = { | |
346 | [ C(RESULT_ACCESS) ] = -1, | |
347 | [ C(RESULT_MISS) ] = -1, | |
348 | }, | |
349 | }, | |
89d6c0b5 PZ |
350 | [ C(NODE) ] = { |
351 | [ C(OP_READ) ] = { | |
352 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
353 | [ C(RESULT_MISS) ] = 0x01b7, | |
354 | }, | |
355 | [ C(OP_WRITE) ] = { | |
356 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
357 | [ C(RESULT_MISS) ] = 0x01b7, | |
358 | }, | |
359 | [ C(OP_PREFETCH) ] = { | |
360 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
361 | [ C(RESULT_MISS) ] = 0x01b7, | |
362 | }, | |
363 | }, | |
f22f54f4 PZ |
364 | }; |
365 | ||
e994d7d2 | 366 | /* |
63b6a675 PZ |
367 | * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; |
368 | * See IA32 SDM Vol 3B 30.6.1.3 | |
e994d7d2 AK |
369 | */ |
370 | ||
63b6a675 PZ |
371 | #define NHM_DMND_DATA_RD (1 << 0) |
372 | #define NHM_DMND_RFO (1 << 1) | |
373 | #define NHM_DMND_IFETCH (1 << 2) | |
374 | #define NHM_DMND_WB (1 << 3) | |
375 | #define NHM_PF_DATA_RD (1 << 4) | |
376 | #define NHM_PF_DATA_RFO (1 << 5) | |
377 | #define NHM_PF_IFETCH (1 << 6) | |
378 | #define NHM_OFFCORE_OTHER (1 << 7) | |
379 | #define NHM_UNCORE_HIT (1 << 8) | |
380 | #define NHM_OTHER_CORE_HIT_SNP (1 << 9) | |
381 | #define NHM_OTHER_CORE_HITM (1 << 10) | |
382 | /* reserved */ | |
383 | #define NHM_REMOTE_CACHE_FWD (1 << 12) | |
384 | #define NHM_REMOTE_DRAM (1 << 13) | |
385 | #define NHM_LOCAL_DRAM (1 << 14) | |
386 | #define NHM_NON_DRAM (1 << 15) | |
387 | ||
87e24f4b PZ |
388 | #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) |
389 | #define NHM_REMOTE (NHM_REMOTE_DRAM) | |
63b6a675 PZ |
390 | |
391 | #define NHM_DMND_READ (NHM_DMND_DATA_RD) | |
392 | #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) | |
393 | #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) | |
394 | ||
395 | #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) | |
87e24f4b | 396 | #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) |
63b6a675 | 397 | #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) |
e994d7d2 AK |
398 | |
399 | static __initconst const u64 nehalem_hw_cache_extra_regs | |
400 | [PERF_COUNT_HW_CACHE_MAX] | |
401 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
402 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
403 | { | |
404 | [ C(LL ) ] = { | |
405 | [ C(OP_READ) ] = { | |
63b6a675 PZ |
406 | [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, |
407 | [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, | |
e994d7d2 AK |
408 | }, |
409 | [ C(OP_WRITE) ] = { | |
63b6a675 PZ |
410 | [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, |
411 | [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, | |
e994d7d2 AK |
412 | }, |
413 | [ C(OP_PREFETCH) ] = { | |
63b6a675 PZ |
414 | [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, |
415 | [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, | |
e994d7d2 | 416 | }, |
89d6c0b5 PZ |
417 | }, |
418 | [ C(NODE) ] = { | |
419 | [ C(OP_READ) ] = { | |
87e24f4b PZ |
420 | [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, |
421 | [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, | |
89d6c0b5 PZ |
422 | }, |
423 | [ C(OP_WRITE) ] = { | |
87e24f4b PZ |
424 | [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, |
425 | [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, | |
89d6c0b5 PZ |
426 | }, |
427 | [ C(OP_PREFETCH) ] = { | |
87e24f4b PZ |
428 | [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, |
429 | [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, | |
89d6c0b5 PZ |
430 | }, |
431 | }, | |
e994d7d2 AK |
432 | }; |
433 | ||
caaa8be3 | 434 | static __initconst const u64 nehalem_hw_cache_event_ids |
f22f54f4 PZ |
435 | [PERF_COUNT_HW_CACHE_MAX] |
436 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
437 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
438 | { | |
439 | [ C(L1D) ] = { | |
440 | [ C(OP_READ) ] = { | |
f4929bd3 PZ |
441 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ |
442 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
f22f54f4 PZ |
443 | }, |
444 | [ C(OP_WRITE) ] = { | |
f4929bd3 PZ |
445 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ |
446 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
f22f54f4 PZ |
447 | }, |
448 | [ C(OP_PREFETCH) ] = { | |
449 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
450 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
451 | }, | |
452 | }, | |
453 | [ C(L1I ) ] = { | |
454 | [ C(OP_READ) ] = { | |
455 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
456 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
457 | }, | |
458 | [ C(OP_WRITE) ] = { | |
459 | [ C(RESULT_ACCESS) ] = -1, | |
460 | [ C(RESULT_MISS) ] = -1, | |
461 | }, | |
462 | [ C(OP_PREFETCH) ] = { | |
463 | [ C(RESULT_ACCESS) ] = 0x0, | |
464 | [ C(RESULT_MISS) ] = 0x0, | |
465 | }, | |
466 | }, | |
467 | [ C(LL ) ] = { | |
468 | [ C(OP_READ) ] = { | |
e994d7d2 AK |
469 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
470 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
471 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ | |
472 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 | 473 | }, |
e994d7d2 AK |
474 | /* |
475 | * Use RFO, not WRITEBACK, because a write miss would typically occur | |
476 | * on RFO. | |
477 | */ | |
f22f54f4 | 478 | [ C(OP_WRITE) ] = { |
e994d7d2 AK |
479 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
480 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
481 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
482 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
483 | }, |
484 | [ C(OP_PREFETCH) ] = { | |
e994d7d2 AK |
485 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
486 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
487 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ | |
488 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
489 | }, |
490 | }, | |
491 | [ C(DTLB) ] = { | |
492 | [ C(OP_READ) ] = { | |
493 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
494 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
495 | }, | |
496 | [ C(OP_WRITE) ] = { | |
497 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
498 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
499 | }, | |
500 | [ C(OP_PREFETCH) ] = { | |
501 | [ C(RESULT_ACCESS) ] = 0x0, | |
502 | [ C(RESULT_MISS) ] = 0x0, | |
503 | }, | |
504 | }, | |
505 | [ C(ITLB) ] = { | |
506 | [ C(OP_READ) ] = { | |
507 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
508 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ | |
509 | }, | |
510 | [ C(OP_WRITE) ] = { | |
511 | [ C(RESULT_ACCESS) ] = -1, | |
512 | [ C(RESULT_MISS) ] = -1, | |
513 | }, | |
514 | [ C(OP_PREFETCH) ] = { | |
515 | [ C(RESULT_ACCESS) ] = -1, | |
516 | [ C(RESULT_MISS) ] = -1, | |
517 | }, | |
518 | }, | |
519 | [ C(BPU ) ] = { | |
520 | [ C(OP_READ) ] = { | |
521 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
522 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
523 | }, | |
524 | [ C(OP_WRITE) ] = { | |
525 | [ C(RESULT_ACCESS) ] = -1, | |
526 | [ C(RESULT_MISS) ] = -1, | |
527 | }, | |
528 | [ C(OP_PREFETCH) ] = { | |
529 | [ C(RESULT_ACCESS) ] = -1, | |
530 | [ C(RESULT_MISS) ] = -1, | |
531 | }, | |
532 | }, | |
89d6c0b5 PZ |
533 | [ C(NODE) ] = { |
534 | [ C(OP_READ) ] = { | |
535 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
536 | [ C(RESULT_MISS) ] = 0x01b7, | |
537 | }, | |
538 | [ C(OP_WRITE) ] = { | |
539 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
540 | [ C(RESULT_MISS) ] = 0x01b7, | |
541 | }, | |
542 | [ C(OP_PREFETCH) ] = { | |
543 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
544 | [ C(RESULT_MISS) ] = 0x01b7, | |
545 | }, | |
546 | }, | |
f22f54f4 PZ |
547 | }; |
548 | ||
caaa8be3 | 549 | static __initconst const u64 core2_hw_cache_event_ids |
f22f54f4 PZ |
550 | [PERF_COUNT_HW_CACHE_MAX] |
551 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
552 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
553 | { | |
554 | [ C(L1D) ] = { | |
555 | [ C(OP_READ) ] = { | |
556 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
557 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
558 | }, | |
559 | [ C(OP_WRITE) ] = { | |
560 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
561 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
562 | }, | |
563 | [ C(OP_PREFETCH) ] = { | |
564 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
565 | [ C(RESULT_MISS) ] = 0, | |
566 | }, | |
567 | }, | |
568 | [ C(L1I ) ] = { | |
569 | [ C(OP_READ) ] = { | |
570 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
571 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
572 | }, | |
573 | [ C(OP_WRITE) ] = { | |
574 | [ C(RESULT_ACCESS) ] = -1, | |
575 | [ C(RESULT_MISS) ] = -1, | |
576 | }, | |
577 | [ C(OP_PREFETCH) ] = { | |
578 | [ C(RESULT_ACCESS) ] = 0, | |
579 | [ C(RESULT_MISS) ] = 0, | |
580 | }, | |
581 | }, | |
582 | [ C(LL ) ] = { | |
583 | [ C(OP_READ) ] = { | |
584 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
585 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
586 | }, | |
587 | [ C(OP_WRITE) ] = { | |
588 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
589 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
590 | }, | |
591 | [ C(OP_PREFETCH) ] = { | |
592 | [ C(RESULT_ACCESS) ] = 0, | |
593 | [ C(RESULT_MISS) ] = 0, | |
594 | }, | |
595 | }, | |
596 | [ C(DTLB) ] = { | |
597 | [ C(OP_READ) ] = { | |
598 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
599 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
600 | }, | |
601 | [ C(OP_WRITE) ] = { | |
602 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
603 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
604 | }, | |
605 | [ C(OP_PREFETCH) ] = { | |
606 | [ C(RESULT_ACCESS) ] = 0, | |
607 | [ C(RESULT_MISS) ] = 0, | |
608 | }, | |
609 | }, | |
610 | [ C(ITLB) ] = { | |
611 | [ C(OP_READ) ] = { | |
612 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
613 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
614 | }, | |
615 | [ C(OP_WRITE) ] = { | |
616 | [ C(RESULT_ACCESS) ] = -1, | |
617 | [ C(RESULT_MISS) ] = -1, | |
618 | }, | |
619 | [ C(OP_PREFETCH) ] = { | |
620 | [ C(RESULT_ACCESS) ] = -1, | |
621 | [ C(RESULT_MISS) ] = -1, | |
622 | }, | |
623 | }, | |
624 | [ C(BPU ) ] = { | |
625 | [ C(OP_READ) ] = { | |
626 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
627 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
628 | }, | |
629 | [ C(OP_WRITE) ] = { | |
630 | [ C(RESULT_ACCESS) ] = -1, | |
631 | [ C(RESULT_MISS) ] = -1, | |
632 | }, | |
633 | [ C(OP_PREFETCH) ] = { | |
634 | [ C(RESULT_ACCESS) ] = -1, | |
635 | [ C(RESULT_MISS) ] = -1, | |
636 | }, | |
637 | }, | |
638 | }; | |
639 | ||
caaa8be3 | 640 | static __initconst const u64 atom_hw_cache_event_ids |
f22f54f4 PZ |
641 | [PERF_COUNT_HW_CACHE_MAX] |
642 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
643 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
644 | { | |
645 | [ C(L1D) ] = { | |
646 | [ C(OP_READ) ] = { | |
647 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
648 | [ C(RESULT_MISS) ] = 0, | |
649 | }, | |
650 | [ C(OP_WRITE) ] = { | |
651 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ | |
652 | [ C(RESULT_MISS) ] = 0, | |
653 | }, | |
654 | [ C(OP_PREFETCH) ] = { | |
655 | [ C(RESULT_ACCESS) ] = 0x0, | |
656 | [ C(RESULT_MISS) ] = 0, | |
657 | }, | |
658 | }, | |
659 | [ C(L1I ) ] = { | |
660 | [ C(OP_READ) ] = { | |
661 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
662 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
663 | }, | |
664 | [ C(OP_WRITE) ] = { | |
665 | [ C(RESULT_ACCESS) ] = -1, | |
666 | [ C(RESULT_MISS) ] = -1, | |
667 | }, | |
668 | [ C(OP_PREFETCH) ] = { | |
669 | [ C(RESULT_ACCESS) ] = 0, | |
670 | [ C(RESULT_MISS) ] = 0, | |
671 | }, | |
672 | }, | |
673 | [ C(LL ) ] = { | |
674 | [ C(OP_READ) ] = { | |
675 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
676 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
677 | }, | |
678 | [ C(OP_WRITE) ] = { | |
679 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
680 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
681 | }, | |
682 | [ C(OP_PREFETCH) ] = { | |
683 | [ C(RESULT_ACCESS) ] = 0, | |
684 | [ C(RESULT_MISS) ] = 0, | |
685 | }, | |
686 | }, | |
687 | [ C(DTLB) ] = { | |
688 | [ C(OP_READ) ] = { | |
689 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ | |
690 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ | |
691 | }, | |
692 | [ C(OP_WRITE) ] = { | |
693 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ | |
694 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ | |
695 | }, | |
696 | [ C(OP_PREFETCH) ] = { | |
697 | [ C(RESULT_ACCESS) ] = 0, | |
698 | [ C(RESULT_MISS) ] = 0, | |
699 | }, | |
700 | }, | |
701 | [ C(ITLB) ] = { | |
702 | [ C(OP_READ) ] = { | |
703 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
704 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
705 | }, | |
706 | [ C(OP_WRITE) ] = { | |
707 | [ C(RESULT_ACCESS) ] = -1, | |
708 | [ C(RESULT_MISS) ] = -1, | |
709 | }, | |
710 | [ C(OP_PREFETCH) ] = { | |
711 | [ C(RESULT_ACCESS) ] = -1, | |
712 | [ C(RESULT_MISS) ] = -1, | |
713 | }, | |
714 | }, | |
715 | [ C(BPU ) ] = { | |
716 | [ C(OP_READ) ] = { | |
717 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
718 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
719 | }, | |
720 | [ C(OP_WRITE) ] = { | |
721 | [ C(RESULT_ACCESS) ] = -1, | |
722 | [ C(RESULT_MISS) ] = -1, | |
723 | }, | |
724 | [ C(OP_PREFETCH) ] = { | |
725 | [ C(RESULT_ACCESS) ] = -1, | |
726 | [ C(RESULT_MISS) ] = -1, | |
727 | }, | |
728 | }, | |
729 | }; | |
730 | ||
60ce0fbd SE |
731 | static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event) |
732 | { | |
733 | /* user explicitly requested branch sampling */ | |
734 | if (has_branch_stack(event)) | |
735 | return true; | |
736 | ||
737 | /* implicit branch sampling to correct PEBS skid */ | |
738 | if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1) | |
739 | return true; | |
740 | ||
741 | return false; | |
742 | } | |
743 | ||
f22f54f4 PZ |
744 | static void intel_pmu_disable_all(void) |
745 | { | |
746 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
747 | ||
748 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
749 | ||
750 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) | |
751 | intel_pmu_disable_bts(); | |
ca037701 PZ |
752 | |
753 | intel_pmu_pebs_disable_all(); | |
caff2bef | 754 | intel_pmu_lbr_disable_all(); |
f22f54f4 PZ |
755 | } |
756 | ||
11164cd4 | 757 | static void intel_pmu_enable_all(int added) |
f22f54f4 PZ |
758 | { |
759 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
760 | ||
d329527e PZ |
761 | intel_pmu_pebs_enable_all(); |
762 | intel_pmu_lbr_enable_all(); | |
144d31e6 GN |
763 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, |
764 | x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); | |
f22f54f4 PZ |
765 | |
766 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { | |
767 | struct perf_event *event = | |
768 | cpuc->events[X86_PMC_IDX_FIXED_BTS]; | |
769 | ||
770 | if (WARN_ON_ONCE(!event)) | |
771 | return; | |
772 | ||
773 | intel_pmu_enable_bts(event->hw.config); | |
774 | } | |
775 | } | |
776 | ||
11164cd4 PZ |
777 | /* |
778 | * Workaround for: | |
779 | * Intel Errata AAK100 (model 26) | |
780 | * Intel Errata AAP53 (model 30) | |
40b91cd1 | 781 | * Intel Errata BD53 (model 44) |
11164cd4 | 782 | * |
351af072 ZY |
783 | * The official story: |
784 | * These chips need to be 'reset' when adding counters by programming the | |
785 | * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either | |
786 | * in sequence on the same PMC or on different PMCs. | |
787 | * | |
788 | * In practise it appears some of these events do in fact count, and | |
789 | * we need to programm all 4 events. | |
11164cd4 | 790 | */ |
351af072 | 791 | static void intel_pmu_nhm_workaround(void) |
11164cd4 | 792 | { |
351af072 ZY |
793 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
794 | static const unsigned long nhm_magic[4] = { | |
795 | 0x4300B5, | |
796 | 0x4300D2, | |
797 | 0x4300B1, | |
798 | 0x4300B1 | |
799 | }; | |
800 | struct perf_event *event; | |
801 | int i; | |
11164cd4 | 802 | |
351af072 ZY |
803 | /* |
804 | * The Errata requires below steps: | |
805 | * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; | |
806 | * 2) Configure 4 PERFEVTSELx with the magic events and clear | |
807 | * the corresponding PMCx; | |
808 | * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; | |
809 | * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; | |
810 | * 5) Clear 4 pairs of ERFEVTSELx and PMCx; | |
811 | */ | |
11164cd4 | 812 | |
351af072 ZY |
813 | /* |
814 | * The real steps we choose are a little different from above. | |
815 | * A) To reduce MSR operations, we don't run step 1) as they | |
816 | * are already cleared before this function is called; | |
817 | * B) Call x86_perf_event_update to save PMCx before configuring | |
818 | * PERFEVTSELx with magic number; | |
819 | * C) With step 5), we do clear only when the PERFEVTSELx is | |
820 | * not used currently. | |
821 | * D) Call x86_perf_event_set_period to restore PMCx; | |
822 | */ | |
11164cd4 | 823 | |
351af072 ZY |
824 | /* We always operate 4 pairs of PERF Counters */ |
825 | for (i = 0; i < 4; i++) { | |
826 | event = cpuc->events[i]; | |
827 | if (event) | |
828 | x86_perf_event_update(event); | |
829 | } | |
11164cd4 | 830 | |
351af072 ZY |
831 | for (i = 0; i < 4; i++) { |
832 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); | |
833 | wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); | |
834 | } | |
835 | ||
836 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); | |
837 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); | |
11164cd4 | 838 | |
351af072 ZY |
839 | for (i = 0; i < 4; i++) { |
840 | event = cpuc->events[i]; | |
841 | ||
842 | if (event) { | |
843 | x86_perf_event_set_period(event); | |
31fa58af | 844 | __x86_pmu_enable_event(&event->hw, |
351af072 ZY |
845 | ARCH_PERFMON_EVENTSEL_ENABLE); |
846 | } else | |
847 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); | |
11164cd4 | 848 | } |
351af072 ZY |
849 | } |
850 | ||
851 | static void intel_pmu_nhm_enable_all(int added) | |
852 | { | |
853 | if (added) | |
854 | intel_pmu_nhm_workaround(); | |
11164cd4 PZ |
855 | intel_pmu_enable_all(added); |
856 | } | |
857 | ||
f22f54f4 PZ |
858 | static inline u64 intel_pmu_get_status(void) |
859 | { | |
860 | u64 status; | |
861 | ||
862 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
863 | ||
864 | return status; | |
865 | } | |
866 | ||
867 | static inline void intel_pmu_ack_status(u64 ack) | |
868 | { | |
869 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
870 | } | |
871 | ||
ca037701 | 872 | static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) |
f22f54f4 | 873 | { |
aff3d91a | 874 | int idx = hwc->idx - X86_PMC_IDX_FIXED; |
f22f54f4 PZ |
875 | u64 ctrl_val, mask; |
876 | ||
877 | mask = 0xfULL << (idx * 4); | |
878 | ||
879 | rdmsrl(hwc->config_base, ctrl_val); | |
880 | ctrl_val &= ~mask; | |
7645a24c | 881 | wrmsrl(hwc->config_base, ctrl_val); |
f22f54f4 PZ |
882 | } |
883 | ||
ca037701 | 884 | static void intel_pmu_disable_event(struct perf_event *event) |
f22f54f4 | 885 | { |
aff3d91a | 886 | struct hw_perf_event *hwc = &event->hw; |
144d31e6 | 887 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
aff3d91a PZ |
888 | |
889 | if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) { | |
f22f54f4 PZ |
890 | intel_pmu_disable_bts(); |
891 | intel_pmu_drain_bts_buffer(); | |
892 | return; | |
893 | } | |
894 | ||
144d31e6 GN |
895 | cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); |
896 | cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); | |
897 | ||
60ce0fbd SE |
898 | /* |
899 | * must disable before any actual event | |
900 | * because any event may be combined with LBR | |
901 | */ | |
902 | if (intel_pmu_needs_lbr_smpl(event)) | |
903 | intel_pmu_lbr_disable(event); | |
904 | ||
f22f54f4 | 905 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
aff3d91a | 906 | intel_pmu_disable_fixed(hwc); |
f22f54f4 PZ |
907 | return; |
908 | } | |
909 | ||
aff3d91a | 910 | x86_pmu_disable_event(event); |
ca037701 | 911 | |
ab608344 | 912 | if (unlikely(event->attr.precise_ip)) |
ef21f683 | 913 | intel_pmu_pebs_disable(event); |
f22f54f4 PZ |
914 | } |
915 | ||
ca037701 | 916 | static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) |
f22f54f4 | 917 | { |
aff3d91a | 918 | int idx = hwc->idx - X86_PMC_IDX_FIXED; |
f22f54f4 | 919 | u64 ctrl_val, bits, mask; |
f22f54f4 PZ |
920 | |
921 | /* | |
922 | * Enable IRQ generation (0x8), | |
923 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
924 | * if requested: | |
925 | */ | |
926 | bits = 0x8ULL; | |
927 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
928 | bits |= 0x2; | |
929 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) | |
930 | bits |= 0x1; | |
931 | ||
932 | /* | |
933 | * ANY bit is supported in v3 and up | |
934 | */ | |
935 | if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) | |
936 | bits |= 0x4; | |
937 | ||
938 | bits <<= (idx * 4); | |
939 | mask = 0xfULL << (idx * 4); | |
940 | ||
941 | rdmsrl(hwc->config_base, ctrl_val); | |
942 | ctrl_val &= ~mask; | |
943 | ctrl_val |= bits; | |
7645a24c | 944 | wrmsrl(hwc->config_base, ctrl_val); |
f22f54f4 PZ |
945 | } |
946 | ||
aff3d91a | 947 | static void intel_pmu_enable_event(struct perf_event *event) |
f22f54f4 | 948 | { |
aff3d91a | 949 | struct hw_perf_event *hwc = &event->hw; |
144d31e6 | 950 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
aff3d91a PZ |
951 | |
952 | if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) { | |
0a3aee0d | 953 | if (!__this_cpu_read(cpu_hw_events.enabled)) |
f22f54f4 PZ |
954 | return; |
955 | ||
956 | intel_pmu_enable_bts(hwc->config); | |
957 | return; | |
958 | } | |
60ce0fbd SE |
959 | /* |
960 | * must enabled before any actual event | |
961 | * because any event may be combined with LBR | |
962 | */ | |
963 | if (intel_pmu_needs_lbr_smpl(event)) | |
964 | intel_pmu_lbr_enable(event); | |
f22f54f4 | 965 | |
144d31e6 GN |
966 | if (event->attr.exclude_host) |
967 | cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); | |
968 | if (event->attr.exclude_guest) | |
969 | cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); | |
970 | ||
f22f54f4 | 971 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
aff3d91a | 972 | intel_pmu_enable_fixed(hwc); |
f22f54f4 PZ |
973 | return; |
974 | } | |
975 | ||
ab608344 | 976 | if (unlikely(event->attr.precise_ip)) |
ef21f683 | 977 | intel_pmu_pebs_enable(event); |
ca037701 | 978 | |
31fa58af | 979 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f22f54f4 PZ |
980 | } |
981 | ||
982 | /* | |
983 | * Save and restart an expired event. Called by NMI contexts, | |
984 | * so it has to be careful about preempting normal event ops: | |
985 | */ | |
de0428a7 | 986 | int intel_pmu_save_and_restart(struct perf_event *event) |
f22f54f4 | 987 | { |
cc2ad4ba PZ |
988 | x86_perf_event_update(event); |
989 | return x86_perf_event_set_period(event); | |
f22f54f4 PZ |
990 | } |
991 | ||
992 | static void intel_pmu_reset(void) | |
993 | { | |
0a3aee0d | 994 | struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); |
f22f54f4 PZ |
995 | unsigned long flags; |
996 | int idx; | |
997 | ||
948b1bb8 | 998 | if (!x86_pmu.num_counters) |
f22f54f4 PZ |
999 | return; |
1000 | ||
1001 | local_irq_save(flags); | |
1002 | ||
1003 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); | |
1004 | ||
948b1bb8 | 1005 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1006 | checking_wrmsrl(x86_pmu_config_addr(idx), 0ull); |
1007 | checking_wrmsrl(x86_pmu_event_addr(idx), 0ull); | |
f22f54f4 | 1008 | } |
948b1bb8 | 1009 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) |
f22f54f4 | 1010 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); |
948b1bb8 | 1011 | |
f22f54f4 PZ |
1012 | if (ds) |
1013 | ds->bts_index = ds->bts_buffer_base; | |
1014 | ||
1015 | local_irq_restore(flags); | |
1016 | } | |
1017 | ||
1018 | /* | |
1019 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
1020 | * rules apply: | |
1021 | */ | |
1022 | static int intel_pmu_handle_irq(struct pt_regs *regs) | |
1023 | { | |
1024 | struct perf_sample_data data; | |
1025 | struct cpu_hw_events *cpuc; | |
1026 | int bit, loops; | |
2e556b5b | 1027 | u64 status; |
b0b2072d | 1028 | int handled; |
f22f54f4 | 1029 | |
dc1d628a | 1030 | perf_sample_data_init(&data, 0); |
f22f54f4 PZ |
1031 | |
1032 | cpuc = &__get_cpu_var(cpu_hw_events); | |
1033 | ||
2bce5dac DZ |
1034 | /* |
1035 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1036 | * inside the nmi handler. As a result, the unmasking was pushed | |
1037 | * into all the nmi handlers. | |
1038 | * | |
1039 | * This handler doesn't seem to have any issues with the unmasking | |
1040 | * so it was left at the top. | |
1041 | */ | |
1042 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1043 | ||
3fb2b8dd | 1044 | intel_pmu_disable_all(); |
b0b2072d | 1045 | handled = intel_pmu_drain_bts_buffer(); |
f22f54f4 PZ |
1046 | status = intel_pmu_get_status(); |
1047 | if (!status) { | |
11164cd4 | 1048 | intel_pmu_enable_all(0); |
b0b2072d | 1049 | return handled; |
f22f54f4 PZ |
1050 | } |
1051 | ||
1052 | loops = 0; | |
1053 | again: | |
2e556b5b | 1054 | intel_pmu_ack_status(status); |
f22f54f4 PZ |
1055 | if (++loops > 100) { |
1056 | WARN_ONCE(1, "perfevents: irq loop stuck!\n"); | |
1057 | perf_event_print_debug(); | |
1058 | intel_pmu_reset(); | |
3fb2b8dd | 1059 | goto done; |
f22f54f4 PZ |
1060 | } |
1061 | ||
1062 | inc_irq_stat(apic_perf_irqs); | |
ca037701 | 1063 | |
caff2bef PZ |
1064 | intel_pmu_lbr_read(); |
1065 | ||
ca037701 PZ |
1066 | /* |
1067 | * PEBS overflow sets bit 62 in the global status register | |
1068 | */ | |
de725dec PZ |
1069 | if (__test_and_clear_bit(62, (unsigned long *)&status)) { |
1070 | handled++; | |
ca037701 | 1071 | x86_pmu.drain_pebs(regs); |
de725dec | 1072 | } |
ca037701 | 1073 | |
984b3f57 | 1074 | for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
f22f54f4 PZ |
1075 | struct perf_event *event = cpuc->events[bit]; |
1076 | ||
de725dec PZ |
1077 | handled++; |
1078 | ||
f22f54f4 PZ |
1079 | if (!test_bit(bit, cpuc->active_mask)) |
1080 | continue; | |
1081 | ||
1082 | if (!intel_pmu_save_and_restart(event)) | |
1083 | continue; | |
1084 | ||
1085 | data.period = event->hw.last_period; | |
1086 | ||
60ce0fbd SE |
1087 | if (has_branch_stack(event)) |
1088 | data.br_stack = &cpuc->lbr_stack; | |
1089 | ||
a8b0ca17 | 1090 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1091 | x86_pmu_stop(event, 0); |
f22f54f4 PZ |
1092 | } |
1093 | ||
f22f54f4 PZ |
1094 | /* |
1095 | * Repeat if there is more work to be done: | |
1096 | */ | |
1097 | status = intel_pmu_get_status(); | |
1098 | if (status) | |
1099 | goto again; | |
1100 | ||
3fb2b8dd | 1101 | done: |
11164cd4 | 1102 | intel_pmu_enable_all(0); |
de725dec | 1103 | return handled; |
f22f54f4 PZ |
1104 | } |
1105 | ||
f22f54f4 | 1106 | static struct event_constraint * |
ca037701 | 1107 | intel_bts_constraints(struct perf_event *event) |
f22f54f4 | 1108 | { |
ca037701 PZ |
1109 | struct hw_perf_event *hwc = &event->hw; |
1110 | unsigned int hw_event, bts_event; | |
f22f54f4 | 1111 | |
18a073a3 PZ |
1112 | if (event->attr.freq) |
1113 | return NULL; | |
1114 | ||
ca037701 PZ |
1115 | hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; |
1116 | bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); | |
f22f54f4 | 1117 | |
ca037701 | 1118 | if (unlikely(hw_event == bts_event && hwc->sample_period == 1)) |
f22f54f4 | 1119 | return &bts_constraint; |
ca037701 | 1120 | |
f22f54f4 PZ |
1121 | return NULL; |
1122 | } | |
1123 | ||
b79e8941 PZ |
1124 | static bool intel_try_alt_er(struct perf_event *event, int orig_idx) |
1125 | { | |
1126 | if (!(x86_pmu.er_flags & ERF_HAS_RSP_1)) | |
1127 | return false; | |
1128 | ||
1129 | if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) { | |
1130 | event->hw.config &= ~INTEL_ARCH_EVENT_MASK; | |
1131 | event->hw.config |= 0x01bb; | |
1132 | event->hw.extra_reg.idx = EXTRA_REG_RSP_1; | |
1133 | event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; | |
1134 | } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) { | |
1135 | event->hw.config &= ~INTEL_ARCH_EVENT_MASK; | |
1136 | event->hw.config |= 0x01b7; | |
1137 | event->hw.extra_reg.idx = EXTRA_REG_RSP_0; | |
1138 | event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; | |
1139 | } | |
1140 | ||
1141 | if (event->hw.extra_reg.idx == orig_idx) | |
1142 | return false; | |
1143 | ||
1144 | return true; | |
1145 | } | |
1146 | ||
efc9f05d SE |
1147 | /* |
1148 | * manage allocation of shared extra msr for certain events | |
1149 | * | |
1150 | * sharing can be: | |
1151 | * per-cpu: to be shared between the various events on a single PMU | |
1152 | * per-core: per-cpu + shared by HT threads | |
1153 | */ | |
a7e3ed1e | 1154 | static struct event_constraint * |
efc9f05d | 1155 | __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, |
b36817e8 SE |
1156 | struct perf_event *event, |
1157 | struct hw_perf_event_extra *reg) | |
a7e3ed1e | 1158 | { |
efc9f05d | 1159 | struct event_constraint *c = &emptyconstraint; |
a7e3ed1e | 1160 | struct er_account *era; |
cd8a38d3 | 1161 | unsigned long flags; |
b79e8941 | 1162 | int orig_idx = reg->idx; |
a7e3ed1e | 1163 | |
efc9f05d | 1164 | /* already allocated shared msr */ |
cd8a38d3 | 1165 | if (reg->alloc) |
b36817e8 | 1166 | return NULL; /* call x86_get_event_constraint() */ |
a7e3ed1e | 1167 | |
b79e8941 | 1168 | again: |
efc9f05d | 1169 | era = &cpuc->shared_regs->regs[reg->idx]; |
cd8a38d3 SE |
1170 | /* |
1171 | * we use spin_lock_irqsave() to avoid lockdep issues when | |
1172 | * passing a fake cpuc | |
1173 | */ | |
1174 | raw_spin_lock_irqsave(&era->lock, flags); | |
efc9f05d SE |
1175 | |
1176 | if (!atomic_read(&era->ref) || era->config == reg->config) { | |
1177 | ||
1178 | /* lock in msr value */ | |
1179 | era->config = reg->config; | |
1180 | era->reg = reg->reg; | |
1181 | ||
1182 | /* one more user */ | |
1183 | atomic_inc(&era->ref); | |
1184 | ||
1185 | /* no need to reallocate during incremental event scheduling */ | |
1186 | reg->alloc = 1; | |
a7e3ed1e AK |
1187 | |
1188 | /* | |
b36817e8 SE |
1189 | * need to call x86_get_event_constraint() |
1190 | * to check if associated event has constraints | |
a7e3ed1e | 1191 | */ |
b36817e8 | 1192 | c = NULL; |
b79e8941 | 1193 | } else if (intel_try_alt_er(event, orig_idx)) { |
2e64694d | 1194 | raw_spin_unlock_irqrestore(&era->lock, flags); |
b79e8941 | 1195 | goto again; |
a7e3ed1e | 1196 | } |
cd8a38d3 | 1197 | raw_spin_unlock_irqrestore(&era->lock, flags); |
a7e3ed1e | 1198 | |
efc9f05d SE |
1199 | return c; |
1200 | } | |
1201 | ||
1202 | static void | |
1203 | __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, | |
1204 | struct hw_perf_event_extra *reg) | |
1205 | { | |
1206 | struct er_account *era; | |
1207 | ||
1208 | /* | |
1209 | * only put constraint if extra reg was actually | |
1210 | * allocated. Also takes care of event which do | |
1211 | * not use an extra shared reg | |
1212 | */ | |
1213 | if (!reg->alloc) | |
1214 | return; | |
1215 | ||
1216 | era = &cpuc->shared_regs->regs[reg->idx]; | |
1217 | ||
1218 | /* one fewer user */ | |
1219 | atomic_dec(&era->ref); | |
1220 | ||
1221 | /* allocate again next time */ | |
1222 | reg->alloc = 0; | |
1223 | } | |
1224 | ||
1225 | static struct event_constraint * | |
1226 | intel_shared_regs_constraints(struct cpu_hw_events *cpuc, | |
1227 | struct perf_event *event) | |
1228 | { | |
b36817e8 SE |
1229 | struct event_constraint *c = NULL, *d; |
1230 | struct hw_perf_event_extra *xreg, *breg; | |
1231 | ||
1232 | xreg = &event->hw.extra_reg; | |
1233 | if (xreg->idx != EXTRA_REG_NONE) { | |
1234 | c = __intel_shared_reg_get_constraints(cpuc, event, xreg); | |
1235 | if (c == &emptyconstraint) | |
1236 | return c; | |
1237 | } | |
1238 | breg = &event->hw.branch_reg; | |
1239 | if (breg->idx != EXTRA_REG_NONE) { | |
1240 | d = __intel_shared_reg_get_constraints(cpuc, event, breg); | |
1241 | if (d == &emptyconstraint) { | |
1242 | __intel_shared_reg_put_constraints(cpuc, xreg); | |
1243 | c = d; | |
1244 | } | |
1245 | } | |
efc9f05d | 1246 | return c; |
a7e3ed1e AK |
1247 | } |
1248 | ||
de0428a7 KW |
1249 | struct event_constraint * |
1250 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) | |
1251 | { | |
1252 | struct event_constraint *c; | |
1253 | ||
1254 | if (x86_pmu.event_constraints) { | |
1255 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
1256 | if ((event->hw.config & c->cmask) == c->code) | |
1257 | return c; | |
1258 | } | |
1259 | } | |
1260 | ||
1261 | return &unconstrained; | |
1262 | } | |
1263 | ||
f22f54f4 PZ |
1264 | static struct event_constraint * |
1265 | intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) | |
1266 | { | |
1267 | struct event_constraint *c; | |
1268 | ||
ca037701 PZ |
1269 | c = intel_bts_constraints(event); |
1270 | if (c) | |
1271 | return c; | |
1272 | ||
1273 | c = intel_pebs_constraints(event); | |
f22f54f4 PZ |
1274 | if (c) |
1275 | return c; | |
1276 | ||
efc9f05d | 1277 | c = intel_shared_regs_constraints(cpuc, event); |
a7e3ed1e AK |
1278 | if (c) |
1279 | return c; | |
1280 | ||
f22f54f4 PZ |
1281 | return x86_get_event_constraints(cpuc, event); |
1282 | } | |
1283 | ||
efc9f05d SE |
1284 | static void |
1285 | intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, | |
a7e3ed1e AK |
1286 | struct perf_event *event) |
1287 | { | |
efc9f05d | 1288 | struct hw_perf_event_extra *reg; |
a7e3ed1e | 1289 | |
efc9f05d SE |
1290 | reg = &event->hw.extra_reg; |
1291 | if (reg->idx != EXTRA_REG_NONE) | |
1292 | __intel_shared_reg_put_constraints(cpuc, reg); | |
b36817e8 SE |
1293 | |
1294 | reg = &event->hw.branch_reg; | |
1295 | if (reg->idx != EXTRA_REG_NONE) | |
1296 | __intel_shared_reg_put_constraints(cpuc, reg); | |
efc9f05d | 1297 | } |
a7e3ed1e | 1298 | |
efc9f05d SE |
1299 | static void intel_put_event_constraints(struct cpu_hw_events *cpuc, |
1300 | struct perf_event *event) | |
1301 | { | |
1302 | intel_put_shared_regs_event_constraints(cpuc, event); | |
a7e3ed1e AK |
1303 | } |
1304 | ||
b4cdc5c2 PZ |
1305 | static int intel_pmu_hw_config(struct perf_event *event) |
1306 | { | |
1307 | int ret = x86_pmu_hw_config(event); | |
1308 | ||
1309 | if (ret) | |
1310 | return ret; | |
1311 | ||
7639dae0 PZ |
1312 | if (event->attr.precise_ip && |
1313 | (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { | |
1314 | /* | |
1315 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
1316 | * (0x003c) so that we can use it with PEBS. | |
1317 | * | |
1318 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
1319 | * PEBS capable. However we can use INST_RETIRED.ANY_P | |
1320 | * (0x00c0), which is a PEBS capable event, to get the same | |
1321 | * count. | |
1322 | * | |
1323 | * INST_RETIRED.ANY_P counts the number of cycles that retires | |
1324 | * CNTMASK instructions. By setting CNTMASK to a value (16) | |
1325 | * larger than the maximum number of instructions that can be | |
1326 | * retired per cycle (4) and then inverting the condition, we | |
1327 | * count all cycles that retire 16 or less instructions, which | |
1328 | * is every cycle. | |
1329 | * | |
1330 | * Thereby we gain a PEBS capable cycle counter. | |
1331 | */ | |
f9b4eeb8 PZ |
1332 | u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); |
1333 | ||
7639dae0 PZ |
1334 | |
1335 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); | |
1336 | event->hw.config = alt_config; | |
1337 | } | |
1338 | ||
60ce0fbd SE |
1339 | if (intel_pmu_needs_lbr_smpl(event)) { |
1340 | ret = intel_pmu_setup_lbr_filter(event); | |
1341 | if (ret) | |
1342 | return ret; | |
1343 | } | |
1344 | ||
b4cdc5c2 PZ |
1345 | if (event->attr.type != PERF_TYPE_RAW) |
1346 | return 0; | |
1347 | ||
1348 | if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) | |
1349 | return 0; | |
1350 | ||
1351 | if (x86_pmu.version < 3) | |
1352 | return -EINVAL; | |
1353 | ||
1354 | if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) | |
1355 | return -EACCES; | |
1356 | ||
1357 | event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
144d31e6 GN |
1362 | struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) |
1363 | { | |
1364 | if (x86_pmu.guest_get_msrs) | |
1365 | return x86_pmu.guest_get_msrs(nr); | |
1366 | *nr = 0; | |
1367 | return NULL; | |
1368 | } | |
1369 | EXPORT_SYMBOL_GPL(perf_guest_get_msrs); | |
1370 | ||
1371 | static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) | |
1372 | { | |
1373 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1374 | struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; | |
1375 | ||
1376 | arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; | |
1377 | arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; | |
1378 | arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; | |
1379 | ||
1380 | *nr = 1; | |
1381 | return arr; | |
1382 | } | |
1383 | ||
1384 | static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) | |
1385 | { | |
1386 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1387 | struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; | |
1388 | int idx; | |
1389 | ||
1390 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1391 | struct perf_event *event = cpuc->events[idx]; | |
1392 | ||
1393 | arr[idx].msr = x86_pmu_config_addr(idx); | |
1394 | arr[idx].host = arr[idx].guest = 0; | |
1395 | ||
1396 | if (!test_bit(idx, cpuc->active_mask)) | |
1397 | continue; | |
1398 | ||
1399 | arr[idx].host = arr[idx].guest = | |
1400 | event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; | |
1401 | ||
1402 | if (event->attr.exclude_host) | |
1403 | arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; | |
1404 | else if (event->attr.exclude_guest) | |
1405 | arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; | |
1406 | } | |
1407 | ||
1408 | *nr = x86_pmu.num_counters; | |
1409 | return arr; | |
1410 | } | |
1411 | ||
1412 | static void core_pmu_enable_event(struct perf_event *event) | |
1413 | { | |
1414 | if (!event->attr.exclude_host) | |
1415 | x86_pmu_enable_event(event); | |
1416 | } | |
1417 | ||
1418 | static void core_pmu_enable_all(int added) | |
1419 | { | |
1420 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1421 | int idx; | |
1422 | ||
1423 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1424 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; | |
1425 | ||
1426 | if (!test_bit(idx, cpuc->active_mask) || | |
1427 | cpuc->events[idx]->attr.exclude_host) | |
1428 | continue; | |
1429 | ||
1430 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); | |
1431 | } | |
1432 | } | |
1433 | ||
caaa8be3 | 1434 | static __initconst const struct x86_pmu core_pmu = { |
f22f54f4 PZ |
1435 | .name = "core", |
1436 | .handle_irq = x86_pmu_handle_irq, | |
1437 | .disable_all = x86_pmu_disable_all, | |
144d31e6 GN |
1438 | .enable_all = core_pmu_enable_all, |
1439 | .enable = core_pmu_enable_event, | |
f22f54f4 | 1440 | .disable = x86_pmu_disable_event, |
b4cdc5c2 | 1441 | .hw_config = x86_pmu_hw_config, |
a072738e | 1442 | .schedule_events = x86_schedule_events, |
f22f54f4 PZ |
1443 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
1444 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
1445 | .event_map = intel_pmu_event_map, | |
f22f54f4 PZ |
1446 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
1447 | .apic = 1, | |
1448 | /* | |
1449 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
1450 | * so we install an artificial 1<<31 period regardless of | |
1451 | * the generic event period: | |
1452 | */ | |
1453 | .max_period = (1ULL << 31) - 1, | |
1454 | .get_event_constraints = intel_get_event_constraints, | |
a7e3ed1e | 1455 | .put_event_constraints = intel_put_event_constraints, |
f22f54f4 | 1456 | .event_constraints = intel_core_event_constraints, |
144d31e6 | 1457 | .guest_get_msrs = core_guest_get_msrs, |
f22f54f4 PZ |
1458 | }; |
1459 | ||
de0428a7 | 1460 | struct intel_shared_regs *allocate_shared_regs(int cpu) |
efc9f05d SE |
1461 | { |
1462 | struct intel_shared_regs *regs; | |
1463 | int i; | |
1464 | ||
1465 | regs = kzalloc_node(sizeof(struct intel_shared_regs), | |
1466 | GFP_KERNEL, cpu_to_node(cpu)); | |
1467 | if (regs) { | |
1468 | /* | |
1469 | * initialize the locks to keep lockdep happy | |
1470 | */ | |
1471 | for (i = 0; i < EXTRA_REG_MAX; i++) | |
1472 | raw_spin_lock_init(®s->regs[i].lock); | |
1473 | ||
1474 | regs->core_id = -1; | |
1475 | } | |
1476 | return regs; | |
1477 | } | |
1478 | ||
a7e3ed1e AK |
1479 | static int intel_pmu_cpu_prepare(int cpu) |
1480 | { | |
1481 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
1482 | ||
b36817e8 | 1483 | if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map)) |
69092624 LM |
1484 | return NOTIFY_OK; |
1485 | ||
efc9f05d SE |
1486 | cpuc->shared_regs = allocate_shared_regs(cpu); |
1487 | if (!cpuc->shared_regs) | |
a7e3ed1e AK |
1488 | return NOTIFY_BAD; |
1489 | ||
a7e3ed1e AK |
1490 | return NOTIFY_OK; |
1491 | } | |
1492 | ||
74846d35 PZ |
1493 | static void intel_pmu_cpu_starting(int cpu) |
1494 | { | |
a7e3ed1e AK |
1495 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
1496 | int core_id = topology_core_id(cpu); | |
1497 | int i; | |
1498 | ||
69092624 LM |
1499 | init_debug_store_on_cpu(cpu); |
1500 | /* | |
1501 | * Deal with CPUs that don't clear their LBRs on power-up. | |
1502 | */ | |
1503 | intel_pmu_lbr_reset(); | |
1504 | ||
b36817e8 SE |
1505 | cpuc->lbr_sel = NULL; |
1506 | ||
1507 | if (!cpuc->shared_regs) | |
69092624 LM |
1508 | return; |
1509 | ||
b36817e8 SE |
1510 | if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) { |
1511 | for_each_cpu(i, topology_thread_cpumask(cpu)) { | |
1512 | struct intel_shared_regs *pc; | |
a7e3ed1e | 1513 | |
b36817e8 SE |
1514 | pc = per_cpu(cpu_hw_events, i).shared_regs; |
1515 | if (pc && pc->core_id == core_id) { | |
1516 | cpuc->kfree_on_online = cpuc->shared_regs; | |
1517 | cpuc->shared_regs = pc; | |
1518 | break; | |
1519 | } | |
a7e3ed1e | 1520 | } |
b36817e8 SE |
1521 | cpuc->shared_regs->core_id = core_id; |
1522 | cpuc->shared_regs->refcnt++; | |
a7e3ed1e AK |
1523 | } |
1524 | ||
b36817e8 SE |
1525 | if (x86_pmu.lbr_sel_map) |
1526 | cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; | |
74846d35 PZ |
1527 | } |
1528 | ||
1529 | static void intel_pmu_cpu_dying(int cpu) | |
1530 | { | |
a7e3ed1e | 1531 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
efc9f05d | 1532 | struct intel_shared_regs *pc; |
a7e3ed1e | 1533 | |
efc9f05d | 1534 | pc = cpuc->shared_regs; |
a7e3ed1e AK |
1535 | if (pc) { |
1536 | if (pc->core_id == -1 || --pc->refcnt == 0) | |
1537 | kfree(pc); | |
efc9f05d | 1538 | cpuc->shared_regs = NULL; |
a7e3ed1e AK |
1539 | } |
1540 | ||
74846d35 PZ |
1541 | fini_debug_store_on_cpu(cpu); |
1542 | } | |
1543 | ||
d010b332 SE |
1544 | static void intel_pmu_flush_branch_stack(void) |
1545 | { | |
1546 | /* | |
1547 | * Intel LBR does not tag entries with the | |
1548 | * PID of the current task, then we need to | |
1549 | * flush it on ctxsw | |
1550 | * For now, we simply reset it | |
1551 | */ | |
1552 | if (x86_pmu.lbr_nr) | |
1553 | intel_pmu_lbr_reset(); | |
1554 | } | |
1555 | ||
caaa8be3 | 1556 | static __initconst const struct x86_pmu intel_pmu = { |
f22f54f4 PZ |
1557 | .name = "Intel", |
1558 | .handle_irq = intel_pmu_handle_irq, | |
1559 | .disable_all = intel_pmu_disable_all, | |
1560 | .enable_all = intel_pmu_enable_all, | |
1561 | .enable = intel_pmu_enable_event, | |
1562 | .disable = intel_pmu_disable_event, | |
b4cdc5c2 | 1563 | .hw_config = intel_pmu_hw_config, |
a072738e | 1564 | .schedule_events = x86_schedule_events, |
f22f54f4 PZ |
1565 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
1566 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
1567 | .event_map = intel_pmu_event_map, | |
f22f54f4 PZ |
1568 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
1569 | .apic = 1, | |
1570 | /* | |
1571 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
1572 | * so we install an artificial 1<<31 period regardless of | |
1573 | * the generic event period: | |
1574 | */ | |
1575 | .max_period = (1ULL << 31) - 1, | |
3f6da390 | 1576 | .get_event_constraints = intel_get_event_constraints, |
a7e3ed1e | 1577 | .put_event_constraints = intel_put_event_constraints, |
3f6da390 | 1578 | |
a7e3ed1e | 1579 | .cpu_prepare = intel_pmu_cpu_prepare, |
74846d35 PZ |
1580 | .cpu_starting = intel_pmu_cpu_starting, |
1581 | .cpu_dying = intel_pmu_cpu_dying, | |
144d31e6 | 1582 | .guest_get_msrs = intel_guest_get_msrs, |
d010b332 | 1583 | .flush_branch_stack = intel_pmu_flush_branch_stack, |
f22f54f4 PZ |
1584 | }; |
1585 | ||
c1d6f42f | 1586 | static __init void intel_clovertown_quirk(void) |
3c44780b PZ |
1587 | { |
1588 | /* | |
1589 | * PEBS is unreliable due to: | |
1590 | * | |
1591 | * AJ67 - PEBS may experience CPL leaks | |
1592 | * AJ68 - PEBS PMI may be delayed by one event | |
1593 | * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] | |
1594 | * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS | |
1595 | * | |
1596 | * AJ67 could be worked around by restricting the OS/USR flags. | |
1597 | * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. | |
1598 | * | |
1599 | * AJ106 could possibly be worked around by not allowing LBR | |
1600 | * usage from PEBS, including the fixup. | |
1601 | * AJ68 could possibly be worked around by always programming | |
ec75a716 | 1602 | * a pebs_event_reset[0] value and coping with the lost events. |
3c44780b PZ |
1603 | * |
1604 | * But taken together it might just make sense to not enable PEBS on | |
1605 | * these chips. | |
1606 | */ | |
1607 | printk(KERN_WARNING "PEBS disabled due to CPU errata.\n"); | |
1608 | x86_pmu.pebs = 0; | |
1609 | x86_pmu.pebs_constraints = NULL; | |
1610 | } | |
1611 | ||
c1d6f42f | 1612 | static __init void intel_sandybridge_quirk(void) |
6a600a8b PZ |
1613 | { |
1614 | printk(KERN_WARNING "PEBS disabled due to CPU errata.\n"); | |
1615 | x86_pmu.pebs = 0; | |
1616 | x86_pmu.pebs_constraints = NULL; | |
1617 | } | |
1618 | ||
c1d6f42f PZ |
1619 | static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { |
1620 | { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, | |
1621 | { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, | |
1622 | { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, | |
1623 | { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, | |
1624 | { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, | |
1625 | { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, | |
1626 | { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, | |
ffb871bc GN |
1627 | }; |
1628 | ||
c1d6f42f PZ |
1629 | static __init void intel_arch_events_quirk(void) |
1630 | { | |
1631 | int bit; | |
1632 | ||
1633 | /* disable event that reported as not presend by cpuid */ | |
1634 | for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { | |
1635 | intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; | |
1636 | printk(KERN_WARNING "CPUID marked event: \'%s\' unavailable\n", | |
1637 | intel_arch_events_map[bit].name); | |
1638 | } | |
1639 | } | |
1640 | ||
1641 | static __init void intel_nehalem_quirk(void) | |
1642 | { | |
1643 | union cpuid10_ebx ebx; | |
1644 | ||
1645 | ebx.full = x86_pmu.events_maskl; | |
1646 | if (ebx.split.no_branch_misses_retired) { | |
1647 | /* | |
1648 | * Erratum AAJ80 detected, we work it around by using | |
1649 | * the BR_MISP_EXEC.ANY event. This will over-count | |
1650 | * branch-misses, but it's still much better than the | |
1651 | * architectural event which is often completely bogus: | |
1652 | */ | |
1653 | intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; | |
1654 | ebx.split.no_branch_misses_retired = 0; | |
1655 | x86_pmu.events_maskl = ebx.full; | |
1656 | printk(KERN_INFO "CPU erratum AAJ80 worked around\n"); | |
1657 | } | |
1658 | } | |
1659 | ||
de0428a7 | 1660 | __init int intel_pmu_init(void) |
f22f54f4 PZ |
1661 | { |
1662 | union cpuid10_edx edx; | |
1663 | union cpuid10_eax eax; | |
ffb871bc | 1664 | union cpuid10_ebx ebx; |
f22f54f4 | 1665 | unsigned int unused; |
f22f54f4 PZ |
1666 | int version; |
1667 | ||
1668 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { | |
a072738e CG |
1669 | switch (boot_cpu_data.x86) { |
1670 | case 0x6: | |
1671 | return p6_pmu_init(); | |
1672 | case 0xf: | |
1673 | return p4_pmu_init(); | |
1674 | } | |
f22f54f4 | 1675 | return -ENODEV; |
f22f54f4 PZ |
1676 | } |
1677 | ||
1678 | /* | |
1679 | * Check whether the Architectural PerfMon supports | |
1680 | * Branch Misses Retired hw_event or not. | |
1681 | */ | |
ffb871bc GN |
1682 | cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); |
1683 | if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) | |
f22f54f4 PZ |
1684 | return -ENODEV; |
1685 | ||
1686 | version = eax.split.version_id; | |
1687 | if (version < 2) | |
1688 | x86_pmu = core_pmu; | |
1689 | else | |
1690 | x86_pmu = intel_pmu; | |
1691 | ||
1692 | x86_pmu.version = version; | |
948b1bb8 RR |
1693 | x86_pmu.num_counters = eax.split.num_counters; |
1694 | x86_pmu.cntval_bits = eax.split.bit_width; | |
1695 | x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; | |
f22f54f4 | 1696 | |
c1d6f42f PZ |
1697 | x86_pmu.events_maskl = ebx.full; |
1698 | x86_pmu.events_mask_len = eax.split.mask_length; | |
1699 | ||
f22f54f4 PZ |
1700 | /* |
1701 | * Quirk: v2 perfmon does not report fixed-purpose events, so | |
1702 | * assume at least 3 events: | |
1703 | */ | |
1704 | if (version > 1) | |
948b1bb8 | 1705 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
f22f54f4 | 1706 | |
8db909a7 PZ |
1707 | /* |
1708 | * v2 and above have a perf capabilities MSR | |
1709 | */ | |
1710 | if (version > 1) { | |
1711 | u64 capabilities; | |
1712 | ||
1713 | rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); | |
1714 | x86_pmu.intel_cap.capabilities = capabilities; | |
1715 | } | |
1716 | ||
ca037701 PZ |
1717 | intel_ds_init(); |
1718 | ||
c1d6f42f PZ |
1719 | x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ |
1720 | ||
f22f54f4 PZ |
1721 | /* |
1722 | * Install the hw-cache-events table: | |
1723 | */ | |
1724 | switch (boot_cpu_data.x86_model) { | |
1725 | case 14: /* 65 nm core solo/duo, "Yonah" */ | |
1726 | pr_cont("Core events, "); | |
1727 | break; | |
1728 | ||
1729 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ | |
c1d6f42f | 1730 | x86_add_quirk(intel_clovertown_quirk); |
f22f54f4 PZ |
1731 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ |
1732 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ | |
1733 | case 29: /* six-core 45 nm xeon "Dunnington" */ | |
1734 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, | |
1735 | sizeof(hw_cache_event_ids)); | |
1736 | ||
caff2bef PZ |
1737 | intel_pmu_lbr_init_core(); |
1738 | ||
f22f54f4 | 1739 | x86_pmu.event_constraints = intel_core2_event_constraints; |
17e31629 | 1740 | x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; |
f22f54f4 PZ |
1741 | pr_cont("Core2 events, "); |
1742 | break; | |
1743 | ||
1744 | case 26: /* 45 nm nehalem, "Bloomfield" */ | |
1745 | case 30: /* 45 nm nehalem, "Lynnfield" */ | |
134fbadf | 1746 | case 46: /* 45 nm nehalem-ex, "Beckton" */ |
f22f54f4 PZ |
1747 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, |
1748 | sizeof(hw_cache_event_ids)); | |
e994d7d2 AK |
1749 | memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, |
1750 | sizeof(hw_cache_extra_regs)); | |
f22f54f4 | 1751 | |
caff2bef PZ |
1752 | intel_pmu_lbr_init_nhm(); |
1753 | ||
f22f54f4 | 1754 | x86_pmu.event_constraints = intel_nehalem_event_constraints; |
17e31629 | 1755 | x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; |
11164cd4 | 1756 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; |
a7e3ed1e | 1757 | x86_pmu.extra_regs = intel_nehalem_extra_regs; |
ec75a716 | 1758 | |
91fc4cc0 | 1759 | /* UOPS_ISSUED.STALLED_CYCLES */ |
f9b4eeb8 PZ |
1760 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
1761 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
91fc4cc0 | 1762 | /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ |
f9b4eeb8 PZ |
1763 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
1764 | X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); | |
94403f88 | 1765 | |
c1d6f42f | 1766 | x86_add_quirk(intel_nehalem_quirk); |
ec75a716 | 1767 | |
11164cd4 | 1768 | pr_cont("Nehalem events, "); |
f22f54f4 | 1769 | break; |
caff2bef | 1770 | |
b622d644 | 1771 | case 28: /* Atom */ |
f22f54f4 PZ |
1772 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, |
1773 | sizeof(hw_cache_event_ids)); | |
1774 | ||
caff2bef PZ |
1775 | intel_pmu_lbr_init_atom(); |
1776 | ||
f22f54f4 | 1777 | x86_pmu.event_constraints = intel_gen_event_constraints; |
17e31629 | 1778 | x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; |
f22f54f4 PZ |
1779 | pr_cont("Atom events, "); |
1780 | break; | |
1781 | ||
1782 | case 37: /* 32 nm nehalem, "Clarkdale" */ | |
1783 | case 44: /* 32 nm nehalem, "Gulftown" */ | |
b2508e82 | 1784 | case 47: /* 32 nm Xeon E7 */ |
f22f54f4 PZ |
1785 | memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, |
1786 | sizeof(hw_cache_event_ids)); | |
e994d7d2 AK |
1787 | memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, |
1788 | sizeof(hw_cache_extra_regs)); | |
f22f54f4 | 1789 | |
caff2bef PZ |
1790 | intel_pmu_lbr_init_nhm(); |
1791 | ||
f22f54f4 | 1792 | x86_pmu.event_constraints = intel_westmere_event_constraints; |
40b91cd1 | 1793 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; |
17e31629 | 1794 | x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; |
a7e3ed1e | 1795 | x86_pmu.extra_regs = intel_westmere_extra_regs; |
b79e8941 | 1796 | x86_pmu.er_flags |= ERF_HAS_RSP_1; |
30112039 IM |
1797 | |
1798 | /* UOPS_ISSUED.STALLED_CYCLES */ | |
f9b4eeb8 PZ |
1799 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
1800 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
30112039 | 1801 | /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ |
f9b4eeb8 PZ |
1802 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
1803 | X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); | |
30112039 | 1804 | |
f22f54f4 PZ |
1805 | pr_cont("Westmere events, "); |
1806 | break; | |
b622d644 | 1807 | |
b06b3d49 | 1808 | case 42: /* SandyBridge */ |
c1d6f42f | 1809 | x86_add_quirk(intel_sandybridge_quirk); |
a34668f6 | 1810 | case 45: /* SandyBridge, "Romely-EP" */ |
b06b3d49 LM |
1811 | memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, |
1812 | sizeof(hw_cache_event_ids)); | |
1813 | ||
c5cc2cd9 | 1814 | intel_pmu_lbr_init_snb(); |
b06b3d49 LM |
1815 | |
1816 | x86_pmu.event_constraints = intel_snb_event_constraints; | |
de0428a7 | 1817 | x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; |
ee89cbc2 SE |
1818 | x86_pmu.extra_regs = intel_snb_extra_regs; |
1819 | /* all extra regs are per-cpu when HT is on */ | |
b79e8941 PZ |
1820 | x86_pmu.er_flags |= ERF_HAS_RSP_1; |
1821 | x86_pmu.er_flags |= ERF_NO_HT_SHARING; | |
e04d1b23 LM |
1822 | |
1823 | /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ | |
f9b4eeb8 PZ |
1824 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
1825 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
e04d1b23 | 1826 | /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ |
f9b4eeb8 PZ |
1827 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
1828 | X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); | |
e04d1b23 | 1829 | |
b06b3d49 LM |
1830 | pr_cont("SandyBridge events, "); |
1831 | break; | |
1832 | ||
f22f54f4 | 1833 | default: |
0af3ac1f AK |
1834 | switch (x86_pmu.version) { |
1835 | case 1: | |
1836 | x86_pmu.event_constraints = intel_v1_event_constraints; | |
1837 | pr_cont("generic architected perfmon v1, "); | |
1838 | break; | |
1839 | default: | |
1840 | /* | |
1841 | * default constraints for v2 and up | |
1842 | */ | |
1843 | x86_pmu.event_constraints = intel_gen_event_constraints; | |
1844 | pr_cont("generic architected perfmon, "); | |
1845 | break; | |
1846 | } | |
f22f54f4 | 1847 | } |
ffb871bc | 1848 | |
f22f54f4 PZ |
1849 | return 0; |
1850 | } |