]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/x86/kernel/cpu/perf_event_intel.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
perf_events: Fix validation of events using an extra reg
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
f22f54f4
PZ		 1#ifdef CONFIG_CPU_SUP_INTEL
2
a7e3ed1e 3/*
efc9f05d
SE		 4 * Per core/cpu state
5 *
6 * Used to coordinate shared registers between HT threads or
7 * among events on a single PMU.
a7e3ed1e 8 */
efc9f05d
SE		 9struct intel_shared_regs {
10 struct er_account regs[EXTRA_REG_MAX];
11 int refcnt; /* per-core: #HT threads */
12 unsigned core_id; /* per-core: core id */
a7e3ed1e
AK		 13};
14
f22f54f4 15/*
b622d644 16 * Intel PerfMon, used on Core and later.
f22f54f4 17 */
ec75a716 18static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4
PZ		 19{
20 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
21 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
22 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
23 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
24 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
25 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
26 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
27};
28
5c543e3c 29static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 30{
31 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
32 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
33 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
34 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
35 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
36 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
37 EVENT_CONSTRAINT_END
38};
39
5c543e3c 40static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 41{
b622d644
PZ		 42 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
43 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
44 /*
45 * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
46 * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
47 * ratio between these counters.
48 */
49 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 50 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
51 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
52 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
53 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
54 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
55 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
56 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
57 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 58 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 59 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
60 EVENT_CONSTRAINT_END
61};
62
5c543e3c 63static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 64{
b622d644
PZ		 65 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
66 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
67 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 68 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
69 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
70 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
71 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
72 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
73 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
74 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
75 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
76 EVENT_CONSTRAINT_END
77};
78
5c543e3c 79static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 80{
efc9f05d 81 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
a7e3ed1e
AK		 82 EVENT_EXTRA_END
83};
84
5c543e3c 85static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 86{
b622d644
PZ		 87 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
88 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
89 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 90 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
91 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
92 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 93 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 94 EVENT_CONSTRAINT_END
95};
96
5c543e3c 97static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 98{
99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
101 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
102 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
103 INTEL_EVENT_CONSTRAINT(0xb7, 0x1), /* OFF_CORE_RESPONSE_0 */
104 INTEL_EVENT_CONSTRAINT(0xbb, 0x8), /* OFF_CORE_RESPONSE_1 */
105 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
106 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
107 EVENT_CONSTRAINT_END
108};
109
5c543e3c 110static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 111{
efc9f05d
SE		 112 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
113 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
a7e3ed1e
AK		 114 EVENT_EXTRA_END
115};
116
5c543e3c 117static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 118{
b622d644
PZ		 119 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
120 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
121 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 122 EVENT_CONSTRAINT_END
123};
124
125static u64 intel_pmu_event_map(int hw_event)
126{
127 return intel_perfmon_event_map[hw_event];
128}
129
b06b3d49
LM		 130static __initconst const u64 snb_hw_cache_event_ids
131 [PERF_COUNT_HW_CACHE_MAX]
132 [PERF_COUNT_HW_CACHE_OP_MAX]
133 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
134{
135 [ C(L1D) ] = {
136 [ C(OP_READ) ] = {
137 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
138 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
139 },
140 [ C(OP_WRITE) ] = {
141 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
142 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
143 },
144 [ C(OP_PREFETCH) ] = {
145 [ C(RESULT_ACCESS) ] = 0x0,
146 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
147 },
148 },
149 [ C(L1I ) ] = {
150 [ C(OP_READ) ] = {
151 [ C(RESULT_ACCESS) ] = 0x0,
152 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
153 },
154 [ C(OP_WRITE) ] = {
155 [ C(RESULT_ACCESS) ] = -1,
156 [ C(RESULT_MISS) ] = -1,
157 },
158 [ C(OP_PREFETCH) ] = {
159 [ C(RESULT_ACCESS) ] = 0x0,
160 [ C(RESULT_MISS) ] = 0x0,
161 },
162 },
163 [ C(LL ) ] = {
b06b3d49 164 [ C(OP_READ) ] = {
63b6a675 165 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 166 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 167 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
168 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 169 },
170 [ C(OP_WRITE) ] = {
63b6a675 171 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 172 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 173 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
174 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 175 },
176 [ C(OP_PREFETCH) ] = {
63b6a675 177 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 178 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 179 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
180 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 181 },
182 },
183 [ C(DTLB) ] = {
184 [ C(OP_READ) ] = {
185 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
186 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
187 },
188 [ C(OP_WRITE) ] = {
189 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
190 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
191 },
192 [ C(OP_PREFETCH) ] = {
193 [ C(RESULT_ACCESS) ] = 0x0,
194 [ C(RESULT_MISS) ] = 0x0,
195 },
196 },
197 [ C(ITLB) ] = {
198 [ C(OP_READ) ] = {
199 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
200 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
201 },
202 [ C(OP_WRITE) ] = {
203 [ C(RESULT_ACCESS) ] = -1,
204 [ C(RESULT_MISS) ] = -1,
205 },
206 [ C(OP_PREFETCH) ] = {
207 [ C(RESULT_ACCESS) ] = -1,
208 [ C(RESULT_MISS) ] = -1,
209 },
210 },
211 [ C(BPU ) ] = {
212 [ C(OP_READ) ] = {
213 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
214 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
215 },
216 [ C(OP_WRITE) ] = {
217 [ C(RESULT_ACCESS) ] = -1,
218 [ C(RESULT_MISS) ] = -1,
219 },
220 [ C(OP_PREFETCH) ] = {
221 [ C(RESULT_ACCESS) ] = -1,
222 [ C(RESULT_MISS) ] = -1,
223 },
224 },
225};
226
caaa8be3 227static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 228 [PERF_COUNT_HW_CACHE_MAX]
229 [PERF_COUNT_HW_CACHE_OP_MAX]
230 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
231{
232 [ C(L1D) ] = {
233 [ C(OP_READ) ] = {
234 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
235 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
236 },
237 [ C(OP_WRITE) ] = {
238 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
239 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
240 },
241 [ C(OP_PREFETCH) ] = {
242 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
243 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
244 },
245 },
246 [ C(L1I ) ] = {
247 [ C(OP_READ) ] = {
248 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
249 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
250 },
251 [ C(OP_WRITE) ] = {
252 [ C(RESULT_ACCESS) ] = -1,
253 [ C(RESULT_MISS) ] = -1,
254 },
255 [ C(OP_PREFETCH) ] = {
256 [ C(RESULT_ACCESS) ] = 0x0,
257 [ C(RESULT_MISS) ] = 0x0,
258 },
259 },
260 [ C(LL ) ] = {
261 [ C(OP_READ) ] = {
63b6a675 262 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 263 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 264 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
265 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 266 },
e994d7d2
AK		 267 /*
268 * Use RFO, not WRITEBACK, because a write miss would typically occur
269 * on RFO.
270 */
f22f54f4 271 [ C(OP_WRITE) ] = {
63b6a675
PZ		 272 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
273 [ C(RESULT_ACCESS) ] = 0x01b7,
274 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 275 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 276 },
277 [ C(OP_PREFETCH) ] = {
63b6a675 278 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 279 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 280 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
281 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 282 },
283 },
284 [ C(DTLB) ] = {
285 [ C(OP_READ) ] = {
286 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
287 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
288 },
289 [ C(OP_WRITE) ] = {
290 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
291 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
292 },
293 [ C(OP_PREFETCH) ] = {
294 [ C(RESULT_ACCESS) ] = 0x0,
295 [ C(RESULT_MISS) ] = 0x0,
296 },
297 },
298 [ C(ITLB) ] = {
299 [ C(OP_READ) ] = {
300 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
301 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
302 },
303 [ C(OP_WRITE) ] = {
304 [ C(RESULT_ACCESS) ] = -1,
305 [ C(RESULT_MISS) ] = -1,
306 },
307 [ C(OP_PREFETCH) ] = {
308 [ C(RESULT_ACCESS) ] = -1,
309 [ C(RESULT_MISS) ] = -1,
310 },
311 },
312 [ C(BPU ) ] = {
313 [ C(OP_READ) ] = {
314 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
315 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
316 },
317 [ C(OP_WRITE) ] = {
318 [ C(RESULT_ACCESS) ] = -1,
319 [ C(RESULT_MISS) ] = -1,
320 },
321 [ C(OP_PREFETCH) ] = {
322 [ C(RESULT_ACCESS) ] = -1,
323 [ C(RESULT_MISS) ] = -1,
324 },
325 },
326};
327
e994d7d2 328/*
63b6a675
PZ		 329 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
330 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 331 */
332
63b6a675
PZ		 333#define NHM_DMND_DATA_RD (1 << 0)
334#define NHM_DMND_RFO (1 << 1)
335#define NHM_DMND_IFETCH (1 << 2)
336#define NHM_DMND_WB (1 << 3)
337#define NHM_PF_DATA_RD (1 << 4)
338#define NHM_PF_DATA_RFO (1 << 5)
339#define NHM_PF_IFETCH (1 << 6)
340#define NHM_OFFCORE_OTHER (1 << 7)
341#define NHM_UNCORE_HIT (1 << 8)
342#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
343#define NHM_OTHER_CORE_HITM (1 << 10)
344 /* reserved */
345#define NHM_REMOTE_CACHE_FWD (1 << 12)
346#define NHM_REMOTE_DRAM (1 << 13)
347#define NHM_LOCAL_DRAM (1 << 14)
348#define NHM_NON_DRAM (1 << 15)
349
350#define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
351
352#define NHM_DMND_READ (NHM_DMND_DATA_RD)
353#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
354#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
355
356#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
357#define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
358#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 359
360static __initconst const u64 nehalem_hw_cache_extra_regs
361 [PERF_COUNT_HW_CACHE_MAX]
362 [PERF_COUNT_HW_CACHE_OP_MAX]
363 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
364{
365 [ C(LL ) ] = {
366 [ C(OP_READ) ] = {
63b6a675
PZ		 367 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
368 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 369 },
370 [ C(OP_WRITE) ] = {
63b6a675
PZ		 371 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
372 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 373 },
374 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 375 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
376 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2
AK		 377 },
378 }
379};
380
caaa8be3 381static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 382 [PERF_COUNT_HW_CACHE_MAX]
383 [PERF_COUNT_HW_CACHE_OP_MAX]
384 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
385{
386 [ C(L1D) ] = {
387 [ C(OP_READ) ] = {
f4929bd3
PZ		 388 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
389 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 390 },
391 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 392 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
393 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 394 },
395 [ C(OP_PREFETCH) ] = {
396 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
397 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
398 },
399 },
400 [ C(L1I ) ] = {
401 [ C(OP_READ) ] = {
402 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
403 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
404 },
405 [ C(OP_WRITE) ] = {
406 [ C(RESULT_ACCESS) ] = -1,
407 [ C(RESULT_MISS) ] = -1,
408 },
409 [ C(OP_PREFETCH) ] = {
410 [ C(RESULT_ACCESS) ] = 0x0,
411 [ C(RESULT_MISS) ] = 0x0,
412 },
413 },
414 [ C(LL ) ] = {
415 [ C(OP_READ) ] = {
e994d7d2
AK		 416 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
417 [ C(RESULT_ACCESS) ] = 0x01b7,
418 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
419 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 420 },
e994d7d2
AK		 421 /*
422 * Use RFO, not WRITEBACK, because a write miss would typically occur
423 * on RFO.
424 */
f22f54f4 425 [ C(OP_WRITE) ] = {
e994d7d2
AK		 426 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
427 [ C(RESULT_ACCESS) ] = 0x01b7,
428 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
429 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 430 },
431 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 432 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
433 [ C(RESULT_ACCESS) ] = 0x01b7,
434 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
435 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 436 },
437 },
438 [ C(DTLB) ] = {
439 [ C(OP_READ) ] = {
440 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
441 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
442 },
443 [ C(OP_WRITE) ] = {
444 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
445 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
446 },
447 [ C(OP_PREFETCH) ] = {
448 [ C(RESULT_ACCESS) ] = 0x0,
449 [ C(RESULT_MISS) ] = 0x0,
450 },
451 },
452 [ C(ITLB) ] = {
453 [ C(OP_READ) ] = {
454 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
455 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
456 },
457 [ C(OP_WRITE) ] = {
458 [ C(RESULT_ACCESS) ] = -1,
459 [ C(RESULT_MISS) ] = -1,
460 },
461 [ C(OP_PREFETCH) ] = {
462 [ C(RESULT_ACCESS) ] = -1,
463 [ C(RESULT_MISS) ] = -1,
464 },
465 },
466 [ C(BPU ) ] = {
467 [ C(OP_READ) ] = {
468 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
469 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
470 },
471 [ C(OP_WRITE) ] = {
472 [ C(RESULT_ACCESS) ] = -1,
473 [ C(RESULT_MISS) ] = -1,
474 },
475 [ C(OP_PREFETCH) ] = {
476 [ C(RESULT_ACCESS) ] = -1,
477 [ C(RESULT_MISS) ] = -1,
478 },
479 },
480};
481
caaa8be3 482static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 483 [PERF_COUNT_HW_CACHE_MAX]
484 [PERF_COUNT_HW_CACHE_OP_MAX]
485 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
486{
487 [ C(L1D) ] = {
488 [ C(OP_READ) ] = {
489 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
490 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
491 },
492 [ C(OP_WRITE) ] = {
493 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
494 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
495 },
496 [ C(OP_PREFETCH) ] = {
497 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
498 [ C(RESULT_MISS) ] = 0,
499 },
500 },
501 [ C(L1I ) ] = {
502 [ C(OP_READ) ] = {
503 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
504 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
505 },
506 [ C(OP_WRITE) ] = {
507 [ C(RESULT_ACCESS) ] = -1,
508 [ C(RESULT_MISS) ] = -1,
509 },
510 [ C(OP_PREFETCH) ] = {
511 [ C(RESULT_ACCESS) ] = 0,
512 [ C(RESULT_MISS) ] = 0,
513 },
514 },
515 [ C(LL ) ] = {
516 [ C(OP_READ) ] = {
517 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
518 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
519 },
520 [ C(OP_WRITE) ] = {
521 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
522 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
523 },
524 [ C(OP_PREFETCH) ] = {
525 [ C(RESULT_ACCESS) ] = 0,
526 [ C(RESULT_MISS) ] = 0,
527 },
528 },
529 [ C(DTLB) ] = {
530 [ C(OP_READ) ] = {
531 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
532 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
533 },
534 [ C(OP_WRITE) ] = {
535 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
536 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
537 },
538 [ C(OP_PREFETCH) ] = {
539 [ C(RESULT_ACCESS) ] = 0,
540 [ C(RESULT_MISS) ] = 0,
541 },
542 },
543 [ C(ITLB) ] = {
544 [ C(OP_READ) ] = {
545 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
546 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
547 },
548 [ C(OP_WRITE) ] = {
549 [ C(RESULT_ACCESS) ] = -1,
550 [ C(RESULT_MISS) ] = -1,
551 },
552 [ C(OP_PREFETCH) ] = {
553 [ C(RESULT_ACCESS) ] = -1,
554 [ C(RESULT_MISS) ] = -1,
555 },
556 },
557 [ C(BPU ) ] = {
558 [ C(OP_READ) ] = {
559 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
560 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
561 },
562 [ C(OP_WRITE) ] = {
563 [ C(RESULT_ACCESS) ] = -1,
564 [ C(RESULT_MISS) ] = -1,
565 },
566 [ C(OP_PREFETCH) ] = {
567 [ C(RESULT_ACCESS) ] = -1,
568 [ C(RESULT_MISS) ] = -1,
569 },
570 },
571};
572
caaa8be3 573static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 574 [PERF_COUNT_HW_CACHE_MAX]
575 [PERF_COUNT_HW_CACHE_OP_MAX]
576 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
577{
578 [ C(L1D) ] = {
579 [ C(OP_READ) ] = {
580 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
581 [ C(RESULT_MISS) ] = 0,
582 },
583 [ C(OP_WRITE) ] = {
584 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
585 [ C(RESULT_MISS) ] = 0,
586 },
587 [ C(OP_PREFETCH) ] = {
588 [ C(RESULT_ACCESS) ] = 0x0,
589 [ C(RESULT_MISS) ] = 0,
590 },
591 },
592 [ C(L1I ) ] = {
593 [ C(OP_READ) ] = {
594 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
595 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
596 },
597 [ C(OP_WRITE) ] = {
598 [ C(RESULT_ACCESS) ] = -1,
599 [ C(RESULT_MISS) ] = -1,
600 },
601 [ C(OP_PREFETCH) ] = {
602 [ C(RESULT_ACCESS) ] = 0,
603 [ C(RESULT_MISS) ] = 0,
604 },
605 },
606 [ C(LL ) ] = {
607 [ C(OP_READ) ] = {
608 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
609 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
610 },
611 [ C(OP_WRITE) ] = {
612 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
613 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
614 },
615 [ C(OP_PREFETCH) ] = {
616 [ C(RESULT_ACCESS) ] = 0,
617 [ C(RESULT_MISS) ] = 0,
618 },
619 },
620 [ C(DTLB) ] = {
621 [ C(OP_READ) ] = {
622 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
623 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
624 },
625 [ C(OP_WRITE) ] = {
626 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
627 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
628 },
629 [ C(OP_PREFETCH) ] = {
630 [ C(RESULT_ACCESS) ] = 0,
631 [ C(RESULT_MISS) ] = 0,
632 },
633 },
634 [ C(ITLB) ] = {
635 [ C(OP_READ) ] = {
636 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
637 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
638 },
639 [ C(OP_WRITE) ] = {
640 [ C(RESULT_ACCESS) ] = -1,
641 [ C(RESULT_MISS) ] = -1,
642 },
643 [ C(OP_PREFETCH) ] = {
644 [ C(RESULT_ACCESS) ] = -1,
645 [ C(RESULT_MISS) ] = -1,
646 },
647 },
648 [ C(BPU ) ] = {
649 [ C(OP_READ) ] = {
650 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
651 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
652 },
653 [ C(OP_WRITE) ] = {
654 [ C(RESULT_ACCESS) ] = -1,
655 [ C(RESULT_MISS) ] = -1,
656 },
657 [ C(OP_PREFETCH) ] = {
658 [ C(RESULT_ACCESS) ] = -1,
659 [ C(RESULT_MISS) ] = -1,
660 },
661 },
662};
663
f22f54f4
PZ		 664static void intel_pmu_disable_all(void)
665{
666 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
667
668 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
669
670 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
671 intel_pmu_disable_bts();
ca037701
PZ		 672
673 intel_pmu_pebs_disable_all();
caff2bef 674 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 675}
676
11164cd4 677static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 678{
679 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
680
d329527e
PZ		 681 intel_pmu_pebs_enable_all();
682 intel_pmu_lbr_enable_all();
f22f54f4
PZ		 683 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
684
685 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
686 struct perf_event *event =
687 cpuc->events[X86_PMC_IDX_FIXED_BTS];
688
689 if (WARN_ON_ONCE(!event))
690 return;
691
692 intel_pmu_enable_bts(event->hw.config);
693 }
694}
695
11164cd4
PZ		 696/*
697 * Workaround for:
698 * Intel Errata AAK100 (model 26)
699 * Intel Errata AAP53 (model 30)
40b91cd1 700 * Intel Errata BD53 (model 44)
11164cd4 701 *
351af072
ZY		 702 * The official story:
703 * These chips need to be 'reset' when adding counters by programming the
704 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
705 * in sequence on the same PMC or on different PMCs.
706 *
707 * In practise it appears some of these events do in fact count, and
708 * we need to programm all 4 events.
11164cd4 709 */
351af072 710static void intel_pmu_nhm_workaround(void)
11164cd4 711{
351af072
ZY		 712 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
713 static const unsigned long nhm_magic[4] = {
714 0x4300B5,
715 0x4300D2,
716 0x4300B1,
717 0x4300B1
718 };
719 struct perf_event *event;
720 int i;
11164cd4 721
351af072
ZY		 722 /*
723 * The Errata requires below steps:
724 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
725 * 2) Configure 4 PERFEVTSELx with the magic events and clear
726 * the corresponding PMCx;
727 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
728 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
729 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
730 */
11164cd4 731
351af072
ZY		 732 /*
733 * The real steps we choose are a little different from above.
734 * A) To reduce MSR operations, we don't run step 1) as they
735 * are already cleared before this function is called;
736 * B) Call x86_perf_event_update to save PMCx before configuring
737 * PERFEVTSELx with magic number;
738 * C) With step 5), we do clear only when the PERFEVTSELx is
739 * not used currently.
740 * D) Call x86_perf_event_set_period to restore PMCx;
741 */
11164cd4 742
351af072
ZY		 743 /* We always operate 4 pairs of PERF Counters */
744 for (i = 0; i < 4; i++) {
745 event = cpuc->events[i];
746 if (event)
747 x86_perf_event_update(event);
748 }
11164cd4 749
351af072
ZY		 750 for (i = 0; i < 4; i++) {
751 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
752 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
753 }
754
755 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
756 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 757
351af072
ZY		 758 for (i = 0; i < 4; i++) {
759 event = cpuc->events[i];
760
761 if (event) {
762 x86_perf_event_set_period(event);
31fa58af 763 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 764 ARCH_PERFMON_EVENTSEL_ENABLE);
765 } else
766 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 767 }
351af072
ZY		 768}
769
770static void intel_pmu_nhm_enable_all(int added)
771{
772 if (added)
773 intel_pmu_nhm_workaround();
11164cd4
PZ		 774 intel_pmu_enable_all(added);
775}
776
f22f54f4
PZ		 777static inline u64 intel_pmu_get_status(void)
778{
779 u64 status;
780
781 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
782
783 return status;
784}
785
786static inline void intel_pmu_ack_status(u64 ack)
787{
788 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
789}
790
ca037701 791static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 792{
aff3d91a 793 int idx = hwc->idx - X86_PMC_IDX_FIXED;
f22f54f4
PZ		 794 u64 ctrl_val, mask;
795
796 mask = 0xfULL << (idx * 4);
797
798 rdmsrl(hwc->config_base, ctrl_val);
799 ctrl_val &= ~mask;
7645a24c 800 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 801}
802
ca037701 803static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 804{
aff3d91a
PZ		 805 struct hw_perf_event *hwc = &event->hw;
806
807 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 808 intel_pmu_disable_bts();
809 intel_pmu_drain_bts_buffer();
810 return;
811 }
812
813 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 814 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 815 return;
816 }
817
aff3d91a 818 x86_pmu_disable_event(event);
ca037701 819
ab608344 820 if (unlikely(event->attr.precise_ip))
ef21f683 821 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 822}
823
ca037701 824static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 825{
aff3d91a 826 int idx = hwc->idx - X86_PMC_IDX_FIXED;
f22f54f4 827 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 828
829 /*
830 * Enable IRQ generation (0x8),
831 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
832 * if requested:
833 */
834 bits = 0x8ULL;
835 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
836 bits |= 0x2;
837 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
838 bits |= 0x1;
839
840 /*
841 * ANY bit is supported in v3 and up
842 */
843 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
844 bits |= 0x4;
845
846 bits <<= (idx * 4);
847 mask = 0xfULL << (idx * 4);
848
849 rdmsrl(hwc->config_base, ctrl_val);
850 ctrl_val &= ~mask;
851 ctrl_val |= bits;
7645a24c 852 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 853}
854
aff3d91a 855static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 856{
aff3d91a
PZ		 857 struct hw_perf_event *hwc = &event->hw;
858
859 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
0a3aee0d 860 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 861 return;
862
863 intel_pmu_enable_bts(hwc->config);
864 return;
865 }
866
867 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 868 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 869 return;
870 }
871
ab608344 872 if (unlikely(event->attr.precise_ip))
ef21f683 873 intel_pmu_pebs_enable(event);
ca037701 874
31fa58af 875 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 876}
877
878/*
879 * Save and restart an expired event. Called by NMI contexts,
880 * so it has to be careful about preempting normal event ops:
881 */
882static int intel_pmu_save_and_restart(struct perf_event *event)
883{
cc2ad4ba
PZ		 884 x86_perf_event_update(event);
885 return x86_perf_event_set_period(event);
f22f54f4
PZ		 886}
887
888static void intel_pmu_reset(void)
889{
0a3aee0d 890 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 891 unsigned long flags;
892 int idx;
893
948b1bb8 894 if (!x86_pmu.num_counters)
f22f54f4
PZ		 895 return;
896
897 local_irq_save(flags);
898
899 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
900
948b1bb8 901 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
41bf4989
RR		 902 checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
903 checking_wrmsrl(x86_pmu_event_addr(idx), 0ull);
f22f54f4 904 }
948b1bb8 905 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
f22f54f4 906 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 907
f22f54f4
PZ		 908 if (ds)
909 ds->bts_index = ds->bts_buffer_base;
910
911 local_irq_restore(flags);
912}
913
914/*
915 * This handler is triggered by the local APIC, so the APIC IRQ handling
916 * rules apply:
917 */
918static int intel_pmu_handle_irq(struct pt_regs *regs)
919{
920 struct perf_sample_data data;
921 struct cpu_hw_events *cpuc;
922 int bit, loops;
2e556b5b 923 u64 status;
b0b2072d 924 int handled;
f22f54f4 925
dc1d628a 926 perf_sample_data_init(&data, 0);
f22f54f4
PZ		 927
928 cpuc = &__get_cpu_var(cpu_hw_events);
929
2bce5dac
DZ		 930 /*
931 * Some chipsets need to unmask the LVTPC in a particular spot
932 * inside the nmi handler. As a result, the unmasking was pushed
933 * into all the nmi handlers.
934 *
935 * This handler doesn't seem to have any issues with the unmasking
936 * so it was left at the top.
937 */
938 apic_write(APIC_LVTPC, APIC_DM_NMI);
939
3fb2b8dd 940 intel_pmu_disable_all();
b0b2072d 941 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 942 status = intel_pmu_get_status();
943 if (!status) {
11164cd4 944 intel_pmu_enable_all(0);
b0b2072d 945 return handled;
f22f54f4
PZ		 946 }
947
948 loops = 0;
949again:
2e556b5b 950 intel_pmu_ack_status(status);
f22f54f4
PZ		 951 if (++loops > 100) {
952 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
953 perf_event_print_debug();
954 intel_pmu_reset();
3fb2b8dd 955 goto done;
f22f54f4
PZ		 956 }
957
958 inc_irq_stat(apic_perf_irqs);
ca037701 959
caff2bef
PZ		 960 intel_pmu_lbr_read();
961
ca037701
PZ		 962 /*
963 * PEBS overflow sets bit 62 in the global status register
964 */
de725dec
PZ		 965 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
966 handled++;
ca037701 967 x86_pmu.drain_pebs(regs);
de725dec 968 }
ca037701 969
984b3f57 970 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 971 struct perf_event *event = cpuc->events[bit];
972
de725dec
PZ		 973 handled++;
974
f22f54f4
PZ		 975 if (!test_bit(bit, cpuc->active_mask))
976 continue;
977
978 if (!intel_pmu_save_and_restart(event))
979 continue;
980
981 data.period = event->hw.last_period;
982
a8b0ca17 983 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 984 x86_pmu_stop(event, 0);
f22f54f4
PZ		 985 }
986
f22f54f4
PZ		 987 /*
988 * Repeat if there is more work to be done:
989 */
990 status = intel_pmu_get_status();
991 if (status)
992 goto again;
993
3fb2b8dd 994done:
11164cd4 995 intel_pmu_enable_all(0);
de725dec 996 return handled;
f22f54f4
PZ		 997}
998
f22f54f4 999static struct event_constraint *
ca037701 1000intel_bts_constraints(struct perf_event *event)
f22f54f4 1001{
ca037701
PZ		 1002 struct hw_perf_event *hwc = &event->hw;
1003 unsigned int hw_event, bts_event;
f22f54f4 1004
18a073a3
PZ		 1005 if (event->attr.freq)
1006 return NULL;
1007
ca037701
PZ		 1008 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1009 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1010
ca037701 1011 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1012 return &bts_constraint;
ca037701 1013
f22f54f4
PZ		 1014 return NULL;
1015}
1016
efc9f05d
SE		 1017/*
1018 * manage allocation of shared extra msr for certain events
1019 *
1020 * sharing can be:
1021 * per-cpu: to be shared between the various events on a single PMU
1022 * per-core: per-cpu + shared by HT threads
1023 */
a7e3ed1e 1024static struct event_constraint *
efc9f05d
SE		 1025__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
1026 struct hw_perf_event_extra *reg)
a7e3ed1e 1027{
efc9f05d 1028 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1029 struct er_account *era;
cd8a38d3 1030 unsigned long flags;
a7e3ed1e 1031
efc9f05d 1032 /* already allocated shared msr */
cd8a38d3 1033 if (reg->alloc)
efc9f05d 1034 return &unconstrained;
a7e3ed1e 1035
efc9f05d 1036 era = &cpuc->shared_regs->regs[reg->idx];
cd8a38d3
SE		 1037 /*
1038 * we use spin_lock_irqsave() to avoid lockdep issues when
1039 * passing a fake cpuc
1040 */
1041 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1042
1043 if (!atomic_read(&era->ref) || era->config == reg->config) {
1044
1045 /* lock in msr value */
1046 era->config = reg->config;
1047 era->reg = reg->reg;
1048
1049 /* one more user */
1050 atomic_inc(&era->ref);
1051
1052 /* no need to reallocate during incremental event scheduling */
1053 reg->alloc = 1;
a7e3ed1e
AK		 1054
1055 /*
efc9f05d
SE		 1056 * All events using extra_reg are unconstrained.
1057 * Avoids calling x86_get_event_constraints()
1058 *
1059 * Must revisit if extra_reg controlling events
1060 * ever have constraints. Worst case we go through
1061 * the regular event constraint table.
a7e3ed1e 1062 */
efc9f05d 1063 c = &unconstrained;
a7e3ed1e 1064 }
cd8a38d3 1065 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1066
efc9f05d
SE		 1067 return c;
1068}
1069
1070static void
1071__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1072 struct hw_perf_event_extra *reg)
1073{
1074 struct er_account *era;
1075
1076 /*
1077 * only put constraint if extra reg was actually
1078 * allocated. Also takes care of event which do
1079 * not use an extra shared reg
1080 */
1081 if (!reg->alloc)
1082 return;
1083
1084 era = &cpuc->shared_regs->regs[reg->idx];
1085
1086 /* one fewer user */
1087 atomic_dec(&era->ref);
1088
1089 /* allocate again next time */
1090 reg->alloc = 0;
1091}
1092
1093static struct event_constraint *
1094intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1095 struct perf_event *event)
1096{
1097 struct event_constraint *c = NULL;
1098 struct hw_perf_event_extra *xreg;
1099
1100 xreg = &event->hw.extra_reg;
1101 if (xreg->idx != EXTRA_REG_NONE)
1102 c = __intel_shared_reg_get_constraints(cpuc, xreg);
1103 return c;
a7e3ed1e
AK		 1104}
1105
f22f54f4
PZ		 1106static struct event_constraint *
1107intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1108{
1109 struct event_constraint *c;
1110
ca037701
PZ		 1111 c = intel_bts_constraints(event);
1112 if (c)
1113 return c;
1114
1115 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1116 if (c)
1117 return c;
1118
efc9f05d 1119 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1120 if (c)
1121 return c;
1122
f22f54f4
PZ		 1123 return x86_get_event_constraints(cpuc, event);
1124}
1125
efc9f05d
SE		 1126static void
1127intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1128 struct perf_event *event)
1129{
efc9f05d 1130 struct hw_perf_event_extra *reg;
a7e3ed1e 1131
efc9f05d
SE		 1132 reg = &event->hw.extra_reg;
1133 if (reg->idx != EXTRA_REG_NONE)
1134 __intel_shared_reg_put_constraints(cpuc, reg);
1135}
a7e3ed1e 1136
efc9f05d
SE		 1137static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1138 struct perf_event *event)
1139{
1140 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1141}
1142
b4cdc5c2
PZ		 1143static int intel_pmu_hw_config(struct perf_event *event)
1144{
1145 int ret = x86_pmu_hw_config(event);
1146
1147 if (ret)
1148 return ret;
1149
7639dae0
PZ		 1150 if (event->attr.precise_ip &&
1151 (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1152 /*
1153 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1154 * (0x003c) so that we can use it with PEBS.
1155 *
1156 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1157 * PEBS capable. However we can use INST_RETIRED.ANY_P
1158 * (0x00c0), which is a PEBS capable event, to get the same
1159 * count.
1160 *
1161 * INST_RETIRED.ANY_P counts the number of cycles that retires
1162 * CNTMASK instructions. By setting CNTMASK to a value (16)
1163 * larger than the maximum number of instructions that can be
1164 * retired per cycle (4) and then inverting the condition, we
1165 * count all cycles that retire 16 or less instructions, which
1166 * is every cycle.
1167 *
1168 * Thereby we gain a PEBS capable cycle counter.
1169 */
1170 u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
1171
1172 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1173 event->hw.config = alt_config;
1174 }
1175
b4cdc5c2
PZ		 1176 if (event->attr.type != PERF_TYPE_RAW)
1177 return 0;
1178
1179 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1180 return 0;
1181
1182 if (x86_pmu.version < 3)
1183 return -EINVAL;
1184
1185 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1186 return -EACCES;
1187
1188 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1189
1190 return 0;
1191}
1192
caaa8be3 1193static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1194 .name = "core",
1195 .handle_irq = x86_pmu_handle_irq,
1196 .disable_all = x86_pmu_disable_all,
1197 .enable_all = x86_pmu_enable_all,
1198 .enable = x86_pmu_enable_event,
1199 .disable = x86_pmu_disable_event,
b4cdc5c2 1200 .hw_config = x86_pmu_hw_config,
a072738e 1201 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1202 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1203 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1204 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1205 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1206 .apic = 1,
1207 /*
1208 * Intel PMCs cannot be accessed sanely above 32 bit width,
1209 * so we install an artificial 1<<31 period regardless of
1210 * the generic event period:
1211 */
1212 .max_period = (1ULL << 31) - 1,
1213 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1214 .put_event_constraints = intel_put_event_constraints,
f22f54f4
PZ		 1215 .event_constraints = intel_core_event_constraints,
1216};
1217
efc9f05d
SE		 1218static struct intel_shared_regs *allocate_shared_regs(int cpu)
1219{
1220 struct intel_shared_regs *regs;
1221 int i;
1222
1223 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1224 GFP_KERNEL, cpu_to_node(cpu));
1225 if (regs) {
1226 /*
1227 * initialize the locks to keep lockdep happy
1228 */
1229 for (i = 0; i < EXTRA_REG_MAX; i++)
1230 raw_spin_lock_init(&regs->regs[i].lock);
1231
1232 regs->core_id = -1;
1233 }
1234 return regs;
1235}
1236
a7e3ed1e
AK		 1237static int intel_pmu_cpu_prepare(int cpu)
1238{
1239 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1240
efc9f05d 1241 if (!x86_pmu.extra_regs)
69092624
LM		 1242 return NOTIFY_OK;
1243
efc9f05d
SE		 1244 cpuc->shared_regs = allocate_shared_regs(cpu);
1245 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1246 return NOTIFY_BAD;
1247
a7e3ed1e
AK		 1248 return NOTIFY_OK;
1249}
1250
74846d35
PZ		 1251static void intel_pmu_cpu_starting(int cpu)
1252{
a7e3ed1e
AK		 1253 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1254 int core_id = topology_core_id(cpu);
1255 int i;
1256
69092624
LM		 1257 init_debug_store_on_cpu(cpu);
1258 /*
1259 * Deal with CPUs that don't clear their LBRs on power-up.
1260 */
1261 intel_pmu_lbr_reset();
1262
efc9f05d 1263 if (!cpuc->shared_regs)
69092624
LM		 1264 return;
1265
a7e3ed1e 1266 for_each_cpu(i, topology_thread_cpumask(cpu)) {
efc9f05d 1267 struct intel_shared_regs *pc;
a7e3ed1e 1268
efc9f05d 1269 pc = per_cpu(cpu_hw_events, i).shared_regs;
a7e3ed1e 1270 if (pc && pc->core_id == core_id) {
efc9f05d
SE		 1271 kfree(cpuc->shared_regs);
1272 cpuc->shared_regs = pc;
a7e3ed1e
AK		 1273 break;
1274 }
1275 }
1276
efc9f05d
SE		 1277 cpuc->shared_regs->core_id = core_id;
1278 cpuc->shared_regs->refcnt++;
74846d35
PZ		 1279}
1280
1281static void intel_pmu_cpu_dying(int cpu)
1282{
a7e3ed1e 1283 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1284 struct intel_shared_regs *pc;
a7e3ed1e 1285
efc9f05d 1286 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1287 if (pc) {
1288 if (pc->core_id == -1 || --pc->refcnt == 0)
1289 kfree(pc);
efc9f05d 1290 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1291 }
1292
74846d35
PZ		 1293 fini_debug_store_on_cpu(cpu);
1294}
1295
caaa8be3 1296static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1297 .name = "Intel",
1298 .handle_irq = intel_pmu_handle_irq,
1299 .disable_all = intel_pmu_disable_all,
1300 .enable_all = intel_pmu_enable_all,
1301 .enable = intel_pmu_enable_event,
1302 .disable = intel_pmu_disable_event,
b4cdc5c2 1303 .hw_config = intel_pmu_hw_config,
a072738e 1304 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1305 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1306 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1307 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1308 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1309 .apic = 1,
1310 /*
1311 * Intel PMCs cannot be accessed sanely above 32 bit width,
1312 * so we install an artificial 1<<31 period regardless of
1313 * the generic event period:
1314 */
1315 .max_period = (1ULL << 31) - 1,
3f6da390 1316 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1317 .put_event_constraints = intel_put_event_constraints,
3f6da390 1318
a7e3ed1e 1319 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1320 .cpu_starting = intel_pmu_cpu_starting,
1321 .cpu_dying = intel_pmu_cpu_dying,
f22f54f4
PZ		 1322};
1323
3c44780b
PZ		 1324static void intel_clovertown_quirks(void)
1325{
1326 /*
1327 * PEBS is unreliable due to:
1328 *
1329 * AJ67 - PEBS may experience CPL leaks
1330 * AJ68 - PEBS PMI may be delayed by one event
1331 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1332 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1333 *
1334 * AJ67 could be worked around by restricting the OS/USR flags.
1335 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1336 *
1337 * AJ106 could possibly be worked around by not allowing LBR
1338 * usage from PEBS, including the fixup.
1339 * AJ68 could possibly be worked around by always programming
ec75a716 1340 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1341 *
1342 * But taken together it might just make sense to not enable PEBS on
1343 * these chips.
1344 */
1345 printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
1346 x86_pmu.pebs = 0;
1347 x86_pmu.pebs_constraints = NULL;
1348}
1349
f22f54f4
PZ		 1350static __init int intel_pmu_init(void)
1351{
1352 union cpuid10_edx edx;
1353 union cpuid10_eax eax;
1354 unsigned int unused;
1355 unsigned int ebx;
1356 int version;
1357
1358 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 1359 switch (boot_cpu_data.x86) {
1360 case 0x6:
1361 return p6_pmu_init();
1362 case 0xf:
1363 return p4_pmu_init();
1364 }
f22f54f4 1365 return -ENODEV;
f22f54f4
PZ		 1366 }
1367
1368 /*
1369 * Check whether the Architectural PerfMon supports
1370 * Branch Misses Retired hw_event or not.
1371 */
1372 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
1373 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
1374 return -ENODEV;
1375
1376 version = eax.split.version_id;
1377 if (version < 2)
1378 x86_pmu = core_pmu;
1379 else
1380 x86_pmu = intel_pmu;
1381
1382 x86_pmu.version = version;
948b1bb8
RR		 1383 x86_pmu.num_counters = eax.split.num_counters;
1384 x86_pmu.cntval_bits = eax.split.bit_width;
1385 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4
PZ		 1386
1387 /*
1388 * Quirk: v2 perfmon does not report fixed-purpose events, so
1389 * assume at least 3 events:
1390 */
1391 if (version > 1)
948b1bb8 1392 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 1393
8db909a7
PZ		 1394 /*
1395 * v2 and above have a perf capabilities MSR
1396 */
1397 if (version > 1) {
1398 u64 capabilities;
1399
1400 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1401 x86_pmu.intel_cap.capabilities = capabilities;
1402 }
1403
ca037701
PZ		 1404 intel_ds_init();
1405
f22f54f4
PZ		 1406 /*
1407 * Install the hw-cache-events table:
1408 */
1409 switch (boot_cpu_data.x86_model) {
1410 case 14: /* 65 nm core solo/duo, "Yonah" */
1411 pr_cont("Core events, ");
1412 break;
1413
1414 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
3c44780b 1415 x86_pmu.quirks = intel_clovertown_quirks;
f22f54f4
PZ		 1416 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1417 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1418 case 29: /* six-core 45 nm xeon "Dunnington" */
1419 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1420 sizeof(hw_cache_event_ids));
1421
caff2bef
PZ		 1422 intel_pmu_lbr_init_core();
1423
f22f54f4 1424 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 1425 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 1426 pr_cont("Core2 events, ");
1427 break;
1428
1429 case 26: /* 45 nm nehalem, "Bloomfield" */
1430 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 1431 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 1432 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1433 sizeof(hw_cache_event_ids));
e994d7d2
AK		 1434 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1435 sizeof(hw_cache_extra_regs));
f22f54f4 1436
caff2bef
PZ		 1437 intel_pmu_lbr_init_nhm();
1438
f22f54f4 1439 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 1440 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 1441 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 1442 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 1443
91fc4cc0
IM		 1444 /* UOPS_ISSUED.STALLED_CYCLES */
1445 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1446 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8f622422 1447 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
94403f88 1448
ec75a716
IM		 1449 if (ebx & 0x40) {
1450 /*
1451 * Erratum AAJ80 detected, we work it around by using
1452 * the BR_MISP_EXEC.ANY event. This will over-count
1453 * branch-misses, but it's still much better than the
1454 * architectural event which is often completely bogus:
1455 */
1456 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1457
1458 pr_cont("erratum AAJ80 worked around, ");
1459 }
11164cd4 1460 pr_cont("Nehalem events, ");
f22f54f4 1461 break;
caff2bef 1462
b622d644 1463 case 28: /* Atom */
f22f54f4
PZ		 1464 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1465 sizeof(hw_cache_event_ids));
1466
caff2bef
PZ		 1467 intel_pmu_lbr_init_atom();
1468
f22f54f4 1469 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 1470 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 1471 pr_cont("Atom events, ");
1472 break;
1473
1474 case 37: /* 32 nm nehalem, "Clarkdale" */
1475 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 1476 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 1477 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
1478 sizeof(hw_cache_event_ids));
e994d7d2
AK		 1479 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1480 sizeof(hw_cache_extra_regs));
f22f54f4 1481
caff2bef
PZ		 1482 intel_pmu_lbr_init_nhm();
1483
f22f54f4 1484 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 1485 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 1486 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 1487 x86_pmu.extra_regs = intel_westmere_extra_regs;
30112039
IM		 1488
1489 /* UOPS_ISSUED.STALLED_CYCLES */
1490 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1491 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1492 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
1493
f22f54f4
PZ		 1494 pr_cont("Westmere events, ");
1495 break;
b622d644 1496
b06b3d49
LM		 1497 case 42: /* SandyBridge */
1498 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
1499 sizeof(hw_cache_event_ids));
1500
1501 intel_pmu_lbr_init_nhm();
1502
1503 x86_pmu.event_constraints = intel_snb_event_constraints;
1504 x86_pmu.pebs_constraints = intel_snb_pebs_events;
e04d1b23
LM		 1505
1506 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
1507 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1508 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
1509 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
1510
b06b3d49
LM		 1511 pr_cont("SandyBridge events, ");
1512 break;
1513
f22f54f4
PZ		 1514 default:
1515 /*
1516 * default constraints for v2 and up
1517 */
1518 x86_pmu.event_constraints = intel_gen_event_constraints;
1519 pr_cont("generic architected perfmon, ");
1520 }
1521 return 0;
1522}
1523
1524#else /* CONFIG_CPU_SUP_INTEL */
1525
1526static int intel_pmu_init(void)
1527{
1528 return 0;
1529}
1530
cd8a38d3
SE		 1531static struct intel_shared_regs *allocate_shared_regs(int cpu)
1532{
1533 return NULL;
1534}
f22f54f4 1535#endif /* CONFIG_CPU_SUP_INTEL */
Ubuntu Artful kernel mirror