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de0428a7 KW |
1 | #include <linux/perf_event.h> |
2 | #include <linux/types.h> | |
3 | ||
4 | #include <asm/perf_event.h> | |
5 | #include <asm/msr.h> | |
3e702ff6 | 6 | #include <asm/insn.h> |
de0428a7 KW |
7 | |
8 | #include "perf_event.h" | |
caff2bef PZ |
9 | |
10 | enum { | |
11 | LBR_FORMAT_32 = 0x00, | |
12 | LBR_FORMAT_LIP = 0x01, | |
13 | LBR_FORMAT_EIP = 0x02, | |
14 | LBR_FORMAT_EIP_FLAGS = 0x03, | |
135c5612 AK |
15 | LBR_FORMAT_EIP_FLAGS2 = 0x04, |
16 | LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_EIP_FLAGS2, | |
17 | }; | |
18 | ||
19 | static enum { | |
20 | LBR_EIP_FLAGS = 1, | |
21 | LBR_TSX = 2, | |
22 | } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = { | |
23 | [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS, | |
24 | [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX, | |
caff2bef PZ |
25 | }; |
26 | ||
c5cc2cd9 SE |
27 | /* |
28 | * Intel LBR_SELECT bits | |
29 | * Intel Vol3a, April 2011, Section 16.7 Table 16-10 | |
30 | * | |
31 | * Hardware branch filter (not available on all CPUs) | |
32 | */ | |
33 | #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */ | |
34 | #define LBR_USER_BIT 1 /* do not capture at ring > 0 */ | |
35 | #define LBR_JCC_BIT 2 /* do not capture conditional branches */ | |
36 | #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */ | |
37 | #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */ | |
38 | #define LBR_RETURN_BIT 5 /* do not capture near returns */ | |
39 | #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */ | |
40 | #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */ | |
41 | #define LBR_FAR_BIT 8 /* do not capture far branches */ | |
42 | ||
43 | #define LBR_KERNEL (1 << LBR_KERNEL_BIT) | |
44 | #define LBR_USER (1 << LBR_USER_BIT) | |
45 | #define LBR_JCC (1 << LBR_JCC_BIT) | |
46 | #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT) | |
47 | #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT) | |
48 | #define LBR_RETURN (1 << LBR_RETURN_BIT) | |
49 | #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT) | |
50 | #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT) | |
51 | #define LBR_FAR (1 << LBR_FAR_BIT) | |
52 | ||
53 | #define LBR_PLM (LBR_KERNEL | LBR_USER) | |
54 | ||
55 | #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */ | |
56 | #define LBR_NOT_SUPP -1 /* LBR filter not supported */ | |
57 | #define LBR_IGN 0 /* ignored */ | |
58 | ||
59 | #define LBR_ANY \ | |
60 | (LBR_JCC |\ | |
61 | LBR_REL_CALL |\ | |
62 | LBR_IND_CALL |\ | |
63 | LBR_RETURN |\ | |
64 | LBR_REL_JMP |\ | |
65 | LBR_IND_JMP |\ | |
66 | LBR_FAR) | |
67 | ||
68 | #define LBR_FROM_FLAG_MISPRED (1ULL << 63) | |
135c5612 AK |
69 | #define LBR_FROM_FLAG_IN_TX (1ULL << 62) |
70 | #define LBR_FROM_FLAG_ABORT (1ULL << 61) | |
c5cc2cd9 | 71 | |
60ce0fbd SE |
72 | #define for_each_branch_sample_type(x) \ |
73 | for ((x) = PERF_SAMPLE_BRANCH_USER; \ | |
74 | (x) < PERF_SAMPLE_BRANCH_MAX; (x) <<= 1) | |
75 | ||
3e702ff6 SE |
76 | /* |
77 | * x86control flow change classification | |
78 | * x86control flow changes include branches, interrupts, traps, faults | |
79 | */ | |
80 | enum { | |
81 | X86_BR_NONE = 0, /* unknown */ | |
82 | ||
83 | X86_BR_USER = 1 << 0, /* branch target is user */ | |
84 | X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ | |
85 | ||
86 | X86_BR_CALL = 1 << 2, /* call */ | |
87 | X86_BR_RET = 1 << 3, /* return */ | |
88 | X86_BR_SYSCALL = 1 << 4, /* syscall */ | |
89 | X86_BR_SYSRET = 1 << 5, /* syscall return */ | |
90 | X86_BR_INT = 1 << 6, /* sw interrupt */ | |
91 | X86_BR_IRET = 1 << 7, /* return from interrupt */ | |
92 | X86_BR_JCC = 1 << 8, /* conditional */ | |
93 | X86_BR_JMP = 1 << 9, /* jump */ | |
94 | X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ | |
95 | X86_BR_IND_CALL = 1 << 11,/* indirect calls */ | |
135c5612 AK |
96 | X86_BR_ABORT = 1 << 12,/* transaction abort */ |
97 | X86_BR_IN_TX = 1 << 13,/* in transaction */ | |
98 | X86_BR_NO_TX = 1 << 14,/* not in transaction */ | |
3e702ff6 SE |
99 | }; |
100 | ||
101 | #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) | |
135c5612 | 102 | #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) |
3e702ff6 SE |
103 | |
104 | #define X86_BR_ANY \ | |
105 | (X86_BR_CALL |\ | |
106 | X86_BR_RET |\ | |
107 | X86_BR_SYSCALL |\ | |
108 | X86_BR_SYSRET |\ | |
109 | X86_BR_INT |\ | |
110 | X86_BR_IRET |\ | |
111 | X86_BR_JCC |\ | |
112 | X86_BR_JMP |\ | |
113 | X86_BR_IRQ |\ | |
135c5612 | 114 | X86_BR_ABORT |\ |
3e702ff6 SE |
115 | X86_BR_IND_CALL) |
116 | ||
117 | #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) | |
118 | ||
119 | #define X86_BR_ANY_CALL \ | |
120 | (X86_BR_CALL |\ | |
121 | X86_BR_IND_CALL |\ | |
122 | X86_BR_SYSCALL |\ | |
123 | X86_BR_IRQ |\ | |
124 | X86_BR_INT) | |
125 | ||
126 | static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); | |
127 | ||
caff2bef PZ |
128 | /* |
129 | * We only support LBR implementations that have FREEZE_LBRS_ON_PMI | |
130 | * otherwise it becomes near impossible to get a reliable stack. | |
131 | */ | |
132 | ||
caff2bef PZ |
133 | static void __intel_pmu_lbr_enable(void) |
134 | { | |
135 | u64 debugctl; | |
60ce0fbd SE |
136 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
137 | ||
138 | if (cpuc->lbr_sel) | |
139 | wrmsrl(MSR_LBR_SELECT, cpuc->lbr_sel->config); | |
caff2bef PZ |
140 | |
141 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
7c5ecaf7 | 142 | debugctl |= (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); |
caff2bef PZ |
143 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
144 | } | |
145 | ||
146 | static void __intel_pmu_lbr_disable(void) | |
147 | { | |
148 | u64 debugctl; | |
149 | ||
150 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
7c5ecaf7 | 151 | debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); |
caff2bef PZ |
152 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
153 | } | |
154 | ||
155 | static void intel_pmu_lbr_reset_32(void) | |
156 | { | |
157 | int i; | |
158 | ||
159 | for (i = 0; i < x86_pmu.lbr_nr; i++) | |
160 | wrmsrl(x86_pmu.lbr_from + i, 0); | |
161 | } | |
162 | ||
163 | static void intel_pmu_lbr_reset_64(void) | |
164 | { | |
165 | int i; | |
166 | ||
167 | for (i = 0; i < x86_pmu.lbr_nr; i++) { | |
168 | wrmsrl(x86_pmu.lbr_from + i, 0); | |
169 | wrmsrl(x86_pmu.lbr_to + i, 0); | |
170 | } | |
171 | } | |
172 | ||
de0428a7 | 173 | void intel_pmu_lbr_reset(void) |
caff2bef | 174 | { |
74846d35 PZ |
175 | if (!x86_pmu.lbr_nr) |
176 | return; | |
177 | ||
8db909a7 | 178 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) |
caff2bef PZ |
179 | intel_pmu_lbr_reset_32(); |
180 | else | |
181 | intel_pmu_lbr_reset_64(); | |
182 | } | |
183 | ||
de0428a7 | 184 | void intel_pmu_lbr_enable(struct perf_event *event) |
caff2bef PZ |
185 | { |
186 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
187 | ||
188 | if (!x86_pmu.lbr_nr) | |
189 | return; | |
190 | ||
caff2bef | 191 | /* |
b83a46e7 PZ |
192 | * Reset the LBR stack if we changed task context to |
193 | * avoid data leaks. | |
caff2bef | 194 | */ |
b83a46e7 | 195 | if (event->ctx->task && cpuc->lbr_context != event->ctx) { |
caff2bef PZ |
196 | intel_pmu_lbr_reset(); |
197 | cpuc->lbr_context = event->ctx; | |
198 | } | |
3e702ff6 | 199 | cpuc->br_sel = event->hw.branch_reg.reg; |
caff2bef PZ |
200 | |
201 | cpuc->lbr_users++; | |
202 | } | |
203 | ||
de0428a7 | 204 | void intel_pmu_lbr_disable(struct perf_event *event) |
caff2bef PZ |
205 | { |
206 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
207 | ||
208 | if (!x86_pmu.lbr_nr) | |
209 | return; | |
210 | ||
211 | cpuc->lbr_users--; | |
b83a46e7 | 212 | WARN_ON_ONCE(cpuc->lbr_users < 0); |
2df202bf | 213 | |
60ce0fbd | 214 | if (cpuc->enabled && !cpuc->lbr_users) { |
2df202bf | 215 | __intel_pmu_lbr_disable(); |
60ce0fbd SE |
216 | /* avoid stale pointer */ |
217 | cpuc->lbr_context = NULL; | |
218 | } | |
caff2bef PZ |
219 | } |
220 | ||
de0428a7 | 221 | void intel_pmu_lbr_enable_all(void) |
caff2bef PZ |
222 | { |
223 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
224 | ||
225 | if (cpuc->lbr_users) | |
226 | __intel_pmu_lbr_enable(); | |
227 | } | |
228 | ||
de0428a7 | 229 | void intel_pmu_lbr_disable_all(void) |
caff2bef PZ |
230 | { |
231 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
232 | ||
233 | if (cpuc->lbr_users) | |
234 | __intel_pmu_lbr_disable(); | |
235 | } | |
236 | ||
60ce0fbd SE |
237 | /* |
238 | * TOS = most recently recorded branch | |
239 | */ | |
caff2bef PZ |
240 | static inline u64 intel_pmu_lbr_tos(void) |
241 | { | |
242 | u64 tos; | |
243 | ||
244 | rdmsrl(x86_pmu.lbr_tos, tos); | |
245 | ||
246 | return tos; | |
247 | } | |
248 | ||
249 | static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) | |
250 | { | |
251 | unsigned long mask = x86_pmu.lbr_nr - 1; | |
252 | u64 tos = intel_pmu_lbr_tos(); | |
253 | int i; | |
254 | ||
63fb3f9b | 255 | for (i = 0; i < x86_pmu.lbr_nr; i++) { |
caff2bef PZ |
256 | unsigned long lbr_idx = (tos - i) & mask; |
257 | union { | |
258 | struct { | |
259 | u32 from; | |
260 | u32 to; | |
261 | }; | |
262 | u64 lbr; | |
263 | } msr_lastbranch; | |
264 | ||
265 | rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); | |
266 | ||
bce38cd5 SE |
267 | cpuc->lbr_entries[i].from = msr_lastbranch.from; |
268 | cpuc->lbr_entries[i].to = msr_lastbranch.to; | |
269 | cpuc->lbr_entries[i].mispred = 0; | |
270 | cpuc->lbr_entries[i].predicted = 0; | |
271 | cpuc->lbr_entries[i].reserved = 0; | |
caff2bef PZ |
272 | } |
273 | cpuc->lbr_stack.nr = i; | |
274 | } | |
275 | ||
caff2bef PZ |
276 | /* |
277 | * Due to lack of segmentation in Linux the effective address (offset) | |
278 | * is the same as the linear address, allowing us to merge the LIP and EIP | |
279 | * LBR formats. | |
280 | */ | |
281 | static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) | |
282 | { | |
283 | unsigned long mask = x86_pmu.lbr_nr - 1; | |
8db909a7 | 284 | int lbr_format = x86_pmu.intel_cap.lbr_format; |
caff2bef PZ |
285 | u64 tos = intel_pmu_lbr_tos(); |
286 | int i; | |
287 | ||
63fb3f9b | 288 | for (i = 0; i < x86_pmu.lbr_nr; i++) { |
caff2bef | 289 | unsigned long lbr_idx = (tos - i) & mask; |
135c5612 AK |
290 | u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0; |
291 | int skip = 0; | |
292 | int lbr_flags = lbr_desc[lbr_format]; | |
caff2bef PZ |
293 | |
294 | rdmsrl(x86_pmu.lbr_from + lbr_idx, from); | |
295 | rdmsrl(x86_pmu.lbr_to + lbr_idx, to); | |
296 | ||
135c5612 | 297 | if (lbr_flags & LBR_EIP_FLAGS) { |
bce38cd5 SE |
298 | mis = !!(from & LBR_FROM_FLAG_MISPRED); |
299 | pred = !mis; | |
135c5612 AK |
300 | skip = 1; |
301 | } | |
302 | if (lbr_flags & LBR_TSX) { | |
303 | in_tx = !!(from & LBR_FROM_FLAG_IN_TX); | |
304 | abort = !!(from & LBR_FROM_FLAG_ABORT); | |
305 | skip = 3; | |
caff2bef | 306 | } |
135c5612 | 307 | from = (u64)((((s64)from) << skip) >> skip); |
caff2bef | 308 | |
bce38cd5 SE |
309 | cpuc->lbr_entries[i].from = from; |
310 | cpuc->lbr_entries[i].to = to; | |
311 | cpuc->lbr_entries[i].mispred = mis; | |
312 | cpuc->lbr_entries[i].predicted = pred; | |
135c5612 AK |
313 | cpuc->lbr_entries[i].in_tx = in_tx; |
314 | cpuc->lbr_entries[i].abort = abort; | |
bce38cd5 | 315 | cpuc->lbr_entries[i].reserved = 0; |
caff2bef PZ |
316 | } |
317 | cpuc->lbr_stack.nr = i; | |
318 | } | |
319 | ||
de0428a7 | 320 | void intel_pmu_lbr_read(void) |
caff2bef PZ |
321 | { |
322 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
323 | ||
324 | if (!cpuc->lbr_users) | |
325 | return; | |
326 | ||
8db909a7 | 327 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) |
caff2bef PZ |
328 | intel_pmu_lbr_read_32(cpuc); |
329 | else | |
330 | intel_pmu_lbr_read_64(cpuc); | |
3e702ff6 SE |
331 | |
332 | intel_pmu_lbr_filter(cpuc); | |
333 | } | |
334 | ||
335 | /* | |
336 | * SW filter is used: | |
337 | * - in case there is no HW filter | |
338 | * - in case the HW filter has errata or limitations | |
339 | */ | |
2b923c8f | 340 | static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event) |
3e702ff6 SE |
341 | { |
342 | u64 br_type = event->attr.branch_sample_type; | |
343 | int mask = 0; | |
344 | ||
345 | if (br_type & PERF_SAMPLE_BRANCH_USER) | |
346 | mask |= X86_BR_USER; | |
347 | ||
2b923c8f | 348 | if (br_type & PERF_SAMPLE_BRANCH_KERNEL) |
3e702ff6 SE |
349 | mask |= X86_BR_KERNEL; |
350 | ||
351 | /* we ignore BRANCH_HV here */ | |
352 | ||
353 | if (br_type & PERF_SAMPLE_BRANCH_ANY) | |
354 | mask |= X86_BR_ANY; | |
355 | ||
356 | if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL) | |
357 | mask |= X86_BR_ANY_CALL; | |
358 | ||
359 | if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN) | |
360 | mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET; | |
361 | ||
362 | if (br_type & PERF_SAMPLE_BRANCH_IND_CALL) | |
363 | mask |= X86_BR_IND_CALL; | |
135c5612 AK |
364 | |
365 | if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX) | |
366 | mask |= X86_BR_ABORT; | |
367 | ||
368 | if (br_type & PERF_SAMPLE_BRANCH_IN_TX) | |
369 | mask |= X86_BR_IN_TX; | |
370 | ||
371 | if (br_type & PERF_SAMPLE_BRANCH_NO_TX) | |
372 | mask |= X86_BR_NO_TX; | |
373 | ||
3e702ff6 SE |
374 | /* |
375 | * stash actual user request into reg, it may | |
376 | * be used by fixup code for some CPU | |
377 | */ | |
378 | event->hw.branch_reg.reg = mask; | |
caff2bef PZ |
379 | } |
380 | ||
60ce0fbd SE |
381 | /* |
382 | * setup the HW LBR filter | |
383 | * Used only when available, may not be enough to disambiguate | |
384 | * all branches, may need the help of the SW filter | |
385 | */ | |
386 | static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event) | |
387 | { | |
388 | struct hw_perf_event_extra *reg; | |
389 | u64 br_type = event->attr.branch_sample_type; | |
390 | u64 mask = 0, m; | |
391 | u64 v; | |
392 | ||
393 | for_each_branch_sample_type(m) { | |
394 | if (!(br_type & m)) | |
395 | continue; | |
396 | ||
397 | v = x86_pmu.lbr_sel_map[m]; | |
398 | if (v == LBR_NOT_SUPP) | |
399 | return -EOPNOTSUPP; | |
60ce0fbd | 400 | |
3e702ff6 SE |
401 | if (v != LBR_IGN) |
402 | mask |= v; | |
60ce0fbd SE |
403 | } |
404 | reg = &event->hw.branch_reg; | |
405 | reg->idx = EXTRA_REG_LBR; | |
406 | ||
407 | /* LBR_SELECT operates in suppress mode so invert mask */ | |
408 | reg->config = ~mask & x86_pmu.lbr_sel_mask; | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
60ce0fbd SE |
413 | int intel_pmu_setup_lbr_filter(struct perf_event *event) |
414 | { | |
3e702ff6 | 415 | int ret = 0; |
60ce0fbd SE |
416 | |
417 | /* | |
418 | * no LBR on this PMU | |
419 | */ | |
420 | if (!x86_pmu.lbr_nr) | |
421 | return -EOPNOTSUPP; | |
422 | ||
423 | /* | |
3e702ff6 | 424 | * setup SW LBR filter |
60ce0fbd | 425 | */ |
2b923c8f | 426 | intel_pmu_setup_sw_lbr_filter(event); |
3e702ff6 SE |
427 | |
428 | /* | |
429 | * setup HW LBR filter, if any | |
430 | */ | |
431 | if (x86_pmu.lbr_sel_map) | |
432 | ret = intel_pmu_setup_hw_lbr_filter(event); | |
433 | ||
434 | return ret; | |
435 | } | |
436 | ||
437 | /* | |
438 | * return the type of control flow change at address "from" | |
439 | * intruction is not necessarily a branch (in case of interrupt). | |
440 | * | |
441 | * The branch type returned also includes the priv level of the | |
442 | * target of the control flow change (X86_BR_USER, X86_BR_KERNEL). | |
443 | * | |
444 | * If a branch type is unknown OR the instruction cannot be | |
445 | * decoded (e.g., text page not present), then X86_BR_NONE is | |
446 | * returned. | |
447 | */ | |
135c5612 | 448 | static int branch_type(unsigned long from, unsigned long to, int abort) |
3e702ff6 SE |
449 | { |
450 | struct insn insn; | |
451 | void *addr; | |
452 | int bytes, size = MAX_INSN_SIZE; | |
453 | int ret = X86_BR_NONE; | |
454 | int ext, to_plm, from_plm; | |
455 | u8 buf[MAX_INSN_SIZE]; | |
456 | int is64 = 0; | |
457 | ||
458 | to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER; | |
459 | from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER; | |
460 | ||
461 | /* | |
462 | * maybe zero if lbr did not fill up after a reset by the time | |
463 | * we get a PMU interrupt | |
464 | */ | |
465 | if (from == 0 || to == 0) | |
466 | return X86_BR_NONE; | |
467 | ||
135c5612 AK |
468 | if (abort) |
469 | return X86_BR_ABORT | to_plm; | |
470 | ||
3e702ff6 SE |
471 | if (from_plm == X86_BR_USER) { |
472 | /* | |
473 | * can happen if measuring at the user level only | |
474 | * and we interrupt in a kernel thread, e.g., idle. | |
475 | */ | |
476 | if (!current->mm) | |
477 | return X86_BR_NONE; | |
478 | ||
479 | /* may fail if text not present */ | |
480 | bytes = copy_from_user_nmi(buf, (void __user *)from, size); | |
481 | if (bytes != size) | |
482 | return X86_BR_NONE; | |
483 | ||
484 | addr = buf; | |
6e15eb3b PZ |
485 | } else { |
486 | /* | |
487 | * The LBR logs any address in the IP, even if the IP just | |
488 | * faulted. This means userspace can control the from address. | |
489 | * Ensure we don't blindy read any address by validating it is | |
490 | * a known text address. | |
491 | */ | |
492 | if (kernel_text_address(from)) | |
493 | addr = (void *)from; | |
494 | else | |
495 | return X86_BR_NONE; | |
496 | } | |
3e702ff6 SE |
497 | |
498 | /* | |
499 | * decoder needs to know the ABI especially | |
500 | * on 64-bit systems running 32-bit apps | |
501 | */ | |
502 | #ifdef CONFIG_X86_64 | |
503 | is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32); | |
504 | #endif | |
505 | insn_init(&insn, addr, is64); | |
506 | insn_get_opcode(&insn); | |
507 | ||
508 | switch (insn.opcode.bytes[0]) { | |
509 | case 0xf: | |
510 | switch (insn.opcode.bytes[1]) { | |
511 | case 0x05: /* syscall */ | |
512 | case 0x34: /* sysenter */ | |
513 | ret = X86_BR_SYSCALL; | |
514 | break; | |
515 | case 0x07: /* sysret */ | |
516 | case 0x35: /* sysexit */ | |
517 | ret = X86_BR_SYSRET; | |
518 | break; | |
519 | case 0x80 ... 0x8f: /* conditional */ | |
520 | ret = X86_BR_JCC; | |
521 | break; | |
522 | default: | |
523 | ret = X86_BR_NONE; | |
524 | } | |
525 | break; | |
526 | case 0x70 ... 0x7f: /* conditional */ | |
527 | ret = X86_BR_JCC; | |
528 | break; | |
529 | case 0xc2: /* near ret */ | |
530 | case 0xc3: /* near ret */ | |
531 | case 0xca: /* far ret */ | |
532 | case 0xcb: /* far ret */ | |
533 | ret = X86_BR_RET; | |
534 | break; | |
535 | case 0xcf: /* iret */ | |
536 | ret = X86_BR_IRET; | |
537 | break; | |
538 | case 0xcc ... 0xce: /* int */ | |
539 | ret = X86_BR_INT; | |
540 | break; | |
541 | case 0xe8: /* call near rel */ | |
542 | case 0x9a: /* call far absolute */ | |
543 | ret = X86_BR_CALL; | |
544 | break; | |
545 | case 0xe0 ... 0xe3: /* loop jmp */ | |
546 | ret = X86_BR_JCC; | |
547 | break; | |
548 | case 0xe9 ... 0xeb: /* jmp */ | |
549 | ret = X86_BR_JMP; | |
550 | break; | |
551 | case 0xff: /* call near absolute, call far absolute ind */ | |
552 | insn_get_modrm(&insn); | |
553 | ext = (insn.modrm.bytes[0] >> 3) & 0x7; | |
554 | switch (ext) { | |
555 | case 2: /* near ind call */ | |
556 | case 3: /* far ind call */ | |
557 | ret = X86_BR_IND_CALL; | |
558 | break; | |
559 | case 4: | |
560 | case 5: | |
561 | ret = X86_BR_JMP; | |
562 | break; | |
563 | } | |
564 | break; | |
565 | default: | |
566 | ret = X86_BR_NONE; | |
60ce0fbd SE |
567 | } |
568 | /* | |
3e702ff6 SE |
569 | * interrupts, traps, faults (and thus ring transition) may |
570 | * occur on any instructions. Thus, to classify them correctly, | |
571 | * we need to first look at the from and to priv levels. If they | |
572 | * are different and to is in the kernel, then it indicates | |
573 | * a ring transition. If the from instruction is not a ring | |
574 | * transition instr (syscall, systenter, int), then it means | |
575 | * it was a irq, trap or fault. | |
576 | * | |
577 | * we have no way of detecting kernel to kernel faults. | |
578 | */ | |
579 | if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL | |
580 | && ret != X86_BR_SYSCALL && ret != X86_BR_INT) | |
581 | ret = X86_BR_IRQ; | |
582 | ||
583 | /* | |
584 | * branch priv level determined by target as | |
585 | * is done by HW when LBR_SELECT is implemented | |
60ce0fbd | 586 | */ |
3e702ff6 SE |
587 | if (ret != X86_BR_NONE) |
588 | ret |= to_plm; | |
60ce0fbd | 589 | |
3e702ff6 SE |
590 | return ret; |
591 | } | |
592 | ||
593 | /* | |
594 | * implement actual branch filter based on user demand. | |
595 | * Hardware may not exactly satisfy that request, thus | |
596 | * we need to inspect opcodes. Mismatched branches are | |
597 | * discarded. Therefore, the number of branches returned | |
598 | * in PERF_SAMPLE_BRANCH_STACK sample may vary. | |
599 | */ | |
600 | static void | |
601 | intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) | |
602 | { | |
603 | u64 from, to; | |
604 | int br_sel = cpuc->br_sel; | |
605 | int i, j, type; | |
606 | bool compress = false; | |
607 | ||
608 | /* if sampling all branches, then nothing to filter */ | |
609 | if ((br_sel & X86_BR_ALL) == X86_BR_ALL) | |
610 | return; | |
611 | ||
612 | for (i = 0; i < cpuc->lbr_stack.nr; i++) { | |
613 | ||
614 | from = cpuc->lbr_entries[i].from; | |
615 | to = cpuc->lbr_entries[i].to; | |
616 | ||
135c5612 AK |
617 | type = branch_type(from, to, cpuc->lbr_entries[i].abort); |
618 | if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) { | |
619 | if (cpuc->lbr_entries[i].in_tx) | |
620 | type |= X86_BR_IN_TX; | |
621 | else | |
622 | type |= X86_BR_NO_TX; | |
623 | } | |
3e702ff6 SE |
624 | |
625 | /* if type does not correspond, then discard */ | |
626 | if (type == X86_BR_NONE || (br_sel & type) != type) { | |
627 | cpuc->lbr_entries[i].from = 0; | |
628 | compress = true; | |
629 | } | |
630 | } | |
631 | ||
632 | if (!compress) | |
633 | return; | |
634 | ||
635 | /* remove all entries with from=0 */ | |
636 | for (i = 0; i < cpuc->lbr_stack.nr; ) { | |
637 | if (!cpuc->lbr_entries[i].from) { | |
638 | j = i; | |
639 | while (++j < cpuc->lbr_stack.nr) | |
640 | cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j]; | |
641 | cpuc->lbr_stack.nr--; | |
642 | if (!cpuc->lbr_entries[i].from) | |
643 | continue; | |
644 | } | |
645 | i++; | |
646 | } | |
60ce0fbd SE |
647 | } |
648 | ||
c5cc2cd9 SE |
649 | /* |
650 | * Map interface branch filters onto LBR filters | |
651 | */ | |
652 | static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = { | |
653 | [PERF_SAMPLE_BRANCH_ANY] = LBR_ANY, | |
654 | [PERF_SAMPLE_BRANCH_USER] = LBR_USER, | |
655 | [PERF_SAMPLE_BRANCH_KERNEL] = LBR_KERNEL, | |
656 | [PERF_SAMPLE_BRANCH_HV] = LBR_IGN, | |
657 | [PERF_SAMPLE_BRANCH_ANY_RETURN] = LBR_RETURN | LBR_REL_JMP | |
658 | | LBR_IND_JMP | LBR_FAR, | |
659 | /* | |
660 | * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches | |
661 | */ | |
662 | [PERF_SAMPLE_BRANCH_ANY_CALL] = | |
663 | LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR, | |
664 | /* | |
665 | * NHM/WSM erratum: must include IND_JMP to capture IND_CALL | |
666 | */ | |
667 | [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL | LBR_IND_JMP, | |
668 | }; | |
669 | ||
670 | static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = { | |
671 | [PERF_SAMPLE_BRANCH_ANY] = LBR_ANY, | |
672 | [PERF_SAMPLE_BRANCH_USER] = LBR_USER, | |
673 | [PERF_SAMPLE_BRANCH_KERNEL] = LBR_KERNEL, | |
674 | [PERF_SAMPLE_BRANCH_HV] = LBR_IGN, | |
675 | [PERF_SAMPLE_BRANCH_ANY_RETURN] = LBR_RETURN | LBR_FAR, | |
676 | [PERF_SAMPLE_BRANCH_ANY_CALL] = LBR_REL_CALL | LBR_IND_CALL | |
677 | | LBR_FAR, | |
678 | [PERF_SAMPLE_BRANCH_IND_CALL] = LBR_IND_CALL, | |
679 | }; | |
680 | ||
681 | /* core */ | |
de0428a7 | 682 | void intel_pmu_lbr_init_core(void) |
caff2bef | 683 | { |
caff2bef | 684 | x86_pmu.lbr_nr = 4; |
225ce539 SE |
685 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
686 | x86_pmu.lbr_from = MSR_LBR_CORE_FROM; | |
687 | x86_pmu.lbr_to = MSR_LBR_CORE_TO; | |
c5cc2cd9 | 688 | |
3e702ff6 SE |
689 | /* |
690 | * SW branch filter usage: | |
691 | * - compensate for lack of HW filter | |
692 | */ | |
c5cc2cd9 | 693 | pr_cont("4-deep LBR, "); |
caff2bef PZ |
694 | } |
695 | ||
c5cc2cd9 | 696 | /* nehalem/westmere */ |
de0428a7 | 697 | void intel_pmu_lbr_init_nhm(void) |
caff2bef | 698 | { |
caff2bef | 699 | x86_pmu.lbr_nr = 16; |
225ce539 SE |
700 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
701 | x86_pmu.lbr_from = MSR_LBR_NHM_FROM; | |
702 | x86_pmu.lbr_to = MSR_LBR_NHM_TO; | |
c5cc2cd9 SE |
703 | |
704 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; | |
705 | x86_pmu.lbr_sel_map = nhm_lbr_sel_map; | |
706 | ||
3e702ff6 SE |
707 | /* |
708 | * SW branch filter usage: | |
709 | * - workaround LBR_SEL errata (see above) | |
710 | * - support syscall, sysret capture. | |
711 | * That requires LBR_FAR but that means far | |
712 | * jmp need to be filtered out | |
713 | */ | |
c5cc2cd9 | 714 | pr_cont("16-deep LBR, "); |
caff2bef PZ |
715 | } |
716 | ||
c5cc2cd9 SE |
717 | /* sandy bridge */ |
718 | void intel_pmu_lbr_init_snb(void) | |
719 | { | |
720 | x86_pmu.lbr_nr = 16; | |
721 | x86_pmu.lbr_tos = MSR_LBR_TOS; | |
722 | x86_pmu.lbr_from = MSR_LBR_NHM_FROM; | |
723 | x86_pmu.lbr_to = MSR_LBR_NHM_TO; | |
724 | ||
725 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; | |
726 | x86_pmu.lbr_sel_map = snb_lbr_sel_map; | |
727 | ||
3e702ff6 SE |
728 | /* |
729 | * SW branch filter usage: | |
730 | * - support syscall, sysret capture. | |
731 | * That requires LBR_FAR but that means far | |
732 | * jmp need to be filtered out | |
733 | */ | |
c5cc2cd9 SE |
734 | pr_cont("16-deep LBR, "); |
735 | } | |
736 | ||
737 | /* atom */ | |
de0428a7 | 738 | void intel_pmu_lbr_init_atom(void) |
caff2bef | 739 | { |
88c9a65e SE |
740 | /* |
741 | * only models starting at stepping 10 seems | |
742 | * to have an operational LBR which can freeze | |
743 | * on PMU interrupt | |
744 | */ | |
3ec18cd8 SE |
745 | if (boot_cpu_data.x86_model == 28 |
746 | && boot_cpu_data.x86_mask < 10) { | |
88c9a65e SE |
747 | pr_cont("LBR disabled due to erratum"); |
748 | return; | |
749 | } | |
750 | ||
caff2bef | 751 | x86_pmu.lbr_nr = 8; |
225ce539 SE |
752 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
753 | x86_pmu.lbr_from = MSR_LBR_CORE_FROM; | |
754 | x86_pmu.lbr_to = MSR_LBR_CORE_TO; | |
c5cc2cd9 | 755 | |
3e702ff6 SE |
756 | /* |
757 | * SW branch filter usage: | |
758 | * - compensate for lack of HW filter | |
759 | */ | |
c5cc2cd9 | 760 | pr_cont("8-deep LBR, "); |
caff2bef | 761 | } |