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Commit | Line | Data |
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de0428a7 KW |
1 | #include <linux/perf_event.h> |
2 | #include <linux/types.h> | |
3 | ||
4 | #include <asm/perf_event.h> | |
5 | #include <asm/msr.h> | |
3e702ff6 | 6 | #include <asm/insn.h> |
de0428a7 KW |
7 | |
8 | #include "perf_event.h" | |
caff2bef PZ |
9 | |
10 | enum { | |
11 | LBR_FORMAT_32 = 0x00, | |
12 | LBR_FORMAT_LIP = 0x01, | |
13 | LBR_FORMAT_EIP = 0x02, | |
14 | LBR_FORMAT_EIP_FLAGS = 0x03, | |
135c5612 AK |
15 | LBR_FORMAT_EIP_FLAGS2 = 0x04, |
16 | LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_EIP_FLAGS2, | |
17 | }; | |
18 | ||
19 | static enum { | |
20 | LBR_EIP_FLAGS = 1, | |
21 | LBR_TSX = 2, | |
22 | } lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = { | |
23 | [LBR_FORMAT_EIP_FLAGS] = LBR_EIP_FLAGS, | |
24 | [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX, | |
caff2bef PZ |
25 | }; |
26 | ||
c5cc2cd9 SE |
27 | /* |
28 | * Intel LBR_SELECT bits | |
29 | * Intel Vol3a, April 2011, Section 16.7 Table 16-10 | |
30 | * | |
31 | * Hardware branch filter (not available on all CPUs) | |
32 | */ | |
33 | #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */ | |
34 | #define LBR_USER_BIT 1 /* do not capture at ring > 0 */ | |
35 | #define LBR_JCC_BIT 2 /* do not capture conditional branches */ | |
36 | #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */ | |
37 | #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */ | |
38 | #define LBR_RETURN_BIT 5 /* do not capture near returns */ | |
39 | #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */ | |
40 | #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */ | |
41 | #define LBR_FAR_BIT 8 /* do not capture far branches */ | |
e9d7f7cd | 42 | #define LBR_CALL_STACK_BIT 9 /* enable call stack */ |
c5cc2cd9 SE |
43 | |
44 | #define LBR_KERNEL (1 << LBR_KERNEL_BIT) | |
45 | #define LBR_USER (1 << LBR_USER_BIT) | |
46 | #define LBR_JCC (1 << LBR_JCC_BIT) | |
47 | #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT) | |
48 | #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT) | |
49 | #define LBR_RETURN (1 << LBR_RETURN_BIT) | |
50 | #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT) | |
51 | #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT) | |
52 | #define LBR_FAR (1 << LBR_FAR_BIT) | |
e9d7f7cd | 53 | #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT) |
c5cc2cd9 SE |
54 | |
55 | #define LBR_PLM (LBR_KERNEL | LBR_USER) | |
56 | ||
57 | #define LBR_SEL_MASK 0x1ff /* valid bits in LBR_SELECT */ | |
58 | #define LBR_NOT_SUPP -1 /* LBR filter not supported */ | |
59 | #define LBR_IGN 0 /* ignored */ | |
60 | ||
61 | #define LBR_ANY \ | |
62 | (LBR_JCC |\ | |
63 | LBR_REL_CALL |\ | |
64 | LBR_IND_CALL |\ | |
65 | LBR_RETURN |\ | |
66 | LBR_REL_JMP |\ | |
67 | LBR_IND_JMP |\ | |
68 | LBR_FAR) | |
69 | ||
70 | #define LBR_FROM_FLAG_MISPRED (1ULL << 63) | |
135c5612 AK |
71 | #define LBR_FROM_FLAG_IN_TX (1ULL << 62) |
72 | #define LBR_FROM_FLAG_ABORT (1ULL << 61) | |
c5cc2cd9 | 73 | |
3e702ff6 SE |
74 | /* |
75 | * x86control flow change classification | |
76 | * x86control flow changes include branches, interrupts, traps, faults | |
77 | */ | |
78 | enum { | |
e9d7f7cd YZ |
79 | X86_BR_NONE = 0, /* unknown */ |
80 | ||
81 | X86_BR_USER = 1 << 0, /* branch target is user */ | |
82 | X86_BR_KERNEL = 1 << 1, /* branch target is kernel */ | |
83 | ||
84 | X86_BR_CALL = 1 << 2, /* call */ | |
85 | X86_BR_RET = 1 << 3, /* return */ | |
86 | X86_BR_SYSCALL = 1 << 4, /* syscall */ | |
87 | X86_BR_SYSRET = 1 << 5, /* syscall return */ | |
88 | X86_BR_INT = 1 << 6, /* sw interrupt */ | |
89 | X86_BR_IRET = 1 << 7, /* return from interrupt */ | |
90 | X86_BR_JCC = 1 << 8, /* conditional */ | |
91 | X86_BR_JMP = 1 << 9, /* jump */ | |
92 | X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */ | |
93 | X86_BR_IND_CALL = 1 << 11,/* indirect calls */ | |
94 | X86_BR_ABORT = 1 << 12,/* transaction abort */ | |
95 | X86_BR_IN_TX = 1 << 13,/* in transaction */ | |
96 | X86_BR_NO_TX = 1 << 14,/* not in transaction */ | |
97 | X86_BR_CALL_STACK = 1 << 15,/* call stack */ | |
3e702ff6 SE |
98 | }; |
99 | ||
100 | #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL) | |
135c5612 | 101 | #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX) |
3e702ff6 SE |
102 | |
103 | #define X86_BR_ANY \ | |
104 | (X86_BR_CALL |\ | |
105 | X86_BR_RET |\ | |
106 | X86_BR_SYSCALL |\ | |
107 | X86_BR_SYSRET |\ | |
108 | X86_BR_INT |\ | |
109 | X86_BR_IRET |\ | |
110 | X86_BR_JCC |\ | |
111 | X86_BR_JMP |\ | |
112 | X86_BR_IRQ |\ | |
135c5612 | 113 | X86_BR_ABORT |\ |
3e702ff6 SE |
114 | X86_BR_IND_CALL) |
115 | ||
116 | #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY) | |
117 | ||
118 | #define X86_BR_ANY_CALL \ | |
119 | (X86_BR_CALL |\ | |
120 | X86_BR_IND_CALL |\ | |
121 | X86_BR_SYSCALL |\ | |
122 | X86_BR_IRQ |\ | |
123 | X86_BR_INT) | |
124 | ||
125 | static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc); | |
126 | ||
caff2bef PZ |
127 | /* |
128 | * We only support LBR implementations that have FREEZE_LBRS_ON_PMI | |
129 | * otherwise it becomes near impossible to get a reliable stack. | |
130 | */ | |
131 | ||
caff2bef PZ |
132 | static void __intel_pmu_lbr_enable(void) |
133 | { | |
134 | u64 debugctl; | |
89cbc767 | 135 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
60ce0fbd SE |
136 | |
137 | if (cpuc->lbr_sel) | |
138 | wrmsrl(MSR_LBR_SELECT, cpuc->lbr_sel->config); | |
caff2bef PZ |
139 | |
140 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
7c5ecaf7 | 141 | debugctl |= (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); |
caff2bef PZ |
142 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
143 | } | |
144 | ||
145 | static void __intel_pmu_lbr_disable(void) | |
146 | { | |
147 | u64 debugctl; | |
148 | ||
149 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
7c5ecaf7 | 150 | debugctl &= ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); |
caff2bef PZ |
151 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); |
152 | } | |
153 | ||
154 | static void intel_pmu_lbr_reset_32(void) | |
155 | { | |
156 | int i; | |
157 | ||
158 | for (i = 0; i < x86_pmu.lbr_nr; i++) | |
159 | wrmsrl(x86_pmu.lbr_from + i, 0); | |
160 | } | |
161 | ||
162 | static void intel_pmu_lbr_reset_64(void) | |
163 | { | |
164 | int i; | |
165 | ||
166 | for (i = 0; i < x86_pmu.lbr_nr; i++) { | |
167 | wrmsrl(x86_pmu.lbr_from + i, 0); | |
168 | wrmsrl(x86_pmu.lbr_to + i, 0); | |
169 | } | |
170 | } | |
171 | ||
de0428a7 | 172 | void intel_pmu_lbr_reset(void) |
caff2bef | 173 | { |
74846d35 PZ |
174 | if (!x86_pmu.lbr_nr) |
175 | return; | |
176 | ||
8db909a7 | 177 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) |
caff2bef PZ |
178 | intel_pmu_lbr_reset_32(); |
179 | else | |
180 | intel_pmu_lbr_reset_64(); | |
181 | } | |
182 | ||
2a0ad3b3 YZ |
183 | void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in) |
184 | { | |
185 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
186 | ||
187 | if (!x86_pmu.lbr_nr) | |
188 | return; | |
189 | ||
190 | /* | |
191 | * When sampling the branck stack in system-wide, it may be | |
192 | * necessary to flush the stack on context switch. This happens | |
193 | * when the branch stack does not tag its entries with the pid | |
194 | * of the current task. Otherwise it becomes impossible to | |
195 | * associate a branch entry with a task. This ambiguity is more | |
196 | * likely to appear when the branch stack supports priv level | |
197 | * filtering and the user sets it to monitor only at the user | |
198 | * level (which could be a useful measurement in system-wide | |
199 | * mode). In that case, the risk is high of having a branch | |
200 | * stack with branch from multiple tasks. | |
201 | */ | |
202 | if (sched_in) { | |
203 | intel_pmu_lbr_reset(); | |
204 | cpuc->lbr_context = ctx; | |
205 | } | |
206 | } | |
207 | ||
63f0c1d8 YZ |
208 | static inline bool branch_user_callstack(unsigned br_sel) |
209 | { | |
210 | return (br_sel & X86_BR_USER) && (br_sel & X86_BR_CALL_STACK); | |
211 | } | |
212 | ||
de0428a7 | 213 | void intel_pmu_lbr_enable(struct perf_event *event) |
caff2bef | 214 | { |
89cbc767 | 215 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
63f0c1d8 | 216 | struct x86_perf_task_context *task_ctx; |
caff2bef PZ |
217 | |
218 | if (!x86_pmu.lbr_nr) | |
219 | return; | |
220 | ||
caff2bef | 221 | /* |
b83a46e7 PZ |
222 | * Reset the LBR stack if we changed task context to |
223 | * avoid data leaks. | |
caff2bef | 224 | */ |
b83a46e7 | 225 | if (event->ctx->task && cpuc->lbr_context != event->ctx) { |
caff2bef PZ |
226 | intel_pmu_lbr_reset(); |
227 | cpuc->lbr_context = event->ctx; | |
228 | } | |
3e702ff6 | 229 | cpuc->br_sel = event->hw.branch_reg.reg; |
caff2bef | 230 | |
63f0c1d8 YZ |
231 | if (branch_user_callstack(cpuc->br_sel) && event->ctx && |
232 | event->ctx->task_ctx_data) { | |
233 | task_ctx = event->ctx->task_ctx_data; | |
234 | task_ctx->lbr_callstack_users++; | |
235 | } | |
236 | ||
caff2bef | 237 | cpuc->lbr_users++; |
2a0ad3b3 | 238 | perf_sched_cb_inc(event->ctx->pmu); |
caff2bef PZ |
239 | } |
240 | ||
de0428a7 | 241 | void intel_pmu_lbr_disable(struct perf_event *event) |
caff2bef | 242 | { |
89cbc767 | 243 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
63f0c1d8 | 244 | struct x86_perf_task_context *task_ctx; |
caff2bef PZ |
245 | |
246 | if (!x86_pmu.lbr_nr) | |
247 | return; | |
248 | ||
63f0c1d8 YZ |
249 | if (branch_user_callstack(cpuc->br_sel) && event->ctx && |
250 | event->ctx->task_ctx_data) { | |
251 | task_ctx = event->ctx->task_ctx_data; | |
252 | task_ctx->lbr_callstack_users--; | |
253 | } | |
254 | ||
caff2bef | 255 | cpuc->lbr_users--; |
b83a46e7 | 256 | WARN_ON_ONCE(cpuc->lbr_users < 0); |
2a0ad3b3 | 257 | perf_sched_cb_dec(event->ctx->pmu); |
2df202bf | 258 | |
60ce0fbd | 259 | if (cpuc->enabled && !cpuc->lbr_users) { |
2df202bf | 260 | __intel_pmu_lbr_disable(); |
60ce0fbd SE |
261 | /* avoid stale pointer */ |
262 | cpuc->lbr_context = NULL; | |
263 | } | |
caff2bef PZ |
264 | } |
265 | ||
de0428a7 | 266 | void intel_pmu_lbr_enable_all(void) |
caff2bef | 267 | { |
89cbc767 | 268 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
caff2bef PZ |
269 | |
270 | if (cpuc->lbr_users) | |
271 | __intel_pmu_lbr_enable(); | |
272 | } | |
273 | ||
de0428a7 | 274 | void intel_pmu_lbr_disable_all(void) |
caff2bef | 275 | { |
89cbc767 | 276 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
caff2bef PZ |
277 | |
278 | if (cpuc->lbr_users) | |
279 | __intel_pmu_lbr_disable(); | |
280 | } | |
281 | ||
60ce0fbd SE |
282 | /* |
283 | * TOS = most recently recorded branch | |
284 | */ | |
caff2bef PZ |
285 | static inline u64 intel_pmu_lbr_tos(void) |
286 | { | |
287 | u64 tos; | |
288 | ||
289 | rdmsrl(x86_pmu.lbr_tos, tos); | |
290 | ||
291 | return tos; | |
292 | } | |
293 | ||
294 | static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc) | |
295 | { | |
296 | unsigned long mask = x86_pmu.lbr_nr - 1; | |
297 | u64 tos = intel_pmu_lbr_tos(); | |
298 | int i; | |
299 | ||
63fb3f9b | 300 | for (i = 0; i < x86_pmu.lbr_nr; i++) { |
caff2bef PZ |
301 | unsigned long lbr_idx = (tos - i) & mask; |
302 | union { | |
303 | struct { | |
304 | u32 from; | |
305 | u32 to; | |
306 | }; | |
307 | u64 lbr; | |
308 | } msr_lastbranch; | |
309 | ||
310 | rdmsrl(x86_pmu.lbr_from + lbr_idx, msr_lastbranch.lbr); | |
311 | ||
bce38cd5 SE |
312 | cpuc->lbr_entries[i].from = msr_lastbranch.from; |
313 | cpuc->lbr_entries[i].to = msr_lastbranch.to; | |
314 | cpuc->lbr_entries[i].mispred = 0; | |
315 | cpuc->lbr_entries[i].predicted = 0; | |
316 | cpuc->lbr_entries[i].reserved = 0; | |
caff2bef PZ |
317 | } |
318 | cpuc->lbr_stack.nr = i; | |
319 | } | |
320 | ||
caff2bef PZ |
321 | /* |
322 | * Due to lack of segmentation in Linux the effective address (offset) | |
323 | * is the same as the linear address, allowing us to merge the LIP and EIP | |
324 | * LBR formats. | |
325 | */ | |
326 | static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc) | |
327 | { | |
328 | unsigned long mask = x86_pmu.lbr_nr - 1; | |
8db909a7 | 329 | int lbr_format = x86_pmu.intel_cap.lbr_format; |
caff2bef PZ |
330 | u64 tos = intel_pmu_lbr_tos(); |
331 | int i; | |
b7af41a1 | 332 | int out = 0; |
caff2bef | 333 | |
63fb3f9b | 334 | for (i = 0; i < x86_pmu.lbr_nr; i++) { |
caff2bef | 335 | unsigned long lbr_idx = (tos - i) & mask; |
135c5612 AK |
336 | u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0; |
337 | int skip = 0; | |
338 | int lbr_flags = lbr_desc[lbr_format]; | |
caff2bef PZ |
339 | |
340 | rdmsrl(x86_pmu.lbr_from + lbr_idx, from); | |
341 | rdmsrl(x86_pmu.lbr_to + lbr_idx, to); | |
342 | ||
135c5612 | 343 | if (lbr_flags & LBR_EIP_FLAGS) { |
bce38cd5 SE |
344 | mis = !!(from & LBR_FROM_FLAG_MISPRED); |
345 | pred = !mis; | |
135c5612 AK |
346 | skip = 1; |
347 | } | |
348 | if (lbr_flags & LBR_TSX) { | |
349 | in_tx = !!(from & LBR_FROM_FLAG_IN_TX); | |
350 | abort = !!(from & LBR_FROM_FLAG_ABORT); | |
351 | skip = 3; | |
caff2bef | 352 | } |
135c5612 | 353 | from = (u64)((((s64)from) << skip) >> skip); |
caff2bef | 354 | |
b7af41a1 AK |
355 | /* |
356 | * Some CPUs report duplicated abort records, | |
357 | * with the second entry not having an abort bit set. | |
358 | * Skip them here. This loop runs backwards, | |
359 | * so we need to undo the previous record. | |
360 | * If the abort just happened outside the window | |
361 | * the extra entry cannot be removed. | |
362 | */ | |
363 | if (abort && x86_pmu.lbr_double_abort && out > 0) | |
364 | out--; | |
365 | ||
366 | cpuc->lbr_entries[out].from = from; | |
367 | cpuc->lbr_entries[out].to = to; | |
368 | cpuc->lbr_entries[out].mispred = mis; | |
369 | cpuc->lbr_entries[out].predicted = pred; | |
370 | cpuc->lbr_entries[out].in_tx = in_tx; | |
371 | cpuc->lbr_entries[out].abort = abort; | |
372 | cpuc->lbr_entries[out].reserved = 0; | |
373 | out++; | |
caff2bef | 374 | } |
b7af41a1 | 375 | cpuc->lbr_stack.nr = out; |
caff2bef PZ |
376 | } |
377 | ||
de0428a7 | 378 | void intel_pmu_lbr_read(void) |
caff2bef | 379 | { |
89cbc767 | 380 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
caff2bef PZ |
381 | |
382 | if (!cpuc->lbr_users) | |
383 | return; | |
384 | ||
8db909a7 | 385 | if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) |
caff2bef PZ |
386 | intel_pmu_lbr_read_32(cpuc); |
387 | else | |
388 | intel_pmu_lbr_read_64(cpuc); | |
3e702ff6 SE |
389 | |
390 | intel_pmu_lbr_filter(cpuc); | |
391 | } | |
392 | ||
393 | /* | |
394 | * SW filter is used: | |
395 | * - in case there is no HW filter | |
396 | * - in case the HW filter has errata or limitations | |
397 | */ | |
e9d7f7cd | 398 | static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event) |
3e702ff6 SE |
399 | { |
400 | u64 br_type = event->attr.branch_sample_type; | |
401 | int mask = 0; | |
402 | ||
403 | if (br_type & PERF_SAMPLE_BRANCH_USER) | |
404 | mask |= X86_BR_USER; | |
405 | ||
2b923c8f | 406 | if (br_type & PERF_SAMPLE_BRANCH_KERNEL) |
3e702ff6 SE |
407 | mask |= X86_BR_KERNEL; |
408 | ||
409 | /* we ignore BRANCH_HV here */ | |
410 | ||
411 | if (br_type & PERF_SAMPLE_BRANCH_ANY) | |
412 | mask |= X86_BR_ANY; | |
413 | ||
414 | if (br_type & PERF_SAMPLE_BRANCH_ANY_CALL) | |
415 | mask |= X86_BR_ANY_CALL; | |
416 | ||
417 | if (br_type & PERF_SAMPLE_BRANCH_ANY_RETURN) | |
418 | mask |= X86_BR_RET | X86_BR_IRET | X86_BR_SYSRET; | |
419 | ||
420 | if (br_type & PERF_SAMPLE_BRANCH_IND_CALL) | |
421 | mask |= X86_BR_IND_CALL; | |
135c5612 AK |
422 | |
423 | if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX) | |
424 | mask |= X86_BR_ABORT; | |
425 | ||
426 | if (br_type & PERF_SAMPLE_BRANCH_IN_TX) | |
427 | mask |= X86_BR_IN_TX; | |
428 | ||
429 | if (br_type & PERF_SAMPLE_BRANCH_NO_TX) | |
430 | mask |= X86_BR_NO_TX; | |
431 | ||
37548914 AK |
432 | if (br_type & PERF_SAMPLE_BRANCH_COND) |
433 | mask |= X86_BR_JCC; | |
434 | ||
e9d7f7cd YZ |
435 | if (br_type & PERF_SAMPLE_BRANCH_CALL_STACK) { |
436 | if (!x86_pmu_has_lbr_callstack()) | |
437 | return -EOPNOTSUPP; | |
438 | if (mask & ~(X86_BR_USER | X86_BR_KERNEL)) | |
439 | return -EINVAL; | |
440 | mask |= X86_BR_CALL | X86_BR_IND_CALL | X86_BR_RET | | |
441 | X86_BR_CALL_STACK; | |
442 | } | |
443 | ||
3e702ff6 SE |
444 | /* |
445 | * stash actual user request into reg, it may | |
446 | * be used by fixup code for some CPU | |
447 | */ | |
448 | event->hw.branch_reg.reg = mask; | |
e9d7f7cd | 449 | return 0; |
caff2bef PZ |
450 | } |
451 | ||
60ce0fbd SE |
452 | /* |
453 | * setup the HW LBR filter | |
454 | * Used only when available, may not be enough to disambiguate | |
455 | * all branches, may need the help of the SW filter | |
456 | */ | |
457 | static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event) | |
458 | { | |
459 | struct hw_perf_event_extra *reg; | |
460 | u64 br_type = event->attr.branch_sample_type; | |
27ac905b YZ |
461 | u64 mask = 0, v; |
462 | int i; | |
60ce0fbd | 463 | |
27ac905b YZ |
464 | for (i = 0; i < PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE; i++) { |
465 | if (!(br_type & (1ULL << i))) | |
60ce0fbd SE |
466 | continue; |
467 | ||
27ac905b | 468 | v = x86_pmu.lbr_sel_map[i]; |
60ce0fbd SE |
469 | if (v == LBR_NOT_SUPP) |
470 | return -EOPNOTSUPP; | |
60ce0fbd | 471 | |
3e702ff6 SE |
472 | if (v != LBR_IGN) |
473 | mask |= v; | |
60ce0fbd SE |
474 | } |
475 | reg = &event->hw.branch_reg; | |
476 | reg->idx = EXTRA_REG_LBR; | |
477 | ||
e9d7f7cd YZ |
478 | /* |
479 | * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate | |
480 | * in suppress mode. So LBR_SELECT should be set to | |
481 | * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK) | |
482 | */ | |
483 | reg->config = mask ^ x86_pmu.lbr_sel_mask; | |
60ce0fbd SE |
484 | |
485 | return 0; | |
486 | } | |
487 | ||
60ce0fbd SE |
488 | int intel_pmu_setup_lbr_filter(struct perf_event *event) |
489 | { | |
3e702ff6 | 490 | int ret = 0; |
60ce0fbd SE |
491 | |
492 | /* | |
493 | * no LBR on this PMU | |
494 | */ | |
495 | if (!x86_pmu.lbr_nr) | |
496 | return -EOPNOTSUPP; | |
497 | ||
498 | /* | |
3e702ff6 | 499 | * setup SW LBR filter |
60ce0fbd | 500 | */ |
e9d7f7cd YZ |
501 | ret = intel_pmu_setup_sw_lbr_filter(event); |
502 | if (ret) | |
503 | return ret; | |
3e702ff6 SE |
504 | |
505 | /* | |
506 | * setup HW LBR filter, if any | |
507 | */ | |
508 | if (x86_pmu.lbr_sel_map) | |
509 | ret = intel_pmu_setup_hw_lbr_filter(event); | |
510 | ||
511 | return ret; | |
512 | } | |
513 | ||
514 | /* | |
515 | * return the type of control flow change at address "from" | |
516 | * intruction is not necessarily a branch (in case of interrupt). | |
517 | * | |
518 | * The branch type returned also includes the priv level of the | |
519 | * target of the control flow change (X86_BR_USER, X86_BR_KERNEL). | |
520 | * | |
521 | * If a branch type is unknown OR the instruction cannot be | |
522 | * decoded (e.g., text page not present), then X86_BR_NONE is | |
523 | * returned. | |
524 | */ | |
135c5612 | 525 | static int branch_type(unsigned long from, unsigned long to, int abort) |
3e702ff6 SE |
526 | { |
527 | struct insn insn; | |
528 | void *addr; | |
6ba48ff4 | 529 | int bytes_read, bytes_left; |
3e702ff6 SE |
530 | int ret = X86_BR_NONE; |
531 | int ext, to_plm, from_plm; | |
532 | u8 buf[MAX_INSN_SIZE]; | |
533 | int is64 = 0; | |
534 | ||
535 | to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER; | |
536 | from_plm = kernel_ip(from) ? X86_BR_KERNEL : X86_BR_USER; | |
537 | ||
538 | /* | |
539 | * maybe zero if lbr did not fill up after a reset by the time | |
540 | * we get a PMU interrupt | |
541 | */ | |
542 | if (from == 0 || to == 0) | |
543 | return X86_BR_NONE; | |
544 | ||
135c5612 AK |
545 | if (abort) |
546 | return X86_BR_ABORT | to_plm; | |
547 | ||
3e702ff6 SE |
548 | if (from_plm == X86_BR_USER) { |
549 | /* | |
550 | * can happen if measuring at the user level only | |
551 | * and we interrupt in a kernel thread, e.g., idle. | |
552 | */ | |
553 | if (!current->mm) | |
554 | return X86_BR_NONE; | |
555 | ||
556 | /* may fail if text not present */ | |
6ba48ff4 DH |
557 | bytes_left = copy_from_user_nmi(buf, (void __user *)from, |
558 | MAX_INSN_SIZE); | |
559 | bytes_read = MAX_INSN_SIZE - bytes_left; | |
560 | if (!bytes_read) | |
3e702ff6 SE |
561 | return X86_BR_NONE; |
562 | ||
563 | addr = buf; | |
6e15eb3b PZ |
564 | } else { |
565 | /* | |
566 | * The LBR logs any address in the IP, even if the IP just | |
567 | * faulted. This means userspace can control the from address. | |
568 | * Ensure we don't blindy read any address by validating it is | |
569 | * a known text address. | |
570 | */ | |
6ba48ff4 | 571 | if (kernel_text_address(from)) { |
6e15eb3b | 572 | addr = (void *)from; |
6ba48ff4 DH |
573 | /* |
574 | * Assume we can get the maximum possible size | |
575 | * when grabbing kernel data. This is not | |
576 | * _strictly_ true since we could possibly be | |
577 | * executing up next to a memory hole, but | |
578 | * it is very unlikely to be a problem. | |
579 | */ | |
580 | bytes_read = MAX_INSN_SIZE; | |
581 | } else { | |
6e15eb3b | 582 | return X86_BR_NONE; |
6ba48ff4 | 583 | } |
6e15eb3b | 584 | } |
3e702ff6 SE |
585 | |
586 | /* | |
587 | * decoder needs to know the ABI especially | |
588 | * on 64-bit systems running 32-bit apps | |
589 | */ | |
590 | #ifdef CONFIG_X86_64 | |
591 | is64 = kernel_ip((unsigned long)addr) || !test_thread_flag(TIF_IA32); | |
592 | #endif | |
6ba48ff4 | 593 | insn_init(&insn, addr, bytes_read, is64); |
3e702ff6 | 594 | insn_get_opcode(&insn); |
6ba48ff4 DH |
595 | if (!insn.opcode.got) |
596 | return X86_BR_ABORT; | |
3e702ff6 SE |
597 | |
598 | switch (insn.opcode.bytes[0]) { | |
599 | case 0xf: | |
600 | switch (insn.opcode.bytes[1]) { | |
601 | case 0x05: /* syscall */ | |
602 | case 0x34: /* sysenter */ | |
603 | ret = X86_BR_SYSCALL; | |
604 | break; | |
605 | case 0x07: /* sysret */ | |
606 | case 0x35: /* sysexit */ | |
607 | ret = X86_BR_SYSRET; | |
608 | break; | |
609 | case 0x80 ... 0x8f: /* conditional */ | |
610 | ret = X86_BR_JCC; | |
611 | break; | |
612 | default: | |
613 | ret = X86_BR_NONE; | |
614 | } | |
615 | break; | |
616 | case 0x70 ... 0x7f: /* conditional */ | |
617 | ret = X86_BR_JCC; | |
618 | break; | |
619 | case 0xc2: /* near ret */ | |
620 | case 0xc3: /* near ret */ | |
621 | case 0xca: /* far ret */ | |
622 | case 0xcb: /* far ret */ | |
623 | ret = X86_BR_RET; | |
624 | break; | |
625 | case 0xcf: /* iret */ | |
626 | ret = X86_BR_IRET; | |
627 | break; | |
628 | case 0xcc ... 0xce: /* int */ | |
629 | ret = X86_BR_INT; | |
630 | break; | |
631 | case 0xe8: /* call near rel */ | |
632 | case 0x9a: /* call far absolute */ | |
633 | ret = X86_BR_CALL; | |
634 | break; | |
635 | case 0xe0 ... 0xe3: /* loop jmp */ | |
636 | ret = X86_BR_JCC; | |
637 | break; | |
638 | case 0xe9 ... 0xeb: /* jmp */ | |
639 | ret = X86_BR_JMP; | |
640 | break; | |
641 | case 0xff: /* call near absolute, call far absolute ind */ | |
642 | insn_get_modrm(&insn); | |
643 | ext = (insn.modrm.bytes[0] >> 3) & 0x7; | |
644 | switch (ext) { | |
645 | case 2: /* near ind call */ | |
646 | case 3: /* far ind call */ | |
647 | ret = X86_BR_IND_CALL; | |
648 | break; | |
649 | case 4: | |
650 | case 5: | |
651 | ret = X86_BR_JMP; | |
652 | break; | |
653 | } | |
654 | break; | |
655 | default: | |
656 | ret = X86_BR_NONE; | |
60ce0fbd SE |
657 | } |
658 | /* | |
3e702ff6 SE |
659 | * interrupts, traps, faults (and thus ring transition) may |
660 | * occur on any instructions. Thus, to classify them correctly, | |
661 | * we need to first look at the from and to priv levels. If they | |
662 | * are different and to is in the kernel, then it indicates | |
663 | * a ring transition. If the from instruction is not a ring | |
664 | * transition instr (syscall, systenter, int), then it means | |
665 | * it was a irq, trap or fault. | |
666 | * | |
667 | * we have no way of detecting kernel to kernel faults. | |
668 | */ | |
669 | if (from_plm == X86_BR_USER && to_plm == X86_BR_KERNEL | |
670 | && ret != X86_BR_SYSCALL && ret != X86_BR_INT) | |
671 | ret = X86_BR_IRQ; | |
672 | ||
673 | /* | |
674 | * branch priv level determined by target as | |
675 | * is done by HW when LBR_SELECT is implemented | |
60ce0fbd | 676 | */ |
3e702ff6 SE |
677 | if (ret != X86_BR_NONE) |
678 | ret |= to_plm; | |
60ce0fbd | 679 | |
3e702ff6 SE |
680 | return ret; |
681 | } | |
682 | ||
683 | /* | |
684 | * implement actual branch filter based on user demand. | |
685 | * Hardware may not exactly satisfy that request, thus | |
686 | * we need to inspect opcodes. Mismatched branches are | |
687 | * discarded. Therefore, the number of branches returned | |
688 | * in PERF_SAMPLE_BRANCH_STACK sample may vary. | |
689 | */ | |
690 | static void | |
691 | intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) | |
692 | { | |
693 | u64 from, to; | |
694 | int br_sel = cpuc->br_sel; | |
695 | int i, j, type; | |
696 | bool compress = false; | |
697 | ||
698 | /* if sampling all branches, then nothing to filter */ | |
699 | if ((br_sel & X86_BR_ALL) == X86_BR_ALL) | |
700 | return; | |
701 | ||
702 | for (i = 0; i < cpuc->lbr_stack.nr; i++) { | |
703 | ||
704 | from = cpuc->lbr_entries[i].from; | |
705 | to = cpuc->lbr_entries[i].to; | |
706 | ||
135c5612 AK |
707 | type = branch_type(from, to, cpuc->lbr_entries[i].abort); |
708 | if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) { | |
709 | if (cpuc->lbr_entries[i].in_tx) | |
710 | type |= X86_BR_IN_TX; | |
711 | else | |
712 | type |= X86_BR_NO_TX; | |
713 | } | |
3e702ff6 SE |
714 | |
715 | /* if type does not correspond, then discard */ | |
716 | if (type == X86_BR_NONE || (br_sel & type) != type) { | |
717 | cpuc->lbr_entries[i].from = 0; | |
718 | compress = true; | |
719 | } | |
720 | } | |
721 | ||
722 | if (!compress) | |
723 | return; | |
724 | ||
725 | /* remove all entries with from=0 */ | |
726 | for (i = 0; i < cpuc->lbr_stack.nr; ) { | |
727 | if (!cpuc->lbr_entries[i].from) { | |
728 | j = i; | |
729 | while (++j < cpuc->lbr_stack.nr) | |
730 | cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j]; | |
731 | cpuc->lbr_stack.nr--; | |
732 | if (!cpuc->lbr_entries[i].from) | |
733 | continue; | |
734 | } | |
735 | i++; | |
736 | } | |
60ce0fbd SE |
737 | } |
738 | ||
c5cc2cd9 SE |
739 | /* |
740 | * Map interface branch filters onto LBR filters | |
741 | */ | |
27ac905b YZ |
742 | static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE] = { |
743 | [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, | |
744 | [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, | |
745 | [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, | |
746 | [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, | |
747 | [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_REL_JMP | |
748 | | LBR_IND_JMP | LBR_FAR, | |
c5cc2cd9 SE |
749 | /* |
750 | * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches | |
751 | */ | |
27ac905b | 752 | [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = |
c5cc2cd9 SE |
753 | LBR_REL_CALL | LBR_IND_CALL | LBR_REL_JMP | LBR_IND_JMP | LBR_FAR, |
754 | /* | |
755 | * NHM/WSM erratum: must include IND_JMP to capture IND_CALL | |
756 | */ | |
27ac905b YZ |
757 | [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL | LBR_IND_JMP, |
758 | [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, | |
c5cc2cd9 SE |
759 | }; |
760 | ||
27ac905b YZ |
761 | static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE] = { |
762 | [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, | |
763 | [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, | |
764 | [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, | |
765 | [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, | |
766 | [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR, | |
767 | [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL | |
768 | | LBR_FAR, | |
769 | [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, | |
770 | [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, | |
c5cc2cd9 SE |
771 | }; |
772 | ||
e9d7f7cd YZ |
773 | static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE] = { |
774 | [PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY, | |
775 | [PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER, | |
776 | [PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL, | |
777 | [PERF_SAMPLE_BRANCH_HV_SHIFT] = LBR_IGN, | |
778 | [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT] = LBR_RETURN | LBR_FAR, | |
779 | [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT] = LBR_REL_CALL | LBR_IND_CALL | |
780 | | LBR_FAR, | |
781 | [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT] = LBR_IND_CALL, | |
782 | [PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC, | |
783 | [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] = LBR_REL_CALL | LBR_IND_CALL | |
784 | | LBR_RETURN | LBR_CALL_STACK, | |
785 | }; | |
786 | ||
c5cc2cd9 | 787 | /* core */ |
066ce64c | 788 | void __init intel_pmu_lbr_init_core(void) |
caff2bef | 789 | { |
caff2bef | 790 | x86_pmu.lbr_nr = 4; |
225ce539 SE |
791 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
792 | x86_pmu.lbr_from = MSR_LBR_CORE_FROM; | |
793 | x86_pmu.lbr_to = MSR_LBR_CORE_TO; | |
c5cc2cd9 | 794 | |
3e702ff6 SE |
795 | /* |
796 | * SW branch filter usage: | |
797 | * - compensate for lack of HW filter | |
798 | */ | |
c5cc2cd9 | 799 | pr_cont("4-deep LBR, "); |
caff2bef PZ |
800 | } |
801 | ||
c5cc2cd9 | 802 | /* nehalem/westmere */ |
066ce64c | 803 | void __init intel_pmu_lbr_init_nhm(void) |
caff2bef | 804 | { |
caff2bef | 805 | x86_pmu.lbr_nr = 16; |
225ce539 SE |
806 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
807 | x86_pmu.lbr_from = MSR_LBR_NHM_FROM; | |
808 | x86_pmu.lbr_to = MSR_LBR_NHM_TO; | |
c5cc2cd9 SE |
809 | |
810 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; | |
811 | x86_pmu.lbr_sel_map = nhm_lbr_sel_map; | |
812 | ||
3e702ff6 SE |
813 | /* |
814 | * SW branch filter usage: | |
815 | * - workaround LBR_SEL errata (see above) | |
816 | * - support syscall, sysret capture. | |
817 | * That requires LBR_FAR but that means far | |
818 | * jmp need to be filtered out | |
819 | */ | |
c5cc2cd9 | 820 | pr_cont("16-deep LBR, "); |
caff2bef PZ |
821 | } |
822 | ||
c5cc2cd9 | 823 | /* sandy bridge */ |
066ce64c | 824 | void __init intel_pmu_lbr_init_snb(void) |
c5cc2cd9 SE |
825 | { |
826 | x86_pmu.lbr_nr = 16; | |
827 | x86_pmu.lbr_tos = MSR_LBR_TOS; | |
828 | x86_pmu.lbr_from = MSR_LBR_NHM_FROM; | |
829 | x86_pmu.lbr_to = MSR_LBR_NHM_TO; | |
830 | ||
831 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; | |
832 | x86_pmu.lbr_sel_map = snb_lbr_sel_map; | |
833 | ||
3e702ff6 SE |
834 | /* |
835 | * SW branch filter usage: | |
836 | * - support syscall, sysret capture. | |
837 | * That requires LBR_FAR but that means far | |
838 | * jmp need to be filtered out | |
839 | */ | |
c5cc2cd9 SE |
840 | pr_cont("16-deep LBR, "); |
841 | } | |
842 | ||
e9d7f7cd YZ |
843 | /* haswell */ |
844 | void intel_pmu_lbr_init_hsw(void) | |
845 | { | |
846 | x86_pmu.lbr_nr = 16; | |
847 | x86_pmu.lbr_tos = MSR_LBR_TOS; | |
848 | x86_pmu.lbr_from = MSR_LBR_NHM_FROM; | |
849 | x86_pmu.lbr_to = MSR_LBR_NHM_TO; | |
850 | ||
851 | x86_pmu.lbr_sel_mask = LBR_SEL_MASK; | |
852 | x86_pmu.lbr_sel_map = hsw_lbr_sel_map; | |
853 | ||
854 | pr_cont("16-deep LBR, "); | |
855 | } | |
856 | ||
c5cc2cd9 | 857 | /* atom */ |
066ce64c | 858 | void __init intel_pmu_lbr_init_atom(void) |
caff2bef | 859 | { |
88c9a65e SE |
860 | /* |
861 | * only models starting at stepping 10 seems | |
862 | * to have an operational LBR which can freeze | |
863 | * on PMU interrupt | |
864 | */ | |
3ec18cd8 SE |
865 | if (boot_cpu_data.x86_model == 28 |
866 | && boot_cpu_data.x86_mask < 10) { | |
88c9a65e SE |
867 | pr_cont("LBR disabled due to erratum"); |
868 | return; | |
869 | } | |
870 | ||
caff2bef | 871 | x86_pmu.lbr_nr = 8; |
225ce539 SE |
872 | x86_pmu.lbr_tos = MSR_LBR_TOS; |
873 | x86_pmu.lbr_from = MSR_LBR_CORE_FROM; | |
874 | x86_pmu.lbr_to = MSR_LBR_CORE_TO; | |
c5cc2cd9 | 875 | |
3e702ff6 SE |
876 | /* |
877 | * SW branch filter usage: | |
878 | * - compensate for lack of HW filter | |
879 | */ | |
c5cc2cd9 | 880 | pr_cont("8-deep LBR, "); |
caff2bef | 881 | } |