[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / perfctr-watchdog.c

/*
 * local apic based NMI watchdog for various CPUs.
 *
 * This file also handles reservation of performance counters for coordination
 * with other users (like oprofile).
 *
 * Note that these events normally don't tick when the CPU idles. This means
 * the frequency varies with CPU load.
 *
 * Original code for K7/P6 written by Keith Owens
 *
 */

#include <linux/percpu.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <asm/nmi.h>
#include <linux/kprobes.h>

#include <asm/apic.h>
#include <asm/perf_event.h>

/*
 * this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
 * offset from MSR_P4_BSU_ESCR0.
 *
 * It will be the max for all platforms (for now)
 */
#define NMI_MAX_COUNTER_BITS 66

/*
 * perfctr_nmi_owner tracks the ownership of the perfctr registers:
 * evtsel_nmi_owner tracks the ownership of the event selection
 * - different performance counters/ event selection may be reserved for
 *   different subsystems this reservation system just tries to coordinate
 *   things a little
 */
static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);

/* converts an msr to an appropriate reservation bit */
static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
{
	/* returns the bit offset of the performance counter register */
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if (msr >= MSR_F15H_PERF_CTR)
			return (msr - MSR_F15H_PERF_CTR) >> 1;
		return msr - MSR_K7_PERFCTR0;
	case X86_VENDOR_INTEL:
		if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
			return msr - MSR_ARCH_PERFMON_PERFCTR0;

		switch (boot_cpu_data.x86) {
		case 6:
			return msr - MSR_P6_PERFCTR0;
		case 11:
			return msr - MSR_KNC_PERFCTR0;
		case 15:
			return msr - MSR_P4_BPU_PERFCTR0;
		}
	}
	return 0;
}

/*
 * converts an msr to an appropriate reservation bit
 * returns the bit offset of the event selection register
 */
static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
{
	/* returns the bit offset of the event selection register */
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if (msr >= MSR_F15H_PERF_CTL)
			return (msr - MSR_F15H_PERF_CTL) >> 1;
		return msr - MSR_K7_EVNTSEL0;
	case X86_VENDOR_INTEL:
		if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
			return msr - MSR_ARCH_PERFMON_EVENTSEL0;

		switch (boot_cpu_data.x86) {
		case 6:
			return msr - MSR_P6_EVNTSEL0;
		case 11:
			return msr - MSR_KNC_EVNTSEL0;
		case 15:
			return msr - MSR_P4_BSU_ESCR0;
		}
	}
	return 0;

}

/* checks for a bit availability (hack for oprofile) */
int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
{
	BUG_ON(counter > NMI_MAX_COUNTER_BITS);

	return !test_bit(counter, perfctr_nmi_owner);
}
EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);

int reserve_perfctr_nmi(unsigned int msr)
{
	unsigned int counter;

	counter = nmi_perfctr_msr_to_bit(msr);
	/* register not managed by the allocator? */
	if (counter > NMI_MAX_COUNTER_BITS)
		return 1;

	if (!test_and_set_bit(counter, perfctr_nmi_owner))
		return 1;
	return 0;
}
EXPORT_SYMBOL(reserve_perfctr_nmi);

void release_perfctr_nmi(unsigned int msr)
{
	unsigned int counter;

	counter = nmi_perfctr_msr_to_bit(msr);
	/* register not managed by the allocator? */
	if (counter > NMI_MAX_COUNTER_BITS)
		return;

	clear_bit(counter, perfctr_nmi_owner);
}
EXPORT_SYMBOL(release_perfctr_nmi);

int reserve_evntsel_nmi(unsigned int msr)
{
	unsigned int counter;

	counter = nmi_evntsel_msr_to_bit(msr);
	/* register not managed by the allocator? */
	if (counter > NMI_MAX_COUNTER_BITS)
		return 1;

	if (!test_and_set_bit(counter, evntsel_nmi_owner))
		return 1;
	return 0;
}
EXPORT_SYMBOL(reserve_evntsel_nmi);

void release_evntsel_nmi(unsigned int msr)
{
	unsigned int counter;

	counter = nmi_evntsel_msr_to_bit(msr);
	/* register not managed by the allocator? */
	if (counter > NMI_MAX_COUNTER_BITS)
		return;

	clear_bit(counter, evntsel_nmi_owner);
}
EXPORT_SYMBOL(release_evntsel_nmi);
Commit	Line	Data
47a486cc CG	1	/*
	2	* local apic based NMI watchdog for various CPUs.
	3	*
	4	* This file also handles reservation of performance counters for coordination
	5	* with other users (like oprofile).
	6	*
	7	* Note that these events normally don't tick when the CPU idles. This means
	8	* the frequency varies with CPU load.
	9	*
	10	* Original code for K7/P6 written by Keith Owens
	11	*
	12	*/
09198e68 AK	13
	14	#include <linux/percpu.h>
	15	#include <linux/module.h>
	16	#include <linux/kernel.h>
	17	#include <linux/bitops.h>
	18	#include <linux/smp.h>
4a7863cc	19	#include <asm/nmi.h>
8b1fa1d7 IM	20	#include <linux/kprobes.h>
8b1fa1d7 IM	21
09198e68	22	#include <asm/apic.h>
cdd6c482	23	#include <asm/perf_event.h>
09198e68	24
47a486cc CG	25	/*
	26	* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
	27	* offset from MSR_P4_BSU_ESCR0.
	28	*
	29	* It will be the max for all platforms (for now)
09198e68 AK	30	*/
	31	#define NMI_MAX_COUNTER_BITS 66
	32
47a486cc CG	33	/*
47a486cc CG	34	* perfctr_nmi_owner tracks the ownership of the perfctr registers:
09198e68 AK	35	* evtsel_nmi_owner tracks the ownership of the event selection
	36	* - different performance counters/ event selection may be reserved for
	37	* different subsystems this reservation system just tries to coordinate
	38	* things a little
	39	*/
	40	static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
	41	static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);
	42
09198e68 AK	43	/* converts an msr to an appropriate reservation bit */
	44	static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
	45	{
5dcccd8d AK	46	/* returns the bit offset of the performance counter register */
	47	switch (boot_cpu_data.x86_vendor) {
	48	case X86_VENDOR_AMD:
69d8e1e8 RR	49	if (msr >= MSR_F15H_PERF_CTR)
69d8e1e8 RR	50	return (msr - MSR_F15H_PERF_CTR) >> 1;
8bdbd962	51	return msr - MSR_K7_PERFCTR0;
5dcccd8d AK	52	case X86_VENDOR_INTEL:
5dcccd8d AK	53	if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
8bdbd962	54	return msr - MSR_ARCH_PERFMON_PERFCTR0;
5dcccd8d AK	55
	56	switch (boot_cpu_data.x86) {
	57	case 6:
8bdbd962	58	return msr - MSR_P6_PERFCTR0;
e717bf4e VW	59	case 11:
e717bf4e VW	60	return msr - MSR_KNC_PERFCTR0;
5dcccd8d	61	case 15:
8bdbd962	62	return msr - MSR_P4_BPU_PERFCTR0;
5dcccd8d AK	63	}
	64	}
	65	return 0;
09198e68 AK	66	}
09198e68 AK	67
47a486cc CG	68	/*
	69	* converts an msr to an appropriate reservation bit
	70	* returns the bit offset of the event selection register
	71	*/
09198e68 AK	72	static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
09198e68 AK	73	{
5dcccd8d AK	74	/* returns the bit offset of the event selection register */
	75	switch (boot_cpu_data.x86_vendor) {
	76	case X86_VENDOR_AMD:
69d8e1e8 RR	77	if (msr >= MSR_F15H_PERF_CTL)
69d8e1e8 RR	78	return (msr - MSR_F15H_PERF_CTL) >> 1;
8bdbd962	79	return msr - MSR_K7_EVNTSEL0;
5dcccd8d AK	80	case X86_VENDOR_INTEL:
5dcccd8d AK	81	if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
8bdbd962	82	return msr - MSR_ARCH_PERFMON_EVENTSEL0;
5dcccd8d AK	83
	84	switch (boot_cpu_data.x86) {
	85	case 6:
8bdbd962	86	return msr - MSR_P6_EVNTSEL0;
e717bf4e VW	87	case 11:
e717bf4e VW	88	return msr - MSR_KNC_EVNTSEL0;
5dcccd8d	89	case 15:
8bdbd962	90	return msr - MSR_P4_BSU_ESCR0;
5dcccd8d AK	91	}
	92	}
	93	return 0;
	94
09198e68 AK	95	}
	96
	97	/* checks for a bit availability (hack for oprofile) */
	98	int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
	99	{
	100	BUG_ON(counter > NMI_MAX_COUNTER_BITS);
	101
8bdbd962	102	return !test_bit(counter, perfctr_nmi_owner);
09198e68	103	}
47a486cc	104	EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
09198e68 AK	105
	106	int reserve_perfctr_nmi(unsigned int msr)
	107	{
	108	unsigned int counter;
	109
	110	counter = nmi_perfctr_msr_to_bit(msr);
124d395f SE	111	/* register not managed by the allocator? */
	112	if (counter > NMI_MAX_COUNTER_BITS)
	113	return 1;
09198e68 AK	114
	115	if (!test_and_set_bit(counter, perfctr_nmi_owner))
	116	return 1;
	117	return 0;
	118	}
47a486cc	119	EXPORT_SYMBOL(reserve_perfctr_nmi);
09198e68 AK	120
	121	void release_perfctr_nmi(unsigned int msr)
	122	{
	123	unsigned int counter;
	124
	125	counter = nmi_perfctr_msr_to_bit(msr);
124d395f SE	126	/* register not managed by the allocator? */
	127	if (counter > NMI_MAX_COUNTER_BITS)
	128	return;
09198e68 AK	129
	130	clear_bit(counter, perfctr_nmi_owner);
	131	}
47a486cc	132	EXPORT_SYMBOL(release_perfctr_nmi);
09198e68 AK	133
	134	int reserve_evntsel_nmi(unsigned int msr)
	135	{
	136	unsigned int counter;
	137
	138	counter = nmi_evntsel_msr_to_bit(msr);
124d395f SE	139	/* register not managed by the allocator? */
	140	if (counter > NMI_MAX_COUNTER_BITS)
	141	return 1;
09198e68 AK	142
	143	if (!test_and_set_bit(counter, evntsel_nmi_owner))
	144	return 1;
	145	return 0;
	146	}
47a486cc	147	EXPORT_SYMBOL(reserve_evntsel_nmi);
09198e68 AK	148
	149	void release_evntsel_nmi(unsigned int msr)
	150	{
	151	unsigned int counter;
	152
	153	counter = nmi_evntsel_msr_to_bit(msr);
124d395f SE	154	/* register not managed by the allocator? */
	155	if (counter > NMI_MAX_COUNTER_BITS)
	156	return;
09198e68 AK	157
	158	clear_bit(counter, evntsel_nmi_owner);
	159	}
09198e68	160	EXPORT_SYMBOL(release_evntsel_nmi);