]>
Commit | Line | Data |
---|---|---|
8167aae6 PG |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Intel Transactional Synchronization Extensions (TSX) control. | |
4 | * | |
5 | * Copyright (C) 2019 Intel Corporation | |
6 | * | |
7 | * Author: | |
8 | * Pawan Gupta <pawan.kumar.gupta@linux.intel.com> | |
9 | */ | |
10 | ||
11 | #include <linux/cpufeature.h> | |
12 | ||
13 | #include <asm/cmdline.h> | |
14 | ||
15 | #include "cpu.h" | |
16 | ||
17 | enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED; | |
18 | ||
19 | void tsx_disable(void) | |
20 | { | |
21 | u64 tsx; | |
22 | ||
23 | rdmsrl(MSR_IA32_TSX_CTRL, tsx); | |
24 | ||
25 | /* Force all transactions to immediately abort */ | |
26 | tsx |= TSX_CTRL_RTM_DISABLE; | |
27 | ||
28 | /* | |
29 | * Ensure TSX support is not enumerated in CPUID. | |
30 | * This is visible to userspace and will ensure they | |
31 | * do not waste resources trying TSX transactions that | |
32 | * will always abort. | |
33 | */ | |
34 | tsx |= TSX_CTRL_CPUID_CLEAR; | |
35 | ||
36 | wrmsrl(MSR_IA32_TSX_CTRL, tsx); | |
37 | } | |
38 | ||
39 | void tsx_enable(void) | |
40 | { | |
41 | u64 tsx; | |
42 | ||
43 | rdmsrl(MSR_IA32_TSX_CTRL, tsx); | |
44 | ||
45 | /* Enable the RTM feature in the cpu */ | |
46 | tsx &= ~TSX_CTRL_RTM_DISABLE; | |
47 | ||
48 | /* | |
49 | * Ensure TSX support is enumerated in CPUID. | |
50 | * This is visible to userspace and will ensure they | |
51 | * can enumerate and use the TSX feature. | |
52 | */ | |
53 | tsx &= ~TSX_CTRL_CPUID_CLEAR; | |
54 | ||
55 | wrmsrl(MSR_IA32_TSX_CTRL, tsx); | |
56 | } | |
57 | ||
58 | static bool __init tsx_ctrl_is_supported(void) | |
59 | { | |
60 | u64 ia32_cap = x86_read_arch_cap_msr(); | |
61 | ||
62 | /* | |
63 | * TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this | |
64 | * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES. | |
65 | * | |
66 | * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a | |
67 | * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES | |
68 | * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get | |
69 | * MSR_IA32_TSX_CTRL support even after a microcode update. Thus, | |
70 | * tsx= cmdline requests will do nothing on CPUs without | |
71 | * MSR_IA32_TSX_CTRL support. | |
72 | */ | |
73 | return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR); | |
74 | } | |
75 | ||
76 | void __init tsx_init(void) | |
77 | { | |
78 | char arg[4] = {}; | |
79 | int ret; | |
80 | ||
81 | if (!tsx_ctrl_is_supported()) | |
82 | return; | |
83 | ||
84 | ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg)); | |
85 | if (ret >= 0) { | |
86 | if (!strcmp(arg, "on")) { | |
87 | tsx_ctrl_state = TSX_CTRL_ENABLE; | |
88 | } else if (!strcmp(arg, "off")) { | |
89 | tsx_ctrl_state = TSX_CTRL_DISABLE; | |
90 | } else { | |
91 | tsx_ctrl_state = TSX_CTRL_DISABLE; | |
92 | pr_err("tsx: invalid option, defaulting to off\n"); | |
93 | } | |
94 | } else { | |
95 | /* tsx= not provided, defaulting to off */ | |
96 | tsx_ctrl_state = TSX_CTRL_DISABLE; | |
97 | } | |
98 | ||
99 | if (tsx_ctrl_state == TSX_CTRL_DISABLE) { | |
100 | tsx_disable(); | |
101 | ||
102 | /* | |
103 | * tsx_disable() will change the state of the | |
104 | * RTM CPUID bit. Clear it here since it is now | |
105 | * expected to be not set. | |
106 | */ | |
107 | setup_clear_cpu_cap(X86_FEATURE_RTM); | |
108 | } else if (tsx_ctrl_state == TSX_CTRL_ENABLE) { | |
109 | ||
110 | /* | |
111 | * HW defaults TSX to be enabled at bootup. | |
112 | * We may still need the TSX enable support | |
113 | * during init for special cases like | |
114 | * kexec after TSX is disabled. | |
115 | */ | |
116 | tsx_enable(); | |
117 | ||
118 | /* | |
119 | * tsx_enable() will change the state of the | |
120 | * RTM CPUID bit. Force it here since it is now | |
121 | * expected to be set. | |
122 | */ | |
123 | setup_force_cpu_cap(X86_FEATURE_RTM); | |
124 | } | |
125 | } |