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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
da6b737b SAS |
2 | /* |
3 | * Architecture specific OF callbacks. | |
4 | */ | |
5 | #include <linux/bootmem.h> | |
69c60c88 | 6 | #include <linux/export.h> |
da6b737b | 7 | #include <linux/io.h> |
19c4f5f7 | 8 | #include <linux/interrupt.h> |
da6b737b SAS |
9 | #include <linux/list.h> |
10 | #include <linux/of.h> | |
11 | #include <linux/of_fdt.h> | |
3879a6f3 | 12 | #include <linux/of_address.h> |
da6b737b | 13 | #include <linux/of_platform.h> |
96e0a079 | 14 | #include <linux/of_irq.h> |
fd5e9826 | 15 | #include <linux/libfdt.h> |
da6b737b | 16 | #include <linux/slab.h> |
96e0a079 SAS |
17 | #include <linux/pci.h> |
18 | #include <linux/of_pci.h> | |
977cb76d | 19 | #include <linux/initrd.h> |
da6b737b | 20 | |
f7a0c786 | 21 | #include <asm/irqdomain.h> |
ffb9fc68 | 22 | #include <asm/hpet.h> |
3879a6f3 | 23 | #include <asm/apic.h> |
96e0a079 | 24 | #include <asm/pci_x86.h> |
ba904f06 | 25 | #include <asm/setup.h> |
95d76acc | 26 | #include <asm/i8259.h> |
19c4f5f7 | 27 | |
3879a6f3 | 28 | __initdata u64 initial_dtb; |
da6b737b | 29 | char __initdata cmd_line[COMMAND_LINE_SIZE]; |
19c4f5f7 | 30 | |
3879a6f3 SAS |
31 | int __initdata of_ioapic; |
32 | ||
da6b737b SAS |
33 | void __init early_init_dt_scan_chosen_arch(unsigned long node) |
34 | { | |
35 | BUG(); | |
36 | } | |
37 | ||
38 | void __init early_init_dt_add_memory_arch(u64 base, u64 size) | |
39 | { | |
40 | BUG(); | |
41 | } | |
42 | ||
43 | void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) | |
44 | { | |
45 | return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); | |
46 | } | |
47 | ||
48 | void __init add_dtb(u64 data) | |
49 | { | |
3879a6f3 SAS |
50 | initial_dtb = data + offsetof(struct setup_data, data); |
51 | } | |
52 | ||
9079b353 SAS |
53 | /* |
54 | * CE4100 ids. Will be moved to machine_device_initcall() once we have it. | |
55 | */ | |
56 | static struct of_device_id __initdata ce4100_ids[] = { | |
57 | { .compatible = "intel,ce4100-cp", }, | |
58 | { .compatible = "isa", }, | |
59 | { .compatible = "pci", }, | |
60 | {}, | |
61 | }; | |
62 | ||
63 | static int __init add_bus_probe(void) | |
64 | { | |
4a66b1d9 | 65 | if (!of_have_populated_dt()) |
9079b353 SAS |
66 | return 0; |
67 | ||
68 | return of_platform_bus_probe(NULL, ce4100_ids, NULL); | |
69 | } | |
d54b675a | 70 | device_initcall(add_bus_probe); |
9079b353 | 71 | |
96e0a079 | 72 | #ifdef CONFIG_PCI |
3d5fe5a6 BH |
73 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
74 | { | |
75 | struct device_node *np; | |
76 | ||
77 | for_each_node_by_type(np, "pci") { | |
78 | const void *prop; | |
79 | unsigned int bus_min; | |
80 | ||
81 | prop = of_get_property(np, "bus-range", NULL); | |
82 | if (!prop) | |
83 | continue; | |
84 | bus_min = be32_to_cpup(prop); | |
85 | if (bus->number == bus_min) | |
86 | return np; | |
87 | } | |
88 | return NULL; | |
89 | } | |
90 | ||
96e0a079 SAS |
91 | static int x86_of_pci_irq_enable(struct pci_dev *dev) |
92 | { | |
96e0a079 SAS |
93 | u32 virq; |
94 | int ret; | |
95 | u8 pin; | |
96 | ||
97 | ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | |
98 | if (ret) | |
99 | return ret; | |
100 | if (!pin) | |
101 | return 0; | |
102 | ||
16b84e5a | 103 | virq = of_irq_parse_and_map_pci(dev, 0, 0); |
96e0a079 SAS |
104 | if (virq == 0) |
105 | return -EINVAL; | |
106 | dev->irq = virq; | |
107 | return 0; | |
108 | } | |
109 | ||
110 | static void x86_of_pci_irq_disable(struct pci_dev *dev) | |
111 | { | |
112 | } | |
113 | ||
148f9bb8 | 114 | void x86_of_pci_init(void) |
96e0a079 | 115 | { |
96e0a079 SAS |
116 | pcibios_enable_irq = x86_of_pci_irq_enable; |
117 | pcibios_disable_irq = x86_of_pci_irq_disable; | |
96e0a079 SAS |
118 | } |
119 | #endif | |
120 | ||
ffb9fc68 SAS |
121 | static void __init dtb_setup_hpet(void) |
122 | { | |
4a66b1d9 | 123 | #ifdef CONFIG_HPET_TIMER |
ffb9fc68 SAS |
124 | struct device_node *dn; |
125 | struct resource r; | |
126 | int ret; | |
127 | ||
128 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet"); | |
129 | if (!dn) | |
130 | return; | |
131 | ret = of_address_to_resource(dn, 0, &r); | |
132 | if (ret) { | |
133 | WARN_ON(1); | |
134 | return; | |
135 | } | |
136 | hpet_address = r.start; | |
4a66b1d9 | 137 | #endif |
ffb9fc68 SAS |
138 | } |
139 | ||
3879a6f3 SAS |
140 | static void __init dtb_lapic_setup(void) |
141 | { | |
142 | #ifdef CONFIG_X86_LOCAL_APIC | |
a906fdaa TG |
143 | struct device_node *dn; |
144 | struct resource r; | |
145 | int ret; | |
146 | ||
147 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic"); | |
148 | if (!dn) | |
3879a6f3 SAS |
149 | return; |
150 | ||
a906fdaa TG |
151 | ret = of_address_to_resource(dn, 0, &r); |
152 | if (WARN_ON(ret)) | |
153 | return; | |
154 | ||
155 | /* Did the boot loader setup the local APIC ? */ | |
93984fbd | 156 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
a906fdaa TG |
157 | if (apic_force_enable(r.start)) |
158 | return; | |
159 | } | |
3879a6f3 SAS |
160 | smp_found_config = 1; |
161 | pic_mode = 1; | |
a906fdaa | 162 | register_lapic_address(r.start); |
3879a6f3 | 163 | generic_processor_info(boot_cpu_physical_apicid, |
a906fdaa | 164 | GET_APIC_VERSION(apic_read(APIC_LVR))); |
3879a6f3 SAS |
165 | #endif |
166 | } | |
167 | ||
168 | #ifdef CONFIG_X86_IO_APIC | |
169 | static unsigned int ioapic_id; | |
170 | ||
bcc7c124 SAS |
171 | struct of_ioapic_type { |
172 | u32 out_type; | |
173 | u32 trigger; | |
174 | u32 polarity; | |
175 | }; | |
176 | ||
177 | static struct of_ioapic_type of_ioapic_type[] = | |
178 | { | |
179 | { | |
180 | .out_type = IRQ_TYPE_EDGE_RISING, | |
181 | .trigger = IOAPIC_EDGE, | |
182 | .polarity = 1, | |
183 | }, | |
184 | { | |
185 | .out_type = IRQ_TYPE_LEVEL_LOW, | |
186 | .trigger = IOAPIC_LEVEL, | |
187 | .polarity = 0, | |
188 | }, | |
189 | { | |
190 | .out_type = IRQ_TYPE_LEVEL_HIGH, | |
191 | .trigger = IOAPIC_LEVEL, | |
192 | .polarity = 1, | |
193 | }, | |
194 | { | |
195 | .out_type = IRQ_TYPE_EDGE_FALLING, | |
196 | .trigger = IOAPIC_EDGE, | |
197 | .polarity = 0, | |
198 | }, | |
199 | }; | |
200 | ||
d32932d0 JL |
201 | static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, |
202 | unsigned int nr_irqs, void *arg) | |
bcc7c124 | 203 | { |
0c3cd0b2 | 204 | struct irq_fwspec *fwspec = (struct irq_fwspec *)arg; |
bcc7c124 | 205 | struct of_ioapic_type *it; |
d32932d0 | 206 | struct irq_alloc_info tmp; |
0c3cd0b2 | 207 | int type_index; |
bcc7c124 | 208 | |
0c3cd0b2 | 209 | if (WARN_ON(fwspec->param_count < 2)) |
bcc7c124 | 210 | return -EINVAL; |
0c3cd0b2 IG |
211 | |
212 | type_index = fwspec->param[1]; | |
213 | if (type_index >= ARRAY_SIZE(of_ioapic_type)) | |
bcc7c124 SAS |
214 | return -EINVAL; |
215 | ||
0c3cd0b2 | 216 | it = &of_ioapic_type[type_index]; |
d32932d0 JL |
217 | ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity); |
218 | tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain)); | |
0c3cd0b2 | 219 | tmp.ioapic_pin = fwspec->param[0]; |
bcc7c124 | 220 | |
d32932d0 | 221 | return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp); |
bcc7c124 SAS |
222 | } |
223 | ||
f7a0c786 TG |
224 | static const struct irq_domain_ops ioapic_irq_domain_ops = { |
225 | .alloc = dt_irqdomain_alloc, | |
226 | .free = mp_irqdomain_free, | |
227 | .activate = mp_irqdomain_activate, | |
228 | .deactivate = mp_irqdomain_deactivate, | |
b4e51854 GL |
229 | }; |
230 | ||
facd8fdb | 231 | static void __init dtb_add_ioapic(struct device_node *dn) |
ece3234a | 232 | { |
facd8fdb | 233 | struct resource r; |
ece3234a | 234 | int ret; |
facd8fdb JL |
235 | struct ioapic_domain_cfg cfg = { |
236 | .type = IOAPIC_DOMAIN_DYNAMIC, | |
237 | .ops = &ioapic_irq_domain_ops, | |
238 | .dev = dn, | |
239 | }; | |
240 | ||
241 | ret = of_address_to_resource(dn, 0, &r); | |
242 | if (ret) { | |
db15e7f2 | 243 | printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); |
facd8fdb | 244 | return; |
ece3234a | 245 | } |
facd8fdb | 246 | mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); |
ece3234a SAS |
247 | } |
248 | ||
facd8fdb | 249 | static void __init dtb_ioapic_setup(void) |
bcc7c124 | 250 | { |
facd8fdb | 251 | struct device_node *dn; |
bcc7c124 | 252 | |
facd8fdb JL |
253 | for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic") |
254 | dtb_add_ioapic(dn); | |
255 | ||
256 | if (nr_ioapics) { | |
257 | of_ioapic = 1; | |
bcc7c124 SAS |
258 | return; |
259 | } | |
facd8fdb JL |
260 | printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); |
261 | } | |
262 | #else | |
263 | static void __init dtb_ioapic_setup(void) {} | |
264 | #endif | |
bcc7c124 | 265 | |
facd8fdb JL |
266 | static void __init dtb_apic_setup(void) |
267 | { | |
268 | dtb_lapic_setup(); | |
269 | dtb_ioapic_setup(); | |
bcc7c124 SAS |
270 | } |
271 | ||
facd8fdb JL |
272 | #ifdef CONFIG_OF_FLATTREE |
273 | static void __init x86_flattree_get_config(void) | |
bcc7c124 | 274 | { |
facd8fdb JL |
275 | u32 size, map_len; |
276 | void *dt; | |
bcc7c124 | 277 | |
facd8fdb | 278 | if (!initial_dtb) |
bcc7c124 SAS |
279 | return; |
280 | ||
facd8fdb JL |
281 | map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128); |
282 | ||
fd5e9826 IG |
283 | dt = early_memremap(initial_dtb, map_len); |
284 | size = fdt_totalsize(dt); | |
facd8fdb | 285 | if (map_len < size) { |
8d4a40bc | 286 | early_memunmap(dt, map_len); |
fd5e9826 | 287 | dt = early_memremap(initial_dtb, size); |
facd8fdb | 288 | map_len = size; |
bcc7c124 | 289 | } |
facd8fdb | 290 | |
fd5e9826 | 291 | early_init_dt_verify(dt); |
facd8fdb | 292 | unflatten_and_copy_device_tree(); |
8d4a40bc | 293 | early_memunmap(dt, map_len); |
bcc7c124 SAS |
294 | } |
295 | #else | |
facd8fdb | 296 | static inline void x86_flattree_get_config(void) { } |
bcc7c124 | 297 | #endif |
facd8fdb JL |
298 | |
299 | void __init x86_dtb_init(void) | |
300 | { | |
301 | x86_flattree_get_config(); | |
302 | ||
303 | if (!of_have_populated_dt()) | |
304 | return; | |
305 | ||
306 | dtb_setup_hpet(); | |
307 | dtb_apic_setup(); | |
308 | } |