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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
da6b737b SAS |
2 | /* |
3 | * Architecture specific OF callbacks. | |
4 | */ | |
5 | #include <linux/bootmem.h> | |
69c60c88 | 6 | #include <linux/export.h> |
da6b737b | 7 | #include <linux/io.h> |
19c4f5f7 | 8 | #include <linux/interrupt.h> |
da6b737b SAS |
9 | #include <linux/list.h> |
10 | #include <linux/of.h> | |
11 | #include <linux/of_fdt.h> | |
3879a6f3 | 12 | #include <linux/of_address.h> |
da6b737b | 13 | #include <linux/of_platform.h> |
96e0a079 | 14 | #include <linux/of_irq.h> |
da6b737b | 15 | #include <linux/slab.h> |
96e0a079 SAS |
16 | #include <linux/pci.h> |
17 | #include <linux/of_pci.h> | |
977cb76d | 18 | #include <linux/initrd.h> |
da6b737b | 19 | |
f7a0c786 | 20 | #include <asm/irqdomain.h> |
ffb9fc68 | 21 | #include <asm/hpet.h> |
3879a6f3 | 22 | #include <asm/apic.h> |
96e0a079 | 23 | #include <asm/pci_x86.h> |
ba904f06 | 24 | #include <asm/setup.h> |
95d76acc | 25 | #include <asm/i8259.h> |
19c4f5f7 | 26 | |
3879a6f3 | 27 | __initdata u64 initial_dtb; |
da6b737b | 28 | char __initdata cmd_line[COMMAND_LINE_SIZE]; |
19c4f5f7 | 29 | |
3879a6f3 SAS |
30 | int __initdata of_ioapic; |
31 | ||
da6b737b SAS |
32 | void __init early_init_dt_scan_chosen_arch(unsigned long node) |
33 | { | |
34 | BUG(); | |
35 | } | |
36 | ||
37 | void __init early_init_dt_add_memory_arch(u64 base, u64 size) | |
38 | { | |
39 | BUG(); | |
40 | } | |
41 | ||
42 | void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) | |
43 | { | |
44 | return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); | |
45 | } | |
46 | ||
47 | void __init add_dtb(u64 data) | |
48 | { | |
3879a6f3 SAS |
49 | initial_dtb = data + offsetof(struct setup_data, data); |
50 | } | |
51 | ||
9079b353 SAS |
52 | /* |
53 | * CE4100 ids. Will be moved to machine_device_initcall() once we have it. | |
54 | */ | |
55 | static struct of_device_id __initdata ce4100_ids[] = { | |
56 | { .compatible = "intel,ce4100-cp", }, | |
57 | { .compatible = "isa", }, | |
58 | { .compatible = "pci", }, | |
59 | {}, | |
60 | }; | |
61 | ||
62 | static int __init add_bus_probe(void) | |
63 | { | |
4a66b1d9 | 64 | if (!of_have_populated_dt()) |
9079b353 SAS |
65 | return 0; |
66 | ||
67 | return of_platform_bus_probe(NULL, ce4100_ids, NULL); | |
68 | } | |
d54b675a | 69 | device_initcall(add_bus_probe); |
9079b353 | 70 | |
96e0a079 | 71 | #ifdef CONFIG_PCI |
3d5fe5a6 BH |
72 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
73 | { | |
74 | struct device_node *np; | |
75 | ||
76 | for_each_node_by_type(np, "pci") { | |
77 | const void *prop; | |
78 | unsigned int bus_min; | |
79 | ||
80 | prop = of_get_property(np, "bus-range", NULL); | |
81 | if (!prop) | |
82 | continue; | |
83 | bus_min = be32_to_cpup(prop); | |
84 | if (bus->number == bus_min) | |
85 | return np; | |
86 | } | |
87 | return NULL; | |
88 | } | |
89 | ||
96e0a079 SAS |
90 | static int x86_of_pci_irq_enable(struct pci_dev *dev) |
91 | { | |
96e0a079 SAS |
92 | u32 virq; |
93 | int ret; | |
94 | u8 pin; | |
95 | ||
96 | ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); | |
97 | if (ret) | |
98 | return ret; | |
99 | if (!pin) | |
100 | return 0; | |
101 | ||
16b84e5a | 102 | virq = of_irq_parse_and_map_pci(dev, 0, 0); |
96e0a079 SAS |
103 | if (virq == 0) |
104 | return -EINVAL; | |
105 | dev->irq = virq; | |
106 | return 0; | |
107 | } | |
108 | ||
109 | static void x86_of_pci_irq_disable(struct pci_dev *dev) | |
110 | { | |
111 | } | |
112 | ||
148f9bb8 | 113 | void x86_of_pci_init(void) |
96e0a079 | 114 | { |
96e0a079 SAS |
115 | pcibios_enable_irq = x86_of_pci_irq_enable; |
116 | pcibios_disable_irq = x86_of_pci_irq_disable; | |
96e0a079 SAS |
117 | } |
118 | #endif | |
119 | ||
ffb9fc68 SAS |
120 | static void __init dtb_setup_hpet(void) |
121 | { | |
4a66b1d9 | 122 | #ifdef CONFIG_HPET_TIMER |
ffb9fc68 SAS |
123 | struct device_node *dn; |
124 | struct resource r; | |
125 | int ret; | |
126 | ||
127 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet"); | |
128 | if (!dn) | |
129 | return; | |
130 | ret = of_address_to_resource(dn, 0, &r); | |
131 | if (ret) { | |
132 | WARN_ON(1); | |
133 | return; | |
134 | } | |
135 | hpet_address = r.start; | |
4a66b1d9 | 136 | #endif |
ffb9fc68 SAS |
137 | } |
138 | ||
3879a6f3 SAS |
139 | static void __init dtb_lapic_setup(void) |
140 | { | |
141 | #ifdef CONFIG_X86_LOCAL_APIC | |
a906fdaa TG |
142 | struct device_node *dn; |
143 | struct resource r; | |
144 | int ret; | |
145 | ||
146 | dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic"); | |
147 | if (!dn) | |
3879a6f3 SAS |
148 | return; |
149 | ||
a906fdaa TG |
150 | ret = of_address_to_resource(dn, 0, &r); |
151 | if (WARN_ON(ret)) | |
152 | return; | |
153 | ||
154 | /* Did the boot loader setup the local APIC ? */ | |
93984fbd | 155 | if (!boot_cpu_has(X86_FEATURE_APIC)) { |
a906fdaa TG |
156 | if (apic_force_enable(r.start)) |
157 | return; | |
158 | } | |
3879a6f3 SAS |
159 | smp_found_config = 1; |
160 | pic_mode = 1; | |
a906fdaa | 161 | register_lapic_address(r.start); |
3879a6f3 | 162 | generic_processor_info(boot_cpu_physical_apicid, |
a906fdaa | 163 | GET_APIC_VERSION(apic_read(APIC_LVR))); |
3879a6f3 SAS |
164 | #endif |
165 | } | |
166 | ||
167 | #ifdef CONFIG_X86_IO_APIC | |
168 | static unsigned int ioapic_id; | |
169 | ||
bcc7c124 SAS |
170 | struct of_ioapic_type { |
171 | u32 out_type; | |
172 | u32 trigger; | |
173 | u32 polarity; | |
174 | }; | |
175 | ||
176 | static struct of_ioapic_type of_ioapic_type[] = | |
177 | { | |
178 | { | |
179 | .out_type = IRQ_TYPE_EDGE_RISING, | |
180 | .trigger = IOAPIC_EDGE, | |
181 | .polarity = 1, | |
182 | }, | |
183 | { | |
184 | .out_type = IRQ_TYPE_LEVEL_LOW, | |
185 | .trigger = IOAPIC_LEVEL, | |
186 | .polarity = 0, | |
187 | }, | |
188 | { | |
189 | .out_type = IRQ_TYPE_LEVEL_HIGH, | |
190 | .trigger = IOAPIC_LEVEL, | |
191 | .polarity = 1, | |
192 | }, | |
193 | { | |
194 | .out_type = IRQ_TYPE_EDGE_FALLING, | |
195 | .trigger = IOAPIC_EDGE, | |
196 | .polarity = 0, | |
197 | }, | |
198 | }; | |
199 | ||
d32932d0 JL |
200 | static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, |
201 | unsigned int nr_irqs, void *arg) | |
bcc7c124 | 202 | { |
d32932d0 | 203 | struct of_phandle_args *irq_data = (void *)arg; |
bcc7c124 | 204 | struct of_ioapic_type *it; |
d32932d0 | 205 | struct irq_alloc_info tmp; |
bcc7c124 | 206 | |
d32932d0 | 207 | if (WARN_ON(irq_data->args_count < 2)) |
bcc7c124 | 208 | return -EINVAL; |
d32932d0 | 209 | if (irq_data->args[1] >= ARRAY_SIZE(of_ioapic_type)) |
bcc7c124 SAS |
210 | return -EINVAL; |
211 | ||
d32932d0 JL |
212 | it = &of_ioapic_type[irq_data->args[1]]; |
213 | ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity); | |
214 | tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain)); | |
215 | tmp.ioapic_pin = irq_data->args[0]; | |
bcc7c124 | 216 | |
d32932d0 | 217 | return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp); |
bcc7c124 SAS |
218 | } |
219 | ||
f7a0c786 TG |
220 | static const struct irq_domain_ops ioapic_irq_domain_ops = { |
221 | .alloc = dt_irqdomain_alloc, | |
222 | .free = mp_irqdomain_free, | |
223 | .activate = mp_irqdomain_activate, | |
224 | .deactivate = mp_irqdomain_deactivate, | |
b4e51854 GL |
225 | }; |
226 | ||
facd8fdb | 227 | static void __init dtb_add_ioapic(struct device_node *dn) |
ece3234a | 228 | { |
facd8fdb | 229 | struct resource r; |
ece3234a | 230 | int ret; |
facd8fdb JL |
231 | struct ioapic_domain_cfg cfg = { |
232 | .type = IOAPIC_DOMAIN_DYNAMIC, | |
233 | .ops = &ioapic_irq_domain_ops, | |
234 | .dev = dn, | |
235 | }; | |
236 | ||
237 | ret = of_address_to_resource(dn, 0, &r); | |
238 | if (ret) { | |
db15e7f2 | 239 | printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); |
facd8fdb | 240 | return; |
ece3234a | 241 | } |
facd8fdb | 242 | mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); |
ece3234a SAS |
243 | } |
244 | ||
facd8fdb | 245 | static void __init dtb_ioapic_setup(void) |
bcc7c124 | 246 | { |
facd8fdb | 247 | struct device_node *dn; |
bcc7c124 | 248 | |
facd8fdb JL |
249 | for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic") |
250 | dtb_add_ioapic(dn); | |
251 | ||
252 | if (nr_ioapics) { | |
253 | of_ioapic = 1; | |
bcc7c124 SAS |
254 | return; |
255 | } | |
facd8fdb JL |
256 | printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); |
257 | } | |
258 | #else | |
259 | static void __init dtb_ioapic_setup(void) {} | |
260 | #endif | |
bcc7c124 | 261 | |
facd8fdb JL |
262 | static void __init dtb_apic_setup(void) |
263 | { | |
264 | dtb_lapic_setup(); | |
265 | dtb_ioapic_setup(); | |
bcc7c124 SAS |
266 | } |
267 | ||
facd8fdb JL |
268 | #ifdef CONFIG_OF_FLATTREE |
269 | static void __init x86_flattree_get_config(void) | |
bcc7c124 | 270 | { |
facd8fdb JL |
271 | u32 size, map_len; |
272 | void *dt; | |
bcc7c124 | 273 | |
facd8fdb | 274 | if (!initial_dtb) |
bcc7c124 SAS |
275 | return; |
276 | ||
facd8fdb JL |
277 | map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128); |
278 | ||
279 | initial_boot_params = dt = early_memremap(initial_dtb, map_len); | |
280 | size = of_get_flat_dt_size(); | |
281 | if (map_len < size) { | |
8d4a40bc | 282 | early_memunmap(dt, map_len); |
facd8fdb JL |
283 | initial_boot_params = dt = early_memremap(initial_dtb, size); |
284 | map_len = size; | |
bcc7c124 | 285 | } |
facd8fdb JL |
286 | |
287 | unflatten_and_copy_device_tree(); | |
8d4a40bc | 288 | early_memunmap(dt, map_len); |
bcc7c124 SAS |
289 | } |
290 | #else | |
facd8fdb | 291 | static inline void x86_flattree_get_config(void) { } |
bcc7c124 | 292 | #endif |
facd8fdb JL |
293 | |
294 | void __init x86_dtb_init(void) | |
295 | { | |
296 | x86_flattree_get_config(); | |
297 | ||
298 | if (!of_have_populated_dt()) | |
299 | return; | |
300 | ||
301 | dtb_setup_hpet(); | |
302 | dtb_apic_setup(); | |
303 | } |