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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
dfa4698c AK |
2 | /* Various workarounds for chipset bugs. |
3 | This code runs very early and can't use the regular PCI subsystem | |
4 | The entries are keyed to PCI bridges which usually identify chipsets | |
5 | uniquely. | |
6 | This is only for whole classes of chipsets with specific problems which | |
7 | need early invasive action (e.g. before the timers are initialized). | |
8 | Most PCI device specific workarounds can be done later and should be | |
9 | in standard PCI quirks | |
10 | Mainboard specific bugs should be handled by DMI entries. | |
11 | CPU specific bugs in setup.c */ | |
12 | ||
13 | #include <linux/pci.h> | |
14 | #include <linux/acpi.h> | |
abb2bafd | 15 | #include <linux/delay.h> |
dfa4698c | 16 | #include <linux/pci_ids.h> |
abb2bafd LW |
17 | #include <linux/bcma/bcma.h> |
18 | #include <linux/bcma/bcma_regs.h> | |
630b3aff | 19 | #include <linux/platform_data/x86/apple.h> |
814c5f1f | 20 | #include <drm/i915_drm.h> |
dfa4698c | 21 | #include <asm/pci-direct.h> |
dfa4698c | 22 | #include <asm/dma.h> |
54ef3400 AK |
23 | #include <asm/io_apic.h> |
24 | #include <asm/apic.h> | |
62187910 | 25 | #include <asm/hpet.h> |
46a7fa27 | 26 | #include <asm/iommu.h> |
1d9b16d1 | 27 | #include <asm/gart.h> |
03bbcb2e | 28 | #include <asm/irq_remapping.h> |
abb2bafd LW |
29 | #include <asm/early_ioremap.h> |
30 | ||
dc5e44a1 GP |
31 | static void __init early_pci_clear_msi(int bus, int slot, int func) |
32 | { | |
33 | int pos; | |
34 | u16 ctrl; | |
35 | ||
36 | if (likely(!pci_early_clear_msi)) | |
37 | return; | |
38 | ||
39 | pr_info_once("Clearing MSI/MSI-X enable bits early in boot (quirk)\n"); | |
40 | ||
41 | pos = pci_early_find_cap(bus, slot, func, PCI_CAP_ID_MSI); | |
42 | if (pos) { | |
43 | ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS); | |
44 | ctrl &= ~PCI_MSI_FLAGS_ENABLE; | |
45 | write_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS, ctrl); | |
46 | ||
47 | /* Read again to flush previous write */ | |
48 | ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSI_FLAGS); | |
49 | } | |
50 | ||
51 | pos = pci_early_find_cap(bus, slot, func, PCI_CAP_ID_MSIX); | |
52 | if (pos) { | |
53 | ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS); | |
54 | ctrl &= ~PCI_MSIX_FLAGS_ENABLE; | |
55 | write_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS, ctrl); | |
56 | ||
57 | /* Read again to flush previous write */ | |
58 | ctrl = read_pci_config_16(bus, slot, func, pos + PCI_MSIX_FLAGS); | |
59 | } | |
60 | } | |
61 | ||
c6b48324 NH |
62 | static void __init fix_hypertransport_config(int num, int slot, int func) |
63 | { | |
64 | u32 htcfg; | |
65 | /* | |
66 | * we found a hypertransport bus | |
67 | * make sure that we are broadcasting | |
68 | * interrupts to all cpus on the ht bus | |
69 | * if we're using extended apic ids | |
70 | */ | |
71 | htcfg = read_pci_config(num, slot, func, 0x68); | |
72 | if (htcfg & (1 << 18)) { | |
7bcbc78d NH |
73 | printk(KERN_INFO "Detected use of extended apic ids " |
74 | "on hypertransport bus\n"); | |
c6b48324 | 75 | if ((htcfg & (1 << 17)) == 0) { |
7bcbc78d NH |
76 | printk(KERN_INFO "Enabling hypertransport extended " |
77 | "apic interrupt broadcast\n"); | |
78 | printk(KERN_INFO "Note this is a bios bug, " | |
79 | "please contact your hw vendor\n"); | |
c6b48324 NH |
80 | htcfg |= (1 << 17); |
81 | write_pci_config(num, slot, func, 0x68, htcfg); | |
82 | } | |
83 | } | |
84 | ||
85 | ||
86 | } | |
87 | ||
88 | static void __init via_bugs(int num, int slot, int func) | |
dfa4698c | 89 | { |
966396d3 | 90 | #ifdef CONFIG_GART_IOMMU |
c987d12f | 91 | if ((max_pfn > MAX_DMA32_PFN || force_iommu) && |
0440d4c0 | 92 | !gart_iommu_aperture_allowed) { |
dfa4698c | 93 | printk(KERN_INFO |
54ef3400 AK |
94 | "Looks like a VIA chipset. Disabling IOMMU." |
95 | " Override with iommu=allowed\n"); | |
0440d4c0 | 96 | gart_iommu_aperture_disabled = 1; |
dfa4698c AK |
97 | } |
98 | #endif | |
99 | } | |
100 | ||
101 | #ifdef CONFIG_ACPI | |
03d0d20e | 102 | #ifdef CONFIG_X86_IO_APIC |
dfa4698c | 103 | |
15a58ed1 | 104 | static int __init nvidia_hpet_check(struct acpi_table_header *header) |
dfa4698c | 105 | { |
dfa4698c AK |
106 | return 0; |
107 | } | |
03d0d20e JG |
108 | #endif /* CONFIG_X86_IO_APIC */ |
109 | #endif /* CONFIG_ACPI */ | |
dfa4698c | 110 | |
c6b48324 | 111 | static void __init nvidia_bugs(int num, int slot, int func) |
dfa4698c AK |
112 | { |
113 | #ifdef CONFIG_ACPI | |
54ef3400 | 114 | #ifdef CONFIG_X86_IO_APIC |
447d29d1 LW |
115 | /* |
116 | * Only applies to Nvidia root ports (bus 0) and not to | |
117 | * Nvidia graphics cards with PCI ports on secondary buses. | |
118 | */ | |
119 | if (num) | |
120 | return; | |
121 | ||
dfa4698c AK |
122 | /* |
123 | * All timer overrides on Nvidia are | |
124 | * wrong unless HPET is enabled. | |
fa18f477 AK |
125 | * Unfortunately that's not true on many Asus boards. |
126 | * We don't know yet how to detect this automatically, but | |
127 | * at least allow a command line override. | |
dfa4698c | 128 | */ |
fa18f477 AK |
129 | if (acpi_use_timer_override) |
130 | return; | |
131 | ||
fe699336 | 132 | if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) { |
dfa4698c AK |
133 | acpi_skip_timer_override = 1; |
134 | printk(KERN_INFO "Nvidia board " | |
135 | "detected. Ignoring ACPI " | |
136 | "timer override.\n"); | |
fa18f477 AK |
137 | printk(KERN_INFO "If you got timer trouble " |
138 | "try acpi_use_timer_override\n"); | |
dfa4698c | 139 | } |
54ef3400 | 140 | #endif |
dfa4698c AK |
141 | #endif |
142 | /* RED-PEN skip them on mptables too? */ | |
143 | ||
144 | } | |
145 | ||
26adcfbf AH |
146 | #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC) |
147 | static u32 __init ati_ixp4x0_rev(int num, int slot, int func) | |
33fb0e4e AH |
148 | { |
149 | u32 d; | |
150 | u8 b; | |
151 | ||
152 | b = read_pci_config_byte(num, slot, func, 0xac); | |
153 | b &= ~(1<<5); | |
154 | write_pci_config_byte(num, slot, func, 0xac, b); | |
155 | ||
156 | d = read_pci_config(num, slot, func, 0x70); | |
157 | d |= 1<<8; | |
158 | write_pci_config(num, slot, func, 0x70, d); | |
159 | ||
160 | d = read_pci_config(num, slot, func, 0x8); | |
161 | d &= 0xff; | |
162 | return d; | |
163 | } | |
164 | ||
165 | static void __init ati_bugs(int num, int slot, int func) | |
166 | { | |
33fb0e4e AH |
167 | u32 d; |
168 | u8 b; | |
169 | ||
170 | if (acpi_use_timer_override) | |
171 | return; | |
172 | ||
173 | d = ati_ixp4x0_rev(num, slot, func); | |
174 | if (d < 0x82) | |
175 | acpi_skip_timer_override = 1; | |
176 | else { | |
177 | /* check for IRQ0 interrupt swap */ | |
178 | outb(0x72, 0xcd6); b = inb(0xcd7); | |
179 | if (!(b & 0x2)) | |
180 | acpi_skip_timer_override = 1; | |
181 | } | |
182 | ||
183 | if (acpi_skip_timer_override) { | |
184 | printk(KERN_INFO "SB4X0 revision 0x%x\n", d); | |
185 | printk(KERN_INFO "Ignoring ACPI timer override.\n"); | |
186 | printk(KERN_INFO "If you got timer trouble " | |
187 | "try acpi_use_timer_override\n"); | |
188 | } | |
33fb0e4e AH |
189 | } |
190 | ||
26adcfbf AH |
191 | static u32 __init ati_sbx00_rev(int num, int slot, int func) |
192 | { | |
7f74f8f2 | 193 | u32 d; |
26adcfbf | 194 | |
26adcfbf AH |
195 | d = read_pci_config(num, slot, func, 0x8); |
196 | d &= 0xff; | |
26adcfbf AH |
197 | |
198 | return d; | |
199 | } | |
200 | ||
201 | static void __init ati_bugs_contd(int num, int slot, int func) | |
202 | { | |
203 | u32 d, rev; | |
204 | ||
26adcfbf | 205 | rev = ati_sbx00_rev(num, slot, func); |
7f74f8f2 AH |
206 | if (rev >= 0x40) |
207 | acpi_fix_pin2_polarity = 1; | |
208 | ||
1d3e09a3 AH |
209 | /* |
210 | * SB600: revisions 0x11, 0x12, 0x13, 0x14, ... | |
211 | * SB700: revisions 0x39, 0x3a, ... | |
212 | * SB800: revisions 0x40, 0x41, ... | |
213 | */ | |
214 | if (rev >= 0x39) | |
26adcfbf AH |
215 | return; |
216 | ||
7f74f8f2 AH |
217 | if (acpi_use_timer_override) |
218 | return; | |
219 | ||
26adcfbf AH |
220 | /* check for IRQ0 interrupt swap */ |
221 | d = read_pci_config(num, slot, func, 0x64); | |
222 | if (!(d & (1<<14))) | |
223 | acpi_skip_timer_override = 1; | |
224 | ||
225 | if (acpi_skip_timer_override) { | |
226 | printk(KERN_INFO "SB600 revision 0x%x\n", rev); | |
227 | printk(KERN_INFO "Ignoring ACPI timer override.\n"); | |
228 | printk(KERN_INFO "If you got timer trouble " | |
229 | "try acpi_use_timer_override\n"); | |
230 | } | |
231 | } | |
232 | #else | |
233 | static void __init ati_bugs(int num, int slot, int func) | |
234 | { | |
235 | } | |
236 | ||
237 | static void __init ati_bugs_contd(int num, int slot, int func) | |
238 | { | |
239 | } | |
240 | #endif | |
241 | ||
03bbcb2e NH |
242 | static void __init intel_remapping_check(int num, int slot, int func) |
243 | { | |
244 | u8 revision; | |
803075db | 245 | u16 device; |
03bbcb2e | 246 | |
803075db | 247 | device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); |
03bbcb2e NH |
248 | revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID); |
249 | ||
250 | /* | |
6f8a1b33 NH |
251 | * Revision <= 13 of all triggering devices id in this quirk |
252 | * have a problem draining interrupts when irq remapping is | |
253 | * enabled, and should be flagged as broken. Additionally | |
254 | * revision 0x22 of device id 0x3405 has this problem. | |
03bbcb2e | 255 | */ |
6f8a1b33 | 256 | if (revision <= 0x13) |
03bbcb2e | 257 | set_irq_remapping_broken(); |
6f8a1b33 | 258 | else if (device == 0x3405 && revision == 0x22) |
803075db | 259 | set_irq_remapping_broken(); |
03bbcb2e NH |
260 | } |
261 | ||
814c5f1f JB |
262 | /* |
263 | * Systems with Intel graphics controllers set aside memory exclusively | |
264 | * for gfx driver use. This memory is not marked in the E820 as reserved | |
265 | * or as RAM, and so is subject to overlap from E820 manipulation later | |
266 | * in the boot process. On some systems, MMIO space is allocated on top, | |
267 | * despite the efforts of the "RAM buffer" approach, which simply rounds | |
268 | * memory boundaries up to 64M to try to catch space that may decode | |
269 | * as RAM and so is not suitable for MMIO. | |
814c5f1f | 270 | */ |
814c5f1f | 271 | |
86e58762 | 272 | #define KB(x) ((x) * 1024UL) |
814c5f1f | 273 | #define MB(x) (KB (KB (x))) |
814c5f1f | 274 | |
6f9fa996 | 275 | static resource_size_t __init i830_tseg_size(void) |
a4dff769 | 276 | { |
c0dd3460 | 277 | u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC); |
a4dff769 | 278 | |
c0dd3460 | 279 | if (!(esmramc & TSEG_ENABLE)) |
a4dff769 VS |
280 | return 0; |
281 | ||
c0dd3460 | 282 | if (esmramc & I830_TSEG_SIZE_1M) |
a4dff769 VS |
283 | return MB(1); |
284 | else | |
285 | return KB(512); | |
286 | } | |
287 | ||
6f9fa996 | 288 | static resource_size_t __init i845_tseg_size(void) |
a4dff769 | 289 | { |
c0dd3460 JL |
290 | u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC); |
291 | u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK; | |
a4dff769 | 292 | |
c0dd3460 | 293 | if (!(esmramc & TSEG_ENABLE)) |
a4dff769 VS |
294 | return 0; |
295 | ||
c0dd3460 JL |
296 | switch (tseg_size) { |
297 | case I845_TSEG_SIZE_512K: return KB(512); | |
298 | case I845_TSEG_SIZE_1M: return MB(1); | |
a4dff769 | 299 | default: |
c0dd3460 | 300 | WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc); |
a4dff769 | 301 | } |
c0dd3460 | 302 | return 0; |
a4dff769 VS |
303 | } |
304 | ||
6f9fa996 | 305 | static resource_size_t __init i85x_tseg_size(void) |
a4dff769 | 306 | { |
c0dd3460 | 307 | u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC); |
a4dff769 | 308 | |
c0dd3460 | 309 | if (!(esmramc & TSEG_ENABLE)) |
a4dff769 VS |
310 | return 0; |
311 | ||
312 | return MB(1); | |
313 | } | |
314 | ||
6f9fa996 | 315 | static resource_size_t __init i830_mem_size(void) |
a4dff769 VS |
316 | { |
317 | return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32); | |
318 | } | |
319 | ||
6f9fa996 | 320 | static resource_size_t __init i85x_mem_size(void) |
a4dff769 VS |
321 | { |
322 | return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32); | |
323 | } | |
324 | ||
325 | /* | |
326 | * On 830/845/85x the stolen memory base isn't available in any | |
327 | * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size. | |
328 | */ | |
6f9fa996 JL |
329 | static resource_size_t __init i830_stolen_base(int num, int slot, int func, |
330 | resource_size_t stolen_size) | |
a4dff769 | 331 | { |
6f9fa996 | 332 | return i830_mem_size() - i830_tseg_size() - stolen_size; |
a4dff769 VS |
333 | } |
334 | ||
6f9fa996 JL |
335 | static resource_size_t __init i845_stolen_base(int num, int slot, int func, |
336 | resource_size_t stolen_size) | |
a4dff769 | 337 | { |
6f9fa996 | 338 | return i830_mem_size() - i845_tseg_size() - stolen_size; |
a4dff769 VS |
339 | } |
340 | ||
6f9fa996 JL |
341 | static resource_size_t __init i85x_stolen_base(int num, int slot, int func, |
342 | resource_size_t stolen_size) | |
a4dff769 | 343 | { |
6f9fa996 | 344 | return i85x_mem_size() - i85x_tseg_size() - stolen_size; |
a4dff769 VS |
345 | } |
346 | ||
6f9fa996 JL |
347 | static resource_size_t __init i865_stolen_base(int num, int slot, int func, |
348 | resource_size_t stolen_size) | |
a4dff769 | 349 | { |
d721b02f | 350 | u16 toud = 0; |
c0dd3460 | 351 | |
c0dd3460 JL |
352 | toud = read_pci_config_16(0, 0, 0, I865_TOUD); |
353 | ||
6f9fa996 | 354 | return toud * KB(64) + i845_tseg_size(); |
c0dd3460 JL |
355 | } |
356 | ||
6f9fa996 JL |
357 | static resource_size_t __init gen3_stolen_base(int num, int slot, int func, |
358 | resource_size_t stolen_size) | |
c0dd3460 JL |
359 | { |
360 | u32 bsm; | |
361 | ||
362 | /* Almost universally we can find the Graphics Base of Stolen Memory | |
363 | * at register BSM (0x5c) in the igfx configuration space. On a few | |
364 | * (desktop) machines this is also mirrored in the bridge device at | |
365 | * different locations, or in the MCHBAR. | |
366 | */ | |
367 | bsm = read_pci_config(num, slot, func, INTEL_BSM); | |
368 | ||
6f9fa996 | 369 | return bsm & INTEL_BSM_MASK; |
a4dff769 VS |
370 | } |
371 | ||
db0c8d8b PZ |
372 | static resource_size_t __init gen11_stolen_base(int num, int slot, int func, |
373 | resource_size_t stolen_size) | |
374 | { | |
375 | u64 bsm; | |
376 | ||
377 | bsm = read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW0); | |
378 | bsm &= INTEL_BSM_MASK; | |
379 | bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32; | |
380 | ||
381 | return bsm; | |
382 | } | |
383 | ||
6f9fa996 | 384 | static resource_size_t __init i830_stolen_size(int num, int slot, int func) |
a4dff769 | 385 | { |
a4dff769 | 386 | u16 gmch_ctrl; |
c0dd3460 | 387 | u16 gms; |
a4dff769 VS |
388 | |
389 | gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL); | |
c0dd3460 JL |
390 | gms = gmch_ctrl & I830_GMCH_GMS_MASK; |
391 | ||
392 | switch (gms) { | |
393 | case I830_GMCH_GMS_STOLEN_512: return KB(512); | |
394 | case I830_GMCH_GMS_STOLEN_1024: return MB(1); | |
395 | case I830_GMCH_GMS_STOLEN_8192: return MB(8); | |
396 | /* local memory isn't part of the normal address space */ | |
397 | case I830_GMCH_GMS_LOCAL: return 0; | |
a4dff769 | 398 | default: |
c0dd3460 | 399 | WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl); |
a4dff769 VS |
400 | } |
401 | ||
c0dd3460 | 402 | return 0; |
a4dff769 VS |
403 | } |
404 | ||
6f9fa996 | 405 | static resource_size_t __init gen3_stolen_size(int num, int slot, int func) |
814c5f1f | 406 | { |
814c5f1f | 407 | u16 gmch_ctrl; |
c0dd3460 | 408 | u16 gms; |
814c5f1f JB |
409 | |
410 | gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL); | |
c0dd3460 JL |
411 | gms = gmch_ctrl & I855_GMCH_GMS_MASK; |
412 | ||
413 | switch (gms) { | |
414 | case I855_GMCH_GMS_STOLEN_1M: return MB(1); | |
415 | case I855_GMCH_GMS_STOLEN_4M: return MB(4); | |
416 | case I855_GMCH_GMS_STOLEN_8M: return MB(8); | |
417 | case I855_GMCH_GMS_STOLEN_16M: return MB(16); | |
418 | case I855_GMCH_GMS_STOLEN_32M: return MB(32); | |
419 | case I915_GMCH_GMS_STOLEN_48M: return MB(48); | |
420 | case I915_GMCH_GMS_STOLEN_64M: return MB(64); | |
421 | case G33_GMCH_GMS_STOLEN_128M: return MB(128); | |
422 | case G33_GMCH_GMS_STOLEN_256M: return MB(256); | |
423 | case INTEL_GMCH_GMS_STOLEN_96M: return MB(96); | |
424 | case INTEL_GMCH_GMS_STOLEN_160M:return MB(160); | |
425 | case INTEL_GMCH_GMS_STOLEN_224M:return MB(224); | |
426 | case INTEL_GMCH_GMS_STOLEN_352M:return MB(352); | |
814c5f1f | 427 | default: |
c0dd3460 | 428 | WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl); |
814c5f1f JB |
429 | } |
430 | ||
c0dd3460 | 431 | return 0; |
814c5f1f JB |
432 | } |
433 | ||
6f9fa996 | 434 | static resource_size_t __init gen6_stolen_size(int num, int slot, int func) |
814c5f1f JB |
435 | { |
436 | u16 gmch_ctrl; | |
c0dd3460 | 437 | u16 gms; |
814c5f1f JB |
438 | |
439 | gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); | |
c0dd3460 | 440 | gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK; |
814c5f1f | 441 | |
6f9fa996 | 442 | return gms * MB(32); |
814c5f1f JB |
443 | } |
444 | ||
6f9fa996 | 445 | static resource_size_t __init gen8_stolen_size(int num, int slot, int func) |
9459d252 BW |
446 | { |
447 | u16 gmch_ctrl; | |
c0dd3460 | 448 | u16 gms; |
9459d252 BW |
449 | |
450 | gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); | |
c0dd3460 JL |
451 | gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK; |
452 | ||
6f9fa996 | 453 | return gms * MB(32); |
9459d252 BW |
454 | } |
455 | ||
6f9fa996 | 456 | static resource_size_t __init chv_stolen_size(int num, int slot, int func) |
3e3b2c39 DL |
457 | { |
458 | u16 gmch_ctrl; | |
c0dd3460 | 459 | u16 gms; |
3e3b2c39 DL |
460 | |
461 | gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); | |
c0dd3460 | 462 | gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK; |
3e3b2c39 DL |
463 | |
464 | /* | |
465 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
466 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
467 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
468 | */ | |
c0dd3460 | 469 | if (gms < 0x11) |
6f9fa996 | 470 | return gms * MB(32); |
c0dd3460 | 471 | else if (gms < 0x17) |
3b51b6f3 | 472 | return (gms - 0x11) * MB(4) + MB(8); |
3e3b2c39 | 473 | else |
3b51b6f3 | 474 | return (gms - 0x17) * MB(4) + MB(36); |
3e3b2c39 | 475 | } |
52ca7045 | 476 | |
6f9fa996 | 477 | static resource_size_t __init gen9_stolen_size(int num, int slot, int func) |
66375014 DL |
478 | { |
479 | u16 gmch_ctrl; | |
c0dd3460 | 480 | u16 gms; |
66375014 DL |
481 | |
482 | gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL); | |
c0dd3460 | 483 | gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK; |
66375014 | 484 | |
c0dd3460 JL |
485 | /* 0x0 to 0xef: 32MB increments starting at 0MB */ |
486 | /* 0xf0 to 0xfe: 4MB increments starting at 4MB */ | |
487 | if (gms < 0xf0) | |
6f9fa996 | 488 | return gms * MB(32); |
66375014 | 489 | else |
3b51b6f3 | 490 | return (gms - 0xf0) * MB(4) + MB(4); |
66375014 DL |
491 | } |
492 | ||
ee0629cf | 493 | struct intel_early_ops { |
6f9fa996 JL |
494 | resource_size_t (*stolen_size)(int num, int slot, int func); |
495 | resource_size_t (*stolen_base)(int num, int slot, int func, | |
496 | resource_size_t size); | |
ee0629cf | 497 | }; |
66375014 | 498 | |
ee0629cf JL |
499 | static const struct intel_early_ops i830_early_ops __initconst = { |
500 | .stolen_base = i830_stolen_base, | |
501 | .stolen_size = i830_stolen_size, | |
a4dff769 VS |
502 | }; |
503 | ||
ee0629cf JL |
504 | static const struct intel_early_ops i845_early_ops __initconst = { |
505 | .stolen_base = i845_stolen_base, | |
506 | .stolen_size = i830_stolen_size, | |
a4dff769 VS |
507 | }; |
508 | ||
ee0629cf JL |
509 | static const struct intel_early_ops i85x_early_ops __initconst = { |
510 | .stolen_base = i85x_stolen_base, | |
511 | .stolen_size = gen3_stolen_size, | |
a4dff769 VS |
512 | }; |
513 | ||
ee0629cf JL |
514 | static const struct intel_early_ops i865_early_ops __initconst = { |
515 | .stolen_base = i865_stolen_base, | |
516 | .stolen_size = gen3_stolen_size, | |
a4dff769 VS |
517 | }; |
518 | ||
ee0629cf JL |
519 | static const struct intel_early_ops gen3_early_ops __initconst = { |
520 | .stolen_base = gen3_stolen_base, | |
521 | .stolen_size = gen3_stolen_size, | |
52ca7045 VS |
522 | }; |
523 | ||
ee0629cf JL |
524 | static const struct intel_early_ops gen6_early_ops __initconst = { |
525 | .stolen_base = gen3_stolen_base, | |
526 | .stolen_size = gen6_stolen_size, | |
52ca7045 VS |
527 | }; |
528 | ||
ee0629cf JL |
529 | static const struct intel_early_ops gen8_early_ops __initconst = { |
530 | .stolen_base = gen3_stolen_base, | |
531 | .stolen_size = gen8_stolen_size, | |
52ca7045 | 532 | }; |
814c5f1f | 533 | |
ee0629cf JL |
534 | static const struct intel_early_ops gen9_early_ops __initconst = { |
535 | .stolen_base = gen3_stolen_base, | |
536 | .stolen_size = gen9_stolen_size, | |
66375014 DL |
537 | }; |
538 | ||
ee0629cf JL |
539 | static const struct intel_early_ops chv_early_ops __initconst = { |
540 | .stolen_base = gen3_stolen_base, | |
541 | .stolen_size = chv_stolen_size, | |
3e3b2c39 DL |
542 | }; |
543 | ||
db0c8d8b PZ |
544 | static const struct intel_early_ops gen11_early_ops __initconst = { |
545 | .stolen_base = gen11_stolen_base, | |
546 | .stolen_size = gen9_stolen_size, | |
547 | }; | |
548 | ||
611f2111 | 549 | /* Intel integrated GPUs for which we need to reserve "stolen memory" */ |
ee0629cf JL |
550 | static const struct pci_device_id intel_early_ids[] __initconst = { |
551 | INTEL_I830_IDS(&i830_early_ops), | |
552 | INTEL_I845G_IDS(&i845_early_ops), | |
553 | INTEL_I85X_IDS(&i85x_early_ops), | |
554 | INTEL_I865G_IDS(&i865_early_ops), | |
555 | INTEL_I915G_IDS(&gen3_early_ops), | |
556 | INTEL_I915GM_IDS(&gen3_early_ops), | |
557 | INTEL_I945G_IDS(&gen3_early_ops), | |
558 | INTEL_I945GM_IDS(&gen3_early_ops), | |
8d9c20e1 | 559 | INTEL_VLV_IDS(&gen6_early_ops), |
86d35d4e TU |
560 | INTEL_PINEVIEW_G_IDS(&gen3_early_ops), |
561 | INTEL_PINEVIEW_M_IDS(&gen3_early_ops), | |
ee0629cf JL |
562 | INTEL_I965G_IDS(&gen3_early_ops), |
563 | INTEL_G33_IDS(&gen3_early_ops), | |
564 | INTEL_I965GM_IDS(&gen3_early_ops), | |
565 | INTEL_GM45_IDS(&gen3_early_ops), | |
566 | INTEL_G45_IDS(&gen3_early_ops), | |
567 | INTEL_IRONLAKE_D_IDS(&gen3_early_ops), | |
568 | INTEL_IRONLAKE_M_IDS(&gen3_early_ops), | |
569 | INTEL_SNB_D_IDS(&gen6_early_ops), | |
570 | INTEL_SNB_M_IDS(&gen6_early_ops), | |
571 | INTEL_IVB_M_IDS(&gen6_early_ops), | |
572 | INTEL_IVB_D_IDS(&gen6_early_ops), | |
8d9c20e1 CS |
573 | INTEL_HSW_IDS(&gen6_early_ops), |
574 | INTEL_BDW_IDS(&gen8_early_ops), | |
ee0629cf JL |
575 | INTEL_CHV_IDS(&chv_early_ops), |
576 | INTEL_SKL_IDS(&gen9_early_ops), | |
577 | INTEL_BXT_IDS(&gen9_early_ops), | |
578 | INTEL_KBL_IDS(&gen9_early_ops), | |
33aa69ed | 579 | INTEL_CFL_IDS(&gen9_early_ops), |
bc384c77 | 580 | INTEL_GLK_IDS(&gen9_early_ops), |
2e1e9d48 | 581 | INTEL_CNL_IDS(&gen9_early_ops), |
db0c8d8b | 582 | INTEL_ICL_11_IDS(&gen11_early_ops), |
d53fef0b | 583 | INTEL_EHL_IDS(&gen11_early_ops), |
31b77c70 | 584 | INTEL_JSL_IDS(&gen11_early_ops), |
6b2436ae | 585 | INTEL_TGL_12_IDS(&gen11_early_ops), |
efbee021 | 586 | INTEL_RKL_IDS(&gen11_early_ops), |
c6bba9e5 | 587 | INTEL_ADLS_IDS(&gen11_early_ops), |
bdd27cad | 588 | INTEL_ADLP_IDS(&gen11_early_ops), |
814c5f1f JB |
589 | }; |
590 | ||
55f56fc4 MA |
591 | struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); |
592 | EXPORT_SYMBOL(intel_graphics_stolen_res); | |
593 | ||
ee0629cf JL |
594 | static void __init |
595 | intel_graphics_stolen(int num, int slot, int func, | |
596 | const struct intel_early_ops *early_ops) | |
814c5f1f | 597 | { |
6f9fa996 JL |
598 | resource_size_t base, size; |
599 | resource_size_t end; | |
ee0629cf JL |
600 | |
601 | size = early_ops->stolen_size(num, slot, func); | |
602 | base = early_ops->stolen_base(num, slot, func, size); | |
603 | ||
604 | if (!size || !base) | |
605 | return; | |
606 | ||
01e5d3b4 | 607 | end = base + size - 1; |
55f56fc4 MA |
608 | |
609 | intel_graphics_stolen_res.start = base; | |
610 | intel_graphics_stolen_res.end = end; | |
611 | ||
612 | printk(KERN_INFO "Reserving Intel graphics memory at %pR\n", | |
613 | &intel_graphics_stolen_res); | |
ee0629cf JL |
614 | |
615 | /* Mark this space as reserved */ | |
09821ff1 | 616 | e820__range_add(base, size, E820_TYPE_RESERVED); |
f9748fa0 | 617 | e820__update_table(e820_table); |
ee0629cf JL |
618 | } |
619 | ||
620 | static void __init intel_graphics_quirks(int num, int slot, int func) | |
621 | { | |
622 | const struct intel_early_ops *early_ops; | |
623 | u16 device; | |
814c5f1f | 624 | int i; |
814c5f1f | 625 | |
611f2111 LDM |
626 | /* |
627 | * Reserve "stolen memory" for an integrated GPU. If we've already | |
628 | * found one, there's nothing to do for other (discrete) GPUs. | |
629 | */ | |
630 | if (resource_size(&intel_graphics_stolen_res)) | |
631 | return; | |
632 | ||
814c5f1f | 633 | device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); |
ee0629cf JL |
634 | |
635 | for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) { | |
636 | kernel_ulong_t driver_data = intel_early_ids[i].driver_data; | |
637 | ||
638 | if (intel_early_ids[i].device != device) | |
639 | continue; | |
640 | ||
641 | early_ops = (typeof(early_ops))driver_data; | |
642 | ||
643 | intel_graphics_stolen(num, slot, func, early_ops); | |
644 | ||
645 | return; | |
814c5f1f JB |
646 | } |
647 | } | |
648 | ||
62187910 FT |
649 | static void __init force_disable_hpet(int num, int slot, int func) |
650 | { | |
651 | #ifdef CONFIG_HPET_TIMER | |
3d45ac4b | 652 | boot_hpet_disable = true; |
62187910 FT |
653 | pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n"); |
654 | #endif | |
655 | } | |
656 | ||
abb2bafd LW |
657 | #define BCM4331_MMIO_SIZE 16384 |
658 | #define BCM4331_PM_CAP 0x40 | |
659 | #define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg) | |
660 | #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg) | |
661 | ||
662 | static void __init apple_airport_reset(int bus, int slot, int func) | |
663 | { | |
664 | void __iomem *mmio; | |
665 | u16 pmcsr; | |
666 | u64 addr; | |
667 | int i; | |
668 | ||
630b3aff | 669 | if (!x86_apple_machine) |
abb2bafd LW |
670 | return; |
671 | ||
672 | /* Card may have been put into PCI_D3hot by grub quirk */ | |
673 | pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL); | |
674 | ||
675 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) { | |
676 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
677 | write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr); | |
678 | mdelay(10); | |
679 | ||
680 | pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL); | |
681 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) { | |
a7a3153a JP |
682 | pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n", |
683 | bus, slot, func); | |
abb2bafd LW |
684 | return; |
685 | } | |
686 | } | |
687 | ||
688 | addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0); | |
689 | addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32; | |
690 | addr &= PCI_BASE_ADDRESS_MEM_MASK; | |
691 | ||
692 | mmio = early_ioremap(addr, BCM4331_MMIO_SIZE); | |
693 | if (!mmio) { | |
a7a3153a JP |
694 | pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n", |
695 | bus, slot, func); | |
abb2bafd LW |
696 | return; |
697 | } | |
698 | ||
699 | pr_info("Resetting Apple AirPort card (left enabled by EFI)\n"); | |
700 | ||
701 | for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++) | |
702 | udelay(10); | |
703 | ||
704 | bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET); | |
705 | bcma_aread32(BCMA_RESET_CTL); | |
706 | udelay(1); | |
707 | ||
708 | bcma_awrite32(BCMA_RESET_CTL, 0); | |
709 | bcma_aread32(BCMA_RESET_CTL); | |
710 | udelay(10); | |
711 | ||
712 | early_iounmap(mmio, BCM4331_MMIO_SIZE); | |
713 | } | |
62187910 | 714 | |
c6b48324 NH |
715 | #define QFLAG_APPLY_ONCE 0x1 |
716 | #define QFLAG_APPLIED 0x2 | |
717 | #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED) | |
dfa4698c | 718 | struct chipset { |
c6b48324 NH |
719 | u32 vendor; |
720 | u32 device; | |
721 | u32 class; | |
722 | u32 class_mask; | |
723 | u32 flags; | |
724 | void (*f)(int num, int slot, int func); | |
dfa4698c AK |
725 | }; |
726 | ||
c993c735 | 727 | static struct chipset early_qrk[] __initdata = { |
c6b48324 NH |
728 | { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
729 | PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs }, | |
730 | { PCI_VENDOR_ID_VIA, PCI_ANY_ID, | |
731 | PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs }, | |
c6b48324 NH |
732 | { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB, |
733 | PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config }, | |
33fb0e4e AH |
734 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS, |
735 | PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs }, | |
26adcfbf AH |
736 | { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, |
737 | PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd }, | |
03bbcb2e NH |
738 | { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST, |
739 | PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, | |
803075db NH |
740 | { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST, |
741 | PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, | |
03bbcb2e NH |
742 | { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST, |
743 | PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check }, | |
814c5f1f | 744 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID, |
611f2111 | 745 | 0, intel_graphics_quirks }, |
62187910 | 746 | /* |
b58d9307 FT |
747 | * HPET on the current version of the Baytrail platform has accuracy |
748 | * problems: it will halt in deep idle state - so we disable it. | |
749 | * | |
750 | * More details can be found in section 18.10.1.3 of the datasheet: | |
751 | * | |
752 | * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf | |
62187910 FT |
753 | */ |
754 | { PCI_VENDOR_ID_INTEL, 0x0f00, | |
755 | PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet}, | |
abb2bafd LW |
756 | { PCI_VENDOR_ID_BROADCOM, 0x4331, |
757 | PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset}, | |
dc5e44a1 | 758 | { PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, early_pci_clear_msi}, |
dfa4698c AK |
759 | {} |
760 | }; | |
761 | ||
850c3210 LW |
762 | static void __init early_pci_scan_bus(int bus); |
763 | ||
15650a2f JB |
764 | /** |
765 | * check_dev_quirk - apply early quirks to a given PCI device | |
766 | * @num: bus number | |
767 | * @slot: slot number | |
768 | * @func: PCI function | |
769 | * | |
770 | * Check the vendor & device ID against the early quirks table. | |
771 | * | |
850c3210 | 772 | * If the device is single function, let early_pci_scan_bus() know so we don't |
15650a2f JB |
773 | * poke at this device again. |
774 | */ | |
775 | static int __init check_dev_quirk(int num, int slot, int func) | |
7bcbc78d NH |
776 | { |
777 | u16 class; | |
778 | u16 vendor; | |
779 | u16 device; | |
780 | u8 type; | |
850c3210 | 781 | u8 sec; |
7bcbc78d NH |
782 | int i; |
783 | ||
784 | class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE); | |
785 | ||
786 | if (class == 0xffff) | |
15650a2f | 787 | return -1; /* no class, treat as single function */ |
7bcbc78d NH |
788 | |
789 | vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID); | |
790 | ||
791 | device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID); | |
792 | ||
793 | for (i = 0; early_qrk[i].f != NULL; i++) { | |
794 | if (((early_qrk[i].vendor == PCI_ANY_ID) || | |
795 | (early_qrk[i].vendor == vendor)) && | |
796 | ((early_qrk[i].device == PCI_ANY_ID) || | |
797 | (early_qrk[i].device == device)) && | |
798 | (!((early_qrk[i].class ^ class) & | |
799 | early_qrk[i].class_mask))) { | |
800 | if ((early_qrk[i].flags & | |
801 | QFLAG_DONE) != QFLAG_DONE) | |
802 | early_qrk[i].f(num, slot, func); | |
803 | early_qrk[i].flags |= QFLAG_APPLIED; | |
804 | } | |
805 | } | |
806 | ||
807 | type = read_pci_config_byte(num, slot, func, | |
808 | PCI_HEADER_TYPE); | |
850c3210 LW |
809 | |
810 | if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { | |
ed5eef51 GP |
811 | /* pci_early_clear_msi scans the buses differently. */ |
812 | if (pci_early_clear_msi) | |
813 | return -1; | |
814 | ||
850c3210 LW |
815 | sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS); |
816 | if (sec > num) | |
817 | early_pci_scan_bus(sec); | |
818 | } | |
819 | ||
7bcbc78d | 820 | if (!(type & 0x80)) |
15650a2f JB |
821 | return -1; |
822 | ||
823 | return 0; | |
7bcbc78d NH |
824 | } |
825 | ||
850c3210 | 826 | static void __init early_pci_scan_bus(int bus) |
dfa4698c | 827 | { |
8659c406 | 828 | int slot, func; |
0637a70a | 829 | |
dfa4698c | 830 | /* Poor man's PCI discovery */ |
8659c406 AK |
831 | for (slot = 0; slot < 32; slot++) |
832 | for (func = 0; func < 8; func++) { | |
833 | /* Only probe function 0 on single fn devices */ | |
850c3210 | 834 | if (check_dev_quirk(bus, slot, func)) |
8659c406 AK |
835 | break; |
836 | } | |
dfa4698c | 837 | } |
850c3210 LW |
838 | |
839 | void __init early_quirks(void) | |
840 | { | |
ed5eef51 GP |
841 | int bus; |
842 | ||
850c3210 LW |
843 | if (!early_pci_allowed()) |
844 | return; | |
845 | ||
846 | early_pci_scan_bus(0); | |
ed5eef51 GP |
847 | /* pci_early_clear_msi scans more buses. */ |
848 | for (bus = 1; pci_early_clear_msi && bus < 256; bus++) | |
849 | early_pci_scan_bus(bus); | |
850c3210 | 850 | } |