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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/entry.S | |
3 | * | |
4 | * Copyright (C) 1991, 1992 Linus Torvalds | |
5 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
1da177e4 LT |
7 | */ |
8 | ||
9 | /* | |
10 | * entry.S contains the system-call and fault low-level handling routines. | |
11 | * | |
8b4777a4 AL |
12 | * Some of this is documented in Documentation/x86/entry_64.txt |
13 | * | |
1da177e4 LT |
14 | * NOTE: This code handles signal-recognition, which happens every time |
15 | * after an interrupt and after each system call. | |
0bd7b798 | 16 | * |
0bd7b798 | 17 | * A note on terminology: |
7fcb3bc3 | 18 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
0bd7b798 | 19 | * at the top of the kernel process stack. |
2e91a17b AK |
20 | * |
21 | * Some macro usage: | |
22 | * - CFI macros are used to generate dwarf2 unwind information for better | |
23 | * backtraces. They don't change any code. | |
2e91a17b | 24 | * - ENTRY/END Define functions in the symbol table. |
2e91a17b | 25 | * - TRACE_IRQ_* - Trace hard interrupt state for lock debugging. |
cb5dd2c5 | 26 | * - idtentry - Define exception entry points. |
1da177e4 LT |
27 | */ |
28 | ||
1da177e4 LT |
29 | #include <linux/linkage.h> |
30 | #include <asm/segment.h> | |
1da177e4 LT |
31 | #include <asm/cache.h> |
32 | #include <asm/errno.h> | |
33 | #include <asm/dwarf2.h> | |
34 | #include <asm/calling.h> | |
e2d5df93 | 35 | #include <asm/asm-offsets.h> |
1da177e4 LT |
36 | #include <asm/msr.h> |
37 | #include <asm/unistd.h> | |
38 | #include <asm/thread_info.h> | |
39 | #include <asm/hw_irq.h> | |
0341c14d | 40 | #include <asm/page_types.h> |
2601e64d | 41 | #include <asm/irqflags.h> |
72fe4858 | 42 | #include <asm/paravirt.h> |
9939ddaf | 43 | #include <asm/percpu.h> |
d7abc0fa | 44 | #include <asm/asm.h> |
91d1aa43 | 45 | #include <asm/context_tracking.h> |
63bcff2a | 46 | #include <asm/smap.h> |
3891a04a | 47 | #include <asm/pgtable_types.h> |
d7e7528b | 48 | #include <linux/err.h> |
1da177e4 | 49 | |
86a1c34a RM |
50 | /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */ |
51 | #include <linux/elf-em.h> | |
52 | #define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) | |
53 | #define __AUDIT_ARCH_64BIT 0x80000000 | |
54 | #define __AUDIT_ARCH_LE 0x40000000 | |
55 | ||
1da177e4 | 56 | .code64 |
ea714547 JO |
57 | .section .entry.text, "ax" |
58 | ||
16444a8a | 59 | |
72fe4858 | 60 | #ifdef CONFIG_PARAVIRT |
2be29982 | 61 | ENTRY(native_usergs_sysret64) |
72fe4858 GOC |
62 | swapgs |
63 | sysretq | |
b3baaa13 | 64 | ENDPROC(native_usergs_sysret64) |
72fe4858 GOC |
65 | #endif /* CONFIG_PARAVIRT */ |
66 | ||
2601e64d | 67 | |
f2db9382 | 68 | .macro TRACE_IRQS_IRETQ |
2601e64d | 69 | #ifdef CONFIG_TRACE_IRQFLAGS |
f2db9382 | 70 | bt $9,EFLAGS(%rsp) /* interrupts off? */ |
2601e64d IM |
71 | jnc 1f |
72 | TRACE_IRQS_ON | |
73 | 1: | |
74 | #endif | |
75 | .endm | |
76 | ||
5963e317 SR |
77 | /* |
78 | * When dynamic function tracer is enabled it will add a breakpoint | |
79 | * to all locations that it is about to modify, sync CPUs, update | |
80 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
81 | * if lockdep is enabled, it might jump back into the debug handler | |
82 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
83 | * | |
84 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
85 | * make sure the stack pointer does not get reset back to the top | |
86 | * of the debug stack, and instead just reuses the current stack. | |
87 | */ | |
88 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
89 | ||
90 | .macro TRACE_IRQS_OFF_DEBUG | |
91 | call debug_stack_set_zero | |
92 | TRACE_IRQS_OFF | |
93 | call debug_stack_reset | |
94 | .endm | |
95 | ||
96 | .macro TRACE_IRQS_ON_DEBUG | |
97 | call debug_stack_set_zero | |
98 | TRACE_IRQS_ON | |
99 | call debug_stack_reset | |
100 | .endm | |
101 | ||
f2db9382 DV |
102 | .macro TRACE_IRQS_IRETQ_DEBUG |
103 | bt $9,EFLAGS(%rsp) /* interrupts off? */ | |
5963e317 SR |
104 | jnc 1f |
105 | TRACE_IRQS_ON_DEBUG | |
106 | 1: | |
107 | .endm | |
108 | ||
109 | #else | |
110 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF | |
111 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
112 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
113 | #endif | |
114 | ||
dcd072e2 | 115 | /* |
e90e147c | 116 | * empty frame |
dcd072e2 AH |
117 | */ |
118 | .macro EMPTY_FRAME start=1 offset=0 | |
7effaa88 | 119 | .if \start |
dcd072e2 | 120 | CFI_STARTPROC simple |
adf14236 | 121 | CFI_SIGNAL_FRAME |
dcd072e2 | 122 | CFI_DEF_CFA rsp,8+\offset |
7effaa88 | 123 | .else |
dcd072e2 | 124 | CFI_DEF_CFA_OFFSET 8+\offset |
7effaa88 | 125 | .endif |
1da177e4 | 126 | .endm |
d99015b1 AH |
127 | |
128 | /* | |
dcd072e2 | 129 | * initial frame state for interrupts (and exceptions without error code) |
d99015b1 | 130 | */ |
dcd072e2 | 131 | .macro INTR_FRAME start=1 offset=0 |
911d2bb5 DV |
132 | EMPTY_FRAME \start, 5*8+\offset |
133 | /*CFI_REL_OFFSET ss, 4*8+\offset*/ | |
134 | CFI_REL_OFFSET rsp, 3*8+\offset | |
135 | /*CFI_REL_OFFSET rflags, 2*8+\offset*/ | |
136 | /*CFI_REL_OFFSET cs, 1*8+\offset*/ | |
137 | CFI_REL_OFFSET rip, 0*8+\offset | |
d99015b1 AH |
138 | .endm |
139 | ||
d99015b1 AH |
140 | /* |
141 | * initial frame state for exceptions with error code (and interrupts | |
142 | * with vector already pushed) | |
143 | */ | |
dcd072e2 | 144 | .macro XCPT_FRAME start=1 offset=0 |
911d2bb5 | 145 | INTR_FRAME \start, 1*8+\offset |
dcd072e2 AH |
146 | .endm |
147 | ||
148 | /* | |
76f5df43 | 149 | * frame that enables passing a complete pt_regs to a C function. |
dcd072e2 | 150 | */ |
76f5df43 | 151 | .macro DEFAULT_FRAME start=1 offset=0 |
f2db9382 DV |
152 | XCPT_FRAME \start, ORIG_RAX+\offset |
153 | CFI_REL_OFFSET rdi, RDI+\offset | |
154 | CFI_REL_OFFSET rsi, RSI+\offset | |
155 | CFI_REL_OFFSET rdx, RDX+\offset | |
156 | CFI_REL_OFFSET rcx, RCX+\offset | |
157 | CFI_REL_OFFSET rax, RAX+\offset | |
158 | CFI_REL_OFFSET r8, R8+\offset | |
159 | CFI_REL_OFFSET r9, R9+\offset | |
160 | CFI_REL_OFFSET r10, R10+\offset | |
161 | CFI_REL_OFFSET r11, R11+\offset | |
dcd072e2 AH |
162 | CFI_REL_OFFSET rbx, RBX+\offset |
163 | CFI_REL_OFFSET rbp, RBP+\offset | |
164 | CFI_REL_OFFSET r12, R12+\offset | |
165 | CFI_REL_OFFSET r13, R13+\offset | |
166 | CFI_REL_OFFSET r14, R14+\offset | |
167 | CFI_REL_OFFSET r15, R15+\offset | |
168 | .endm | |
d99015b1 | 169 | |
1da177e4 | 170 | /* |
b87cf63e | 171 | * 64bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 172 | * |
b87cf63e DV |
173 | * 64bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
174 | * then loads new ss, cs, and rip from previously programmed MSRs. | |
175 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
176 | * are not needed). SYSCALL does not save anything on the stack | |
177 | * and does not change rsp. | |
178 | * | |
179 | * Registers on entry: | |
1da177e4 | 180 | * rax system call number |
b87cf63e DV |
181 | * rcx return address |
182 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 183 | * rdi arg0 |
1da177e4 | 184 | * rsi arg1 |
0bd7b798 | 185 | * rdx arg2 |
b87cf63e | 186 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
187 | * r8 arg4 |
188 | * r9 arg5 | |
b87cf63e | 189 | * (note: r12-r15,rbp,rbx are callee-preserved in C ABI) |
0bd7b798 | 190 | * |
1da177e4 LT |
191 | * Only called from user space. |
192 | * | |
7fcb3bc3 | 193 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
194 | * it deals with uncanonical addresses better. SYSRET has trouble |
195 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 196 | */ |
1da177e4 LT |
197 | |
198 | ENTRY(system_call) | |
7effaa88 | 199 | CFI_STARTPROC simple |
adf14236 | 200 | CFI_SIGNAL_FRAME |
ef593260 | 201 | CFI_DEF_CFA rsp,0 |
7effaa88 JB |
202 | CFI_REGISTER rip,rcx |
203 | /*CFI_REGISTER rflags,r11*/ | |
9ed8e7d8 DV |
204 | |
205 | /* | |
206 | * Interrupts are off on entry. | |
207 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
208 | * it is too small to ever cause noticeable irq latency. | |
209 | */ | |
72fe4858 GOC |
210 | SWAPGS_UNSAFE_STACK |
211 | /* | |
212 | * A hypervisor implementation might want to use a label | |
213 | * after the swapgs, so that it can do the swapgs | |
214 | * for the guest and jump here on syscall. | |
215 | */ | |
f6b2bc84 | 216 | GLOBAL(system_call_after_swapgs) |
72fe4858 | 217 | |
c38e5038 | 218 | movq %rsp,PER_CPU_VAR(rsp_scratch) |
9af45651 | 219 | movq PER_CPU_VAR(kernel_stack),%rsp |
9ed8e7d8 DV |
220 | |
221 | /* Construct struct pt_regs on stack */ | |
222 | pushq_cfi $__USER_DS /* pt_regs->ss */ | |
223 | pushq_cfi PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ | |
33db1fd4 | 224 | /* |
9ed8e7d8 DV |
225 | * Re-enable interrupts. |
226 | * We use 'rsp_scratch' as a scratch space, hence irq-off block above | |
227 | * must execute atomically in the face of possible interrupt-driven | |
228 | * task preemption. We must enable interrupts only after we're done | |
229 | * with using rsp_scratch: | |
33db1fd4 DV |
230 | */ |
231 | ENABLE_INTERRUPTS(CLBR_NONE) | |
9ed8e7d8 DV |
232 | pushq_cfi %r11 /* pt_regs->flags */ |
233 | pushq_cfi $__USER_CS /* pt_regs->cs */ | |
234 | pushq_cfi %rcx /* pt_regs->ip */ | |
235 | CFI_REL_OFFSET rip,0 | |
236 | pushq_cfi_reg rax /* pt_regs->orig_ax */ | |
237 | pushq_cfi_reg rdi /* pt_regs->di */ | |
238 | pushq_cfi_reg rsi /* pt_regs->si */ | |
239 | pushq_cfi_reg rdx /* pt_regs->dx */ | |
240 | pushq_cfi_reg rcx /* pt_regs->cx */ | |
241 | pushq_cfi $-ENOSYS /* pt_regs->ax */ | |
242 | pushq_cfi_reg r8 /* pt_regs->r8 */ | |
243 | pushq_cfi_reg r9 /* pt_regs->r9 */ | |
244 | pushq_cfi_reg r10 /* pt_regs->r10 */ | |
a71ffdd7 DV |
245 | pushq_cfi_reg r11 /* pt_regs->r11 */ |
246 | sub $(6*8),%rsp /* pt_regs->bp,bx,r12-15 not saved */ | |
27be87c5 | 247 | CFI_ADJUST_CFA_OFFSET 6*8 |
9ed8e7d8 | 248 | |
dca5b52a | 249 | testl $_TIF_WORK_SYSCALL_ENTRY, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) |
1da177e4 | 250 | jnz tracesys |
86a1c34a | 251 | system_call_fastpath: |
fca460f9 | 252 | #if __SYSCALL_MASK == ~0 |
1da177e4 | 253 | cmpq $__NR_syscall_max,%rax |
fca460f9 PA |
254 | #else |
255 | andl $__SYSCALL_MASK,%eax | |
256 | cmpl $__NR_syscall_max,%eax | |
257 | #endif | |
146b2b09 | 258 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
1da177e4 | 259 | movq %r10,%rcx |
146b2b09 | 260 | call *sys_call_table(,%rax,8) |
f2db9382 | 261 | movq %rax,RAX(%rsp) |
146b2b09 | 262 | 1: |
1da177e4 | 263 | /* |
146b2b09 DV |
264 | * Syscall return path ending with SYSRET (fast path). |
265 | * Has incompletely filled pt_regs. | |
0bd7b798 | 266 | */ |
10cd706d | 267 | LOCKDEP_SYS_EXIT |
4416c5a6 DV |
268 | /* |
269 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
270 | * it is too small to ever cause noticeable irq latency. | |
271 | */ | |
72fe4858 | 272 | DISABLE_INTERRUPTS(CLBR_NONE) |
b3494a4a AL |
273 | |
274 | /* | |
275 | * We must check ti flags with interrupts (or at least preemption) | |
276 | * off because we must *never* return to userspace without | |
277 | * processing exit work that is enqueued if we're preempted here. | |
278 | * In particular, returning to userspace with any of the one-shot | |
279 | * flags (TIF_NOTIFY_RESUME, TIF_USER_RETURN_NOTIFY, etc) set is | |
280 | * very bad. | |
281 | */ | |
06ab9c1b IM |
282 | testl $_TIF_ALLWORK_MASK, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) |
283 | jnz int_ret_from_sys_call_irqs_off /* Go to the slow path */ | |
b3494a4a | 284 | |
bcddc015 | 285 | CFI_REMEMBER_STATE |
4416c5a6 | 286 | |
29722cd4 DV |
287 | RESTORE_C_REGS_EXCEPT_RCX_R11 |
288 | movq RIP(%rsp),%rcx | |
7effaa88 | 289 | CFI_REGISTER rip,rcx |
29722cd4 | 290 | movq EFLAGS(%rsp),%r11 |
7effaa88 | 291 | /*CFI_REGISTER rflags,r11*/ |
263042e4 | 292 | movq RSP(%rsp),%rsp |
b87cf63e DV |
293 | /* |
294 | * 64bit SYSRET restores rip from rcx, | |
295 | * rflags from r11 (but RF and VM bits are forced to 0), | |
296 | * cs and ss are loaded from MSRs. | |
4416c5a6 | 297 | * Restoration of rflags re-enables interrupts. |
b87cf63e | 298 | */ |
2be29982 | 299 | USERGS_SYSRET64 |
1da177e4 | 300 | |
bcddc015 | 301 | CFI_RESTORE_STATE |
1da177e4 | 302 | |
7fcb3bc3 | 303 | /* Do syscall entry tracing */ |
0bd7b798 | 304 | tracesys: |
76f5df43 | 305 | movq %rsp, %rdi |
47eb582e | 306 | movl $AUDIT_ARCH_X86_64, %esi |
1dcf74f6 AL |
307 | call syscall_trace_enter_phase1 |
308 | test %rax, %rax | |
309 | jnz tracesys_phase2 /* if needed, run the slow path */ | |
76f5df43 | 310 | RESTORE_C_REGS_EXCEPT_RAX /* else restore clobbered regs */ |
f2db9382 | 311 | movq ORIG_RAX(%rsp), %rax |
1dcf74f6 AL |
312 | jmp system_call_fastpath /* and return to the fast path */ |
313 | ||
314 | tracesys_phase2: | |
76f5df43 | 315 | SAVE_EXTRA_REGS |
1dcf74f6 | 316 | movq %rsp, %rdi |
47eb582e | 317 | movl $AUDIT_ARCH_X86_64, %esi |
1dcf74f6 AL |
318 | movq %rax,%rdx |
319 | call syscall_trace_enter_phase2 | |
320 | ||
d4d67150 | 321 | /* |
e90e147c | 322 | * Reload registers from stack in case ptrace changed them. |
1dcf74f6 | 323 | * We don't reload %rax because syscall_trace_entry_phase2() returned |
d4d67150 RM |
324 | * the value it wants us to use in the table lookup. |
325 | */ | |
76f5df43 DV |
326 | RESTORE_C_REGS_EXCEPT_RAX |
327 | RESTORE_EXTRA_REGS | |
fca460f9 | 328 | #if __SYSCALL_MASK == ~0 |
1da177e4 | 329 | cmpq $__NR_syscall_max,%rax |
fca460f9 PA |
330 | #else |
331 | andl $__SYSCALL_MASK,%eax | |
332 | cmpl $__NR_syscall_max,%eax | |
333 | #endif | |
a6de5a21 | 334 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
1da177e4 LT |
335 | movq %r10,%rcx /* fixup for C */ |
336 | call *sys_call_table(,%rax,8) | |
f2db9382 | 337 | movq %rax,RAX(%rsp) |
a6de5a21 | 338 | 1: |
7fcb3bc3 | 339 | /* Use IRET because user could have changed pt_regs->foo */ |
0bd7b798 AH |
340 | |
341 | /* | |
1da177e4 | 342 | * Syscall return path ending with IRET. |
7fcb3bc3 | 343 | * Has correct iret frame. |
bcddc015 | 344 | */ |
bc8b2b92 | 345 | GLOBAL(int_ret_from_sys_call) |
72fe4858 | 346 | DISABLE_INTERRUPTS(CLBR_NONE) |
4416c5a6 | 347 | int_ret_from_sys_call_irqs_off: /* jumps come here from the irqs-off SYSRET path */ |
2601e64d | 348 | TRACE_IRQS_OFF |
1da177e4 LT |
349 | movl $_TIF_ALLWORK_MASK,%edi |
350 | /* edi: mask to check */ | |
bc8b2b92 | 351 | GLOBAL(int_with_check) |
10cd706d | 352 | LOCKDEP_SYS_EXIT_IRQ |
1da177e4 | 353 | GET_THREAD_INFO(%rcx) |
26ccb8a7 | 354 | movl TI_flags(%rcx),%edx |
1da177e4 LT |
355 | andl %edi,%edx |
356 | jnz int_careful | |
fffbb5dc DV |
357 | andl $~TS_COMPAT,TI_status(%rcx) |
358 | jmp syscall_return | |
1da177e4 LT |
359 | |
360 | /* Either reschedule or signal or syscall exit tracking needed. */ | |
361 | /* First do a reschedule test. */ | |
362 | /* edx: work, edi: workmask */ | |
363 | int_careful: | |
364 | bt $TIF_NEED_RESCHED,%edx | |
365 | jnc int_very_careful | |
2601e64d | 366 | TRACE_IRQS_ON |
72fe4858 | 367 | ENABLE_INTERRUPTS(CLBR_NONE) |
df5d1874 | 368 | pushq_cfi %rdi |
0430499c | 369 | SCHEDULE_USER |
df5d1874 | 370 | popq_cfi %rdi |
72fe4858 | 371 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 372 | TRACE_IRQS_OFF |
1da177e4 LT |
373 | jmp int_with_check |
374 | ||
7fcb3bc3 | 375 | /* handle signals and tracing -- both require a full pt_regs */ |
1da177e4 | 376 | int_very_careful: |
2601e64d | 377 | TRACE_IRQS_ON |
72fe4858 | 378 | ENABLE_INTERRUPTS(CLBR_NONE) |
76f5df43 | 379 | SAVE_EXTRA_REGS |
0bd7b798 | 380 | /* Check for syscall exit trace */ |
d4d67150 | 381 | testl $_TIF_WORK_SYSCALL_EXIT,%edx |
1da177e4 | 382 | jz int_signal |
df5d1874 | 383 | pushq_cfi %rdi |
0bd7b798 | 384 | leaq 8(%rsp),%rdi # &ptregs -> arg1 |
1da177e4 | 385 | call syscall_trace_leave |
df5d1874 | 386 | popq_cfi %rdi |
d4d67150 | 387 | andl $~(_TIF_WORK_SYSCALL_EXIT|_TIF_SYSCALL_EMU),%edi |
1da177e4 | 388 | jmp int_restore_rest |
0bd7b798 | 389 | |
1da177e4 | 390 | int_signal: |
8f4d37ec | 391 | testl $_TIF_DO_NOTIFY_MASK,%edx |
1da177e4 LT |
392 | jz 1f |
393 | movq %rsp,%rdi # &ptregs -> arg1 | |
394 | xorl %esi,%esi # oldset -> arg2 | |
395 | call do_notify_resume | |
eca91e78 | 396 | 1: movl $_TIF_WORK_MASK,%edi |
1da177e4 | 397 | int_restore_rest: |
76f5df43 | 398 | RESTORE_EXTRA_REGS |
72fe4858 | 399 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 400 | TRACE_IRQS_OFF |
1da177e4 | 401 | jmp int_with_check |
fffbb5dc DV |
402 | |
403 | syscall_return: | |
404 | /* The IRETQ could re-enable interrupts: */ | |
405 | DISABLE_INTERRUPTS(CLBR_ANY) | |
406 | TRACE_IRQS_IRETQ | |
407 | ||
408 | /* | |
409 | * Try to use SYSRET instead of IRET if we're returning to | |
410 | * a completely clean 64-bit userspace context. | |
411 | */ | |
412 | movq RCX(%rsp),%rcx | |
413 | cmpq %rcx,RIP(%rsp) /* RCX == RIP */ | |
414 | jne opportunistic_sysret_failed | |
415 | ||
416 | /* | |
417 | * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP | |
418 | * in kernel space. This essentially lets the user take over | |
419 | * the kernel, since userspace controls RSP. It's not worth | |
420 | * testing for canonicalness exactly -- this check detects any | |
421 | * of the 17 high bits set, which is true for non-canonical | |
422 | * or kernel addresses. (This will pessimize vsyscall=native. | |
423 | * Big deal.) | |
424 | * | |
425 | * If virtual addresses ever become wider, this will need | |
426 | * to be updated to remain correct on both old and new CPUs. | |
427 | */ | |
428 | .ifne __VIRTUAL_MASK_SHIFT - 47 | |
429 | .error "virtual address width changed -- SYSRET checks need update" | |
430 | .endif | |
431 | shr $__VIRTUAL_MASK_SHIFT, %rcx | |
432 | jnz opportunistic_sysret_failed | |
433 | ||
434 | cmpq $__USER_CS,CS(%rsp) /* CS must match SYSRET */ | |
435 | jne opportunistic_sysret_failed | |
436 | ||
437 | movq R11(%rsp),%r11 | |
438 | cmpq %r11,EFLAGS(%rsp) /* R11 == RFLAGS */ | |
439 | jne opportunistic_sysret_failed | |
440 | ||
441 | /* | |
442 | * SYSRET can't restore RF. SYSRET can restore TF, but unlike IRET, | |
443 | * restoring TF results in a trap from userspace immediately after | |
444 | * SYSRET. This would cause an infinite loop whenever #DB happens | |
445 | * with register state that satisfies the opportunistic SYSRET | |
446 | * conditions. For example, single-stepping this user code: | |
447 | * | |
448 | * movq $stuck_here,%rcx | |
449 | * pushfq | |
450 | * popq %r11 | |
451 | * stuck_here: | |
452 | * | |
453 | * would never get past 'stuck_here'. | |
454 | */ | |
455 | testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 | |
456 | jnz opportunistic_sysret_failed | |
457 | ||
458 | /* nothing to check for RSP */ | |
459 | ||
460 | cmpq $__USER_DS,SS(%rsp) /* SS must match SYSRET */ | |
461 | jne opportunistic_sysret_failed | |
462 | ||
463 | /* | |
464 | * We win! This label is here just for ease of understanding | |
465 | * perf profiles. Nothing jumps here. | |
466 | */ | |
467 | syscall_return_via_sysret: | |
468 | CFI_REMEMBER_STATE | |
469 | /* r11 is already restored (see code above) */ | |
470 | RESTORE_C_REGS_EXCEPT_R11 | |
471 | movq RSP(%rsp),%rsp | |
472 | USERGS_SYSRET64 | |
473 | CFI_RESTORE_STATE | |
474 | ||
475 | opportunistic_sysret_failed: | |
476 | SWAPGS | |
477 | jmp restore_c_regs_and_iret | |
1da177e4 | 478 | CFI_ENDPROC |
bcddc015 | 479 | END(system_call) |
0bd7b798 | 480 | |
fffbb5dc | 481 | |
1d4b4b29 AV |
482 | .macro FORK_LIKE func |
483 | ENTRY(stub_\func) | |
484 | CFI_STARTPROC | |
76f5df43 DV |
485 | DEFAULT_FRAME 0, 8 /* offset 8: return address */ |
486 | SAVE_EXTRA_REGS 8 | |
1d4b4b29 | 487 | call sys_\func |
76f5df43 | 488 | ret |
1d4b4b29 AV |
489 | CFI_ENDPROC |
490 | END(stub_\func) | |
491 | .endm | |
492 | ||
493 | FORK_LIKE clone | |
494 | FORK_LIKE fork | |
495 | FORK_LIKE vfork | |
1da177e4 | 496 | |
1da177e4 LT |
497 | ENTRY(stub_execve) |
498 | CFI_STARTPROC | |
fc3e958a DV |
499 | DEFAULT_FRAME 0, 8 |
500 | call sys_execve | |
501 | return_from_execve: | |
502 | testl %eax, %eax | |
503 | jz 1f | |
504 | /* exec failed, can use fast SYSRET code path in this case */ | |
505 | ret | |
506 | 1: | |
507 | /* must use IRET code path (pt_regs->cs may have changed) */ | |
508 | addq $8, %rsp | |
509 | ZERO_EXTRA_REGS | |
510 | movq %rax,RAX(%rsp) | |
511 | jmp int_ret_from_sys_call | |
1da177e4 | 512 | CFI_ENDPROC |
4b787e0b | 513 | END(stub_execve) |
0bd7b798 | 514 | |
27d6ec7a DD |
515 | ENTRY(stub_execveat) |
516 | CFI_STARTPROC | |
fc3e958a DV |
517 | DEFAULT_FRAME 0, 8 |
518 | call sys_execveat | |
519 | jmp return_from_execve | |
27d6ec7a DD |
520 | CFI_ENDPROC |
521 | END(stub_execveat) | |
522 | ||
1da177e4 LT |
523 | /* |
524 | * sigreturn is special because it needs to restore all registers on return. | |
525 | * This cannot be done with SYSRET, so use the IRET return path instead. | |
0bd7b798 | 526 | */ |
1da177e4 LT |
527 | ENTRY(stub_rt_sigreturn) |
528 | CFI_STARTPROC | |
7effaa88 | 529 | addq $8, %rsp |
76f5df43 DV |
530 | DEFAULT_FRAME 0 |
531 | SAVE_EXTRA_REGS | |
1da177e4 LT |
532 | call sys_rt_sigreturn |
533 | movq %rax,RAX(%rsp) # fixme, this could be done at the higher layer | |
76f5df43 | 534 | RESTORE_EXTRA_REGS |
1da177e4 LT |
535 | jmp int_ret_from_sys_call |
536 | CFI_ENDPROC | |
4b787e0b | 537 | END(stub_rt_sigreturn) |
1da177e4 | 538 | |
c5a37394 | 539 | #ifdef CONFIG_X86_X32_ABI |
c5a37394 PA |
540 | ENTRY(stub_x32_rt_sigreturn) |
541 | CFI_STARTPROC | |
542 | addq $8, %rsp | |
76f5df43 DV |
543 | DEFAULT_FRAME 0 |
544 | SAVE_EXTRA_REGS | |
c5a37394 PA |
545 | call sys32_x32_rt_sigreturn |
546 | movq %rax,RAX(%rsp) # fixme, this could be done at the higher layer | |
76f5df43 | 547 | RESTORE_EXTRA_REGS |
c5a37394 PA |
548 | jmp int_ret_from_sys_call |
549 | CFI_ENDPROC | |
550 | END(stub_x32_rt_sigreturn) | |
551 | ||
d1a797f3 PA |
552 | ENTRY(stub_x32_execve) |
553 | CFI_STARTPROC | |
fc3e958a DV |
554 | DEFAULT_FRAME 0, 8 |
555 | call compat_sys_execve | |
556 | jmp return_from_execve | |
d1a797f3 PA |
557 | CFI_ENDPROC |
558 | END(stub_x32_execve) | |
559 | ||
27d6ec7a DD |
560 | ENTRY(stub_x32_execveat) |
561 | CFI_STARTPROC | |
fc3e958a DV |
562 | DEFAULT_FRAME 0, 8 |
563 | call compat_sys_execveat | |
564 | jmp return_from_execve | |
27d6ec7a DD |
565 | CFI_ENDPROC |
566 | END(stub_x32_execveat) | |
567 | ||
c5a37394 PA |
568 | #endif |
569 | ||
1eeb207f DV |
570 | /* |
571 | * A newly forked process directly context switches into this address. | |
572 | * | |
573 | * rdi: prev task we switched from | |
574 | */ | |
575 | ENTRY(ret_from_fork) | |
576 | DEFAULT_FRAME | |
577 | ||
578 | LOCK ; btr $TIF_FORK,TI_flags(%r8) | |
579 | ||
580 | pushq_cfi $0x0002 | |
581 | popfq_cfi # reset kernel eflags | |
582 | ||
583 | call schedule_tail # rdi: 'prev' task parameter | |
584 | ||
585 | GET_THREAD_INFO(%rcx) | |
586 | ||
587 | RESTORE_EXTRA_REGS | |
588 | ||
589 | testl $3,CS(%rsp) # from kernel_thread? | |
590 | jz 1f | |
591 | ||
1e3fbb8a AL |
592 | /* |
593 | * By the time we get here, we have no idea whether our pt_regs, | |
594 | * ti flags, and ti status came from the 64-bit SYSCALL fast path, | |
595 | * the slow path, or one of the ia32entry paths. | |
596 | * Use int_ret_from_sys_call to return, since it can safely handle | |
597 | * all of the above. | |
598 | */ | |
599 | jmp int_ret_from_sys_call | |
1eeb207f DV |
600 | |
601 | 1: | |
602 | movq %rbp, %rdi | |
603 | call *%rbx | |
604 | movl $0, RAX(%rsp) | |
605 | RESTORE_EXTRA_REGS | |
606 | jmp int_ret_from_sys_call | |
607 | CFI_ENDPROC | |
608 | END(ret_from_fork) | |
609 | ||
939b7871 PA |
610 | /* |
611 | * Build the entry stubs and pointer table with some assembler magic. | |
612 | * We pack 7 stubs into a single 32-byte chunk, which will fit in a | |
613 | * single cache line on all modern x86 implementations. | |
614 | */ | |
615 | .section .init.rodata,"a" | |
616 | ENTRY(interrupt) | |
ea714547 | 617 | .section .entry.text |
939b7871 PA |
618 | .p2align 5 |
619 | .p2align CONFIG_X86_L1_CACHE_SHIFT | |
620 | ENTRY(irq_entries_start) | |
621 | INTR_FRAME | |
622 | vector=FIRST_EXTERNAL_VECTOR | |
2414e021 | 623 | .rept (FIRST_SYSTEM_VECTOR-FIRST_EXTERNAL_VECTOR+6)/7 |
939b7871 PA |
624 | .balign 32 |
625 | .rept 7 | |
2414e021 | 626 | .if vector < FIRST_SYSTEM_VECTOR |
8665596e | 627 | .if vector <> FIRST_EXTERNAL_VECTOR |
939b7871 PA |
628 | CFI_ADJUST_CFA_OFFSET -8 |
629 | .endif | |
df5d1874 | 630 | 1: pushq_cfi $(~vector+0x80) /* Note: always in signed byte range */ |
8665596e | 631 | .if ((vector-FIRST_EXTERNAL_VECTOR)%7) <> 6 |
939b7871 PA |
632 | jmp 2f |
633 | .endif | |
634 | .previous | |
635 | .quad 1b | |
ea714547 | 636 | .section .entry.text |
939b7871 PA |
637 | vector=vector+1 |
638 | .endif | |
639 | .endr | |
640 | 2: jmp common_interrupt | |
641 | .endr | |
642 | CFI_ENDPROC | |
643 | END(irq_entries_start) | |
644 | ||
645 | .previous | |
646 | END(interrupt) | |
647 | .previous | |
648 | ||
d99015b1 | 649 | /* |
1da177e4 LT |
650 | * Interrupt entry/exit. |
651 | * | |
652 | * Interrupt entry points save only callee clobbered registers in fast path. | |
d99015b1 AH |
653 | * |
654 | * Entry runs with interrupts off. | |
655 | */ | |
1da177e4 | 656 | |
722024db | 657 | /* 0(%rsp): ~(interrupt number) */ |
1da177e4 | 658 | .macro interrupt func |
f6f64681 | 659 | cld |
e90e147c DV |
660 | /* |
661 | * Since nothing in interrupt handling code touches r12...r15 members | |
662 | * of "struct pt_regs", and since interrupts can nest, we can save | |
663 | * four stack slots and simultaneously provide | |
664 | * an unwind-friendly stack layout by saving "truncated" pt_regs | |
665 | * exactly up to rbp slot, without these members. | |
666 | */ | |
76f5df43 DV |
667 | ALLOC_PT_GPREGS_ON_STACK -RBP |
668 | SAVE_C_REGS -RBP | |
669 | /* this goes to 0(%rsp) for unwinder, not for saving the value: */ | |
670 | SAVE_EXTRA_REGS_RBP -RBP | |
671 | ||
672 | leaq -RBP(%rsp),%rdi /* arg1 for \func (pointer to pt_regs) */ | |
f6f64681 | 673 | |
76f5df43 | 674 | testl $3, CS-RBP(%rsp) |
f6f64681 DV |
675 | je 1f |
676 | SWAPGS | |
76f5df43 | 677 | 1: |
f6f64681 | 678 | /* |
e90e147c | 679 | * Save previous stack pointer, optionally switch to interrupt stack. |
f6f64681 DV |
680 | * irq_count is used to check if a CPU is already on an interrupt stack |
681 | * or not. While this is essentially redundant with preempt_count it is | |
682 | * a little cheaper to use a separate counter in the PDA (short of | |
683 | * moving irq_enter into assembly, which would be too much work) | |
684 | */ | |
76f5df43 DV |
685 | movq %rsp, %rsi |
686 | incl PER_CPU_VAR(irq_count) | |
f6f64681 DV |
687 | cmovzq PER_CPU_VAR(irq_stack_ptr),%rsp |
688 | CFI_DEF_CFA_REGISTER rsi | |
f6f64681 | 689 | pushq %rsi |
911d2bb5 DV |
690 | /* |
691 | * For debugger: | |
692 | * "CFA (Current Frame Address) is the value on stack + offset" | |
693 | */ | |
f6f64681 | 694 | CFI_ESCAPE 0x0f /* DW_CFA_def_cfa_expression */, 6, \ |
911d2bb5 | 695 | 0x77 /* DW_OP_breg7 (rsp) */, 0, \ |
f6f64681 | 696 | 0x06 /* DW_OP_deref */, \ |
911d2bb5 | 697 | 0x08 /* DW_OP_const1u */, SIZEOF_PTREGS-RBP, \ |
f6f64681 DV |
698 | 0x22 /* DW_OP_plus */ |
699 | /* We entered an interrupt context - irqs are off: */ | |
700 | TRACE_IRQS_OFF | |
701 | ||
1da177e4 LT |
702 | call \func |
703 | .endm | |
704 | ||
722024db AH |
705 | /* |
706 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
707 | * then jump to common_interrupt. | |
708 | */ | |
939b7871 PA |
709 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
710 | common_interrupt: | |
7effaa88 | 711 | XCPT_FRAME |
ee4eb87b | 712 | ASM_CLAC |
722024db | 713 | addq $-0x80,(%rsp) /* Adjust vector to [-256,-1] range */ |
1da177e4 | 714 | interrupt do_IRQ |
34061f13 | 715 | /* 0(%rsp): old RSP */ |
7effaa88 | 716 | ret_from_intr: |
72fe4858 | 717 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 718 | TRACE_IRQS_OFF |
56895530 | 719 | decl PER_CPU_VAR(irq_count) |
625dbc3b | 720 | |
a2bbe750 FW |
721 | /* Restore saved previous stack */ |
722 | popq %rsi | |
911d2bb5 | 723 | CFI_DEF_CFA rsi,SIZEOF_PTREGS-RBP /* reg/off reset after def_cfa_expr */ |
e90e147c | 724 | /* return code expects complete pt_regs - adjust rsp accordingly: */ |
f2db9382 | 725 | leaq -RBP(%rsi),%rsp |
7effaa88 | 726 | CFI_DEF_CFA_REGISTER rsp |
f2db9382 | 727 | CFI_ADJUST_CFA_OFFSET RBP |
625dbc3b | 728 | |
f2db9382 | 729 | testl $3,CS(%rsp) |
1da177e4 | 730 | je retint_kernel |
1da177e4 | 731 | /* Interrupt came from user space */ |
a3675b32 DV |
732 | |
733 | GET_THREAD_INFO(%rcx) | |
1da177e4 | 734 | /* |
1da177e4 | 735 | * %rcx: thread info. Interrupts off. |
0bd7b798 | 736 | */ |
1da177e4 LT |
737 | retint_with_reschedule: |
738 | movl $_TIF_WORK_MASK,%edi | |
7effaa88 | 739 | retint_check: |
10cd706d | 740 | LOCKDEP_SYS_EXIT_IRQ |
26ccb8a7 | 741 | movl TI_flags(%rcx),%edx |
1da177e4 | 742 | andl %edi,%edx |
7effaa88 | 743 | CFI_REMEMBER_STATE |
1da177e4 | 744 | jnz retint_careful |
10cd706d PZ |
745 | |
746 | retint_swapgs: /* return to user-space */ | |
2601e64d IM |
747 | /* |
748 | * The iretq could re-enable interrupts: | |
749 | */ | |
72fe4858 | 750 | DISABLE_INTERRUPTS(CLBR_ANY) |
2601e64d | 751 | TRACE_IRQS_IRETQ |
2a23c6b8 | 752 | |
72fe4858 | 753 | SWAPGS |
fffbb5dc | 754 | jmp restore_c_regs_and_iret |
2601e64d | 755 | |
627276cb | 756 | /* Returning to kernel space */ |
6ba71b76 | 757 | retint_kernel: |
627276cb DV |
758 | #ifdef CONFIG_PREEMPT |
759 | /* Interrupts are off */ | |
760 | /* Check if we need preemption */ | |
627276cb | 761 | bt $9,EFLAGS(%rsp) /* interrupts were off? */ |
6ba71b76 | 762 | jnc 1f |
36acef25 DV |
763 | 0: cmpl $0,PER_CPU_VAR(__preempt_count) |
764 | jnz 1f | |
627276cb | 765 | call preempt_schedule_irq |
36acef25 | 766 | jmp 0b |
6ba71b76 | 767 | 1: |
627276cb | 768 | #endif |
2601e64d IM |
769 | /* |
770 | * The iretq could re-enable interrupts: | |
771 | */ | |
772 | TRACE_IRQS_IRETQ | |
fffbb5dc DV |
773 | |
774 | /* | |
775 | * At this label, code paths which return to kernel and to user, | |
776 | * which come from interrupts/exception and from syscalls, merge. | |
777 | */ | |
778 | restore_c_regs_and_iret: | |
76f5df43 DV |
779 | RESTORE_C_REGS |
780 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
3701d863 | 781 | |
f7f3d791 | 782 | irq_return: |
7209a75d AL |
783 | INTERRUPT_RETURN |
784 | ||
785 | ENTRY(native_iret) | |
3891a04a PA |
786 | /* |
787 | * Are we returning to a stack segment from the LDT? Note: in | |
788 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
789 | */ | |
34273f41 | 790 | #ifdef CONFIG_X86_ESPFIX64 |
3891a04a | 791 | testb $4,(SS-RIP)(%rsp) |
7209a75d | 792 | jnz native_irq_return_ldt |
34273f41 | 793 | #endif |
3891a04a | 794 | |
af726f21 | 795 | .global native_irq_return_iret |
7209a75d | 796 | native_irq_return_iret: |
b645af2d AL |
797 | /* |
798 | * This may fault. Non-paranoid faults on return to userspace are | |
799 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
800 | * Double-faults due to espfix64 are handled in do_double_fault. | |
801 | * Other faults here are fatal. | |
802 | */ | |
1da177e4 | 803 | iretq |
3701d863 | 804 | |
34273f41 | 805 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 806 | native_irq_return_ldt: |
3891a04a PA |
807 | pushq_cfi %rax |
808 | pushq_cfi %rdi | |
809 | SWAPGS | |
810 | movq PER_CPU_VAR(espfix_waddr),%rdi | |
811 | movq %rax,(0*8)(%rdi) /* RAX */ | |
812 | movq (2*8)(%rsp),%rax /* RIP */ | |
813 | movq %rax,(1*8)(%rdi) | |
814 | movq (3*8)(%rsp),%rax /* CS */ | |
815 | movq %rax,(2*8)(%rdi) | |
816 | movq (4*8)(%rsp),%rax /* RFLAGS */ | |
817 | movq %rax,(3*8)(%rdi) | |
818 | movq (6*8)(%rsp),%rax /* SS */ | |
819 | movq %rax,(5*8)(%rdi) | |
820 | movq (5*8)(%rsp),%rax /* RSP */ | |
821 | movq %rax,(4*8)(%rdi) | |
822 | andl $0xffff0000,%eax | |
823 | popq_cfi %rdi | |
824 | orq PER_CPU_VAR(espfix_stack),%rax | |
825 | SWAPGS | |
826 | movq %rax,%rsp | |
827 | popq_cfi %rax | |
7209a75d | 828 | jmp native_irq_return_iret |
34273f41 | 829 | #endif |
3891a04a | 830 | |
7effaa88 | 831 | /* edi: workmask, edx: work */ |
1da177e4 | 832 | retint_careful: |
7effaa88 | 833 | CFI_RESTORE_STATE |
1da177e4 LT |
834 | bt $TIF_NEED_RESCHED,%edx |
835 | jnc retint_signal | |
2601e64d | 836 | TRACE_IRQS_ON |
72fe4858 | 837 | ENABLE_INTERRUPTS(CLBR_NONE) |
df5d1874 | 838 | pushq_cfi %rdi |
0430499c | 839 | SCHEDULE_USER |
df5d1874 | 840 | popq_cfi %rdi |
1da177e4 | 841 | GET_THREAD_INFO(%rcx) |
72fe4858 | 842 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 843 | TRACE_IRQS_OFF |
1da177e4 | 844 | jmp retint_check |
0bd7b798 | 845 | |
1da177e4 | 846 | retint_signal: |
8f4d37ec | 847 | testl $_TIF_DO_NOTIFY_MASK,%edx |
10ffdbb8 | 848 | jz retint_swapgs |
2601e64d | 849 | TRACE_IRQS_ON |
72fe4858 | 850 | ENABLE_INTERRUPTS(CLBR_NONE) |
76f5df43 | 851 | SAVE_EXTRA_REGS |
0bd7b798 | 852 | movq $-1,ORIG_RAX(%rsp) |
3829ee6b | 853 | xorl %esi,%esi # oldset |
1da177e4 LT |
854 | movq %rsp,%rdi # &pt_regs |
855 | call do_notify_resume | |
76f5df43 | 856 | RESTORE_EXTRA_REGS |
72fe4858 | 857 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 858 | TRACE_IRQS_OFF |
be9e6870 | 859 | GET_THREAD_INFO(%rcx) |
eca91e78 | 860 | jmp retint_with_reschedule |
1da177e4 | 861 | |
1da177e4 | 862 | CFI_ENDPROC |
4b787e0b | 863 | END(common_interrupt) |
3891a04a | 864 | |
1da177e4 LT |
865 | /* |
866 | * APIC interrupts. | |
0bd7b798 | 867 | */ |
cf910e83 | 868 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 869 | ENTRY(\sym) |
7effaa88 | 870 | INTR_FRAME |
ee4eb87b | 871 | ASM_CLAC |
df5d1874 | 872 | pushq_cfi $~(\num) |
39e95433 | 873 | .Lcommon_\sym: |
322648d1 | 874 | interrupt \do_sym |
1da177e4 LT |
875 | jmp ret_from_intr |
876 | CFI_ENDPROC | |
322648d1 AH |
877 | END(\sym) |
878 | .endm | |
1da177e4 | 879 | |
cf910e83 SA |
880 | #ifdef CONFIG_TRACING |
881 | #define trace(sym) trace_##sym | |
882 | #define smp_trace(sym) smp_trace_##sym | |
883 | ||
884 | .macro trace_apicinterrupt num sym | |
885 | apicinterrupt3 \num trace(\sym) smp_trace(\sym) | |
886 | .endm | |
887 | #else | |
888 | .macro trace_apicinterrupt num sym do_sym | |
889 | .endm | |
890 | #endif | |
891 | ||
892 | .macro apicinterrupt num sym do_sym | |
893 | apicinterrupt3 \num \sym \do_sym | |
894 | trace_apicinterrupt \num \sym | |
895 | .endm | |
896 | ||
322648d1 | 897 | #ifdef CONFIG_SMP |
cf910e83 | 898 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR \ |
322648d1 | 899 | irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
cf910e83 | 900 | apicinterrupt3 REBOOT_VECTOR \ |
4ef702c1 | 901 | reboot_interrupt smp_reboot_interrupt |
322648d1 | 902 | #endif |
1da177e4 | 903 | |
03b48632 | 904 | #ifdef CONFIG_X86_UV |
cf910e83 | 905 | apicinterrupt3 UV_BAU_MESSAGE \ |
322648d1 | 906 | uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 907 | #endif |
322648d1 AH |
908 | apicinterrupt LOCAL_TIMER_VECTOR \ |
909 | apic_timer_interrupt smp_apic_timer_interrupt | |
4a4de9c7 DS |
910 | apicinterrupt X86_PLATFORM_IPI_VECTOR \ |
911 | x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 912 | |
d78f2664 | 913 | #ifdef CONFIG_HAVE_KVM |
cf910e83 | 914 | apicinterrupt3 POSTED_INTR_VECTOR \ |
d78f2664 YZ |
915 | kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
916 | #endif | |
917 | ||
33e5ff63 | 918 | #ifdef CONFIG_X86_MCE_THRESHOLD |
322648d1 | 919 | apicinterrupt THRESHOLD_APIC_VECTOR \ |
7856f6cc | 920 | threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
921 | #endif |
922 | ||
923 | #ifdef CONFIG_X86_THERMAL_VECTOR | |
322648d1 AH |
924 | apicinterrupt THERMAL_APIC_VECTOR \ |
925 | thermal_interrupt smp_thermal_interrupt | |
33e5ff63 | 926 | #endif |
1812924b | 927 | |
322648d1 AH |
928 | #ifdef CONFIG_SMP |
929 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR \ | |
930 | call_function_single_interrupt smp_call_function_single_interrupt | |
931 | apicinterrupt CALL_FUNCTION_VECTOR \ | |
932 | call_function_interrupt smp_call_function_interrupt | |
933 | apicinterrupt RESCHEDULE_VECTOR \ | |
934 | reschedule_interrupt smp_reschedule_interrupt | |
935 | #endif | |
1da177e4 | 936 | |
322648d1 AH |
937 | apicinterrupt ERROR_APIC_VECTOR \ |
938 | error_interrupt smp_error_interrupt | |
939 | apicinterrupt SPURIOUS_APIC_VECTOR \ | |
940 | spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 941 | |
e360adbe PZ |
942 | #ifdef CONFIG_IRQ_WORK |
943 | apicinterrupt IRQ_WORK_VECTOR \ | |
944 | irq_work_interrupt smp_irq_work_interrupt | |
241771ef IM |
945 | #endif |
946 | ||
1da177e4 LT |
947 | /* |
948 | * Exception entry points. | |
0bd7b798 | 949 | */ |
9b476688 | 950 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) |
577ed45e AL |
951 | |
952 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 | |
322648d1 | 953 | ENTRY(\sym) |
577ed45e AL |
954 | /* Sanity check */ |
955 | .if \shift_ist != -1 && \paranoid == 0 | |
956 | .error "using shift_ist requires paranoid=1" | |
957 | .endif | |
958 | ||
cb5dd2c5 AL |
959 | .if \has_error_code |
960 | XCPT_FRAME | |
961 | .else | |
7effaa88 | 962 | INTR_FRAME |
cb5dd2c5 | 963 | .endif |
1da177e4 | 964 | |
ee4eb87b | 965 | ASM_CLAC |
b8b1d08b | 966 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
cb5dd2c5 AL |
967 | |
968 | .ifeq \has_error_code | |
969 | pushq_cfi $-1 /* ORIG_RAX: no syscall to restart */ | |
970 | .endif | |
971 | ||
76f5df43 | 972 | ALLOC_PT_GPREGS_ON_STACK |
cb5dd2c5 AL |
973 | |
974 | .if \paranoid | |
48e08d0f AL |
975 | .if \paranoid == 1 |
976 | CFI_REMEMBER_STATE | |
977 | testl $3, CS(%rsp) /* If coming from userspace, switch */ | |
978 | jnz 1f /* stacks. */ | |
979 | .endif | |
ebfc453e | 980 | call paranoid_entry |
cb5dd2c5 AL |
981 | .else |
982 | call error_entry | |
983 | .endif | |
ebfc453e | 984 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 985 | |
1bd24efc | 986 | DEFAULT_FRAME 0 |
cb5dd2c5 AL |
987 | |
988 | .if \paranoid | |
577ed45e AL |
989 | .if \shift_ist != -1 |
990 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ | |
991 | .else | |
b8b1d08b | 992 | TRACE_IRQS_OFF |
cb5dd2c5 | 993 | .endif |
577ed45e | 994 | .endif |
cb5dd2c5 AL |
995 | |
996 | movq %rsp,%rdi /* pt_regs pointer */ | |
997 | ||
998 | .if \has_error_code | |
999 | movq ORIG_RAX(%rsp),%rsi /* get error code */ | |
1000 | movq $-1,ORIG_RAX(%rsp) /* no syscall to restart */ | |
1001 | .else | |
1002 | xorl %esi,%esi /* no error code */ | |
1003 | .endif | |
1004 | ||
577ed45e | 1005 | .if \shift_ist != -1 |
9b476688 | 1006 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
1007 | .endif |
1008 | ||
322648d1 | 1009 | call \do_sym |
cb5dd2c5 | 1010 | |
577ed45e | 1011 | .if \shift_ist != -1 |
9b476688 | 1012 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
1013 | .endif |
1014 | ||
ebfc453e | 1015 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 1016 | .if \paranoid |
ebfc453e | 1017 | jmp paranoid_exit |
cb5dd2c5 | 1018 | .else |
ebfc453e | 1019 | jmp error_exit |
cb5dd2c5 AL |
1020 | .endif |
1021 | ||
48e08d0f AL |
1022 | .if \paranoid == 1 |
1023 | CFI_RESTORE_STATE | |
1024 | /* | |
1025 | * Paranoid entry from userspace. Switch stacks and treat it | |
1026 | * as a normal entry. This means that paranoid handlers | |
1027 | * run in real process context if user_mode(regs). | |
1028 | */ | |
1029 | 1: | |
1030 | call error_entry | |
1031 | ||
1032 | DEFAULT_FRAME 0 | |
1033 | ||
1034 | movq %rsp,%rdi /* pt_regs pointer */ | |
1035 | call sync_regs | |
1036 | movq %rax,%rsp /* switch stack */ | |
1037 | ||
1038 | movq %rsp,%rdi /* pt_regs pointer */ | |
1039 | ||
1040 | .if \has_error_code | |
1041 | movq ORIG_RAX(%rsp),%rsi /* get error code */ | |
1042 | movq $-1,ORIG_RAX(%rsp) /* no syscall to restart */ | |
1043 | .else | |
1044 | xorl %esi,%esi /* no error code */ | |
1045 | .endif | |
1046 | ||
1047 | call \do_sym | |
1048 | ||
1049 | jmp error_exit /* %ebx: no swapgs flag */ | |
1050 | .endif | |
1051 | ||
b8b1d08b | 1052 | CFI_ENDPROC |
ddeb8f21 | 1053 | END(\sym) |
322648d1 | 1054 | .endm |
b8b1d08b | 1055 | |
25c74b10 | 1056 | #ifdef CONFIG_TRACING |
cb5dd2c5 AL |
1057 | .macro trace_idtentry sym do_sym has_error_code:req |
1058 | idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code | |
1059 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
1060 | .endm |
1061 | #else | |
cb5dd2c5 AL |
1062 | .macro trace_idtentry sym do_sym has_error_code:req |
1063 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
1064 | .endm |
1065 | #endif | |
1066 | ||
cb5dd2c5 AL |
1067 | idtentry divide_error do_divide_error has_error_code=0 |
1068 | idtentry overflow do_overflow has_error_code=0 | |
1069 | idtentry bounds do_bounds has_error_code=0 | |
1070 | idtentry invalid_op do_invalid_op has_error_code=0 | |
1071 | idtentry device_not_available do_device_not_available has_error_code=0 | |
48e08d0f | 1072 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 |
cb5dd2c5 AL |
1073 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 |
1074 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
1075 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
1076 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
1077 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
1078 | idtentry alignment_check do_alignment_check has_error_code=1 | |
1079 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
5cec93c2 | 1080 | |
2601e64d | 1081 | |
9f1e87ea CG |
1082 | /* Reload gs selector with exception handling */ |
1083 | /* edi: new selector */ | |
9f9d489a | 1084 | ENTRY(native_load_gs_index) |
7effaa88 | 1085 | CFI_STARTPROC |
df5d1874 | 1086 | pushfq_cfi |
b8aa287f | 1087 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
9f1e87ea | 1088 | SWAPGS |
0bd7b798 | 1089 | gs_change: |
9f1e87ea | 1090 | movl %edi,%gs |
1da177e4 | 1091 | 2: mfence /* workaround */ |
72fe4858 | 1092 | SWAPGS |
df5d1874 | 1093 | popfq_cfi |
9f1e87ea | 1094 | ret |
7effaa88 | 1095 | CFI_ENDPROC |
6efdcfaf | 1096 | END(native_load_gs_index) |
0bd7b798 | 1097 | |
d7abc0fa | 1098 | _ASM_EXTABLE(gs_change,bad_gs) |
9f1e87ea | 1099 | .section .fixup,"ax" |
1da177e4 | 1100 | /* running with kernelgs */ |
0bd7b798 | 1101 | bad_gs: |
72fe4858 | 1102 | SWAPGS /* switch back to user gs */ |
1da177e4 | 1103 | xorl %eax,%eax |
9f1e87ea CG |
1104 | movl %eax,%gs |
1105 | jmp 2b | |
1106 | .previous | |
0bd7b798 | 1107 | |
2699500b | 1108 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 1109 | ENTRY(do_softirq_own_stack) |
7effaa88 | 1110 | CFI_STARTPROC |
df5d1874 | 1111 | pushq_cfi %rbp |
2699500b AK |
1112 | CFI_REL_OFFSET rbp,0 |
1113 | mov %rsp,%rbp | |
1114 | CFI_DEF_CFA_REGISTER rbp | |
56895530 | 1115 | incl PER_CPU_VAR(irq_count) |
26f80bd6 | 1116 | cmove PER_CPU_VAR(irq_stack_ptr),%rsp |
2699500b | 1117 | push %rbp # backlink for old unwinder |
ed6b676c | 1118 | call __do_softirq |
2699500b | 1119 | leaveq |
df5d1874 | 1120 | CFI_RESTORE rbp |
7effaa88 | 1121 | CFI_DEF_CFA_REGISTER rsp |
2699500b | 1122 | CFI_ADJUST_CFA_OFFSET -8 |
56895530 | 1123 | decl PER_CPU_VAR(irq_count) |
ed6b676c | 1124 | ret |
7effaa88 | 1125 | CFI_ENDPROC |
7d65f4a6 | 1126 | END(do_softirq_own_stack) |
75154f40 | 1127 | |
3d75e1b8 | 1128 | #ifdef CONFIG_XEN |
cb5dd2c5 | 1129 | idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
1130 | |
1131 | /* | |
9f1e87ea CG |
1132 | * A note on the "critical region" in our callback handler. |
1133 | * We want to avoid stacking callback handlers due to events occurring | |
1134 | * during handling of the last event. To do this, we keep events disabled | |
1135 | * until we've done all processing. HOWEVER, we must enable events before | |
1136 | * popping the stack frame (can't be done atomically) and so it would still | |
1137 | * be possible to get enough handler activations to overflow the stack. | |
1138 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
1139 | * like to avoid the possibility. | |
1140 | * So, on entry to the handler we detect whether we interrupted an | |
1141 | * existing activation in its critical region -- if so, we pop the current | |
1142 | * activation and restart the handler using the previous one. | |
1143 | */ | |
3d75e1b8 JF |
1144 | ENTRY(xen_do_hypervisor_callback) # do_hypervisor_callback(struct *pt_regs) |
1145 | CFI_STARTPROC | |
9f1e87ea CG |
1146 | /* |
1147 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
1148 | * see the correct pointer to the pt_regs | |
1149 | */ | |
3d75e1b8 JF |
1150 | movq %rdi, %rsp # we don't return, adjust the stack frame |
1151 | CFI_ENDPROC | |
dcd072e2 | 1152 | DEFAULT_FRAME |
56895530 | 1153 | 11: incl PER_CPU_VAR(irq_count) |
3d75e1b8 JF |
1154 | movq %rsp,%rbp |
1155 | CFI_DEF_CFA_REGISTER rbp | |
26f80bd6 | 1156 | cmovzq PER_CPU_VAR(irq_stack_ptr),%rsp |
3d75e1b8 JF |
1157 | pushq %rbp # backlink for old unwinder |
1158 | call xen_evtchn_do_upcall | |
1159 | popq %rsp | |
1160 | CFI_DEF_CFA_REGISTER rsp | |
56895530 | 1161 | decl PER_CPU_VAR(irq_count) |
fdfd811d DV |
1162 | #ifndef CONFIG_PREEMPT |
1163 | call xen_maybe_preempt_hcall | |
1164 | #endif | |
3d75e1b8 JF |
1165 | jmp error_exit |
1166 | CFI_ENDPROC | |
371c394a | 1167 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
1168 | |
1169 | /* | |
9f1e87ea CG |
1170 | * Hypervisor uses this for application faults while it executes. |
1171 | * We get here for two reasons: | |
1172 | * 1. Fault while reloading DS, ES, FS or GS | |
1173 | * 2. Fault while executing IRET | |
1174 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
1175 | * registers that could be reloaded and zeroed the others. | |
1176 | * Category 2 we fix up by killing the current process. We cannot use the | |
1177 | * normal Linux return path in this case because if we use the IRET hypercall | |
1178 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
1179 | * We distinguish between categories by comparing each saved segment register | |
1180 | * with its current contents: any discrepancy means we in category 1. | |
1181 | */ | |
3d75e1b8 | 1182 | ENTRY(xen_failsafe_callback) |
dcd072e2 AH |
1183 | INTR_FRAME 1 (6*8) |
1184 | /*CFI_REL_OFFSET gs,GS*/ | |
1185 | /*CFI_REL_OFFSET fs,FS*/ | |
1186 | /*CFI_REL_OFFSET es,ES*/ | |
1187 | /*CFI_REL_OFFSET ds,DS*/ | |
1188 | CFI_REL_OFFSET r11,8 | |
1189 | CFI_REL_OFFSET rcx,0 | |
3d75e1b8 JF |
1190 | movw %ds,%cx |
1191 | cmpw %cx,0x10(%rsp) | |
1192 | CFI_REMEMBER_STATE | |
1193 | jne 1f | |
1194 | movw %es,%cx | |
1195 | cmpw %cx,0x18(%rsp) | |
1196 | jne 1f | |
1197 | movw %fs,%cx | |
1198 | cmpw %cx,0x20(%rsp) | |
1199 | jne 1f | |
1200 | movw %gs,%cx | |
1201 | cmpw %cx,0x28(%rsp) | |
1202 | jne 1f | |
1203 | /* All segments match their saved values => Category 2 (Bad IRET). */ | |
1204 | movq (%rsp),%rcx | |
1205 | CFI_RESTORE rcx | |
1206 | movq 8(%rsp),%r11 | |
1207 | CFI_RESTORE r11 | |
1208 | addq $0x30,%rsp | |
1209 | CFI_ADJUST_CFA_OFFSET -0x30 | |
14ae22ba IM |
1210 | pushq_cfi $0 /* RIP */ |
1211 | pushq_cfi %r11 | |
1212 | pushq_cfi %rcx | |
4a5c3e77 | 1213 | jmp general_protection |
3d75e1b8 JF |
1214 | CFI_RESTORE_STATE |
1215 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ | |
1216 | movq (%rsp),%rcx | |
1217 | CFI_RESTORE rcx | |
1218 | movq 8(%rsp),%r11 | |
1219 | CFI_RESTORE r11 | |
1220 | addq $0x30,%rsp | |
1221 | CFI_ADJUST_CFA_OFFSET -0x30 | |
a349e23d | 1222 | pushq_cfi $-1 /* orig_ax = -1 => not a system call */ |
76f5df43 DV |
1223 | ALLOC_PT_GPREGS_ON_STACK |
1224 | SAVE_C_REGS | |
1225 | SAVE_EXTRA_REGS | |
3d75e1b8 JF |
1226 | jmp error_exit |
1227 | CFI_ENDPROC | |
3d75e1b8 JF |
1228 | END(xen_failsafe_callback) |
1229 | ||
cf910e83 | 1230 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 SY |
1231 | xen_hvm_callback_vector xen_evtchn_do_upcall |
1232 | ||
3d75e1b8 | 1233 | #endif /* CONFIG_XEN */ |
ddeb8f21 | 1234 | |
bc2b0331 | 1235 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 1236 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 S |
1237 | hyperv_callback_vector hyperv_vector_handler |
1238 | #endif /* CONFIG_HYPERV */ | |
1239 | ||
577ed45e AL |
1240 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
1241 | idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK | |
6f442be2 | 1242 | idtentry stack_segment do_stack_segment has_error_code=1 |
6cac5a92 | 1243 | #ifdef CONFIG_XEN |
cb5dd2c5 AL |
1244 | idtentry xen_debug do_debug has_error_code=0 |
1245 | idtentry xen_int3 do_int3 has_error_code=0 | |
1246 | idtentry xen_stack_segment do_stack_segment has_error_code=1 | |
6cac5a92 | 1247 | #endif |
cb5dd2c5 AL |
1248 | idtentry general_protection do_general_protection has_error_code=1 |
1249 | trace_idtentry page_fault do_page_fault has_error_code=1 | |
631bc487 | 1250 | #ifdef CONFIG_KVM_GUEST |
cb5dd2c5 | 1251 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 1252 | #endif |
ddeb8f21 | 1253 | #ifdef CONFIG_X86_MCE |
cb5dd2c5 | 1254 | idtentry machine_check has_error_code=0 paranoid=1 do_sym=*machine_check_vector(%rip) |
ddeb8f21 AH |
1255 | #endif |
1256 | ||
ebfc453e DV |
1257 | /* |
1258 | * Save all registers in pt_regs, and switch gs if needed. | |
1259 | * Use slow, but surefire "are we in kernel?" check. | |
1260 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
1261 | */ | |
1262 | ENTRY(paranoid_entry) | |
1263 | XCPT_FRAME 1 15*8 | |
1eeb207f DV |
1264 | cld |
1265 | SAVE_C_REGS 8 | |
1266 | SAVE_EXTRA_REGS 8 | |
1267 | movl $1,%ebx | |
1268 | movl $MSR_GS_BASE,%ecx | |
1269 | rdmsr | |
1270 | testl %edx,%edx | |
1271 | js 1f /* negative -> in kernel */ | |
1272 | SWAPGS | |
1273 | xorl %ebx,%ebx | |
1274 | 1: ret | |
1275 | CFI_ENDPROC | |
ebfc453e | 1276 | END(paranoid_entry) |
ddeb8f21 | 1277 | |
ebfc453e DV |
1278 | /* |
1279 | * "Paranoid" exit path from exception stack. This is invoked | |
1280 | * only on return from non-NMI IST interrupts that came | |
1281 | * from kernel space. | |
1282 | * | |
1283 | * We may be returning to very strange contexts (e.g. very early | |
1284 | * in syscall entry), so checking for preemption here would | |
1285 | * be complicated. Fortunately, we there's no good reason | |
1286 | * to try to handle preemption here. | |
1287 | */ | |
1288 | /* On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) */ | |
ddeb8f21 | 1289 | ENTRY(paranoid_exit) |
1f130a78 | 1290 | DEFAULT_FRAME |
ddeb8f21 | 1291 | DISABLE_INTERRUPTS(CLBR_NONE) |
5963e317 | 1292 | TRACE_IRQS_OFF_DEBUG |
ddeb8f21 | 1293 | testl %ebx,%ebx /* swapgs needed? */ |
0d550836 | 1294 | jnz paranoid_exit_no_swapgs |
f2db9382 | 1295 | TRACE_IRQS_IRETQ |
ddeb8f21 | 1296 | SWAPGS_UNSAFE_STACK |
0d550836 DV |
1297 | jmp paranoid_exit_restore |
1298 | paranoid_exit_no_swapgs: | |
f2db9382 | 1299 | TRACE_IRQS_IRETQ_DEBUG |
0d550836 | 1300 | paranoid_exit_restore: |
76f5df43 DV |
1301 | RESTORE_EXTRA_REGS |
1302 | RESTORE_C_REGS | |
1303 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
48e08d0f | 1304 | INTERRUPT_RETURN |
ddeb8f21 AH |
1305 | CFI_ENDPROC |
1306 | END(paranoid_exit) | |
1307 | ||
1308 | /* | |
ebfc453e DV |
1309 | * Save all registers in pt_regs, and switch gs if needed. |
1310 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
ddeb8f21 AH |
1311 | */ |
1312 | ENTRY(error_entry) | |
ebfc453e | 1313 | XCPT_FRAME 1 15*8 |
ddeb8f21 | 1314 | cld |
76f5df43 DV |
1315 | SAVE_C_REGS 8 |
1316 | SAVE_EXTRA_REGS 8 | |
ddeb8f21 AH |
1317 | xorl %ebx,%ebx |
1318 | testl $3,CS+8(%rsp) | |
1319 | je error_kernelspace | |
1320 | error_swapgs: | |
1321 | SWAPGS | |
1322 | error_sti: | |
1323 | TRACE_IRQS_OFF | |
1324 | ret | |
ddeb8f21 | 1325 | |
ebfc453e DV |
1326 | /* |
1327 | * There are two places in the kernel that can potentially fault with | |
1328 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1329 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1330 | * for these here too. | |
1331 | */ | |
ddeb8f21 | 1332 | error_kernelspace: |
3bab13b0 | 1333 | CFI_REL_OFFSET rcx, RCX+8 |
ddeb8f21 | 1334 | incl %ebx |
7209a75d | 1335 | leaq native_irq_return_iret(%rip),%rcx |
ddeb8f21 | 1336 | cmpq %rcx,RIP+8(%rsp) |
b645af2d | 1337 | je error_bad_iret |
ae24ffe5 BG |
1338 | movl %ecx,%eax /* zero extend */ |
1339 | cmpq %rax,RIP+8(%rsp) | |
1340 | je bstep_iret | |
ddeb8f21 | 1341 | cmpq $gs_change,RIP+8(%rsp) |
9f1e87ea | 1342 | je error_swapgs |
ddeb8f21 | 1343 | jmp error_sti |
ae24ffe5 BG |
1344 | |
1345 | bstep_iret: | |
1346 | /* Fix truncated RIP */ | |
1347 | movq %rcx,RIP+8(%rsp) | |
b645af2d AL |
1348 | /* fall through */ |
1349 | ||
1350 | error_bad_iret: | |
1351 | SWAPGS | |
1352 | mov %rsp,%rdi | |
1353 | call fixup_bad_iret | |
1354 | mov %rax,%rsp | |
1355 | decl %ebx /* Return to usergs */ | |
1356 | jmp error_sti | |
e6b04b6b | 1357 | CFI_ENDPROC |
ddeb8f21 AH |
1358 | END(error_entry) |
1359 | ||
1360 | ||
ebfc453e | 1361 | /* On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) */ |
ddeb8f21 AH |
1362 | ENTRY(error_exit) |
1363 | DEFAULT_FRAME | |
1364 | movl %ebx,%eax | |
76f5df43 | 1365 | RESTORE_EXTRA_REGS |
ddeb8f21 AH |
1366 | DISABLE_INTERRUPTS(CLBR_NONE) |
1367 | TRACE_IRQS_OFF | |
1368 | GET_THREAD_INFO(%rcx) | |
1369 | testl %eax,%eax | |
1370 | jne retint_kernel | |
1371 | LOCKDEP_SYS_EXIT_IRQ | |
1372 | movl TI_flags(%rcx),%edx | |
1373 | movl $_TIF_WORK_MASK,%edi | |
1374 | andl %edi,%edx | |
1375 | jnz retint_careful | |
1376 | jmp retint_swapgs | |
1377 | CFI_ENDPROC | |
1378 | END(error_exit) | |
1379 | ||
0784b364 | 1380 | /* Runs on exception stack */ |
ddeb8f21 AH |
1381 | ENTRY(nmi) |
1382 | INTR_FRAME | |
1383 | PARAVIRT_ADJUST_EXCEPTION_FRAME | |
3f3c8b8c SR |
1384 | /* |
1385 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1386 | * the iretq it performs will take us out of NMI context. | |
1387 | * This means that we can have nested NMIs where the next | |
1388 | * NMI is using the top of the stack of the previous NMI. We | |
1389 | * can't let it execute because the nested NMI will corrupt the | |
1390 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1391 | * anyway. | |
1392 | * | |
1393 | * To handle this case we do the following: | |
1394 | * Check the a special location on the stack that contains | |
1395 | * a variable that is set when NMIs are executing. | |
1396 | * The interrupted task's stack is also checked to see if it | |
1397 | * is an NMI stack. | |
1398 | * If the variable is not set and the stack is not the NMI | |
1399 | * stack then: | |
1400 | * o Set the special variable on the stack | |
1401 | * o Copy the interrupt frame into a "saved" location on the stack | |
1402 | * o Copy the interrupt frame into a "copy" location on the stack | |
1403 | * o Continue processing the NMI | |
1404 | * If the variable is set or the previous stack is the NMI stack: | |
1405 | * o Modify the "copy" location to jump to the repeate_nmi | |
1406 | * o return back to the first NMI | |
1407 | * | |
1408 | * Now on exit of the first NMI, we first clear the stack variable | |
1409 | * The NMI stack will tell any nested NMIs at that point that it is | |
1410 | * nested. Then we pop the stack normally with iret, and if there was | |
1411 | * a nested NMI that updated the copy interrupt stack frame, a | |
1412 | * jump will be made to the repeat_nmi code that will handle the second | |
1413 | * NMI. | |
1414 | */ | |
1415 | ||
146b2b09 | 1416 | /* Use %rdx as our temp variable throughout */ |
3f3c8b8c | 1417 | pushq_cfi %rdx |
62610913 | 1418 | CFI_REL_OFFSET rdx, 0 |
3f3c8b8c | 1419 | |
45d5a168 SR |
1420 | /* |
1421 | * If %cs was not the kernel segment, then the NMI triggered in user | |
1422 | * space, which means it is definitely not nested. | |
1423 | */ | |
a38449ef | 1424 | cmpl $__KERNEL_CS, 16(%rsp) |
45d5a168 SR |
1425 | jne first_nmi |
1426 | ||
3f3c8b8c SR |
1427 | /* |
1428 | * Check the special variable on the stack to see if NMIs are | |
1429 | * executing. | |
1430 | */ | |
a38449ef | 1431 | cmpl $1, -8(%rsp) |
3f3c8b8c SR |
1432 | je nested_nmi |
1433 | ||
1434 | /* | |
1435 | * Now test if the previous stack was an NMI stack. | |
1436 | * We need the double check. We check the NMI stack to satisfy the | |
1437 | * race when the first NMI clears the variable before returning. | |
1438 | * We check the variable because the first NMI could be in a | |
1439 | * breakpoint routine using a breakpoint stack. | |
1440 | */ | |
0784b364 DV |
1441 | lea 6*8(%rsp), %rdx |
1442 | /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ | |
1443 | cmpq %rdx, 4*8(%rsp) | |
1444 | /* If the stack pointer is above the NMI stack, this is a normal NMI */ | |
1445 | ja first_nmi | |
1446 | subq $EXCEPTION_STKSZ, %rdx | |
1447 | cmpq %rdx, 4*8(%rsp) | |
1448 | /* If it is below the NMI stack, it is a normal NMI */ | |
1449 | jb first_nmi | |
1450 | /* Ah, it is within the NMI stack, treat it as nested */ | |
1451 | jmp nested_nmi | |
1452 | ||
62610913 | 1453 | CFI_REMEMBER_STATE |
3f3c8b8c SR |
1454 | |
1455 | nested_nmi: | |
1456 | /* | |
1457 | * Do nothing if we interrupted the fixup in repeat_nmi. | |
1458 | * It's about to repeat the NMI handler, so we are fine | |
1459 | * with ignoring this one. | |
1460 | */ | |
1461 | movq $repeat_nmi, %rdx | |
1462 | cmpq 8(%rsp), %rdx | |
1463 | ja 1f | |
1464 | movq $end_repeat_nmi, %rdx | |
1465 | cmpq 8(%rsp), %rdx | |
1466 | ja nested_nmi_out | |
1467 | ||
1468 | 1: | |
1469 | /* Set up the interrupted NMIs stack to jump to repeat_nmi */ | |
28696f43 | 1470 | leaq -1*8(%rsp), %rdx |
3f3c8b8c | 1471 | movq %rdx, %rsp |
28696f43 SQ |
1472 | CFI_ADJUST_CFA_OFFSET 1*8 |
1473 | leaq -10*8(%rsp), %rdx | |
3f3c8b8c SR |
1474 | pushq_cfi $__KERNEL_DS |
1475 | pushq_cfi %rdx | |
1476 | pushfq_cfi | |
1477 | pushq_cfi $__KERNEL_CS | |
1478 | pushq_cfi $repeat_nmi | |
1479 | ||
1480 | /* Put stack back */ | |
28696f43 SQ |
1481 | addq $(6*8), %rsp |
1482 | CFI_ADJUST_CFA_OFFSET -6*8 | |
3f3c8b8c SR |
1483 | |
1484 | nested_nmi_out: | |
1485 | popq_cfi %rdx | |
62610913 | 1486 | CFI_RESTORE rdx |
3f3c8b8c SR |
1487 | |
1488 | /* No need to check faults here */ | |
1489 | INTERRUPT_RETURN | |
1490 | ||
62610913 | 1491 | CFI_RESTORE_STATE |
3f3c8b8c SR |
1492 | first_nmi: |
1493 | /* | |
1494 | * Because nested NMIs will use the pushed location that we | |
1495 | * stored in rdx, we must keep that space available. | |
1496 | * Here's what our stack frame will look like: | |
1497 | * +-------------------------+ | |
1498 | * | original SS | | |
1499 | * | original Return RSP | | |
1500 | * | original RFLAGS | | |
1501 | * | original CS | | |
1502 | * | original RIP | | |
1503 | * +-------------------------+ | |
1504 | * | temp storage for rdx | | |
1505 | * +-------------------------+ | |
1506 | * | NMI executing variable | | |
1507 | * +-------------------------+ | |
3f3c8b8c SR |
1508 | * | copied SS | |
1509 | * | copied Return RSP | | |
1510 | * | copied RFLAGS | | |
1511 | * | copied CS | | |
1512 | * | copied RIP | | |
1513 | * +-------------------------+ | |
28696f43 SQ |
1514 | * | Saved SS | |
1515 | * | Saved Return RSP | | |
1516 | * | Saved RFLAGS | | |
1517 | * | Saved CS | | |
1518 | * | Saved RIP | | |
1519 | * +-------------------------+ | |
3f3c8b8c SR |
1520 | * | pt_regs | |
1521 | * +-------------------------+ | |
1522 | * | |
79fb4ad6 SR |
1523 | * The saved stack frame is used to fix up the copied stack frame |
1524 | * that a nested NMI may change to make the interrupted NMI iret jump | |
1525 | * to the repeat_nmi. The original stack frame and the temp storage | |
3f3c8b8c SR |
1526 | * is also used by nested NMIs and can not be trusted on exit. |
1527 | */ | |
79fb4ad6 | 1528 | /* Do not pop rdx, nested NMIs will corrupt that part of the stack */ |
62610913 JB |
1529 | movq (%rsp), %rdx |
1530 | CFI_RESTORE rdx | |
1531 | ||
3f3c8b8c SR |
1532 | /* Set the NMI executing variable on the stack. */ |
1533 | pushq_cfi $1 | |
1534 | ||
28696f43 SQ |
1535 | /* |
1536 | * Leave room for the "copied" frame | |
1537 | */ | |
1538 | subq $(5*8), %rsp | |
444723dc | 1539 | CFI_ADJUST_CFA_OFFSET 5*8 |
28696f43 | 1540 | |
3f3c8b8c SR |
1541 | /* Copy the stack frame to the Saved frame */ |
1542 | .rept 5 | |
28696f43 | 1543 | pushq_cfi 11*8(%rsp) |
3f3c8b8c | 1544 | .endr |
911d2bb5 | 1545 | CFI_DEF_CFA_OFFSET 5*8 |
62610913 | 1546 | |
79fb4ad6 SR |
1547 | /* Everything up to here is safe from nested NMIs */ |
1548 | ||
62610913 JB |
1549 | /* |
1550 | * If there was a nested NMI, the first NMI's iret will return | |
1551 | * here. But NMIs are still enabled and we can take another | |
1552 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1553 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1554 | * it will just return, as we are about to repeat an NMI anyway. | |
1555 | * This makes it safe to copy to the stack frame that a nested | |
1556 | * NMI will update. | |
1557 | */ | |
1558 | repeat_nmi: | |
1559 | /* | |
1560 | * Update the stack variable to say we are still in NMI (the update | |
1561 | * is benign for the non-repeat case, where 1 was pushed just above | |
1562 | * to this very stack slot). | |
1563 | */ | |
28696f43 | 1564 | movq $1, 10*8(%rsp) |
3f3c8b8c SR |
1565 | |
1566 | /* Make another copy, this one may be modified by nested NMIs */ | |
28696f43 SQ |
1567 | addq $(10*8), %rsp |
1568 | CFI_ADJUST_CFA_OFFSET -10*8 | |
3f3c8b8c | 1569 | .rept 5 |
28696f43 | 1570 | pushq_cfi -6*8(%rsp) |
3f3c8b8c | 1571 | .endr |
28696f43 | 1572 | subq $(5*8), %rsp |
911d2bb5 | 1573 | CFI_DEF_CFA_OFFSET 5*8 |
62610913 | 1574 | end_repeat_nmi: |
3f3c8b8c SR |
1575 | |
1576 | /* | |
1577 | * Everything below this point can be preempted by a nested | |
79fb4ad6 SR |
1578 | * NMI if the first NMI took an exception and reset our iret stack |
1579 | * so that we repeat another NMI. | |
3f3c8b8c | 1580 | */ |
1fd466ef | 1581 | pushq_cfi $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 DV |
1582 | ALLOC_PT_GPREGS_ON_STACK |
1583 | ||
1fd466ef | 1584 | /* |
ebfc453e | 1585 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1586 | * as we should not be calling schedule in NMI context. |
1587 | * Even with normal interrupts enabled. An NMI should not be | |
1588 | * setting NEED_RESCHED or anything that normal interrupts and | |
1589 | * exceptions might do. | |
1590 | */ | |
ebfc453e | 1591 | call paranoid_entry |
ddeb8f21 | 1592 | DEFAULT_FRAME 0 |
7fbb98c5 SR |
1593 | |
1594 | /* | |
1595 | * Save off the CR2 register. If we take a page fault in the NMI then | |
1596 | * it could corrupt the CR2 value. If the NMI preempts a page fault | |
1597 | * handler before it was able to read the CR2 register, and then the | |
1598 | * NMI itself takes a page fault, the page fault that was preempted | |
1599 | * will read the information from the NMI page fault and not the | |
1600 | * origin fault. Save it off and restore it if it changes. | |
1601 | * Use the r12 callee-saved register. | |
1602 | */ | |
1603 | movq %cr2, %r12 | |
1604 | ||
ddeb8f21 AH |
1605 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
1606 | movq %rsp,%rdi | |
1607 | movq $-1,%rsi | |
1608 | call do_nmi | |
7fbb98c5 SR |
1609 | |
1610 | /* Did the NMI take a page fault? Restore cr2 if it did */ | |
1611 | movq %cr2, %rcx | |
1612 | cmpq %rcx, %r12 | |
1613 | je 1f | |
1614 | movq %r12, %cr2 | |
1615 | 1: | |
1616 | ||
ddeb8f21 AH |
1617 | testl %ebx,%ebx /* swapgs needed? */ |
1618 | jnz nmi_restore | |
ddeb8f21 AH |
1619 | nmi_swapgs: |
1620 | SWAPGS_UNSAFE_STACK | |
1621 | nmi_restore: | |
76f5df43 DV |
1622 | RESTORE_EXTRA_REGS |
1623 | RESTORE_C_REGS | |
444723dc | 1624 | /* Pop the extra iret frame at once */ |
76f5df43 | 1625 | REMOVE_PT_GPREGS_FROM_STACK 6*8 |
28696f43 | 1626 | |
3f3c8b8c | 1627 | /* Clear the NMI executing stack variable */ |
28696f43 | 1628 | movq $0, 5*8(%rsp) |
ddeb8f21 | 1629 | jmp irq_return |
9f1e87ea | 1630 | CFI_ENDPROC |
ddeb8f21 AH |
1631 | END(nmi) |
1632 | ||
1633 | ENTRY(ignore_sysret) | |
1634 | CFI_STARTPROC | |
1635 | mov $-ENOSYS,%eax | |
1636 | sysret | |
1637 | CFI_ENDPROC | |
1638 | END(ignore_sysret) | |
1639 |