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x86/fpu: Change __thread_clear_has_fpu() to 'struct fpu' parameter
[mirror_ubuntu-zesty-kernel.git] / arch / x86 / kernel / fpu / core.c
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1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
1361b83a 8#include <asm/fpu-internal.h>
1da177e4 9
085cc281
IM
10/*
11 * Track whether the kernel is using the FPU state
12 * currently.
13 *
14 * This flag is used:
15 *
16 * - by IRQ context code to potentially use the FPU
17 * if it's unused.
18 *
19 * - to debug kernel_fpu_begin()/end() correctness
20 */
14e153ef
ON
21static DEFINE_PER_CPU(bool, in_kernel_fpu);
22
416d49ac 23static void kernel_fpu_disable(void)
7575637a
ON
24{
25 WARN_ON(this_cpu_read(in_kernel_fpu));
26 this_cpu_write(in_kernel_fpu, true);
27}
28
416d49ac 29static void kernel_fpu_enable(void)
7575637a 30{
3103ae3a 31 WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu));
7575637a
ON
32 this_cpu_write(in_kernel_fpu, false);
33}
34
085cc281
IM
35static bool kernel_fpu_disabled(void)
36{
37 return this_cpu_read(in_kernel_fpu);
38}
39
8546c008
LT
40/*
41 * Were we in an interrupt that interrupted kernel mode?
42 *
304bceda 43 * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that
8546c008
LT
44 * pair does nothing at all: the thread must not have fpu (so
45 * that we don't try to save the FPU state), and TS must
46 * be set (so that the clts/stts pair does nothing that is
47 * visible in the interrupted kernel thread).
5187b28f 48 *
4b2e762e
ON
49 * Except for the eagerfpu case when we return true; in the likely case
50 * the thread has FPU but we are not going to set/clear TS.
8546c008 51 */
416d49ac 52static bool interrupted_kernel_fpu_idle(void)
8546c008 53{
085cc281 54 if (kernel_fpu_disabled())
14e153ef
ON
55 return false;
56
5d2bd700 57 if (use_eager_fpu())
4b2e762e 58 return true;
304bceda 59
276983f8 60 return !current->thread.fpu.has_fpu && (read_cr0() & X86_CR0_TS);
8546c008
LT
61}
62
63/*
64 * Were we in user mode (or vm86 mode) when we were
65 * interrupted?
66 *
67 * Doing kernel_fpu_begin/end() is ok if we are running
68 * in an interrupt context from user mode - we'll just
69 * save the FPU state as required.
70 */
416d49ac 71static bool interrupted_user_mode(void)
8546c008
LT
72{
73 struct pt_regs *regs = get_irq_regs();
f39b6f0e 74 return regs && user_mode(regs);
8546c008
LT
75}
76
77/*
78 * Can we use the FPU in kernel mode with the
79 * whole "kernel_fpu_begin/end()" sequence?
80 *
81 * It's always ok in process context (ie "not interrupt")
82 * but it is sometimes ok even from an irq.
83 */
84bool irq_fpu_usable(void)
85{
86 return !in_interrupt() ||
87 interrupted_user_mode() ||
88 interrupted_kernel_fpu_idle();
89}
90EXPORT_SYMBOL(irq_fpu_usable);
91
b1a74bf8 92void __kernel_fpu_begin(void)
8546c008
LT
93{
94 struct task_struct *me = current;
276983f8 95 struct fpu *fpu = &me->thread.fpu;
8546c008 96
3103ae3a 97 kernel_fpu_disable();
14e153ef 98
276983f8
IM
99 if (fpu->has_fpu) {
100 fpu_save_init(fpu);
7aeccb83 101 } else {
c6ae41e7 102 this_cpu_write(fpu_owner_task, NULL);
7aeccb83
ON
103 if (!use_eager_fpu())
104 clts();
8546c008
LT
105 }
106}
b1a74bf8 107EXPORT_SYMBOL(__kernel_fpu_begin);
8546c008 108
b1a74bf8 109void __kernel_fpu_end(void)
8546c008 110{
33a3ebdc 111 struct task_struct *me = current;
276983f8 112 struct fpu *fpu = &me->thread.fpu;
33a3ebdc 113
276983f8 114 if (fpu->has_fpu) {
33a3ebdc 115 if (WARN_ON(restore_fpu_checking(me)))
b85e67d1 116 fpu_reset_state(me);
33a3ebdc 117 } else if (!use_eager_fpu()) {
304bceda 118 stts();
731bd6a9 119 }
14e153ef 120
3103ae3a 121 kernel_fpu_enable();
8546c008 122}
b1a74bf8 123EXPORT_SYMBOL(__kernel_fpu_end);
8546c008 124
4af08f2f
IM
125/*
126 * Save the FPU state (initialize it if necessary):
87cdb98a
IM
127 *
128 * This only ever gets called for the current task.
4af08f2f 129 */
0a781551 130void fpu__save(struct task_struct *tsk)
8546c008 131{
276983f8
IM
132 struct fpu *fpu = &tsk->thread.fpu;
133
87cdb98a
IM
134 WARN_ON(tsk != current);
135
8546c008 136 preempt_disable();
276983f8 137 if (fpu->has_fpu) {
1a2a7f4e
ON
138 if (use_eager_fpu()) {
139 __save_fpu(tsk);
140 } else {
276983f8 141 fpu_save_init(fpu);
1a2a7f4e
ON
142 __thread_fpu_end(tsk);
143 }
a9241ea5 144 }
8546c008
LT
145 preempt_enable();
146}
4af08f2f 147EXPORT_SYMBOL_GPL(fpu__save);
8546c008 148
c0ee2cf6 149void fpstate_init(struct fpu *fpu)
1da177e4 150{
60e019eb 151 if (!cpu_has_fpu) {
86603283
AK
152 finit_soft_fpu(&fpu->state->soft);
153 return;
e8a496ac 154 }
e8a496ac 155
1d23c451
ON
156 memset(fpu->state, 0, xstate_size);
157
1da177e4 158 if (cpu_has_fxsr) {
5d2bd700 159 fx_finit(&fpu->state->fxsave);
1da177e4 160 } else {
86603283 161 struct i387_fsave_struct *fp = &fpu->state->fsave;
61c4628b
SS
162 fp->cwd = 0xffff037fu;
163 fp->swd = 0xffff0000u;
164 fp->twd = 0xffffffffu;
165 fp->fos = 0xffff0000u;
1da177e4 166 }
86603283 167}
c0ee2cf6 168EXPORT_SYMBOL_GPL(fpstate_init);
86603283 169
8ffb53ab
IM
170/*
171 * FPU state allocation:
172 */
f55f88e2 173static struct kmem_cache *task_xstate_cachep;
8ffb53ab
IM
174
175void fpstate_cache_init(void)
176{
177 task_xstate_cachep =
178 kmem_cache_create("task_xstate", xstate_size,
179 __alignof__(union thread_xstate),
180 SLAB_PANIC | SLAB_NOTRACK, NULL);
181 setup_xstate_comp();
182}
183
ed97b085 184int fpstate_alloc(struct fpu *fpu)
6fbe6712
IM
185{
186 if (fpu->state)
187 return 0;
ed97b085 188
6fbe6712
IM
189 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
190 if (!fpu->state)
191 return -ENOMEM;
ed97b085
IM
192
193 /* The CPU requires the FPU state to be aligned to 16 byte boundaries: */
6fbe6712 194 WARN_ON((unsigned long)fpu->state & 15);
ed97b085 195
6fbe6712
IM
196 return 0;
197}
ed97b085 198EXPORT_SYMBOL_GPL(fpstate_alloc);
6fbe6712 199
5a12bf63
IM
200void fpstate_free(struct fpu *fpu)
201{
202 if (fpu->state) {
203 kmem_cache_free(task_xstate_cachep, fpu->state);
204 fpu->state = NULL;
205 }
206}
207EXPORT_SYMBOL_GPL(fpstate_free);
208
bfd6fc05
IM
209/*
210 * Copy the current task's FPU state to a new task's FPU context.
211 *
212 * In the 'eager' case we just save to the destination context.
213 *
214 * In the 'lazy' case we save to the source context, mark the FPU lazy
215 * via stts() and copy the source context into the destination context.
216 */
e102f30f
IM
217static void fpu_copy(struct task_struct *dst, struct task_struct *src)
218{
bfd6fc05
IM
219 WARN_ON(src != current);
220
e102f30f
IM
221 if (use_eager_fpu()) {
222 memset(&dst->thread.fpu.state->xsave, 0, xstate_size);
223 __save_fpu(dst);
224 } else {
225 struct fpu *dfpu = &dst->thread.fpu;
226 struct fpu *sfpu = &src->thread.fpu;
227
228 fpu__save(src);
229 memcpy(dfpu->state, sfpu->state, xstate_size);
230 }
231}
232
a752b53d
IM
233int fpu__copy(struct task_struct *dst, struct task_struct *src)
234{
235 dst->thread.fpu.counter = 0;
236 dst->thread.fpu.has_fpu = 0;
237 dst->thread.fpu.state = NULL;
238
239 task_disable_lazy_fpu_restore(dst);
240
241 if (tsk_used_math(src)) {
242 int err = fpstate_alloc(&dst->thread.fpu);
243
244 if (err)
245 return err;
246 fpu_copy(dst, src);
247 }
248 return 0;
249}
250
97185c95
IM
251/*
252 * Allocate the backing store for the current task's FPU registers
253 * and initialize the registers themselves as well.
254 *
255 * Can fail.
256 */
257int fpstate_alloc_init(struct task_struct *curr)
258{
259 int ret;
260
261 if (WARN_ON_ONCE(curr != current))
262 return -EINVAL;
263 if (WARN_ON_ONCE(curr->flags & PF_USED_MATH))
264 return -EINVAL;
265
266 /*
267 * Memory allocation at the first usage of the FPU and other state.
268 */
ed97b085 269 ret = fpstate_alloc(&curr->thread.fpu);
97185c95
IM
270 if (ret)
271 return ret;
272
c0ee2cf6 273 fpstate_init(&curr->thread.fpu);
97185c95
IM
274
275 /* Safe to do for the current task: */
276 curr->flags |= PF_USED_MATH;
277
278 return 0;
279}
280EXPORT_SYMBOL_GPL(fpstate_alloc_init);
281
86603283
AK
282/*
283 * The _current_ task is using the FPU for the first time
284 * so initialize it and set the mxcsr to its default
285 * value at reset if we support XMM instructions and then
0d2eb44f 286 * remember the current task has used the FPU.
86603283 287 */
67e97fc2 288static int fpu__unlazy_stopped(struct task_struct *child)
86603283
AK
289{
290 int ret;
291
67e97fc2
IM
292 if (WARN_ON_ONCE(child == current))
293 return -EINVAL;
294
071ae621 295 if (child->flags & PF_USED_MATH) {
67e97fc2 296 task_disable_lazy_fpu_restore(child);
86603283
AK
297 return 0;
298 }
299
44210111 300 /*
86603283 301 * Memory allocation at the first usage of the FPU and other state.
44210111 302 */
ed97b085 303 ret = fpstate_alloc(&child->thread.fpu);
86603283
AK
304 if (ret)
305 return ret;
306
c0ee2cf6 307 fpstate_init(&child->thread.fpu);
86603283 308
071ae621
IM
309 /* Safe to do for stopped child tasks: */
310 child->flags |= PF_USED_MATH;
311
aa283f49 312 return 0;
1da177e4
LT
313}
314
93b90712 315/*
3a0aee48 316 * 'fpu__restore()' saves the current math information in the
93b90712
IM
317 * old math state array, and gets the new ones from the current task
318 *
319 * Careful.. There are problems with IBM-designed IRQ13 behaviour.
320 * Don't touch unless you *really* know how it works.
321 *
322 * Must be called with kernel preemption disabled (eg with local
323 * local interrupts as in the case of do_device_not_available).
324 */
3a0aee48 325void fpu__restore(void)
93b90712
IM
326{
327 struct task_struct *tsk = current;
328
329 if (!tsk_used_math(tsk)) {
330 local_irq_enable();
331 /*
332 * does a slab alloc which can sleep
333 */
334 if (fpstate_alloc_init(tsk)) {
335 /*
336 * ran out of memory!
337 */
338 do_group_exit(SIGKILL);
339 return;
340 }
341 local_irq_disable();
342 }
343
344 /* Avoid __kernel_fpu_begin() right after __thread_fpu_begin() */
345 kernel_fpu_disable();
346 __thread_fpu_begin(tsk);
347 if (unlikely(restore_fpu_checking(tsk))) {
348 fpu_reset_state(tsk);
349 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
350 } else {
351 tsk->thread.fpu.counter++;
352 }
353 kernel_fpu_enable();
354}
3a0aee48 355EXPORT_SYMBOL_GPL(fpu__restore);
93b90712 356
81683cc8
IM
357void fpu__flush_thread(struct task_struct *tsk)
358{
359 if (!use_eager_fpu()) {
360 /* FPU state will be reallocated lazily at the first use. */
361 drop_fpu(tsk);
362 fpstate_free(&tsk->thread.fpu);
363 } else {
364 if (!tsk_used_math(tsk)) {
365 /* kthread execs. TODO: cleanup this horror. */
366 if (WARN_ON(fpstate_alloc_init(tsk)))
367 force_sig(SIGKILL, tsk);
368 user_fpu_begin();
369 }
370 restore_init_xstate();
371 }
372}
373
5b3efd50
SS
374/*
375 * The xstateregs_active() routine is the same as the fpregs_active() routine,
376 * as the "regset->n" for the xstate regset will be updated based on the feature
377 * capabilites supported by the xsave.
378 */
44210111
RM
379int fpregs_active(struct task_struct *target, const struct user_regset *regset)
380{
381 return tsk_used_math(target) ? regset->n : 0;
382}
1da177e4 383
44210111 384int xfpregs_active(struct task_struct *target, const struct user_regset *regset)
1da177e4 385{
44210111
RM
386 return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0;
387}
1da177e4 388
44210111
RM
389int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
390 unsigned int pos, unsigned int count,
391 void *kbuf, void __user *ubuf)
392{
aa283f49
SS
393 int ret;
394
44210111
RM
395 if (!cpu_has_fxsr)
396 return -ENODEV;
397
67e97fc2 398 ret = fpu__unlazy_stopped(target);
aa283f49
SS
399 if (ret)
400 return ret;
44210111 401
29104e10
SS
402 sanitize_i387_state(target);
403
44210111 404 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
86603283 405 &target->thread.fpu.state->fxsave, 0, -1);
1da177e4 406}
44210111
RM
407
408int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
409 unsigned int pos, unsigned int count,
410 const void *kbuf, const void __user *ubuf)
411{
412 int ret;
413
414 if (!cpu_has_fxsr)
415 return -ENODEV;
416
67e97fc2 417 ret = fpu__unlazy_stopped(target);
aa283f49
SS
418 if (ret)
419 return ret;
420
29104e10
SS
421 sanitize_i387_state(target);
422
44210111 423 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
86603283 424 &target->thread.fpu.state->fxsave, 0, -1);
44210111
RM
425
426 /*
427 * mxcsr reserved bits must be masked to zero for security reasons.
428 */
86603283 429 target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
44210111 430
42deec6f
SS
431 /*
432 * update the header bits in the xsave header, indicating the
433 * presence of FP and SSE state.
434 */
435 if (cpu_has_xsave)
86603283 436 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE;
42deec6f 437
44210111
RM
438 return ret;
439}
440
5b3efd50
SS
441int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
442 unsigned int pos, unsigned int count,
443 void *kbuf, void __user *ubuf)
444{
18ecb3bf 445 struct xsave_struct *xsave;
5b3efd50
SS
446 int ret;
447
448 if (!cpu_has_xsave)
449 return -ENODEV;
450
67e97fc2 451 ret = fpu__unlazy_stopped(target);
5b3efd50
SS
452 if (ret)
453 return ret;
454
18ecb3bf
BP
455 xsave = &target->thread.fpu.state->xsave;
456
5b3efd50 457 /*
ff7fbc72
SS
458 * Copy the 48bytes defined by the software first into the xstate
459 * memory layout in the thread struct, so that we can copy the entire
460 * xstateregs to the user using one user_regset_copyout().
5b3efd50 461 */
e7f180dc
ON
462 memcpy(&xsave->i387.sw_reserved,
463 xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
5b3efd50 464 /*
ff7fbc72 465 * Copy the xstate memory layout.
5b3efd50 466 */
e7f180dc 467 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
5b3efd50
SS
468 return ret;
469}
470
471int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
472 unsigned int pos, unsigned int count,
473 const void *kbuf, const void __user *ubuf)
474{
18ecb3bf 475 struct xsave_struct *xsave;
5b3efd50 476 int ret;
5b3efd50
SS
477
478 if (!cpu_has_xsave)
479 return -ENODEV;
480
67e97fc2 481 ret = fpu__unlazy_stopped(target);
5b3efd50
SS
482 if (ret)
483 return ret;
484
18ecb3bf
BP
485 xsave = &target->thread.fpu.state->xsave;
486
e7f180dc 487 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
5b3efd50
SS
488 /*
489 * mxcsr reserved bits must be masked to zero for security reasons.
490 */
e7f180dc
ON
491 xsave->i387.mxcsr &= mxcsr_feature_mask;
492 xsave->xsave_hdr.xstate_bv &= pcntxt_mask;
5b3efd50
SS
493 /*
494 * These bits must be zero.
495 */
e7f180dc 496 memset(&xsave->xsave_hdr.reserved, 0, 48);
5b3efd50
SS
497 return ret;
498}
499
44210111 500#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
1da177e4 501
1da177e4
LT
502/*
503 * FPU tag word conversions.
504 */
505
3b095a04 506static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
1da177e4
LT
507{
508 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
3b095a04 509
1da177e4 510 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
3b095a04 511 tmp = ~twd;
44210111 512 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
3b095a04
CG
513 /* and move the valid bits to the lower byte. */
514 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
515 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
516 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
f668964e 517
3b095a04 518 return tmp;
1da177e4
LT
519}
520
497888cf 521#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
44210111
RM
522#define FP_EXP_TAG_VALID 0
523#define FP_EXP_TAG_ZERO 1
524#define FP_EXP_TAG_SPECIAL 2
525#define FP_EXP_TAG_EMPTY 3
526
527static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
528{
529 struct _fpxreg *st;
530 u32 tos = (fxsave->swd >> 11) & 7;
531 u32 twd = (unsigned long) fxsave->twd;
532 u32 tag;
533 u32 ret = 0xffff0000u;
534 int i;
1da177e4 535
44210111 536 for (i = 0; i < 8; i++, twd >>= 1) {
3b095a04
CG
537 if (twd & 0x1) {
538 st = FPREG_ADDR(fxsave, (i - tos) & 7);
1da177e4 539
3b095a04 540 switch (st->exponent & 0x7fff) {
1da177e4 541 case 0x7fff:
44210111 542 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
543 break;
544 case 0x0000:
3b095a04
CG
545 if (!st->significand[0] &&
546 !st->significand[1] &&
547 !st->significand[2] &&
44210111
RM
548 !st->significand[3])
549 tag = FP_EXP_TAG_ZERO;
550 else
551 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
552 break;
553 default:
44210111
RM
554 if (st->significand[3] & 0x8000)
555 tag = FP_EXP_TAG_VALID;
556 else
557 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
558 break;
559 }
560 } else {
44210111 561 tag = FP_EXP_TAG_EMPTY;
1da177e4 562 }
44210111 563 ret |= tag << (2 * i);
1da177e4
LT
564 }
565 return ret;
566}
567
568/*
44210111 569 * FXSR floating point environment conversions.
1da177e4
LT
570 */
571
72a671ce 572void
f668964e 573convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
1da177e4 574{
86603283 575 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
44210111
RM
576 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
577 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
578 int i;
1da177e4 579
44210111
RM
580 env->cwd = fxsave->cwd | 0xffff0000u;
581 env->swd = fxsave->swd | 0xffff0000u;
582 env->twd = twd_fxsr_to_i387(fxsave);
583
584#ifdef CONFIG_X86_64
585 env->fip = fxsave->rip;
586 env->foo = fxsave->rdp;
10c11f30
BG
587 /*
588 * should be actually ds/cs at fpu exception time, but
589 * that information is not available in 64bit mode.
590 */
591 env->fcs = task_pt_regs(tsk)->cs;
44210111 592 if (tsk == current) {
10c11f30 593 savesegment(ds, env->fos);
1da177e4 594 } else {
10c11f30 595 env->fos = tsk->thread.ds;
1da177e4 596 }
10c11f30 597 env->fos |= 0xffff0000;
44210111
RM
598#else
599 env->fip = fxsave->fip;
609b5297 600 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
44210111
RM
601 env->foo = fxsave->foo;
602 env->fos = fxsave->fos;
603#endif
1da177e4 604
44210111
RM
605 for (i = 0; i < 8; ++i)
606 memcpy(&to[i], &from[i], sizeof(to[0]));
1da177e4
LT
607}
608
72a671ce
SS
609void convert_to_fxsr(struct task_struct *tsk,
610 const struct user_i387_ia32_struct *env)
1da177e4 611
1da177e4 612{
86603283 613 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
44210111
RM
614 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
615 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
616 int i;
1da177e4 617
44210111
RM
618 fxsave->cwd = env->cwd;
619 fxsave->swd = env->swd;
620 fxsave->twd = twd_i387_to_fxsr(env->twd);
621 fxsave->fop = (u16) ((u32) env->fcs >> 16);
622#ifdef CONFIG_X86_64
623 fxsave->rip = env->fip;
624 fxsave->rdp = env->foo;
625 /* cs and ds ignored */
626#else
627 fxsave->fip = env->fip;
628 fxsave->fcs = (env->fcs & 0xffff);
629 fxsave->foo = env->foo;
630 fxsave->fos = env->fos;
631#endif
1da177e4 632
44210111
RM
633 for (i = 0; i < 8; ++i)
634 memcpy(&to[i], &from[i], sizeof(from[0]));
1da177e4
LT
635}
636
44210111
RM
637int fpregs_get(struct task_struct *target, const struct user_regset *regset,
638 unsigned int pos, unsigned int count,
639 void *kbuf, void __user *ubuf)
1da177e4 640{
44210111 641 struct user_i387_ia32_struct env;
aa283f49 642 int ret;
1da177e4 643
67e97fc2 644 ret = fpu__unlazy_stopped(target);
aa283f49
SS
645 if (ret)
646 return ret;
1da177e4 647
60e019eb 648 if (!static_cpu_has(X86_FEATURE_FPU))
e8a496ac
SS
649 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
650
60e019eb 651 if (!cpu_has_fxsr)
44210111 652 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
86603283 653 &target->thread.fpu.state->fsave, 0,
61c4628b 654 -1);
1da177e4 655
29104e10
SS
656 sanitize_i387_state(target);
657
44210111
RM
658 if (kbuf && pos == 0 && count == sizeof(env)) {
659 convert_from_fxsr(kbuf, target);
660 return 0;
1da177e4 661 }
44210111
RM
662
663 convert_from_fxsr(&env, target);
f668964e 664
44210111 665 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
1da177e4
LT
666}
667
44210111
RM
668int fpregs_set(struct task_struct *target, const struct user_regset *regset,
669 unsigned int pos, unsigned int count,
670 const void *kbuf, const void __user *ubuf)
1da177e4 671{
44210111
RM
672 struct user_i387_ia32_struct env;
673 int ret;
1da177e4 674
67e97fc2 675 ret = fpu__unlazy_stopped(target);
aa283f49
SS
676 if (ret)
677 return ret;
678
29104e10
SS
679 sanitize_i387_state(target);
680
60e019eb 681 if (!static_cpu_has(X86_FEATURE_FPU))
e8a496ac
SS
682 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
683
60e019eb 684 if (!cpu_has_fxsr)
44210111 685 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
60e019eb
PA
686 &target->thread.fpu.state->fsave, 0,
687 -1);
44210111
RM
688
689 if (pos > 0 || count < sizeof(env))
690 convert_from_fxsr(&env, target);
691
692 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
693 if (!ret)
694 convert_to_fxsr(target, &env);
695
42deec6f
SS
696 /*
697 * update the header bit in the xsave header, indicating the
698 * presence of FP.
699 */
700 if (cpu_has_xsave)
86603283 701 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;
44210111 702 return ret;
1da177e4
LT
703}
704
1da177e4
LT
705/*
706 * FPU state for core dumps.
60b3b9af
RM
707 * This is only used for a.out dumps now.
708 * It is declared generically using elf_fpregset_t (which is
709 * struct user_i387_struct) but is in fact only used for 32-bit
710 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
1da177e4 711 */
3b095a04 712int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu)
1da177e4 713{
1da177e4 714 struct task_struct *tsk = current;
f668964e 715 int fpvalid;
1da177e4
LT
716
717 fpvalid = !!used_math();
60b3b9af
RM
718 if (fpvalid)
719 fpvalid = !fpregs_get(tsk, NULL,
720 0, sizeof(struct user_i387_ia32_struct),
721 fpu, NULL);
1da177e4
LT
722
723 return fpvalid;
724}
129f6946 725EXPORT_SYMBOL(dump_fpu);
1da177e4 726
60b3b9af 727#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */