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1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
1361b83a 8#include <asm/fpu-internal.h>
1da177e4 9
085cc281
IM
10/*
11 * Track whether the kernel is using the FPU state
12 * currently.
13 *
14 * This flag is used:
15 *
16 * - by IRQ context code to potentially use the FPU
17 * if it's unused.
18 *
19 * - to debug kernel_fpu_begin()/end() correctness
20 */
14e153ef
ON
21static DEFINE_PER_CPU(bool, in_kernel_fpu);
22
b0c050c5 23/*
36b544dc 24 * Track which context is using the FPU on the CPU:
b0c050c5 25 */
36b544dc 26DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
b0c050c5 27
416d49ac 28static void kernel_fpu_disable(void)
7575637a
ON
29{
30 WARN_ON(this_cpu_read(in_kernel_fpu));
31 this_cpu_write(in_kernel_fpu, true);
32}
33
416d49ac 34static void kernel_fpu_enable(void)
7575637a 35{
3103ae3a 36 WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu));
7575637a
ON
37 this_cpu_write(in_kernel_fpu, false);
38}
39
085cc281
IM
40static bool kernel_fpu_disabled(void)
41{
42 return this_cpu_read(in_kernel_fpu);
43}
44
8546c008
LT
45/*
46 * Were we in an interrupt that interrupted kernel mode?
47 *
304bceda 48 * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that
8546c008
LT
49 * pair does nothing at all: the thread must not have fpu (so
50 * that we don't try to save the FPU state), and TS must
51 * be set (so that the clts/stts pair does nothing that is
52 * visible in the interrupted kernel thread).
5187b28f 53 *
4b2e762e
ON
54 * Except for the eagerfpu case when we return true; in the likely case
55 * the thread has FPU but we are not going to set/clear TS.
8546c008 56 */
416d49ac 57static bool interrupted_kernel_fpu_idle(void)
8546c008 58{
085cc281 59 if (kernel_fpu_disabled())
14e153ef
ON
60 return false;
61
5d2bd700 62 if (use_eager_fpu())
4b2e762e 63 return true;
304bceda 64
276983f8 65 return !current->thread.fpu.has_fpu && (read_cr0() & X86_CR0_TS);
8546c008
LT
66}
67
68/*
69 * Were we in user mode (or vm86 mode) when we were
70 * interrupted?
71 *
72 * Doing kernel_fpu_begin/end() is ok if we are running
73 * in an interrupt context from user mode - we'll just
74 * save the FPU state as required.
75 */
416d49ac 76static bool interrupted_user_mode(void)
8546c008
LT
77{
78 struct pt_regs *regs = get_irq_regs();
f39b6f0e 79 return regs && user_mode(regs);
8546c008
LT
80}
81
82/*
83 * Can we use the FPU in kernel mode with the
84 * whole "kernel_fpu_begin/end()" sequence?
85 *
86 * It's always ok in process context (ie "not interrupt")
87 * but it is sometimes ok even from an irq.
88 */
89bool irq_fpu_usable(void)
90{
91 return !in_interrupt() ||
92 interrupted_user_mode() ||
93 interrupted_kernel_fpu_idle();
94}
95EXPORT_SYMBOL(irq_fpu_usable);
96
b1a74bf8 97void __kernel_fpu_begin(void)
8546c008 98{
36b544dc 99 struct fpu *fpu = &current->thread.fpu;
8546c008 100
3103ae3a 101 kernel_fpu_disable();
14e153ef 102
276983f8
IM
103 if (fpu->has_fpu) {
104 fpu_save_init(fpu);
7aeccb83 105 } else {
36b544dc 106 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
7aeccb83
ON
107 if (!use_eager_fpu())
108 clts();
8546c008
LT
109 }
110}
b1a74bf8 111EXPORT_SYMBOL(__kernel_fpu_begin);
8546c008 112
b1a74bf8 113void __kernel_fpu_end(void)
8546c008 114{
af2d94fd 115 struct fpu *fpu = &current->thread.fpu;
33a3ebdc 116
276983f8 117 if (fpu->has_fpu) {
11f2d50b 118 if (WARN_ON(restore_fpu_checking(fpu)))
af2d94fd 119 fpu_reset_state(fpu);
33a3ebdc 120 } else if (!use_eager_fpu()) {
304bceda 121 stts();
731bd6a9 122 }
14e153ef 123
3103ae3a 124 kernel_fpu_enable();
8546c008 125}
b1a74bf8 126EXPORT_SYMBOL(__kernel_fpu_end);
8546c008 127
a4d8fc2e 128static void __save_fpu(struct fpu *fpu)
2d75bcf3
IM
129{
130 if (use_xsave()) {
131 if (unlikely(system_state == SYSTEM_BOOTING))
a4d8fc2e 132 xsave_state_booting(&fpu->state->xsave);
2d75bcf3 133 else
a4d8fc2e 134 xsave_state(&fpu->state->xsave);
2d75bcf3 135 } else {
a4d8fc2e 136 fpu_fxsave(fpu);
2d75bcf3
IM
137 }
138}
139
4af08f2f
IM
140/*
141 * Save the FPU state (initialize it if necessary):
87cdb98a
IM
142 *
143 * This only ever gets called for the current task.
4af08f2f 144 */
0c070595 145void fpu__save(struct fpu *fpu)
8546c008 146{
0c070595 147 WARN_ON(fpu != &current->thread.fpu);
87cdb98a 148
8546c008 149 preempt_disable();
276983f8 150 if (fpu->has_fpu) {
1a2a7f4e 151 if (use_eager_fpu()) {
a4d8fc2e 152 __save_fpu(fpu);
1a2a7f4e 153 } else {
276983f8 154 fpu_save_init(fpu);
35191e3f 155 __thread_fpu_end(fpu);
1a2a7f4e 156 }
a9241ea5 157 }
8546c008
LT
158 preempt_enable();
159}
4af08f2f 160EXPORT_SYMBOL_GPL(fpu__save);
8546c008 161
c0ee2cf6 162void fpstate_init(struct fpu *fpu)
1da177e4 163{
60e019eb 164 if (!cpu_has_fpu) {
86603283
AK
165 finit_soft_fpu(&fpu->state->soft);
166 return;
e8a496ac 167 }
e8a496ac 168
1d23c451
ON
169 memset(fpu->state, 0, xstate_size);
170
1da177e4 171 if (cpu_has_fxsr) {
5d2bd700 172 fx_finit(&fpu->state->fxsave);
1da177e4 173 } else {
86603283 174 struct i387_fsave_struct *fp = &fpu->state->fsave;
61c4628b
SS
175 fp->cwd = 0xffff037fu;
176 fp->swd = 0xffff0000u;
177 fp->twd = 0xffffffffu;
178 fp->fos = 0xffff0000u;
1da177e4 179 }
86603283 180}
c0ee2cf6 181EXPORT_SYMBOL_GPL(fpstate_init);
86603283 182
8ffb53ab
IM
183/*
184 * FPU state allocation:
185 */
f55f88e2 186static struct kmem_cache *task_xstate_cachep;
8ffb53ab
IM
187
188void fpstate_cache_init(void)
189{
190 task_xstate_cachep =
191 kmem_cache_create("task_xstate", xstate_size,
192 __alignof__(union thread_xstate),
193 SLAB_PANIC | SLAB_NOTRACK, NULL);
194 setup_xstate_comp();
195}
196
ed97b085 197int fpstate_alloc(struct fpu *fpu)
6fbe6712
IM
198{
199 if (fpu->state)
200 return 0;
ed97b085 201
6fbe6712
IM
202 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
203 if (!fpu->state)
204 return -ENOMEM;
ed97b085
IM
205
206 /* The CPU requires the FPU state to be aligned to 16 byte boundaries: */
6fbe6712 207 WARN_ON((unsigned long)fpu->state & 15);
ed97b085 208
6fbe6712
IM
209 return 0;
210}
ed97b085 211EXPORT_SYMBOL_GPL(fpstate_alloc);
6fbe6712 212
5a12bf63
IM
213void fpstate_free(struct fpu *fpu)
214{
215 if (fpu->state) {
216 kmem_cache_free(task_xstate_cachep, fpu->state);
217 fpu->state = NULL;
218 }
219}
220EXPORT_SYMBOL_GPL(fpstate_free);
221
bfd6fc05
IM
222/*
223 * Copy the current task's FPU state to a new task's FPU context.
224 *
225 * In the 'eager' case we just save to the destination context.
226 *
227 * In the 'lazy' case we save to the source context, mark the FPU lazy
228 * via stts() and copy the source context into the destination context.
229 */
f9bc977f 230static void fpu_copy(struct fpu *dst_fpu, struct fpu *src_fpu)
e102f30f 231{
f9bc977f 232 WARN_ON(src_fpu != &current->thread.fpu);
bfd6fc05 233
e102f30f 234 if (use_eager_fpu()) {
f9bc977f 235 memset(&dst_fpu->state->xsave, 0, xstate_size);
a4d8fc2e 236 __save_fpu(dst_fpu);
e102f30f 237 } else {
0c070595 238 fpu__save(src_fpu);
a4d8fc2e 239 memcpy(dst_fpu->state, src_fpu->state, xstate_size);
e102f30f
IM
240 }
241}
242
c69e098b 243int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu)
a752b53d 244{
c69e098b
IM
245 dst_fpu->counter = 0;
246 dst_fpu->has_fpu = 0;
247 dst_fpu->state = NULL;
248 dst_fpu->last_cpu = -1;
a752b53d 249
c5bedc68
IM
250 if (src_fpu->fpstate_active) {
251 int err = fpstate_alloc(dst_fpu);
a752b53d
IM
252
253 if (err)
254 return err;
f9bc977f 255 fpu_copy(dst_fpu, src_fpu);
a752b53d
IM
256 }
257 return 0;
258}
259
97185c95
IM
260/*
261 * Allocate the backing store for the current task's FPU registers
262 * and initialize the registers themselves as well.
263 *
264 * Can fail.
265 */
266int fpstate_alloc_init(struct task_struct *curr)
267{
c5bedc68 268 struct fpu *fpu = &curr->thread.fpu;
97185c95
IM
269 int ret;
270
271 if (WARN_ON_ONCE(curr != current))
272 return -EINVAL;
c5bedc68 273 if (WARN_ON_ONCE(fpu->fpstate_active))
97185c95
IM
274 return -EINVAL;
275
276 /*
277 * Memory allocation at the first usage of the FPU and other state.
278 */
ed97b085 279 ret = fpstate_alloc(&curr->thread.fpu);
97185c95
IM
280 if (ret)
281 return ret;
282
c0ee2cf6 283 fpstate_init(&curr->thread.fpu);
97185c95
IM
284
285 /* Safe to do for the current task: */
c5bedc68 286 fpu->fpstate_active = 1;
97185c95
IM
287
288 return 0;
289}
290EXPORT_SYMBOL_GPL(fpstate_alloc_init);
291
86603283 292/*
af7f8721
IM
293 * This function is called before we modify a stopped child's
294 * FPU state context.
295 *
296 * If the child has not used the FPU before then initialize its
297 * FPU context.
298 *
299 * If the child has used the FPU before then unlazy it.
300 *
301 * [ After this function call, after the context is modified and
302 * the child task is woken up, the child task will restore
303 * the modified FPU state from the modified context. If we
304 * didn't clear its lazy status here then the lazy in-registers
305 * state pending on its former CPU could be restored, losing
306 * the modifications. ]
307 *
308 * This function is also called before we read a stopped child's
309 * FPU state - to make sure it's modified.
310 *
311 * TODO: A future optimization would be to skip the unlazying in
312 * the read-only case, it's not strictly necessary for
313 * read-only access to the context.
86603283 314 */
67e97fc2 315static int fpu__unlazy_stopped(struct task_struct *child)
86603283 316{
c5bedc68 317 struct fpu *child_fpu = &child->thread.fpu;
86603283
AK
318 int ret;
319
67e97fc2
IM
320 if (WARN_ON_ONCE(child == current))
321 return -EINVAL;
322
c5bedc68 323 if (child_fpu->fpstate_active) {
eb6a3251 324 child->thread.fpu.last_cpu = -1;
86603283
AK
325 return 0;
326 }
327
44210111 328 /*
86603283 329 * Memory allocation at the first usage of the FPU and other state.
44210111 330 */
ed97b085 331 ret = fpstate_alloc(&child->thread.fpu);
86603283
AK
332 if (ret)
333 return ret;
334
c0ee2cf6 335 fpstate_init(&child->thread.fpu);
86603283 336
071ae621 337 /* Safe to do for stopped child tasks: */
c5bedc68 338 child_fpu->fpstate_active = 1;
071ae621 339
aa283f49 340 return 0;
1da177e4
LT
341}
342
93b90712 343/*
3a0aee48 344 * 'fpu__restore()' saves the current math information in the
93b90712
IM
345 * old math state array, and gets the new ones from the current task
346 *
347 * Careful.. There are problems with IBM-designed IRQ13 behaviour.
348 * Don't touch unless you *really* know how it works.
349 *
350 * Must be called with kernel preemption disabled (eg with local
351 * local interrupts as in the case of do_device_not_available).
352 */
3a0aee48 353void fpu__restore(void)
93b90712
IM
354{
355 struct task_struct *tsk = current;
4540d3fa 356 struct fpu *fpu = &tsk->thread.fpu;
93b90712 357
c5bedc68 358 if (!fpu->fpstate_active) {
93b90712
IM
359 local_irq_enable();
360 /*
361 * does a slab alloc which can sleep
362 */
363 if (fpstate_alloc_init(tsk)) {
364 /*
365 * ran out of memory!
366 */
367 do_group_exit(SIGKILL);
368 return;
369 }
370 local_irq_disable();
371 }
372
373 /* Avoid __kernel_fpu_begin() right after __thread_fpu_begin() */
374 kernel_fpu_disable();
4540d3fa 375 __thread_fpu_begin(fpu);
11f2d50b 376 if (unlikely(restore_fpu_checking(fpu))) {
af2d94fd 377 fpu_reset_state(fpu);
93b90712
IM
378 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
379 } else {
380 tsk->thread.fpu.counter++;
381 }
382 kernel_fpu_enable();
383}
3a0aee48 384EXPORT_SYMBOL_GPL(fpu__restore);
93b90712 385
81683cc8
IM
386void fpu__flush_thread(struct task_struct *tsk)
387{
c5bedc68
IM
388 struct fpu *fpu = &tsk->thread.fpu;
389
4c138410
IM
390 WARN_ON(tsk != current);
391
81683cc8
IM
392 if (!use_eager_fpu()) {
393 /* FPU state will be reallocated lazily at the first use. */
ca6787ba 394 drop_fpu(fpu);
81683cc8
IM
395 fpstate_free(&tsk->thread.fpu);
396 } else {
c5bedc68 397 if (!fpu->fpstate_active) {
81683cc8
IM
398 /* kthread execs. TODO: cleanup this horror. */
399 if (WARN_ON(fpstate_alloc_init(tsk)))
400 force_sig(SIGKILL, tsk);
401 user_fpu_begin();
402 }
403 restore_init_xstate();
404 }
405}
406
5b3efd50
SS
407/*
408 * The xstateregs_active() routine is the same as the fpregs_active() routine,
409 * as the "regset->n" for the xstate regset will be updated based on the feature
410 * capabilites supported by the xsave.
411 */
44210111
RM
412int fpregs_active(struct task_struct *target, const struct user_regset *regset)
413{
c5bedc68
IM
414 struct fpu *target_fpu = &target->thread.fpu;
415
416 return target_fpu->fpstate_active ? regset->n : 0;
44210111 417}
1da177e4 418
44210111 419int xfpregs_active(struct task_struct *target, const struct user_regset *regset)
1da177e4 420{
c5bedc68
IM
421 struct fpu *target_fpu = &target->thread.fpu;
422
423 return (cpu_has_fxsr && target_fpu->fpstate_active) ? regset->n : 0;
44210111 424}
1da177e4 425
44210111
RM
426int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
427 unsigned int pos, unsigned int count,
428 void *kbuf, void __user *ubuf)
429{
aa283f49
SS
430 int ret;
431
44210111
RM
432 if (!cpu_has_fxsr)
433 return -ENODEV;
434
67e97fc2 435 ret = fpu__unlazy_stopped(target);
aa283f49
SS
436 if (ret)
437 return ret;
44210111 438
29104e10
SS
439 sanitize_i387_state(target);
440
44210111 441 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
86603283 442 &target->thread.fpu.state->fxsave, 0, -1);
1da177e4 443}
44210111
RM
444
445int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
446 unsigned int pos, unsigned int count,
447 const void *kbuf, const void __user *ubuf)
448{
449 int ret;
450
451 if (!cpu_has_fxsr)
452 return -ENODEV;
453
67e97fc2 454 ret = fpu__unlazy_stopped(target);
aa283f49
SS
455 if (ret)
456 return ret;
457
29104e10
SS
458 sanitize_i387_state(target);
459
44210111 460 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
86603283 461 &target->thread.fpu.state->fxsave, 0, -1);
44210111
RM
462
463 /*
464 * mxcsr reserved bits must be masked to zero for security reasons.
465 */
86603283 466 target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
44210111 467
42deec6f
SS
468 /*
469 * update the header bits in the xsave header, indicating the
470 * presence of FP and SSE state.
471 */
472 if (cpu_has_xsave)
86603283 473 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE;
42deec6f 474
44210111
RM
475 return ret;
476}
477
5b3efd50
SS
478int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
479 unsigned int pos, unsigned int count,
480 void *kbuf, void __user *ubuf)
481{
18ecb3bf 482 struct xsave_struct *xsave;
5b3efd50
SS
483 int ret;
484
485 if (!cpu_has_xsave)
486 return -ENODEV;
487
67e97fc2 488 ret = fpu__unlazy_stopped(target);
5b3efd50
SS
489 if (ret)
490 return ret;
491
18ecb3bf
BP
492 xsave = &target->thread.fpu.state->xsave;
493
5b3efd50 494 /*
ff7fbc72
SS
495 * Copy the 48bytes defined by the software first into the xstate
496 * memory layout in the thread struct, so that we can copy the entire
497 * xstateregs to the user using one user_regset_copyout().
5b3efd50 498 */
e7f180dc
ON
499 memcpy(&xsave->i387.sw_reserved,
500 xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
5b3efd50 501 /*
ff7fbc72 502 * Copy the xstate memory layout.
5b3efd50 503 */
e7f180dc 504 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
5b3efd50
SS
505 return ret;
506}
507
508int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
509 unsigned int pos, unsigned int count,
510 const void *kbuf, const void __user *ubuf)
511{
18ecb3bf 512 struct xsave_struct *xsave;
5b3efd50 513 int ret;
5b3efd50
SS
514
515 if (!cpu_has_xsave)
516 return -ENODEV;
517
67e97fc2 518 ret = fpu__unlazy_stopped(target);
5b3efd50
SS
519 if (ret)
520 return ret;
521
18ecb3bf
BP
522 xsave = &target->thread.fpu.state->xsave;
523
e7f180dc 524 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
5b3efd50
SS
525 /*
526 * mxcsr reserved bits must be masked to zero for security reasons.
527 */
e7f180dc
ON
528 xsave->i387.mxcsr &= mxcsr_feature_mask;
529 xsave->xsave_hdr.xstate_bv &= pcntxt_mask;
5b3efd50
SS
530 /*
531 * These bits must be zero.
532 */
e7f180dc 533 memset(&xsave->xsave_hdr.reserved, 0, 48);
5b3efd50
SS
534 return ret;
535}
536
44210111 537#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
1da177e4 538
1da177e4
LT
539/*
540 * FPU tag word conversions.
541 */
542
3b095a04 543static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
1da177e4
LT
544{
545 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
3b095a04 546
1da177e4 547 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
3b095a04 548 tmp = ~twd;
44210111 549 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
3b095a04
CG
550 /* and move the valid bits to the lower byte. */
551 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
552 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
553 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
f668964e 554
3b095a04 555 return tmp;
1da177e4
LT
556}
557
497888cf 558#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
44210111
RM
559#define FP_EXP_TAG_VALID 0
560#define FP_EXP_TAG_ZERO 1
561#define FP_EXP_TAG_SPECIAL 2
562#define FP_EXP_TAG_EMPTY 3
563
564static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
565{
566 struct _fpxreg *st;
567 u32 tos = (fxsave->swd >> 11) & 7;
568 u32 twd = (unsigned long) fxsave->twd;
569 u32 tag;
570 u32 ret = 0xffff0000u;
571 int i;
1da177e4 572
44210111 573 for (i = 0; i < 8; i++, twd >>= 1) {
3b095a04
CG
574 if (twd & 0x1) {
575 st = FPREG_ADDR(fxsave, (i - tos) & 7);
1da177e4 576
3b095a04 577 switch (st->exponent & 0x7fff) {
1da177e4 578 case 0x7fff:
44210111 579 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
580 break;
581 case 0x0000:
3b095a04
CG
582 if (!st->significand[0] &&
583 !st->significand[1] &&
584 !st->significand[2] &&
44210111
RM
585 !st->significand[3])
586 tag = FP_EXP_TAG_ZERO;
587 else
588 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
589 break;
590 default:
44210111
RM
591 if (st->significand[3] & 0x8000)
592 tag = FP_EXP_TAG_VALID;
593 else
594 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
595 break;
596 }
597 } else {
44210111 598 tag = FP_EXP_TAG_EMPTY;
1da177e4 599 }
44210111 600 ret |= tag << (2 * i);
1da177e4
LT
601 }
602 return ret;
603}
604
605/*
44210111 606 * FXSR floating point environment conversions.
1da177e4
LT
607 */
608
72a671ce 609void
f668964e 610convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
1da177e4 611{
86603283 612 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
44210111
RM
613 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
614 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
615 int i;
1da177e4 616
44210111
RM
617 env->cwd = fxsave->cwd | 0xffff0000u;
618 env->swd = fxsave->swd | 0xffff0000u;
619 env->twd = twd_fxsr_to_i387(fxsave);
620
621#ifdef CONFIG_X86_64
622 env->fip = fxsave->rip;
623 env->foo = fxsave->rdp;
10c11f30
BG
624 /*
625 * should be actually ds/cs at fpu exception time, but
626 * that information is not available in 64bit mode.
627 */
628 env->fcs = task_pt_regs(tsk)->cs;
44210111 629 if (tsk == current) {
10c11f30 630 savesegment(ds, env->fos);
1da177e4 631 } else {
10c11f30 632 env->fos = tsk->thread.ds;
1da177e4 633 }
10c11f30 634 env->fos |= 0xffff0000;
44210111
RM
635#else
636 env->fip = fxsave->fip;
609b5297 637 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
44210111
RM
638 env->foo = fxsave->foo;
639 env->fos = fxsave->fos;
640#endif
1da177e4 641
44210111
RM
642 for (i = 0; i < 8; ++i)
643 memcpy(&to[i], &from[i], sizeof(to[0]));
1da177e4
LT
644}
645
72a671ce
SS
646void convert_to_fxsr(struct task_struct *tsk,
647 const struct user_i387_ia32_struct *env)
1da177e4 648
1da177e4 649{
86603283 650 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
44210111
RM
651 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
652 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
653 int i;
1da177e4 654
44210111
RM
655 fxsave->cwd = env->cwd;
656 fxsave->swd = env->swd;
657 fxsave->twd = twd_i387_to_fxsr(env->twd);
658 fxsave->fop = (u16) ((u32) env->fcs >> 16);
659#ifdef CONFIG_X86_64
660 fxsave->rip = env->fip;
661 fxsave->rdp = env->foo;
662 /* cs and ds ignored */
663#else
664 fxsave->fip = env->fip;
665 fxsave->fcs = (env->fcs & 0xffff);
666 fxsave->foo = env->foo;
667 fxsave->fos = env->fos;
668#endif
1da177e4 669
44210111
RM
670 for (i = 0; i < 8; ++i)
671 memcpy(&to[i], &from[i], sizeof(from[0]));
1da177e4
LT
672}
673
44210111
RM
674int fpregs_get(struct task_struct *target, const struct user_regset *regset,
675 unsigned int pos, unsigned int count,
676 void *kbuf, void __user *ubuf)
1da177e4 677{
44210111 678 struct user_i387_ia32_struct env;
aa283f49 679 int ret;
1da177e4 680
67e97fc2 681 ret = fpu__unlazy_stopped(target);
aa283f49
SS
682 if (ret)
683 return ret;
1da177e4 684
60e019eb 685 if (!static_cpu_has(X86_FEATURE_FPU))
e8a496ac
SS
686 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
687
60e019eb 688 if (!cpu_has_fxsr)
44210111 689 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
86603283 690 &target->thread.fpu.state->fsave, 0,
61c4628b 691 -1);
1da177e4 692
29104e10
SS
693 sanitize_i387_state(target);
694
44210111
RM
695 if (kbuf && pos == 0 && count == sizeof(env)) {
696 convert_from_fxsr(kbuf, target);
697 return 0;
1da177e4 698 }
44210111
RM
699
700 convert_from_fxsr(&env, target);
f668964e 701
44210111 702 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
1da177e4
LT
703}
704
44210111
RM
705int fpregs_set(struct task_struct *target, const struct user_regset *regset,
706 unsigned int pos, unsigned int count,
707 const void *kbuf, const void __user *ubuf)
1da177e4 708{
44210111
RM
709 struct user_i387_ia32_struct env;
710 int ret;
1da177e4 711
67e97fc2 712 ret = fpu__unlazy_stopped(target);
aa283f49
SS
713 if (ret)
714 return ret;
715
29104e10
SS
716 sanitize_i387_state(target);
717
60e019eb 718 if (!static_cpu_has(X86_FEATURE_FPU))
e8a496ac
SS
719 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
720
60e019eb 721 if (!cpu_has_fxsr)
44210111 722 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
60e019eb
PA
723 &target->thread.fpu.state->fsave, 0,
724 -1);
44210111
RM
725
726 if (pos > 0 || count < sizeof(env))
727 convert_from_fxsr(&env, target);
728
729 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
730 if (!ret)
731 convert_to_fxsr(target, &env);
732
42deec6f
SS
733 /*
734 * update the header bit in the xsave header, indicating the
735 * presence of FP.
736 */
737 if (cpu_has_xsave)
86603283 738 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;
44210111 739 return ret;
1da177e4
LT
740}
741
1da177e4
LT
742/*
743 * FPU state for core dumps.
60b3b9af
RM
744 * This is only used for a.out dumps now.
745 * It is declared generically using elf_fpregset_t (which is
746 * struct user_i387_struct) but is in fact only used for 32-bit
747 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
1da177e4 748 */
c5bedc68 749int dump_fpu(struct pt_regs *regs, struct user_i387_struct *ufpu)
1da177e4 750{
1da177e4 751 struct task_struct *tsk = current;
c5bedc68 752 struct fpu *fpu = &tsk->thread.fpu;
f668964e 753 int fpvalid;
1da177e4 754
c5bedc68 755 fpvalid = fpu->fpstate_active;
60b3b9af
RM
756 if (fpvalid)
757 fpvalid = !fpregs_get(tsk, NULL,
758 0, sizeof(struct user_i387_ia32_struct),
c5bedc68 759 ufpu, NULL);
1da177e4
LT
760
761 return fpvalid;
762}
129f6946 763EXPORT_SYMBOL(dump_fpu);
1da177e4 764
60b3b9af 765#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */