[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / fpu / regset.c

/*
 * FPU register's regset abstraction, for ptrace, core dumps, etc.
 */
#include <asm/fpu/internal.h>
#include <asm/fpu/signal.h>
#include <asm/fpu/regset.h>
#include <asm/fpu/xstate.h>
#include <linux/sched/task_stack.h>

/*
 * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
 * as the "regset->n" for the xstate regset will be updated based on the feature
 * capabilities supported by the xsave.
 */
int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
{
	struct fpu *target_fpu = &target->thread.fpu;

	return target_fpu->fpstate_active ? regset->n : 0;
}

int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
{
	struct fpu *target_fpu = &target->thread.fpu;

	if (boot_cpu_has(X86_FEATURE_FXSR) && target_fpu->fpstate_active)
		return regset->n;
	else
		return 0;
}

int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
		unsigned int pos, unsigned int count,
		void *kbuf, void __user *ubuf)
{
	struct fpu *fpu = &target->thread.fpu;

	if (!boot_cpu_has(X86_FEATURE_FXSR))
		return -ENODEV;

	fpu__activate_fpstate_read(fpu);
	fpstate_sanitize_xstate(fpu);

	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
				   &fpu->state.fxsave, 0, -1);
}

int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
		unsigned int pos, unsigned int count,
		const void *kbuf, const void __user *ubuf)
{
	struct fpu *fpu = &target->thread.fpu;
	int ret;

	if (!boot_cpu_has(X86_FEATURE_FXSR))
		return -ENODEV;

	fpu__activate_fpstate_write(fpu);
	fpstate_sanitize_xstate(fpu);

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
				 &fpu->state.fxsave, 0, -1);

	/*
	 * mxcsr reserved bits must be masked to zero for security reasons.
	 */
	fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;

	/*
	 * update the header bits in the xsave header, indicating the
	 * presence of FP and SSE state.
	 */
	if (boot_cpu_has(X86_FEATURE_XSAVE))
		fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;

	return ret;
}

int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
		unsigned int pos, unsigned int count,
		void *kbuf, void __user *ubuf)
{
	struct fpu *fpu = &target->thread.fpu;
	struct xregs_state *xsave;
	int ret;

	if (!boot_cpu_has(X86_FEATURE_XSAVE))
		return -ENODEV;

	xsave = &fpu->state.xsave;

	fpu__activate_fpstate_read(fpu);

	if (using_compacted_format()) {
		ret = copyout_from_xsaves(pos, count, kbuf, ubuf, xsave);
	} else {
		fpstate_sanitize_xstate(fpu);
		/*
		 * Copy the 48 bytes defined by the software into the xsave
		 * area in the thread struct, so that we can copy the whole
		 * area to user using one user_regset_copyout().
		 */
		memcpy(&xsave->i387.sw_reserved, xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));

		/*
		 * Copy the xstate memory layout.
		 */
		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
	}
	return ret;
}

int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
		  unsigned int pos, unsigned int count,
		  const void *kbuf, const void __user *ubuf)
{
	struct fpu *fpu = &target->thread.fpu;
	struct xregs_state *xsave;
	int ret;

	if (!boot_cpu_has(X86_FEATURE_XSAVE))
		return -ENODEV;

	/*
	 * A whole standard-format XSAVE buffer is needed:
	 */
	if ((pos != 0) || (count < fpu_user_xstate_size))
		return -EFAULT;

	xsave = &fpu->state.xsave;

	fpu__activate_fpstate_write(fpu);

	if (boot_cpu_has(X86_FEATURE_XSAVES)) {
		ret = copyin_to_xsaves(kbuf, ubuf, xsave);
	} else {
		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);

		/* xcomp_bv must be 0 when using uncompacted format */
		if (!ret && xsave->header.xcomp_bv)
			ret = -EINVAL;
	}

	/*
	 * In case of failure, mark all states as init:
	 */
	if (ret)
		fpstate_init(&fpu->state);

	/*
	 * mxcsr reserved bits must be masked to zero for security reasons.
	 */
	xsave->i387.mxcsr &= mxcsr_feature_mask;
	xsave->header.xfeatures &= xfeatures_mask;
	/*
	 * These bits must be zero.
	 */
	memset(&xsave->header.reserved, 0, 48);

	return ret;
}

#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION

/*
 * FPU tag word conversions.
 */

static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
{
	unsigned int tmp; /* to avoid 16 bit prefixes in the code */

	/* Transform each pair of bits into 01 (valid) or 00 (empty) */
	tmp = ~twd;
	tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
	/* and move the valid bits to the lower byte. */
	tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
	tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
	tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */

	return tmp;
}

#define FPREG_ADDR(f, n)	((void *)&(f)->st_space + (n) * 16)
#define FP_EXP_TAG_VALID	0
#define FP_EXP_TAG_ZERO		1
#define FP_EXP_TAG_SPECIAL	2
#define FP_EXP_TAG_EMPTY	3

static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
{
	struct _fpxreg *st;
	u32 tos = (fxsave->swd >> 11) & 7;
	u32 twd = (unsigned long) fxsave->twd;
	u32 tag;
	u32 ret = 0xffff0000u;
	int i;

	for (i = 0; i < 8; i++, twd >>= 1) {
		if (twd & 0x1) {
			st = FPREG_ADDR(fxsave, (i - tos) & 7);

			switch (st->exponent & 0x7fff) {
			case 0x7fff:
				tag = FP_EXP_TAG_SPECIAL;
				break;
			case 0x0000:
				if (!st->significand[0] &&
				    !st->significand[1] &&
				    !st->significand[2] &&
				    !st->significand[3])
					tag = FP_EXP_TAG_ZERO;
				else
					tag = FP_EXP_TAG_SPECIAL;
				break;
			default:
				if (st->significand[3] & 0x8000)
					tag = FP_EXP_TAG_VALID;
				else
					tag = FP_EXP_TAG_SPECIAL;
				break;
			}
		} else {
			tag = FP_EXP_TAG_EMPTY;
		}
		ret |= tag << (2 * i);
	}
	return ret;
}

/*
 * FXSR floating point environment conversions.
 */

void
convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
{
	struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
	struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
	struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
	int i;

	env->cwd = fxsave->cwd | 0xffff0000u;
	env->swd = fxsave->swd | 0xffff0000u;
	env->twd = twd_fxsr_to_i387(fxsave);

#ifdef CONFIG_X86_64
	env->fip = fxsave->rip;
	env->foo = fxsave->rdp;
	/*
	 * should be actually ds/cs at fpu exception time, but
	 * that information is not available in 64bit mode.
	 */
	env->fcs = task_pt_regs(tsk)->cs;
	if (tsk == current) {
		savesegment(ds, env->fos);
	} else {
		env->fos = tsk->thread.ds;
	}
	env->fos |= 0xffff0000;
#else
	env->fip = fxsave->fip;
	env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
	env->foo = fxsave->foo;
	env->fos = fxsave->fos;
#endif

	for (i = 0; i < 8; ++i)
		memcpy(&to[i], &from[i], sizeof(to[0]));
}

void convert_to_fxsr(struct task_struct *tsk,
		     const struct user_i387_ia32_struct *env)

{
	struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
	struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
	struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
	int i;

	fxsave->cwd = env->cwd;
	fxsave->swd = env->swd;
	fxsave->twd = twd_i387_to_fxsr(env->twd);
	fxsave->fop = (u16) ((u32) env->fcs >> 16);
#ifdef CONFIG_X86_64
	fxsave->rip = env->fip;
	fxsave->rdp = env->foo;
	/* cs and ds ignored */
#else
	fxsave->fip = env->fip;
	fxsave->fcs = (env->fcs & 0xffff);
	fxsave->foo = env->foo;
	fxsave->fos = env->fos;
#endif

	for (i = 0; i < 8; ++i)
		memcpy(&to[i], &from[i], sizeof(from[0]));
}

int fpregs_get(struct task_struct *target, const struct user_regset *regset,
	       unsigned int pos, unsigned int count,
	       void *kbuf, void __user *ubuf)
{
	struct fpu *fpu = &target->thread.fpu;
	struct user_i387_ia32_struct env;

	fpu__activate_fpstate_read(fpu);

	if (!boot_cpu_has(X86_FEATURE_FPU))
		return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);

	if (!boot_cpu_has(X86_FEATURE_FXSR))
		return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
					   &fpu->state.fsave, 0,
					   -1);

	fpstate_sanitize_xstate(fpu);

	if (kbuf && pos == 0 && count == sizeof(env)) {
		convert_from_fxsr(kbuf, target);
		return 0;
	}

	convert_from_fxsr(&env, target);

	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
}

int fpregs_set(struct task_struct *target, const struct user_regset *regset,
	       unsigned int pos, unsigned int count,
	       const void *kbuf, const void __user *ubuf)
{
	struct fpu *fpu = &target->thread.fpu;
	struct user_i387_ia32_struct env;
	int ret;

	fpu__activate_fpstate_write(fpu);
	fpstate_sanitize_xstate(fpu);

	if (!boot_cpu_has(X86_FEATURE_FPU))
		return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);

	if (!boot_cpu_has(X86_FEATURE_FXSR))
		return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
					  &fpu->state.fsave, 0,
					  -1);

	if (pos > 0 || count < sizeof(env))
		convert_from_fxsr(&env, target);

	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
	if (!ret)
		convert_to_fxsr(target, &env);

	/*
	 * update the header bit in the xsave header, indicating the
	 * presence of FP.
	 */
	if (boot_cpu_has(X86_FEATURE_XSAVE))
		fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
	return ret;
}

/*
 * FPU state for core dumps.
 * This is only used for a.out dumps now.
 * It is declared generically using elf_fpregset_t (which is
 * struct user_i387_struct) but is in fact only used for 32-bit
 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
 */
int dump_fpu(struct pt_regs *regs, struct user_i387_struct *ufpu)
{
	struct task_struct *tsk = current;
	struct fpu *fpu = &tsk->thread.fpu;
	int fpvalid;

	fpvalid = fpu->fpstate_active;
	if (fpvalid)
		fpvalid = !fpregs_get(tsk, NULL,
				      0, sizeof(struct user_i387_ia32_struct),
				      ufpu, NULL);

	return fpvalid;
}
EXPORT_SYMBOL(dump_fpu);

#endif	/* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
Commit	Line	Data
0c306bcf IM	1	/*
	2	* FPU register's regset abstraction, for ptrace, core dumps, etc.
	3	*/
	4	#include <asm/fpu/internal.h>
	5	#include <asm/fpu/signal.h>
	6	#include <asm/fpu/regset.h>
91c3dba7	7	#include <asm/fpu/xstate.h>
68db0cf1	8	#include <linux/sched/task_stack.h>
0c306bcf IM	9
	10	/*
	11	* The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
	12	* as the "regset->n" for the xstate regset will be updated based on the feature
6a6256f9	13	* capabilities supported by the xsave.
0c306bcf IM	14	*/
	15	int regset_fpregs_active(struct task_struct target, const struct user_regset regset)
	16	{
	17	struct fpu *target_fpu = &target->thread.fpu;
	18
	19	return target_fpu->fpstate_active ? regset->n : 0;
	20	}
	21
	22	int regset_xregset_fpregs_active(struct task_struct target, const struct user_regset regset)
	23	{
	24	struct fpu *target_fpu = &target->thread.fpu;
	25
01f8fd73 BP	26	if (boot_cpu_has(X86_FEATURE_FXSR) && target_fpu->fpstate_active)
	27	return regset->n;
	28	else
	29	return 0;
0c306bcf IM	30	}
	31
	32	int xfpregs_get(struct task_struct target, const struct user_regset regset,
	33	unsigned int pos, unsigned int count,
	34	void kbuf, void __user ubuf)
	35	{
	36	struct fpu *fpu = &target->thread.fpu;
	37
01f8fd73	38	if (!boot_cpu_has(X86_FEATURE_FXSR))
0c306bcf IM	39	return -ENODEV;
0c306bcf IM	40
05602812	41	fpu__activate_fpstate_read(fpu);
0c306bcf IM	42	fpstate_sanitize_xstate(fpu);
	43
	44	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	45	&fpu->state.fxsave, 0, -1);
	46	}
	47
	48	int xfpregs_set(struct task_struct target, const struct user_regset regset,
	49	unsigned int pos, unsigned int count,
	50	const void kbuf, const void __user ubuf)
	51	{
	52	struct fpu *fpu = &target->thread.fpu;
	53	int ret;
	54
01f8fd73	55	if (!boot_cpu_has(X86_FEATURE_FXSR))
0c306bcf IM	56	return -ENODEV;
0c306bcf IM	57
6a81d7eb	58	fpu__activate_fpstate_write(fpu);
0c306bcf IM	59	fpstate_sanitize_xstate(fpu);
	60
	61	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	62	&fpu->state.fxsave, 0, -1);
	63
	64	/*
	65	* mxcsr reserved bits must be masked to zero for security reasons.
	66	*/
	67	fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
	68
	69	/*
	70	* update the header bits in the xsave header, indicating the
	71	* presence of FP and SSE state.
	72	*/
d366bf7e	73	if (boot_cpu_has(X86_FEATURE_XSAVE))
d91cab78	74	fpu->state.xsave.header.xfeatures \|= XFEATURE_MASK_FPSSE;
0c306bcf IM	75
	76	return ret;
	77	}
	78
	79	int xstateregs_get(struct task_struct target, const struct user_regset regset,
	80	unsigned int pos, unsigned int count,
	81	void kbuf, void __user ubuf)
	82	{
	83	struct fpu *fpu = &target->thread.fpu;
c47ada30	84	struct xregs_state *xsave;
0c306bcf IM	85	int ret;
0c306bcf IM	86
d366bf7e	87	if (!boot_cpu_has(X86_FEATURE_XSAVE))
0c306bcf IM	88	return -ENODEV;
0c306bcf IM	89
0c306bcf IM	90	xsave = &fpu->state.xsave;
0c306bcf IM	91
91c3dba7 YY	92	fpu__activate_fpstate_read(fpu);
	93
	94	if (using_compacted_format()) {
	95	ret = copyout_from_xsaves(pos, count, kbuf, ubuf, xsave);
	96	} else {
	97	fpstate_sanitize_xstate(fpu);
	98	/*
	99	* Copy the 48 bytes defined by the software into the xsave
	100	* area in the thread struct, so that we can copy the whole
	101	* area to user using one user_regset_copyout().
	102	*/
	103	memcpy(&xsave->i387.sw_reserved, xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
	104
	105	/*
	106	* Copy the xstate memory layout.
	107	*/
	108	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
	109	}
0c306bcf IM	110	return ret;
	111	}
	112
	113	int xstateregs_set(struct task_struct target, const struct user_regset regset,
	114	unsigned int pos, unsigned int count,
	115	const void kbuf, const void __user ubuf)
	116	{
	117	struct fpu *fpu = &target->thread.fpu;
c47ada30	118	struct xregs_state *xsave;
0c306bcf IM	119	int ret;
0c306bcf IM	120
d366bf7e	121	if (!boot_cpu_has(X86_FEATURE_XSAVE))
0c306bcf IM	122	return -ENODEV;
0c306bcf IM	123
91c3dba7 YY	124	/*
	125	* A whole standard-format XSAVE buffer is needed:
	126	*/
	127	if ((pos != 0) \|\| (count < fpu_user_xstate_size))
	128	return -EFAULT;
0c306bcf IM	129
	130	xsave = &fpu->state.xsave;
	131
91c3dba7 YY	132	fpu__activate_fpstate_write(fpu);
91c3dba7 YY	133
efe5d6ac	134	if (boot_cpu_has(X86_FEATURE_XSAVES)) {
91c3dba7	135	ret = copyin_to_xsaves(kbuf, ubuf, xsave);
efe5d6ac	136	} else {
91c3dba7 YY	137	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
91c3dba7 YY	138
efe5d6ac EB	139	/* xcomp_bv must be 0 when using uncompacted format */
	140	if (!ret && xsave->header.xcomp_bv)
	141	ret = -EINVAL;
	142	}
	143
91c3dba7 YY	144	/*
	145	* In case of failure, mark all states as init:
	146	*/
	147	if (ret)
	148	fpstate_init(&fpu->state);
	149
0c306bcf IM	150	/*
	151	* mxcsr reserved bits must be masked to zero for security reasons.
	152	*/
	153	xsave->i387.mxcsr &= mxcsr_feature_mask;
	154	xsave->header.xfeatures &= xfeatures_mask;
	155	/*
	156	* These bits must be zero.
	157	*/
	158	memset(&xsave->header.reserved, 0, 48);
	159
	160	return ret;
	161	}
	162
	163	#if defined CONFIG_X86_32 \|\| defined CONFIG_IA32_EMULATION
	164
	165	/*
	166	* FPU tag word conversions.
	167	*/
	168
	169	static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
	170	{
	171	unsigned int tmp; /* to avoid 16 bit prefixes in the code */
	172
	173	/* Transform each pair of bits into 01 (valid) or 00 (empty) */
	174	tmp = ~twd;
	175	tmp = (tmp \| (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
	176	/* and move the valid bits to the lower byte. */
	177	tmp = (tmp \| (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
	178	tmp = (tmp \| (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
	179	tmp = (tmp \| (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
	180
	181	return tmp;
	182	}
	183
	184	#define FPREG_ADDR(f, n) ((void )&(f)->st_space + (n) 16)
	185	#define FP_EXP_TAG_VALID 0
	186	#define FP_EXP_TAG_ZERO 1
	187	#define FP_EXP_TAG_SPECIAL 2
	188	#define FP_EXP_TAG_EMPTY 3
	189
c47ada30	190	static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
0c306bcf IM	191	{
	192	struct _fpxreg *st;
	193	u32 tos = (fxsave->swd >> 11) & 7;
	194	u32 twd = (unsigned long) fxsave->twd;
	195	u32 tag;
	196	u32 ret = 0xffff0000u;
	197	int i;
	198
	199	for (i = 0; i < 8; i++, twd >>= 1) {
	200	if (twd & 0x1) {
	201	st = FPREG_ADDR(fxsave, (i - tos) & 7);
	202
	203	switch (st->exponent & 0x7fff) {
	204	case 0x7fff:
	205	tag = FP_EXP_TAG_SPECIAL;
	206	break;
	207	case 0x0000:
	208	if (!st->significand[0] &&
	209	!st->significand[1] &&
	210	!st->significand[2] &&
	211	!st->significand[3])
	212	tag = FP_EXP_TAG_ZERO;
	213	else
	214	tag = FP_EXP_TAG_SPECIAL;
	215	break;
	216	default:
	217	if (st->significand[3] & 0x8000)
	218	tag = FP_EXP_TAG_VALID;
	219	else
	220	tag = FP_EXP_TAG_SPECIAL;
	221	break;
	222	}
	223	} else {
	224	tag = FP_EXP_TAG_EMPTY;
	225	}
	226	ret \|= tag << (2 * i);
	227	}
	228	return ret;
	229	}
	230
	231	/*
	232	* FXSR floating point environment conversions.
	233	*/
	234
	235	void
	236	convert_from_fxsr(struct user_i387_ia32_struct env, struct task_struct tsk)
	237	{
c47ada30	238	struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
0c306bcf IM	239	struct _fpreg to = (struct _fpreg ) &env->st_space[0];
	240	struct _fpxreg from = (struct _fpxreg ) &fxsave->st_space[0];
	241	int i;
	242
	243	env->cwd = fxsave->cwd \| 0xffff0000u;
	244	env->swd = fxsave->swd \| 0xffff0000u;
	245	env->twd = twd_fxsr_to_i387(fxsave);
	246
	247	#ifdef CONFIG_X86_64
	248	env->fip = fxsave->rip;
	249	env->foo = fxsave->rdp;
	250	/*
	251	* should be actually ds/cs at fpu exception time, but
	252	* that information is not available in 64bit mode.
	253	*/
	254	env->fcs = task_pt_regs(tsk)->cs;
	255	if (tsk == current) {
	256	savesegment(ds, env->fos);
	257	} else {
	258	env->fos = tsk->thread.ds;
	259	}
	260	env->fos \|= 0xffff0000;
	261	#else
	262	env->fip = fxsave->fip;
	263	env->fcs = (u16) fxsave->fcs \| ((u32) fxsave->fop << 16);
	264	env->foo = fxsave->foo;
	265	env->fos = fxsave->fos;
	266	#endif
	267
	268	for (i = 0; i < 8; ++i)
	269	memcpy(&to[i], &from[i], sizeof(to[0]));
	270	}
	271
	272	void convert_to_fxsr(struct task_struct *tsk,
	273	const struct user_i387_ia32_struct *env)
	274
	275	{
c47ada30	276	struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
0c306bcf IM	277	struct _fpreg from = (struct _fpreg ) &env->st_space[0];
	278	struct _fpxreg to = (struct _fpxreg ) &fxsave->st_space[0];
	279	int i;
	280
	281	fxsave->cwd = env->cwd;
	282	fxsave->swd = env->swd;
	283	fxsave->twd = twd_i387_to_fxsr(env->twd);
	284	fxsave->fop = (u16) ((u32) env->fcs >> 16);
	285	#ifdef CONFIG_X86_64
	286	fxsave->rip = env->fip;
	287	fxsave->rdp = env->foo;
	288	/* cs and ds ignored */
	289	#else
	290	fxsave->fip = env->fip;
	291	fxsave->fcs = (env->fcs & 0xffff);
	292	fxsave->foo = env->foo;
	293	fxsave->fos = env->fos;
	294	#endif
	295
	296	for (i = 0; i < 8; ++i)
	297	memcpy(&to[i], &from[i], sizeof(from[0]));
	298	}
	299
	300	int fpregs_get(struct task_struct target, const struct user_regset regset,
	301	unsigned int pos, unsigned int count,
	302	void kbuf, void __user ubuf)
	303	{
	304	struct fpu *fpu = &target->thread.fpu;
	305	struct user_i387_ia32_struct env;
	306
05602812	307	fpu__activate_fpstate_read(fpu);
0c306bcf	308
78df526c	309	if (!boot_cpu_has(X86_FEATURE_FPU))
0c306bcf IM	310	return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
0c306bcf IM	311
01f8fd73	312	if (!boot_cpu_has(X86_FEATURE_FXSR))
0c306bcf IM	313	return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
	314	&fpu->state.fsave, 0,
	315	-1);
	316
	317	fpstate_sanitize_xstate(fpu);
	318
	319	if (kbuf && pos == 0 && count == sizeof(env)) {
	320	convert_from_fxsr(kbuf, target);
	321	return 0;
	322	}
	323
	324	convert_from_fxsr(&env, target);
	325
	326	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
	327	}
	328
	329	int fpregs_set(struct task_struct target, const struct user_regset regset,
	330	unsigned int pos, unsigned int count,
	331	const void kbuf, const void __user ubuf)
	332	{
	333	struct fpu *fpu = &target->thread.fpu;
	334	struct user_i387_ia32_struct env;
	335	int ret;
	336
6a81d7eb	337	fpu__activate_fpstate_write(fpu);
0c306bcf IM	338	fpstate_sanitize_xstate(fpu);
0c306bcf IM	339
78df526c	340	if (!boot_cpu_has(X86_FEATURE_FPU))
0c306bcf IM	341	return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
0c306bcf IM	342
01f8fd73	343	if (!boot_cpu_has(X86_FEATURE_FXSR))
0c306bcf IM	344	return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
	345	&fpu->state.fsave, 0,
	346	-1);
	347
	348	if (pos > 0 \|\| count < sizeof(env))
	349	convert_from_fxsr(&env, target);
	350
	351	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
	352	if (!ret)
	353	convert_to_fxsr(target, &env);
	354
	355	/*
	356	* update the header bit in the xsave header, indicating the
	357	* presence of FP.
	358	*/
d366bf7e	359	if (boot_cpu_has(X86_FEATURE_XSAVE))
d91cab78	360	fpu->state.xsave.header.xfeatures \|= XFEATURE_MASK_FP;
0c306bcf IM	361	return ret;
	362	}
	363
	364	/*
	365	* FPU state for core dumps.
	366	* This is only used for a.out dumps now.
	367	* It is declared generically using elf_fpregset_t (which is
	368	* struct user_i387_struct) but is in fact only used for 32-bit
	369	* dumps, so on 64-bit it is really struct user_i387_ia32_struct.
	370	*/
	371	int dump_fpu(struct pt_regs regs, struct user_i387_struct ufpu)
	372	{
	373	struct task_struct *tsk = current;
	374	struct fpu *fpu = &tsk->thread.fpu;
	375	int fpvalid;
	376
	377	fpvalid = fpu->fpstate_active;
	378	if (fpvalid)
	379	fpvalid = !fpregs_get(tsk, NULL,
	380	0, sizeof(struct user_i387_ia32_struct),
	381	ufpu, NULL);
	382
	383	return fpvalid;
	384	}
	385	EXPORT_SYMBOL(dump_fpu);
	386
	387	#endif /* CONFIG_X86_32 \|\| CONFIG_IA32_EMULATION */