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dc1e35c6
SS
1/*
2 * xsave/xrstor support.
3 *
4 * Author: Suresh Siddha <suresh.b.siddha@intel.com>
5 */
dc1e35c6 6#include <linux/compat.h>
7e7ce87f 7#include <linux/cpu.h>
84594296 8#include <linux/pkeys.h>
59a36d16 9
df6b35f4 10#include <asm/fpu/api.h>
78f7f1e5 11#include <asm/fpu/internal.h>
fcbc99c4 12#include <asm/fpu/signal.h>
59a36d16 13#include <asm/fpu/regset.h>
91c3dba7 14#include <asm/fpu/xstate.h>
b992c660 15
375074cc 16#include <asm/tlbflush.h>
dc1e35c6 17
1f96b1ef
DH
18/*
19 * Although we spell it out in here, the Processor Trace
20 * xfeature is completely unused. We use other mechanisms
21 * to save/restore PT state in Linux.
22 */
5b073430
IM
23static const char *xfeature_names[] =
24{
25 "x87 floating point registers" ,
26 "SSE registers" ,
27 "AVX registers" ,
28 "MPX bounds registers" ,
29 "MPX CSR" ,
30 "AVX-512 opmask" ,
31 "AVX-512 Hi256" ,
32 "AVX-512 ZMM_Hi256" ,
1f96b1ef 33 "Processor Trace (unused)" ,
c8df4009 34 "Protection Keys User registers",
5b073430
IM
35 "unknown xstate feature" ,
36};
37
dc1e35c6 38/*
614df7fb 39 * Mask of xstate features supported by the CPU and the kernel:
dc1e35c6 40 */
5b073430 41u64 xfeatures_mask __read_mostly;
dc1e35c6 42
dad8c4fe
DH
43static unsigned int xstate_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1};
44static unsigned int xstate_sizes[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1};
614df7fb 45static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8];
84246fe4 46
a1141e0b
FY
47/*
48 * The XSAVE area of kernel can be in standard or compacted format;
49 * it is always in standard format for user mode. This is the user
50 * mode standard format size used for signal and ptrace frames.
51 */
52unsigned int fpu_user_xstate_size;
53
0a265375
DH
54/*
55 * Clear all of the X86_FEATURE_* bits that are unavailable
56 * when the CPU has no XSAVE support.
57 */
58void fpu__xstate_clear_all_cpu_caps(void)
59{
60 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
61 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
62 setup_clear_cpu_cap(X86_FEATURE_XSAVEC);
63 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
64 setup_clear_cpu_cap(X86_FEATURE_AVX);
65 setup_clear_cpu_cap(X86_FEATURE_AVX2);
66 setup_clear_cpu_cap(X86_FEATURE_AVX512F);
67 setup_clear_cpu_cap(X86_FEATURE_AVX512PF);
68 setup_clear_cpu_cap(X86_FEATURE_AVX512ER);
69 setup_clear_cpu_cap(X86_FEATURE_AVX512CD);
d0500494
FY
70 setup_clear_cpu_cap(X86_FEATURE_AVX512DQ);
71 setup_clear_cpu_cap(X86_FEATURE_AVX512BW);
72 setup_clear_cpu_cap(X86_FEATURE_AVX512VL);
0a265375 73 setup_clear_cpu_cap(X86_FEATURE_MPX);
eb7c5f87 74 setup_clear_cpu_cap(X86_FEATURE_XGETBV1);
c8df4009 75 setup_clear_cpu_cap(X86_FEATURE_PKU);
0a265375
DH
76}
77
5b073430
IM
78/*
79 * Return whether the system supports a given xfeature.
80 *
81 * Also return the name of the (most advanced) feature that the caller requested:
82 */
83int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name)
84{
85 u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask;
86
87 if (unlikely(feature_name)) {
88 long xfeature_idx, max_idx;
89 u64 xfeatures_print;
90 /*
91 * So we use FLS here to be able to print the most advanced
92 * feature that was requested but is missing. So if a driver
d91cab78 93 * asks about "XFEATURE_MASK_SSE | XFEATURE_MASK_YMM" we'll print the
5b073430
IM
94 * missing AVX feature - this is the most informative message
95 * to users:
96 */
97 if (xfeatures_missing)
98 xfeatures_print = xfeatures_missing;
99 else
100 xfeatures_print = xfeatures_needed;
101
102 xfeature_idx = fls64(xfeatures_print)-1;
103 max_idx = ARRAY_SIZE(xfeature_names)-1;
104 xfeature_idx = min(xfeature_idx, max_idx);
105
106 *feature_name = xfeature_names[xfeature_idx];
107 }
108
109 if (xfeatures_missing)
110 return 0;
111
112 return 1;
113}
114EXPORT_SYMBOL_GPL(cpu_has_xfeatures);
115
1499ce2d
YY
116static int xfeature_is_supervisor(int xfeature_nr)
117{
118 /*
119 * We currently do not support supervisor states, but if
120 * we did, we could find out like this.
121 *
122 * SDM says: If state component 'i' is a user state component,
123 * ECX[0] return 0; if state component i is a supervisor
124 * state component, ECX[0] returns 1.
125 */
126 u32 eax, ebx, ecx, edx;
127
128 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
129 return !!(ecx & 1);
130}
131
132static int xfeature_is_user(int xfeature_nr)
133{
134 return !xfeature_is_supervisor(xfeature_nr);
135}
136
29104e10 137/*
aeb997b9
IM
138 * When executing XSAVEOPT (or other optimized XSAVE instructions), if
139 * a processor implementation detects that an FPU state component is still
140 * (or is again) in its initialized state, it may clear the corresponding
141 * bit in the header.xfeatures field, and can skip the writeout of registers
142 * to the corresponding memory layout.
73a3aeb3
IM
143 *
144 * This means that when the bit is zero, the state component might still contain
145 * some previous - non-initialized register state.
146 *
147 * Before writing xstate information to user-space we sanitize those components,
148 * to always ensure that the memory layout of a feature will be in the init state
149 * if the corresponding header bit is zero. This is to ensure that user-space doesn't
150 * see some stale state in the memory layout during signal handling, debugging etc.
29104e10 151 */
36e49e7f 152void fpstate_sanitize_xstate(struct fpu *fpu)
29104e10 153{
c47ada30 154 struct fxregs_state *fx = &fpu->state.fxsave;
73a3aeb3 155 int feature_bit;
400e4b20 156 u64 xfeatures;
29104e10 157
1ac91a76 158 if (!use_xsaveopt())
29104e10
SS
159 return;
160
36e49e7f 161 xfeatures = fpu->state.xsave.header.xfeatures;
29104e10
SS
162
163 /*
164 * None of the feature bits are in init state. So nothing else
0d2eb44f 165 * to do for us, as the memory layout is up to date.
29104e10 166 */
400e4b20 167 if ((xfeatures & xfeatures_mask) == xfeatures_mask)
29104e10
SS
168 return;
169
170 /*
171 * FP is in init state
172 */
d91cab78 173 if (!(xfeatures & XFEATURE_MASK_FP)) {
29104e10
SS
174 fx->cwd = 0x37f;
175 fx->swd = 0;
176 fx->twd = 0;
177 fx->fop = 0;
178 fx->rip = 0;
179 fx->rdp = 0;
180 memset(&fx->st_space[0], 0, 128);
181 }
182
183 /*
184 * SSE is in init state
185 */
d91cab78 186 if (!(xfeatures & XFEATURE_MASK_SSE))
29104e10
SS
187 memset(&fx->xmm_space[0], 0, 256);
188
73a3aeb3
IM
189 /*
190 * First two features are FPU and SSE, which above we handled
191 * in a special way already:
192 */
193 feature_bit = 0x2;
400e4b20 194 xfeatures = (xfeatures_mask & ~xfeatures) >> 2;
29104e10
SS
195
196 /*
73a3aeb3
IM
197 * Update all the remaining memory layouts according to their
198 * standard xstate layout, if their header bit is in the init
199 * state:
29104e10 200 */
400e4b20
IM
201 while (xfeatures) {
202 if (xfeatures & 0x1) {
a1141e0b 203 int offset = xstate_comp_offsets[feature_bit];
29104e10
SS
204 int size = xstate_sizes[feature_bit];
205
73a3aeb3 206 memcpy((void *)fx + offset,
6f575023 207 (void *)&init_fpstate.xsave + offset,
29104e10
SS
208 size);
209 }
210
400e4b20 211 xfeatures >>= 1;
29104e10
SS
212 feature_bit++;
213 }
214}
215
dc1e35c6 216/*
55cc4678
IM
217 * Enable the extended processor state save/restore feature.
218 * Called once per CPU onlining.
dc1e35c6 219 */
55cc4678 220void fpu__init_cpu_xstate(void)
dc1e35c6 221{
d366bf7e 222 if (!boot_cpu_has(X86_FEATURE_XSAVE) || !xfeatures_mask)
55cc4678 223 return;
b8be15d5
YY
224 /*
225 * Make it clear that XSAVES supervisor states are not yet
226 * implemented should anyone expect it to work by changing
227 * bits in XFEATURE_MASK_* macros and XCR0.
228 */
229 WARN_ONCE((xfeatures_mask & XFEATURE_MASK_SUPERVISOR),
230 "x86/fpu: XSAVES supervisor states are not yet implemented.\n");
231
232 xfeatures_mask &= ~XFEATURE_MASK_SUPERVISOR;
55cc4678 233
375074cc 234 cr4_set_bits(X86_CR4_OSXSAVE);
614df7fb 235 xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask);
dc1e35c6
SS
236}
237
e6e888f9
DH
238/*
239 * Note that in the future we will likely need a pair of
240 * functions here: one for user xstates and the other for
241 * system xstates. For now, they are the same.
242 */
243static int xfeature_enabled(enum xfeature xfeature)
244{
245 return !!(xfeatures_mask & (1UL << xfeature));
246}
247
a1488f8b 248/*
39f1acd2
IM
249 * Record the offsets and sizes of various xstates contained
250 * in the XSAVE state memory layout.
a1488f8b 251 */
4995b9db 252static void __init setup_xstate_features(void)
a1488f8b 253{
ee9ae257 254 u32 eax, ebx, ecx, edx, i;
e6e888f9
DH
255 /* start at the beginnning of the "extended state" */
256 unsigned int last_good_offset = offsetof(struct xregs_state,
257 extended_state_area);
ac73b27a
YY
258 /*
259 * The FP xstates and SSE xstates are legacy states. They are always
260 * in the fixed offsets in the xsave area in either compacted form
261 * or standard form.
262 */
263 xstate_offsets[0] = 0;
264 xstate_sizes[0] = offsetof(struct fxregs_state, xmm_space);
265 xstate_offsets[1] = xstate_sizes[0];
266 xstate_sizes[1] = FIELD_SIZEOF(struct fxregs_state, xmm_space);
a1488f8b 267
ee9ae257 268 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
e6e888f9
DH
269 if (!xfeature_enabled(i))
270 continue;
a1488f8b 271
e6e888f9 272 cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
1499ce2d
YY
273
274 /*
275 * If an xfeature is supervisor state, the offset
276 * in EBX is invalid. We leave it to -1.
277 */
278 if (xfeature_is_user(i))
279 xstate_offsets[i] = ebx;
280
ee9ae257 281 xstate_sizes[i] = eax;
e6e888f9
DH
282 /*
283 * In our xstate size checks, we assume that the
284 * highest-numbered xstate feature has the
285 * highest offset in the buffer. Ensure it does.
286 */
287 WARN_ONCE(last_good_offset > xstate_offsets[i],
288 "x86/fpu: misordered xstate at %d\n", last_good_offset);
289 last_good_offset = xstate_offsets[i];
39f1acd2 290 }
a1488f8b
SS
291}
292
32231879 293static void __init print_xstate_feature(u64 xstate_mask)
69496e10 294{
33588b52 295 const char *feature_name;
69496e10 296
33588b52 297 if (cpu_has_xfeatures(xstate_mask, &feature_name))
c8df4009 298 pr_info("x86/fpu: Supporting XSAVE feature 0x%03Lx: '%s'\n", xstate_mask, feature_name);
69496e10
IM
299}
300
301/*
302 * Print out all the supported xstate features:
303 */
32231879 304static void __init print_xstate_features(void)
69496e10 305{
d91cab78
DH
306 print_xstate_feature(XFEATURE_MASK_FP);
307 print_xstate_feature(XFEATURE_MASK_SSE);
308 print_xstate_feature(XFEATURE_MASK_YMM);
309 print_xstate_feature(XFEATURE_MASK_BNDREGS);
310 print_xstate_feature(XFEATURE_MASK_BNDCSR);
311 print_xstate_feature(XFEATURE_MASK_OPMASK);
312 print_xstate_feature(XFEATURE_MASK_ZMM_Hi256);
313 print_xstate_feature(XFEATURE_MASK_Hi16_ZMM);
c8df4009 314 print_xstate_feature(XFEATURE_MASK_PKRU);
69496e10
IM
315}
316
03482e08
YY
317/*
318 * This check is important because it is easy to get XSTATE_*
319 * confused with XSTATE_BIT_*.
320 */
321#define CHECK_XFEATURE(nr) do { \
322 WARN_ON(nr < FIRST_EXTENDED_XFEATURE); \
323 WARN_ON(nr >= XFEATURE_MAX); \
324} while (0)
325
326/*
327 * We could cache this like xstate_size[], but we only use
328 * it here, so it would be a waste of space.
329 */
330static int xfeature_is_aligned(int xfeature_nr)
331{
332 u32 eax, ebx, ecx, edx;
333
334 CHECK_XFEATURE(xfeature_nr);
335 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
336 /*
337 * The value returned by ECX[1] indicates the alignment
338 * of state component 'i' when the compacted format
339 * of the extended region of an XSAVE area is used:
340 */
341 return !!(ecx & 2);
342}
343
7496d645
FY
344/*
345 * This function sets up offsets and sizes of all extended states in
346 * xsave area. This supports both standard format and compacted format
347 * of the xsave aread.
7496d645 348 */
32231879 349static void __init setup_xstate_comp(void)
7496d645 350{
614df7fb 351 unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8];
7496d645
FY
352 int i;
353
8ff925e1
FY
354 /*
355 * The FP xstates and SSE xstates are legacy states. They are always
356 * in the fixed offsets in the xsave area in either compacted form
357 * or standard form.
358 */
359 xstate_comp_offsets[0] = 0;
c47ada30 360 xstate_comp_offsets[1] = offsetof(struct fxregs_state, xmm_space);
7496d645 361
782511b0 362 if (!boot_cpu_has(X86_FEATURE_XSAVES)) {
ee9ae257 363 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
633d54c4 364 if (xfeature_enabled(i)) {
7496d645
FY
365 xstate_comp_offsets[i] = xstate_offsets[i];
366 xstate_comp_sizes[i] = xstate_sizes[i];
367 }
368 }
369 return;
370 }
371
8a93c9e0
DH
372 xstate_comp_offsets[FIRST_EXTENDED_XFEATURE] =
373 FXSAVE_SIZE + XSAVE_HDR_SIZE;
7496d645 374
ee9ae257 375 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
633d54c4 376 if (xfeature_enabled(i))
7496d645
FY
377 xstate_comp_sizes[i] = xstate_sizes[i];
378 else
379 xstate_comp_sizes[i] = 0;
380
03482e08 381 if (i > FIRST_EXTENDED_XFEATURE) {
7496d645
FY
382 xstate_comp_offsets[i] = xstate_comp_offsets[i-1]
383 + xstate_comp_sizes[i-1];
384
03482e08
YY
385 if (xfeature_is_aligned(i))
386 xstate_comp_offsets[i] =
387 ALIGN(xstate_comp_offsets[i], 64);
388 }
7496d645
FY
389 }
390}
391
996952e0
YY
392/*
393 * Print out xstate component offsets and sizes
394 */
395static void __init print_xstate_offset_size(void)
396{
397 int i;
398
399 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
400 if (!xfeature_enabled(i))
401 continue;
402 pr_info("x86/fpu: xstate_offset[%d]: %4d, xstate_sizes[%d]: %4d\n",
403 i, xstate_comp_offsets[i], i, xstate_sizes[i]);
404 }
405}
406
dc1e35c6
SS
407/*
408 * setup the xstate image representing the init state
409 */
32231879 410static void __init setup_init_fpu_buf(void)
dc1e35c6 411{
e49a449b 412 static int on_boot_cpu __initdata = 1;
e97131a8
IM
413
414 WARN_ON_FPU(!on_boot_cpu);
415 on_boot_cpu = 0;
416
d366bf7e 417 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5d2bd700
SS
418 return;
419
420 setup_xstate_features();
69496e10 421 print_xstate_features();
a1488f8b 422
7d937060 423 if (boot_cpu_has(X86_FEATURE_XSAVES))
6f575023 424 init_fpstate.xsave.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask;
47c2f292 425
29104e10 426 /*
7d937060 427 * Init all the features state with header.xfeatures being 0x0
29104e10 428 */
d65fcd60 429 copy_kernel_to_xregs_booting(&init_fpstate.xsave);
3e261c14 430
29104e10
SS
431 /*
432 * Dump the init state again. This is to identify the init state
433 * of any feature which is not represented by all zero's.
434 */
c6813144 435 copy_xregs_to_kernel_booting(&init_fpstate.xsave);
dc1e35c6
SS
436}
437
65ac2e9b
DH
438static int xfeature_uncompacted_offset(int xfeature_nr)
439{
440 u32 eax, ebx, ecx, edx;
441
1499ce2d
YY
442 /*
443 * Only XSAVES supports supervisor states and it uses compacted
444 * format. Checking a supervisor state's uncompacted offset is
445 * an error.
446 */
447 if (XFEATURE_MASK_SUPERVISOR & (1 << xfeature_nr)) {
448 WARN_ONCE(1, "No fixed offset for xstate %d\n", xfeature_nr);
449 return -1;
450 }
451
65ac2e9b
DH
452 CHECK_XFEATURE(xfeature_nr);
453 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
454 return ebx;
455}
456
457static int xfeature_size(int xfeature_nr)
458{
459 u32 eax, ebx, ecx, edx;
460
461 CHECK_XFEATURE(xfeature_nr);
462 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
463 return eax;
464}
465
466/*
467 * 'XSAVES' implies two different things:
468 * 1. saving of supervisor/system state
469 * 2. using the compacted format
470 *
471 * Use this function when dealing with the compacted format so
472 * that it is obvious which aspect of 'XSAVES' is being handled
473 * by the calling code.
474 */
99aa22d0 475int using_compacted_format(void)
65ac2e9b 476{
782511b0 477 return boot_cpu_has(X86_FEATURE_XSAVES);
65ac2e9b
DH
478}
479
480static void __xstate_dump_leaves(void)
481{
482 int i;
483 u32 eax, ebx, ecx, edx;
484 static int should_dump = 1;
485
486 if (!should_dump)
487 return;
488 should_dump = 0;
489 /*
490 * Dump out a few leaves past the ones that we support
491 * just in case there are some goodies up there
492 */
493 for (i = 0; i < XFEATURE_MAX + 10; i++) {
494 cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
495 pr_warn("CPUID[%02x, %02x]: eax=%08x ebx=%08x ecx=%08x edx=%08x\n",
496 XSTATE_CPUID, i, eax, ebx, ecx, edx);
497 }
498}
499
500#define XSTATE_WARN_ON(x) do { \
501 if (WARN_ONCE(x, "XSAVE consistency problem, dumping leaves")) { \
502 __xstate_dump_leaves(); \
503 } \
504} while (0)
505
ef78f2a4
DH
506#define XCHECK_SZ(sz, nr, nr_macro, __struct) do { \
507 if ((nr == nr_macro) && \
508 WARN_ONCE(sz != sizeof(__struct), \
509 "%s: struct is %zu bytes, cpu state %d bytes\n", \
510 __stringify(nr_macro), sizeof(__struct), sz)) { \
511 __xstate_dump_leaves(); \
512 } \
513} while (0)
514
515/*
516 * We have a C struct for each 'xstate'. We need to ensure
517 * that our software representation matches what the CPU
518 * tells us about the state's size.
519 */
520static void check_xstate_against_struct(int nr)
521{
522 /*
523 * Ask the CPU for the size of the state.
524 */
525 int sz = xfeature_size(nr);
526 /*
527 * Match each CPU state with the corresponding software
528 * structure.
529 */
530 XCHECK_SZ(sz, nr, XFEATURE_YMM, struct ymmh_struct);
531 XCHECK_SZ(sz, nr, XFEATURE_BNDREGS, struct mpx_bndreg_state);
532 XCHECK_SZ(sz, nr, XFEATURE_BNDCSR, struct mpx_bndcsr_state);
533 XCHECK_SZ(sz, nr, XFEATURE_OPMASK, struct avx_512_opmask_state);
534 XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state);
535 XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state);
c8df4009 536 XCHECK_SZ(sz, nr, XFEATURE_PKRU, struct pkru_state);
ef78f2a4
DH
537
538 /*
539 * Make *SURE* to add any feature numbers in below if
540 * there are "holes" in the xsave state component
541 * numbers.
542 */
543 if ((nr < XFEATURE_YMM) ||
1f96b1ef
DH
544 (nr >= XFEATURE_MAX) ||
545 (nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR)) {
ef78f2a4
DH
546 WARN_ONCE(1, "no structure for xstate: %d\n", nr);
547 XSTATE_WARN_ON(1);
548 }
549}
550
65ac2e9b
DH
551/*
552 * This essentially double-checks what the cpu told us about
553 * how large the XSAVE buffer needs to be. We are recalculating
554 * it to be safe.
555 */
556static void do_extra_xstate_size_checks(void)
557{
558 int paranoid_xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE;
559 int i;
560
561 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
562 if (!xfeature_enabled(i))
563 continue;
ef78f2a4
DH
564
565 check_xstate_against_struct(i);
65ac2e9b
DH
566 /*
567 * Supervisor state components can be managed only by
568 * XSAVES, which is compacted-format only.
569 */
570 if (!using_compacted_format())
571 XSTATE_WARN_ON(xfeature_is_supervisor(i));
572
573 /* Align from the end of the previous feature */
574 if (xfeature_is_aligned(i))
575 paranoid_xstate_size = ALIGN(paranoid_xstate_size, 64);
576 /*
577 * The offset of a given state in the non-compacted
578 * format is given to us in a CPUID leaf. We check
579 * them for being ordered (increasing offsets) in
580 * setup_xstate_features().
581 */
582 if (!using_compacted_format())
583 paranoid_xstate_size = xfeature_uncompacted_offset(i);
584 /*
585 * The compacted-format offset always depends on where
586 * the previous state ended.
587 */
588 paranoid_xstate_size += xfeature_size(i);
589 }
bf15a8cf 590 XSTATE_WARN_ON(paranoid_xstate_size != fpu_kernel_xstate_size);
65ac2e9b
DH
591}
592
a1141e0b 593
7e7ce87f 594/*
a1141e0b 595 * Get total size of enabled xstates in XCR0/xfeatures_mask.
65ac2e9b
DH
596 *
597 * Note the SDM's wording here. "sub-function 0" only enumerates
598 * the size of the *user* states. If we use it to size a buffer
599 * that we use 'XSAVES' on, we could potentially overflow the
600 * buffer because 'XSAVES' saves system states too.
601 *
602 * Note that we do not currently set any bits on IA32_XSS so
603 * 'XCR0 | IA32_XSS == XCR0' for now.
7e7ce87f 604 */
a1141e0b 605static unsigned int __init get_xsaves_size(void)
7e7ce87f
FY
606{
607 unsigned int eax, ebx, ecx, edx;
a1141e0b
FY
608 /*
609 * - CPUID function 0DH, sub-function 1:
610 * EBX enumerates the size (in bytes) required by
611 * the XSAVES instruction for an XSAVE area
612 * containing all the state components
613 * corresponding to bits currently set in
614 * XCR0 | IA32_XSS.
615 */
616 cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);
617 return ebx;
618}
7e7ce87f 619
a1141e0b
FY
620static unsigned int __init get_xsave_size(void)
621{
622 unsigned int eax, ebx, ecx, edx;
623 /*
624 * - CPUID function 0DH, sub-function 0:
625 * EBX enumerates the size (in bytes) required by
626 * the XSAVE instruction for an XSAVE area
627 * containing all the *user* state components
628 * corresponding to bits currently set in XCR0.
629 */
630 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
631 return ebx;
4109ca06
DH
632}
633
634/*
635 * Will the runtime-enumerated 'xstate_size' fit in the init
636 * task's statically-allocated buffer?
637 */
638static bool is_supported_xstate_size(unsigned int test_xstate_size)
639{
640 if (test_xstate_size <= sizeof(union fpregs_state))
641 return true;
642
643 pr_warn("x86/fpu: xstate buffer too small (%zu < %d), disabling xsave\n",
644 sizeof(union fpregs_state), test_xstate_size);
645 return false;
646}
647
648static int init_xstate_size(void)
649{
650 /* Recompute the context size for enabled features: */
a1141e0b
FY
651 unsigned int possible_xstate_size;
652 unsigned int xsave_size;
653
654 xsave_size = get_xsave_size();
655
656 if (boot_cpu_has(X86_FEATURE_XSAVES))
657 possible_xstate_size = get_xsaves_size();
658 else
659 possible_xstate_size = xsave_size;
4109ca06
DH
660
661 /* Ensure we have the space to store all enabled: */
662 if (!is_supported_xstate_size(possible_xstate_size))
663 return -EINVAL;
664
665 /*
666 * The size is OK, we are definitely going to use xsave,
667 * make it known to the world that we need more space.
668 */
bf15a8cf 669 fpu_kernel_xstate_size = possible_xstate_size;
65ac2e9b 670 do_extra_xstate_size_checks();
a1141e0b
FY
671
672 /*
673 * User space is always in standard format.
674 */
675 fpu_user_xstate_size = xsave_size;
4109ca06
DH
676 return 0;
677}
678
d91cab78
DH
679/*
680 * We enabled the XSAVE hardware, but something went wrong and
681 * we can not use it. Disable it.
682 */
683static void fpu__init_disable_system_xstate(void)
4109ca06
DH
684{
685 xfeatures_mask = 0;
686 cr4_clear_bits(X86_CR4_OSXSAVE);
687 fpu__xstate_clear_all_cpu_caps();
7e7ce87f
FY
688}
689
dc1e35c6
SS
690/*
691 * Enable and initialize the xsave feature.
55cc4678 692 * Called once per system bootup.
dc1e35c6 693 */
32231879 694void __init fpu__init_system_xstate(void)
dc1e35c6
SS
695{
696 unsigned int eax, ebx, ecx, edx;
e49a449b 697 static int on_boot_cpu __initdata = 1;
4109ca06 698 int err;
e97131a8
IM
699
700 WARN_ON_FPU(!on_boot_cpu);
701 on_boot_cpu = 0;
dc1e35c6 702
d366bf7e 703 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
e9dbfd67
IM
704 pr_info("x86/fpu: Legacy x87 FPU detected.\n");
705 return;
706 }
707
ee813d53 708 if (boot_cpu_data.cpuid_level < XSTATE_CPUID) {
e97131a8 709 WARN_ON_FPU(1);
ee813d53
RR
710 return;
711 }
712
713 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
614df7fb 714 xfeatures_mask = eax + ((u64)edx << 32);
dc1e35c6 715
d91cab78 716 if ((xfeatures_mask & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) {
ec3ed4a2
DH
717 /*
718 * This indicates that something really unexpected happened
719 * with the enumeration. Disable XSAVE and try to continue
720 * booting without it. This is too early to BUG().
721 */
614df7fb 722 pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask);
ec3ed4a2 723 goto out_disable;
dc1e35c6
SS
724 }
725
a5fe93a5 726 xfeatures_mask &= fpu__get_supported_xfeatures_mask();
97e80a70 727
55cc4678
IM
728 /* Enable xstate instructions to be able to continue with initialization: */
729 fpu__init_cpu_xstate();
4109ca06 730 err = init_xstate_size();
ec3ed4a2
DH
731 if (err)
732 goto out_disable;
dc1e35c6 733
91c3dba7
YY
734 /*
735 * Update info used for ptrace frames; use standard-format size and no
736 * supervisor xstates:
737 */
738 update_regset_xstate_info(fpu_user_xstate_size, xfeatures_mask & ~XFEATURE_MASK_SUPERVISOR);
739
b992c660 740 fpu__init_prepare_fx_sw_frame();
5d2bd700 741 setup_init_fpu_buf();
5fd402df 742 setup_xstate_comp();
996952e0 743 print_xstate_offset_size();
dc1e35c6 744
b0815359 745 pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n",
614df7fb 746 xfeatures_mask,
bf15a8cf 747 fpu_kernel_xstate_size,
782511b0 748 boot_cpu_has(X86_FEATURE_XSAVES) ? "compacted" : "standard");
ec3ed4a2
DH
749 return;
750
751out_disable:
752 /* something went wrong, try to boot without any XSAVE support */
753 fpu__init_disable_system_xstate();
dc1e35c6 754}
82d4150c 755
9254aaa0
IM
756/*
757 * Restore minimal FPU state after suspend:
758 */
759void fpu__resume_cpu(void)
760{
761 /*
762 * Restore XCR0 on xsave capable CPUs:
763 */
d366bf7e 764 if (boot_cpu_has(X86_FEATURE_XSAVE))
9254aaa0
IM
765 xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask);
766}
767
b8b9b6ba
DH
768/*
769 * Given an xstate feature mask, calculate where in the xsave
770 * buffer the state is. Callers should ensure that the buffer
771 * is valid.
772 *
773 * Note: does not work for compacted buffers.
774 */
775void *__raw_xsave_addr(struct xregs_state *xsave, int xstate_feature_mask)
776{
777 int feature_nr = fls64(xstate_feature_mask) - 1;
778
5060b915
YY
779 if (!xfeature_enabled(feature_nr)) {
780 WARN_ON_FPU(1);
781 return NULL;
782 }
783
b8b9b6ba
DH
784 return (void *)xsave + xstate_comp_offsets[feature_nr];
785}
7496d645
FY
786/*
787 * Given the xsave area and a state inside, this function returns the
788 * address of the state.
789 *
790 * This is the API that is called to get xstate address in either
791 * standard format or compacted format of xsave area.
792 *
0c4109be
DH
793 * Note that if there is no data for the field in the xsave buffer
794 * this will return NULL.
795 *
7496d645 796 * Inputs:
0c4109be
DH
797 * xstate: the thread's storage area for all FPU data
798 * xstate_feature: state which is defined in xsave.h (e.g.
d91cab78 799 * XFEATURE_MASK_FP, XFEATURE_MASK_SSE, etc...)
7496d645 800 * Output:
0c4109be
DH
801 * address of the state in the xsave area, or NULL if the
802 * field is not present in the xsave buffer.
7496d645 803 */
0c4109be 804void *get_xsave_addr(struct xregs_state *xsave, int xstate_feature)
7496d645 805{
0c4109be
DH
806 /*
807 * Do we even *have* xsave state?
808 */
809 if (!boot_cpu_has(X86_FEATURE_XSAVE))
810 return NULL;
811
0c4109be
DH
812 /*
813 * We should not ever be requesting features that we
814 * have not enabled. Remember that pcntxt_mask is
815 * what we write to the XCR0 register.
816 */
817 WARN_ONCE(!(xfeatures_mask & xstate_feature),
818 "get of unsupported state");
819 /*
820 * This assumes the last 'xsave*' instruction to
821 * have requested that 'xstate_feature' be saved.
822 * If it did not, we might be seeing and old value
823 * of the field in the buffer.
824 *
825 * This can happen because the last 'xsave' did not
826 * request that this feature be saved (unlikely)
827 * or because the "init optimization" caused it
828 * to not be saved.
829 */
830 if (!(xsave->header.xfeatures & xstate_feature))
7496d645
FY
831 return NULL;
832
b8b9b6ba 833 return __raw_xsave_addr(xsave, xstate_feature);
7496d645 834}
ba7b3920 835EXPORT_SYMBOL_GPL(get_xsave_addr);
04cd027b
DH
836
837/*
838 * This wraps up the common operations that need to occur when retrieving
839 * data from xsave state. It first ensures that the current task was
840 * using the FPU and retrieves the data in to a buffer. It then calculates
841 * the offset of the requested field in the buffer.
842 *
843 * This function is safe to call whether the FPU is in use or not.
844 *
845 * Note that this only works on the current task.
846 *
847 * Inputs:
d91cab78
DH
848 * @xsave_state: state which is defined in xsave.h (e.g. XFEATURE_MASK_FP,
849 * XFEATURE_MASK_SSE, etc...)
04cd027b
DH
850 * Output:
851 * address of the state in the xsave area or NULL if the state
852 * is not present or is in its 'init state'.
853 */
854const void *get_xsave_field_ptr(int xsave_state)
855{
856 struct fpu *fpu = &current->thread.fpu;
857
858 if (!fpu->fpstate_active)
859 return NULL;
860 /*
861 * fpu__save() takes the CPU's xstate registers
862 * and saves them off to the 'fpu memory buffer.
863 */
864 fpu__save(fpu);
865
866 return get_xsave_addr(&fpu->state.xsave, xsave_state);
867}
b8b9b6ba 868
84594296
DH
869#define NR_VALID_PKRU_BITS (CONFIG_NR_PROTECTION_KEYS * 2)
870#define PKRU_VALID_MASK (NR_VALID_PKRU_BITS - 1)
871
872/*
b79daf85
DH
873 * This will go out and modify PKRU register to set the access
874 * rights for @pkey to @init_val.
84594296
DH
875 */
876int arch_set_user_pkey_access(struct task_struct *tsk, int pkey,
877 unsigned long init_val)
878{
b79daf85 879 u32 old_pkru;
84594296
DH
880 int pkey_shift = (pkey * PKRU_BITS_PER_PKEY);
881 u32 new_pkru_bits = 0;
882
84594296
DH
883 /*
884 * This check implies XSAVE support. OSPKE only gets
885 * set if we enable XSAVE and we enable PKU in XCR0.
886 */
887 if (!boot_cpu_has(X86_FEATURE_OSPKE))
888 return -EINVAL;
b79daf85
DH
889 /*
890 * For most XSAVE components, this would be an arduous task:
891 * brining fpstate up to date with fpregs, updating fpstate,
892 * then re-populating fpregs. But, for components that are
893 * never lazily managed, we can just access the fpregs
894 * directly. PKRU is never managed lazily, so we can just
895 * manipulate it directly. Make sure it stays that way.
896 */
897 WARN_ON_ONCE(!use_eager_fpu());
84594296 898
91c3dba7 899 /* Set the bits we need in PKRU: */
84594296
DH
900 if (init_val & PKEY_DISABLE_ACCESS)
901 new_pkru_bits |= PKRU_AD_BIT;
902 if (init_val & PKEY_DISABLE_WRITE)
903 new_pkru_bits |= PKRU_WD_BIT;
904
91c3dba7 905 /* Shift the bits in to the correct place in PKRU for pkey: */
84594296
DH
906 new_pkru_bits <<= pkey_shift;
907
b79daf85
DH
908 /* Get old PKRU and mask off any old bits in place: */
909 old_pkru = read_pkru();
910 old_pkru &= ~((PKRU_AD_BIT|PKRU_WD_BIT) << pkey_shift);
84594296 911
b79daf85
DH
912 /* Write old part along with new part: */
913 write_pkru(old_pkru | new_pkru_bits);
91c3dba7
YY
914
915 return 0;
916}
917
918/*
919 * This is similar to user_regset_copyout(), but will not add offset to
920 * the source data pointer or increment pos, count, kbuf, and ubuf.
921 */
922static inline int xstate_copyout(unsigned int pos, unsigned int count,
923 void *kbuf, void __user *ubuf,
924 const void *data, const int start_pos,
925 const int end_pos)
926{
927 if ((count == 0) || (pos < start_pos))
928 return 0;
929
930 if (end_pos < 0 || pos < end_pos) {
931 unsigned int copy = (end_pos < 0 ? count : min(count, end_pos - pos));
932
933 if (kbuf) {
934 memcpy(kbuf + pos, data, copy);
935 } else {
936 if (__copy_to_user(ubuf + pos, data, copy))
937 return -EFAULT;
938 }
939 }
940 return 0;
941}
942
943/*
944 * Convert from kernel XSAVES compacted format to standard format and copy
945 * to a ptrace buffer. It supports partial copy but pos always starts from
946 * zero. This is called from xstateregs_get() and there we check the CPU
947 * has XSAVES.
948 */
949int copyout_from_xsaves(unsigned int pos, unsigned int count, void *kbuf,
950 void __user *ubuf, struct xregs_state *xsave)
951{
952 unsigned int offset, size;
953 int ret, i;
954 struct xstate_header header;
955
956 /*
957 * Currently copy_regset_to_user() starts from pos 0:
958 */
959 if (unlikely(pos != 0))
960 return -EFAULT;
961
962 /*
963 * The destination is a ptrace buffer; we put in only user xstates:
964 */
965 memset(&header, 0, sizeof(header));
966 header.xfeatures = xsave->header.xfeatures;
967 header.xfeatures &= ~XFEATURE_MASK_SUPERVISOR;
968
969 /*
970 * Copy xregs_state->header:
971 */
972 offset = offsetof(struct xregs_state, header);
973 size = sizeof(header);
974
975 ret = xstate_copyout(offset, size, kbuf, ubuf, &header, 0, count);
976
977 if (ret)
978 return ret;
979
980 for (i = 0; i < XFEATURE_MAX; i++) {
981 /*
982 * Copy only in-use xstates:
983 */
984 if ((header.xfeatures >> i) & 1) {
985 void *src = __raw_xsave_addr(xsave, 1 << i);
986
987 offset = xstate_offsets[i];
988 size = xstate_sizes[i];
989
990 ret = xstate_copyout(offset, size, kbuf, ubuf, src, 0, count);
991
992 if (ret)
993 return ret;
994
995 if (offset + size >= count)
996 break;
997 }
998
999 }
1000
1001 /*
1002 * Fill xsave->i387.sw_reserved value for ptrace frame:
1003 */
1004 offset = offsetof(struct fxregs_state, sw_reserved);
1005 size = sizeof(xstate_fx_sw_bytes);
1006
1007 ret = xstate_copyout(offset, size, kbuf, ubuf, xstate_fx_sw_bytes, 0, count);
1008
1009 if (ret)
1010 return ret;
1011
1012 return 0;
1013}
1014
1015/*
1016 * Convert from a ptrace standard-format buffer to kernel XSAVES format
1017 * and copy to the target thread. This is called from xstateregs_set() and
1018 * there we check the CPU has XSAVES and a whole standard-sized buffer
1019 * exists.
1020 */
1021int copyin_to_xsaves(const void *kbuf, const void __user *ubuf,
1022 struct xregs_state *xsave)
1023{
1024 unsigned int offset, size;
1025 int i;
1026 u64 xfeatures;
1027 u64 allowed_features;
1028
1029 offset = offsetof(struct xregs_state, header);
1030 size = sizeof(xfeatures);
1031
1032 if (kbuf) {
1033 memcpy(&xfeatures, kbuf + offset, size);
1034 } else {
1035 if (__copy_from_user(&xfeatures, ubuf + offset, size))
1036 return -EFAULT;
1037 }
1038
1039 /*
1040 * Reject if the user sets any disabled or supervisor features:
1041 */
1042 allowed_features = xfeatures_mask & ~XFEATURE_MASK_SUPERVISOR;
1043
1044 if (xfeatures & ~allowed_features)
1045 return -EINVAL;
1046
1047 for (i = 0; i < XFEATURE_MAX; i++) {
1048 u64 mask = ((u64)1 << i);
1049
1050 if (xfeatures & mask) {
1051 void *dst = __raw_xsave_addr(xsave, 1 << i);
1052
1053 offset = xstate_offsets[i];
1054 size = xstate_sizes[i];
1055
1056 if (kbuf) {
1057 memcpy(dst, kbuf + offset, size);
1058 } else {
1059 if (__copy_from_user(dst, ubuf + offset, size))
1060 return -EFAULT;
1061 }
1062 }
1063 }
1064
1065 /*
1066 * The state that came in from userspace was user-state only.
1067 * Mask all the user states out of 'xfeatures':
1068 */
1069 xsave->header.xfeatures &= XFEATURE_MASK_SUPERVISOR;
1070
1071 /*
1072 * Add back in the features that came in from userspace:
1073 */
1074 xsave->header.xfeatures |= xfeatures;
84594296
DH
1075
1076 return 0;
1077}