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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
7 *
9f5314fb 8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
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9 */
10
83f5d894 11#include <linux/kernel.h>
ac23d4ee 12#include <linux/threads.h>
7f1baa06 13#include <linux/cpu.h>
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14#include <linux/cpumask.h>
15#include <linux/string.h>
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16#include <linux/ctype.h>
17#include <linux/init.h>
18#include <linux/sched.h>
ac23d4ee 19#include <linux/module.h>
0c81c746 20#include <linux/hardirq.h>
7f1baa06 21#include <linux/timer.h>
a3d732f9 22#include <linux/proc_fs.h>
7f1baa06 23#include <asm/current.h>
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24#include <asm/smp.h>
25#include <asm/ipi.h>
26#include <asm/genapic.h>
83f5d894 27#include <asm/pgtable.h>
bdbcdd48 28#include <asm/uv/uv.h>
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29#include <asm/uv/uv_mmrs.h>
30#include <asm/uv/uv_hub.h>
7019cc2d 31#include <asm/uv/bios.h>
ac23d4ee 32
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33DEFINE_PER_CPU(int, x2apic_extra_bits);
34
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35static enum uv_system_type uv_system_type;
36
f8827c01 37static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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38{
39 if (!strcmp(oem_id, "SGI")) {
40 if (!strcmp(oem_table_id, "UVL"))
41 uv_system_type = UV_LEGACY_APIC;
42 else if (!strcmp(oem_table_id, "UVX"))
43 uv_system_type = UV_X2APIC;
44 else if (!strcmp(oem_table_id, "UVH")) {
45 uv_system_type = UV_NON_UNIQUE_APIC;
46 return 1;
47 }
48 }
49 return 0;
50}
51
52enum uv_system_type get_uv_system_type(void)
53{
54 return uv_system_type;
55}
56
57int is_uv_system(void)
58{
59 return uv_system_type != UV_NONE;
60}
8067794b 61EXPORT_SYMBOL_GPL(is_uv_system);
1b9b89e7 62
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63DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
64EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
65
66struct uv_blade_info *uv_blade_info;
67EXPORT_SYMBOL_GPL(uv_blade_info);
68
69short *uv_node_to_blade;
70EXPORT_SYMBOL_GPL(uv_node_to_blade);
71
72short *uv_cpu_to_blade;
73EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
74
75short uv_possible_blades;
76EXPORT_SYMBOL_GPL(uv_possible_blades);
77
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78unsigned long sn_rtc_cycles_per_second;
79EXPORT_SYMBOL(sn_rtc_cycles_per_second);
80
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81/* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
82
bcda016e 83static const struct cpumask *uv_target_cpus(void)
ac23d4ee 84{
bcda016e 85 return cpumask_of(0);
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86}
87
bcda016e 88static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
ac23d4ee 89{
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90 cpumask_clear(retmask);
91 cpumask_set_cpu(cpu, retmask);
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92}
93
94int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip)
95{
96 unsigned long val;
9f5314fb 97 int pnode;
ac23d4ee 98
9f5314fb 99 pnode = uv_apicid_to_pnode(phys_apicid);
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100 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
101 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
102 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
34d05591 103 APIC_DM_INIT;
9f5314fb 104 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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105 mdelay(10);
106
107 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
108 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
109 (((long)start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
110 APIC_DM_STARTUP;
9f5314fb 111 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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112 return 0;
113}
114
115static void uv_send_IPI_one(int cpu, int vector)
116{
34d05591 117 unsigned long val, apicid, lapicid;
9f5314fb 118 int pnode;
ac23d4ee 119
1e0b5d00 120 apicid = per_cpu(x86_cpu_to_apicid, cpu);
34d05591 121 lapicid = apicid & 0x3f; /* ZZZ macro needed */
9f5314fb 122 pnode = uv_apicid_to_pnode(apicid);
ac23d4ee 123 val =
34d05591 124 (1UL << UVH_IPI_INT_SEND_SHFT) | (lapicid <<
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125 UVH_IPI_INT_APIC_ID_SHFT) |
126 (vector << UVH_IPI_INT_VECTOR_SHFT);
9f5314fb 127 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
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128}
129
bcda016e 130static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
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131{
132 unsigned int cpu;
133
bcda016e 134 for_each_cpu(cpu, mask)
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135 uv_send_IPI_one(cpu, vector);
136}
137
bcda016e 138static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
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139{
140 unsigned int cpu;
141 unsigned int this_cpu = smp_processor_id();
142
bcda016e 143 for_each_cpu(cpu, mask)
e7986739 144 if (cpu != this_cpu)
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145 uv_send_IPI_one(cpu, vector);
146}
147
148static void uv_send_IPI_allbutself(int vector)
149{
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150 unsigned int cpu;
151 unsigned int this_cpu = smp_processor_id();
ac23d4ee 152
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153 for_each_online_cpu(cpu)
154 if (cpu != this_cpu)
155 uv_send_IPI_one(cpu, vector);
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156}
157
158static void uv_send_IPI_all(int vector)
159{
bcda016e 160 uv_send_IPI_mask(cpu_online_mask, vector);
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161}
162
163static int uv_apic_id_registered(void)
164{
165 return 1;
166}
167
277d1f58 168static void uv_init_apic_ldr(void)
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169{
170}
171
bcda016e 172static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
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173{
174 int cpu;
175
176 /*
177 * We're using fixed IRQ delivery, can only return one phys APIC ID.
178 * May as well be the first.
179 */
bcda016e 180 cpu = cpumask_first(cpumask);
247bc6ca 181 if ((unsigned)cpu < nr_cpu_ids)
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182 return per_cpu(x86_cpu_to_apicid, cpu);
183 else
184 return BAD_APICID;
185}
186
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187static unsigned int uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
188 const struct cpumask *andmask)
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189{
190 int cpu;
191
192 /*
193 * We're using fixed IRQ delivery, can only return one phys APIC ID.
194 * May as well be the first.
195 */
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196 for_each_cpu_and(cpu, cpumask, andmask)
197 if (cpumask_test_cpu(cpu, cpu_online_mask))
198 break;
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199 if (cpu < nr_cpu_ids)
200 return per_cpu(x86_cpu_to_apicid, cpu);
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201 return BAD_APICID;
202}
203
f910a9dc 204static unsigned int get_apic_id(unsigned long x)
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205{
206 unsigned int id;
207
208 WARN_ON(preemptible() && num_online_cpus() > 1);
f910a9dc 209 id = x | __get_cpu_var(x2apic_extra_bits);
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210
211 return id;
212}
213
1b9b89e7 214static unsigned long set_apic_id(unsigned int id)
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215{
216 unsigned long x;
217
218 /* maskout x2apic_extra_bits ? */
219 x = id;
220 return x;
221}
222
223static unsigned int uv_read_apic_id(void)
224{
225
226 return get_apic_id(apic_read(APIC_ID));
227}
228
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229static unsigned int phys_pkg_id(int index_msb)
230{
0c81c746 231 return uv_read_apic_id() >> index_msb;
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232}
233
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234static void uv_send_IPI_self(int vector)
235{
236 apic_write(APIC_SELF_IPI, vector);
237}
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238
239struct genapic apic_x2apic_uv_x = {
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240
241 .name = "UV large system",
242 .probe = NULL,
243 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
244 .apic_id_registered = uv_apic_id_registered,
245
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246 .irq_delivery_mode = dest_Fixed,
247 .irq_dest_mode = (APIC_DEST_PHYSICAL != 0),
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248
249 .target_cpus = uv_target_cpus,
250 .ESR_DISABLE = 0,
251 .apic_destination_logical = 0,
252 .check_apicid_used = NULL,
253 .check_apicid_present = NULL,
254
255 .no_balance_irq = 0,
256 .no_ioapic_check = 0,
257
258 .vector_allocation_domain = uv_vector_allocation_domain,
259 .init_apic_ldr = uv_init_apic_ldr,
260
261 .ioapic_phys_id_map = NULL,
262 .setup_apic_routing = NULL,
263 .multi_timer_check = NULL,
264 .apicid_to_node = NULL,
265 .cpu_to_logical_apicid = NULL,
266 .cpu_present_to_apicid = NULL,
267 .apicid_to_cpu_present = NULL,
268 .setup_portio_remap = NULL,
269 .check_phys_apicid_present = NULL,
270 .enable_apic_mode = NULL,
271 .phys_pkg_id = phys_pkg_id,
272 .mps_oem_check = NULL,
273
274 .get_apic_id = get_apic_id,
275 .set_apic_id = set_apic_id,
276 .apic_id_mask = 0xFFFFFFFFu,
277
278 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid,
279 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and,
280
281 .send_IPI_mask = uv_send_IPI_mask,
282 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
283 .send_IPI_allbutself = uv_send_IPI_allbutself,
284 .send_IPI_all = uv_send_IPI_all,
285 .send_IPI_self = uv_send_IPI_self,
286
287 .wakeup_cpu = NULL,
288 .trampoline_phys_low = 0,
289 .trampoline_phys_high = 0,
290 .wait_for_init_deassert = NULL,
291 .smp_callin_clear_local_apic = NULL,
292 .store_NMI_vector = NULL,
293 .restore_NMI_vector = NULL,
294 .inquire_remote_apic = NULL,
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295};
296
9f5314fb 297static __cpuinit void set_x2apic_extra_bits(int pnode)
ac23d4ee 298{
9f5314fb 299 __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
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300}
301
302/*
303 * Called on boot cpu.
304 */
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305static __init int boot_pnode_to_blade(int pnode)
306{
307 int blade;
308
309 for (blade = 0; blade < uv_num_possible_blades(); blade++)
310 if (pnode == uv_blade_info[blade].pnode)
311 return blade;
312 BUG();
313}
314
315struct redir_addr {
316 unsigned long redirect;
317 unsigned long alias;
318};
319
320#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
321
322static __initdata struct redir_addr redir_addrs[] = {
323 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
324 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
325 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
326};
327
328static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
329{
330 union uvh_si_alias0_overlay_config_u alias;
331 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
332 int i;
333
334 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
335 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
336 if (alias.s.base == 0) {
337 *size = (1UL << alias.s.m_alias);
338 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
339 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
340 return;
341 }
342 }
343 BUG();
344}
345
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346static __init void map_low_mmrs(void)
347{
348 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
349 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
350}
351
352enum map_type {map_wb, map_uc};
353
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354static __init void map_high(char *id, unsigned long base, int shift,
355 int max_pnode, enum map_type map_type)
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356{
357 unsigned long bytes, paddr;
358
359 paddr = base << shift;
d2f904bb 360 bytes = (1UL << shift) * (max_pnode + 1);
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361 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
362 paddr + bytes);
363 if (map_type == map_uc)
364 init_extra_mapping_uc(paddr, bytes);
365 else
366 init_extra_mapping_wb(paddr, bytes);
367
368}
369static __init void map_gru_high(int max_pnode)
370{
371 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
372 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
373
374 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
375 if (gru.s.enable)
d2f904bb 376 map_high("GRU", gru.s.base, shift, max_pnode, map_wb);
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377}
378
379static __init void map_config_high(int max_pnode)
380{
381 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg;
382 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT;
383
384 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR);
385 if (cfg.s.enable)
d2f904bb 386 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc);
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387}
388
389static __init void map_mmr_high(int max_pnode)
390{
391 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
392 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
393
394 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
395 if (mmr.s.enable)
d2f904bb 396 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc);
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397}
398
399static __init void map_mmioh_high(int max_pnode)
400{
401 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
402 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
403
404 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
405 if (mmioh.s.enable)
d2f904bb 406 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc);
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407}
408
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409static __init void uv_rtc_init(void)
410{
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411 long status;
412 u64 ticks_per_sec;
7019cc2d 413
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414 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
415 &ticks_per_sec);
416 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
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417 printk(KERN_WARNING
418 "unable to determine platform RTC clock frequency, "
419 "guessing.\n");
420 /* BIOS gives wrong value for clock freq. so guess */
421 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
422 } else
423 sn_rtc_cycles_per_second = ticks_per_sec;
424}
425
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426/*
427 * percpu heartbeat timer
428 */
429static void uv_heartbeat(unsigned long ignored)
430{
431 struct timer_list *timer = &uv_hub_info->scir.timer;
432 unsigned char bits = uv_hub_info->scir.state;
433
434 /* flip heartbeat bit */
435 bits ^= SCIR_CPU_HEARTBEAT;
436
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437 /* is this cpu idle? */
438 if (idle_cpu(raw_smp_processor_id()))
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439 bits &= ~SCIR_CPU_ACTIVITY;
440 else
441 bits |= SCIR_CPU_ACTIVITY;
442
443 /* update system controller interface reg */
444 uv_set_scir_bits(bits);
445
446 /* enable next timer period */
447 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
448}
449
450static void __cpuinit uv_heartbeat_enable(int cpu)
451{
452 if (!uv_cpu_hub_info(cpu)->scir.enabled) {
453 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
454
455 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
456 setup_timer(timer, uv_heartbeat, cpu);
457 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
458 add_timer_on(timer, cpu);
459 uv_cpu_hub_info(cpu)->scir.enabled = 1;
460 }
461
462 /* check boot cpu */
463 if (!uv_cpu_hub_info(0)->scir.enabled)
464 uv_heartbeat_enable(0);
465}
466
77be80e4 467#ifdef CONFIG_HOTPLUG_CPU
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468static void __cpuinit uv_heartbeat_disable(int cpu)
469{
470 if (uv_cpu_hub_info(cpu)->scir.enabled) {
471 uv_cpu_hub_info(cpu)->scir.enabled = 0;
472 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
473 }
474 uv_set_cpu_scir_bits(cpu, 0xff);
475}
476
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477/*
478 * cpu hotplug notifier
479 */
480static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
481 unsigned long action, void *hcpu)
482{
483 long cpu = (long)hcpu;
484
485 switch (action) {
486 case CPU_ONLINE:
487 uv_heartbeat_enable(cpu);
488 break;
489 case CPU_DOWN_PREPARE:
490 uv_heartbeat_disable(cpu);
491 break;
492 default:
493 break;
494 }
495 return NOTIFY_OK;
496}
497
498static __init void uv_scir_register_cpu_notifier(void)
499{
500 hotcpu_notifier(uv_scir_cpu_notify, 0);
501}
502
503#else /* !CONFIG_HOTPLUG_CPU */
504
505static __init void uv_scir_register_cpu_notifier(void)
506{
507}
508
509static __init int uv_init_heartbeat(void)
510{
511 int cpu;
512
513 if (is_uv_system())
514 for_each_online_cpu(cpu)
515 uv_heartbeat_enable(cpu);
516 return 0;
517}
518
519late_initcall(uv_init_heartbeat);
520
521#endif /* !CONFIG_HOTPLUG_CPU */
522
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523/*
524 * Called on each cpu to initialize the per_cpu UV data area.
525 * ZZZ hotplug not supported yet
526 */
527void __cpuinit uv_cpu_init(void)
528{
529 /* CPU 0 initilization will be done via uv_system_init. */
530 if (!uv_blade_info)
531 return;
532
533 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
534
535 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
536 set_x2apic_extra_bits(uv_hub_info->pnode);
537}
538
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539
540void __init uv_system_init(void)
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541{
542 union uvh_si_addr_map_config_u m_n_config;
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543 union uvh_node_id_u node_id;
544 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
545 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
83f5d894 546 int max_pnode = 0;
9f5314fb 547 unsigned long mmr_base, present;
ac23d4ee 548
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549 map_low_mmrs();
550
ac23d4ee 551 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
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552 m_val = m_n_config.s.m_skt;
553 n_val = m_n_config.s.n_skt;
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554 mmr_base =
555 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
556 ~UV_MMR_ENABLE;
557 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
558
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559 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
560 uv_possible_blades +=
561 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
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562 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
563
564 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
ef020ab0 565 uv_blade_info = kmalloc(bytes, GFP_KERNEL);
ac23d4ee 566
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567 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
568
ac23d4ee 569 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
ef020ab0 570 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
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571 memset(uv_node_to_blade, 255, bytes);
572
573 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
ef020ab0 574 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
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575 memset(uv_cpu_to_blade, 255, bytes);
576
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577 blade = 0;
578 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
579 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
580 for (j = 0; j < 64; j++) {
581 if (!test_bit(j, &present))
582 continue;
583 uv_blade_info[blade].pnode = (i * 64 + j);
584 uv_blade_info[blade].nr_possible_cpus = 0;
ac23d4ee 585 uv_blade_info[blade].nr_online_cpus = 0;
9f5314fb 586 blade++;
ac23d4ee 587 }
9f5314fb 588 }
ac23d4ee 589
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590 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
591 gnode_upper = (((unsigned long)node_id.s.node_id) &
592 ~((1 << n_val) - 1)) << m_val;
593
7f594232 594 uv_bios_init();
922402f1 595 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
b0f20989 596 &sn_coherency_id, &sn_region_size);
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597 uv_rtc_init();
598
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599 for_each_present_cpu(cpu) {
600 nid = cpu_to_node(cpu);
601 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu));
602 blade = boot_pnode_to_blade(pnode);
603 lcpu = uv_blade_info[blade].nr_possible_cpus;
604 uv_blade_info[blade].nr_possible_cpus++;
605
606 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
189f67c4 607 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
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608 uv_cpu_hub_info(cpu)->m_val = m_val;
609 uv_cpu_hub_info(cpu)->n_val = m_val;
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610 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
611 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
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612 uv_cpu_hub_info(cpu)->pnode = pnode;
613 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) - 1;
614 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
615 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
ac23d4ee 616 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
b0f20989 617 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
7f1baa06 618 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu;
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619 uv_node_to_blade[nid] = blade;
620 uv_cpu_to_blade[cpu] = blade;
83f5d894 621 max_pnode = max(pnode, max_pnode);
ac23d4ee 622
83f5d894 623 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
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624 "lcpu %d, blade %d\n",
625 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid,
626 lcpu, blade);
ac23d4ee 627 }
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628
629 map_gru_high(max_pnode);
630 map_mmr_high(max_pnode);
631 map_config_high(max_pnode);
632 map_mmioh_high(max_pnode);
ac23d4ee 633
8da077d6 634 uv_cpu_init();
7f1baa06 635 uv_scir_register_cpu_notifier();
a3d732f9 636 proc_mkdir("sgi_uv", NULL);
ac23d4ee 637}