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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
5b171e82 | 3 | * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
7 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
8 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1ab60e0f | 9 | * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> |
1da177e4 LT |
10 | */ |
11 | ||
12 | ||
13 | #include <linux/linkage.h> | |
14 | #include <linux/threads.h> | |
f6c2e333 | 15 | #include <linux/init.h> |
1da177e4 | 16 | #include <asm/segment.h> |
67dcbb6b | 17 | #include <asm/pgtable.h> |
1da177e4 LT |
18 | #include <asm/page.h> |
19 | #include <asm/msr.h> | |
20 | #include <asm/cache.h> | |
369101da | 21 | #include <asm/processor-flags.h> |
b12d8db8 | 22 | #include <asm/percpu.h> |
9900aa2f | 23 | #include <asm/nops.h> |
7bbcdb1c | 24 | #include "../entry/calling.h" |
784d5699 | 25 | #include <asm/export.h> |
1ab60e0f | 26 | |
49a69787 GOC |
27 | #ifdef CONFIG_PARAVIRT |
28 | #include <asm/asm-offsets.h> | |
29 | #include <asm/paravirt.h> | |
ffc4bc9c | 30 | #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg |
49a69787 | 31 | #else |
ffc4bc9c | 32 | #define GET_CR2_INTO(reg) movq %cr2, reg |
9900aa2f | 33 | #define INTERRUPT_RETURN iretq |
49a69787 GOC |
34 | #endif |
35 | ||
3ad2f3fb | 36 | /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE |
1ab60e0f VG |
37 | * because we need identity-mapped pages. |
38 | * | |
1da177e4 LT |
39 | */ |
40 | ||
a6523748 EH |
41 | #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
42 | ||
4375c299 | 43 | #if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH) |
032370b9 KS |
44 | PGD_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE) |
45 | PGD_START_KERNEL = pgd_index(__START_KERNEL_map) | |
4375c299 | 46 | #endif |
a6523748 EH |
47 | L3_START_KERNEL = pud_index(__START_KERNEL_map) |
48 | ||
1da177e4 | 49 | .text |
4ae59b91 | 50 | __HEAD |
1ab60e0f VG |
51 | .code64 |
52 | .globl startup_64 | |
53 | startup_64: | |
2704fbb6 | 54 | UNWIND_HINT_EMPTY |
1da177e4 | 55 | /* |
1256276c | 56 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
57 | * and someone has loaded an identity mapped page table |
58 | * for us. These identity mapped page tables map all of the | |
59 | * kernel pages and possibly all of memory. | |
60 | * | |
8170e6be | 61 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
62 | * |
63 | * We come here either directly from a 64bit bootloader, or from | |
5b171e82 | 64 | * arch/x86/boot/compressed/head_64.S. |
1ab60e0f VG |
65 | * |
66 | * We only come here initially at boot nothing else comes here. | |
67 | * | |
68 | * Since we may be loaded at an address different from what we were | |
69 | * compiled to run at we first fixup the physical addresses in our page | |
70 | * tables and then reload them. | |
1da177e4 LT |
71 | */ |
72 | ||
22dc3918 JP |
73 | /* Set up the stack for verify_cpu(), similar to initial_stack below */ |
74 | leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp | |
91ed140d | 75 | |
04633df0 BP |
76 | /* Sanitize CPU configuration */ |
77 | call verify_cpu | |
78 | ||
5868f365 TL |
79 | /* |
80 | * Perform pagetable fixups. Additionally, if SME is active, encrypt | |
81 | * the kernel and retrieve the modifier (SME encryption mask if SME | |
82 | * is active) to be added to the initial pgdir entry that will be | |
83 | * programmed into CR3. | |
84 | */ | |
1ab60e0f | 85 | leaq _text(%rip), %rdi |
c88d7150 KS |
86 | pushq %rsi |
87 | call __startup_64 | |
88 | popq %rsi | |
1da177e4 | 89 | |
5868f365 TL |
90 | /* Form the CR3 value being sure to include the CR3 modifier */ |
91 | addq $(early_top_pgt - __START_KERNEL_map), %rax | |
8170e6be | 92 | jmp 1f |
90b1c208 | 93 | ENTRY(secondary_startup_64) |
2704fbb6 | 94 | UNWIND_HINT_EMPTY |
1ab60e0f | 95 | /* |
1256276c | 96 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
97 | * and someone has loaded a mapped page table. |
98 | * | |
8170e6be | 99 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
100 | * |
101 | * We come here either from startup_64 (using physical addresses) | |
102 | * or from trampoline.S (using virtual addresses). | |
103 | * | |
104 | * Using virtual addresses from trampoline.S removes the need | |
105 | * to have any identity mapped pages in the kernel page table | |
106 | * after the boot processor executes this code. | |
1da177e4 LT |
107 | */ |
108 | ||
04633df0 BP |
109 | /* Sanitize CPU configuration */ |
110 | call verify_cpu | |
111 | ||
5868f365 TL |
112 | /* |
113 | * Retrieve the modifier (SME encryption mask if SME is active) to be | |
114 | * added to the initial pgdir entry that will be programmed into CR3. | |
115 | */ | |
116 | pushq %rsi | |
117 | call __startup_secondary_64 | |
118 | popq %rsi | |
119 | ||
120 | /* Form the CR3 value being sure to include the CR3 modifier */ | |
121 | addq $(init_top_pgt - __START_KERNEL_map), %rax | |
8170e6be PA |
122 | 1: |
123 | ||
032370b9 | 124 | /* Enable PAE mode, PGE and LA57 */ |
8170e6be | 125 | movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx |
032370b9 KS |
126 | #ifdef CONFIG_X86_5LEVEL |
127 | orl $X86_CR4_LA57, %ecx | |
128 | #endif | |
8170e6be | 129 | movq %rcx, %cr4 |
1da177e4 | 130 | |
032370b9 | 131 | /* Setup early boot stage 4-/5-level pagetables. */ |
1ab60e0f | 132 | addq phys_base(%rip), %rax |
1da177e4 LT |
133 | movq %rax, %cr3 |
134 | ||
1ab60e0f VG |
135 | /* Ensure I am executing from virtual addresses */ |
136 | movq $1f, %rax | |
137 | jmp *%rax | |
138 | 1: | |
2704fbb6 | 139 | UNWIND_HINT_EMPTY |
1ab60e0f | 140 | |
1da177e4 LT |
141 | /* Check if nx is implemented */ |
142 | movl $0x80000001, %eax | |
143 | cpuid | |
144 | movl %edx,%edi | |
145 | ||
146 | /* Setup EFER (Extended Feature Enable Register) */ | |
147 | movl $MSR_EFER, %ecx | |
148 | rdmsr | |
1ab60e0f VG |
149 | btsl $_EFER_SCE, %eax /* Enable System Call */ |
150 | btl $20,%edi /* No Execute supported? */ | |
1da177e4 LT |
151 | jnc 1f |
152 | btsl $_EFER_NX, %eax | |
78d77df7 | 153 | btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) |
1ab60e0f | 154 | 1: wrmsr /* Make changes effective */ |
1da177e4 LT |
155 | |
156 | /* Setup cr0 */ | |
369101da | 157 | movl $CR0_STATE, %eax |
1da177e4 LT |
158 | /* Make changes effective */ |
159 | movq %rax, %cr0 | |
160 | ||
161 | /* Setup a boot time stack */ | |
b32f96c7 | 162 | movq initial_stack(%rip), %rsp |
1da177e4 LT |
163 | |
164 | /* zero EFLAGS after setting rsp */ | |
165 | pushq $0 | |
166 | popfq | |
167 | ||
168 | /* | |
169 | * We must switch to a new descriptor in kernel space for the GDT | |
170 | * because soon the kernel won't have access anymore to the userspace | |
171 | * addresses where we're currently running on. We have to do that here | |
172 | * because in 32bit we couldn't load a 64bit linear address. | |
173 | */ | |
a939098a | 174 | lgdt early_gdt_descr(%rip) |
1da177e4 | 175 | |
8ec6993d BG |
176 | /* set up data segments */ |
177 | xorl %eax,%eax | |
ffb60175 ZA |
178 | movl %eax,%ds |
179 | movl %eax,%ss | |
180 | movl %eax,%es | |
181 | ||
182 | /* | |
183 | * We don't really need to load %fs or %gs, but load them anyway | |
184 | * to kill any stale realmode selectors. This allows execution | |
185 | * under VT hardware. | |
186 | */ | |
187 | movl %eax,%fs | |
188 | movl %eax,%gs | |
189 | ||
f32ff538 TH |
190 | /* Set up %gs. |
191 | * | |
947e76cd BG |
192 | * The base of %gs always points to the bottom of the irqstack |
193 | * union. If the stack protector canary is enabled, it is | |
194 | * located at %gs:40. Note that, on SMP, the boot cpu uses | |
195 | * init data section till per cpu areas are set up. | |
f32ff538 | 196 | */ |
1da177e4 | 197 | movl $MSR_GS_BASE,%ecx |
650fb439 BG |
198 | movl initial_gs(%rip),%eax |
199 | movl initial_gs+4(%rip),%edx | |
a9468df5 | 200 | wrmsr |
1da177e4 | 201 | |
8170e6be | 202 | /* rsi is pointer to real mode structure with interesting info. |
1da177e4 | 203 | pass it to C */ |
8170e6be | 204 | movq %rsi, %rdi |
a9468df5 | 205 | |
79d243a0 | 206 | .Ljump_to_C_code: |
a9468df5 JP |
207 | /* |
208 | * Jump to run C code and to be on a real kernel address. | |
1da177e4 | 209 | * Since we are running on identity-mapped space we have to jump |
26374c7b EB |
210 | * to the full 64bit address, this is only possible as indirect |
211 | * jump. In addition we need to ensure %cs is set so we make this | |
212 | * a far return. | |
8170e6be PA |
213 | * |
214 | * Note: do not change to far jump indirect with 64bit offset. | |
215 | * | |
216 | * AMD does not support far jump indirect with 64bit offset. | |
217 | * AMD64 Architecture Programmer's Manual, Volume 3: states only | |
218 | * JMP FAR mem16:16 FF /5 Far jump indirect, | |
219 | * with the target specified by a far pointer in memory. | |
220 | * JMP FAR mem16:32 FF /5 Far jump indirect, | |
221 | * with the target specified by a far pointer in memory. | |
222 | * | |
223 | * Intel64 does support 64bit offset. | |
224 | * Software Developer Manual Vol 2: states: | |
225 | * FF /5 JMP m16:16 Jump far, absolute indirect, | |
226 | * address given in m16:16 | |
227 | * FF /5 JMP m16:32 Jump far, absolute indirect, | |
228 | * address given in m16:32. | |
229 | * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, | |
230 | * address given in m16:64. | |
1da177e4 | 231 | */ |
31dcfec1 JP |
232 | pushq $.Lafter_lret # put return address on stack for unwinder |
233 | xorq %rbp, %rbp # clear frame pointer | |
595c1e64 | 234 | movq initial_code(%rip), %rax |
26374c7b EB |
235 | pushq $__KERNEL_CS # set correct cs |
236 | pushq %rax # target address in negative space | |
237 | lretq | |
31dcfec1 | 238 | .Lafter_lret: |
015a2ea5 | 239 | END(secondary_startup_64) |
1da177e4 | 240 | |
04633df0 BP |
241 | #include "verify_cpu.S" |
242 | ||
42e78e97 FY |
243 | #ifdef CONFIG_HOTPLUG_CPU |
244 | /* | |
245 | * Boot CPU0 entry point. It's called from play_dead(). Everything has been set | |
246 | * up already except stack. We just set up stack here. Then call | |
79d243a0 | 247 | * start_secondary() via .Ljump_to_C_code. |
42e78e97 FY |
248 | */ |
249 | ENTRY(start_cpu0) | |
a9468df5 | 250 | movq initial_stack(%rip), %rsp |
2704fbb6 | 251 | UNWIND_HINT_EMPTY |
79d243a0 | 252 | jmp .Ljump_to_C_code |
42e78e97 FY |
253 | ENDPROC(start_cpu0) |
254 | #endif | |
255 | ||
b32f96c7 | 256 | /* Both SMP bootup and ACPI suspend change these variables */ |
da5968ae | 257 | __REFDATA |
8170e6be PA |
258 | .balign 8 |
259 | GLOBAL(initial_code) | |
1da177e4 | 260 | .quad x86_64_start_kernel |
8170e6be | 261 | GLOBAL(initial_gs) |
2add8e23 | 262 | .quad INIT_PER_CPU_VAR(irq_stack_union) |
b32f96c7 | 263 | GLOBAL(initial_stack) |
22dc3918 JP |
264 | /* |
265 | * The SIZEOF_PTREGS gap is a convention which helps the in-kernel | |
266 | * unwinder reliably detect the end of the stack. | |
267 | */ | |
268 | .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS | |
b9af7c0d | 269 | __FINITDATA |
1da177e4 | 270 | |
8170e6be | 271 | __INIT |
cdeb6048 | 272 | ENTRY(early_idt_handler_array) |
749c970a AK |
273 | i = 0 |
274 | .rept NUM_EXCEPTION_VECTORS | |
82c62fa0 | 275 | .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 |
2704fbb6 JP |
276 | UNWIND_HINT_IRET_REGS |
277 | pushq $0 # Dummy error code, to make stack frame uniform | |
278 | .else | |
279 | UNWIND_HINT_IRET_REGS offset=8 | |
9900aa2f PA |
280 | .endif |
281 | pushq $i # 72(%rsp) Vector number | |
cdeb6048 | 282 | jmp early_idt_handler_common |
2704fbb6 | 283 | UNWIND_HINT_IRET_REGS |
749c970a | 284 | i = i + 1 |
cdeb6048 | 285 | .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc |
749c970a | 286 | .endr |
2704fbb6 | 287 | UNWIND_HINT_IRET_REGS offset=16 |
015a2ea5 | 288 | END(early_idt_handler_array) |
8866cd9d | 289 | |
cdeb6048 AL |
290 | early_idt_handler_common: |
291 | /* | |
292 | * The stack is the hardware frame, an error code or zero, and the | |
293 | * vector number. | |
294 | */ | |
9900aa2f PA |
295 | cld |
296 | ||
b957591f | 297 | incl early_recursion_flag(%rip) |
9900aa2f | 298 | |
7bbcdb1c AL |
299 | /* The vector number is currently in the pt_regs->di slot. */ |
300 | pushq %rsi /* pt_regs->si */ | |
301 | movq 8(%rsp), %rsi /* RSI = vector number */ | |
302 | movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ | |
303 | pushq %rdx /* pt_regs->dx */ | |
304 | pushq %rcx /* pt_regs->cx */ | |
305 | pushq %rax /* pt_regs->ax */ | |
306 | pushq %r8 /* pt_regs->r8 */ | |
307 | pushq %r9 /* pt_regs->r9 */ | |
308 | pushq %r10 /* pt_regs->r10 */ | |
309 | pushq %r11 /* pt_regs->r11 */ | |
310 | pushq %rbx /* pt_regs->bx */ | |
311 | pushq %rbp /* pt_regs->bp */ | |
312 | pushq %r12 /* pt_regs->r12 */ | |
313 | pushq %r13 /* pt_regs->r13 */ | |
314 | pushq %r14 /* pt_regs->r14 */ | |
315 | pushq %r15 /* pt_regs->r15 */ | |
2704fbb6 | 316 | UNWIND_HINT_REGS |
7bbcdb1c | 317 | |
7bbcdb1c | 318 | cmpq $14,%rsi /* Page fault? */ |
8170e6be | 319 | jnz 10f |
7bbcdb1c | 320 | GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ |
8170e6be PA |
321 | call early_make_pgtable |
322 | andl %eax,%eax | |
7bbcdb1c | 323 | jz 20f /* All good */ |
9900aa2f | 324 | |
8170e6be | 325 | 10: |
7bbcdb1c | 326 | movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ |
9900aa2f | 327 | call early_fixup_exception |
076f9776 | 328 | |
0e861fbb | 329 | 20: |
9900aa2f | 330 | decl early_recursion_flag(%rip) |
26c4ef9c | 331 | jmp restore_regs_and_return_to_kernel |
015a2ea5 | 332 | END(early_idt_handler_common) |
9900aa2f | 333 | |
8170e6be PA |
334 | __INITDATA |
335 | ||
9900aa2f | 336 | .balign 4 |
0e861fbb | 337 | GLOBAL(early_recursion_flag) |
b957591f | 338 | .long 0 |
1da177e4 | 339 | |
f0cf5d1a | 340 | #define NEXT_PAGE(name) \ |
67dcbb6b | 341 | .balign PAGE_SIZE; \ |
8170e6be | 342 | GLOBAL(name) |
f0cf5d1a | 343 | |
d9e9a641 DH |
344 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
345 | /* | |
346 | * Each PGD needs to be 8k long and 8k aligned. We do not | |
347 | * ever go out to userspace with these, so we do not | |
348 | * strictly *need* the second page, but this allows us to | |
349 | * have a single set_pgd() implementation that does not | |
350 | * need to worry about whether it has 4k or 8k to work | |
351 | * with. | |
352 | * | |
353 | * This ensures PGDs are 8k long: | |
354 | */ | |
355 | #define PTI_USER_PGD_FILL 512 | |
356 | /* This ensures they are 8k-aligned: */ | |
357 | #define NEXT_PGD_PAGE(name) \ | |
358 | .balign 2 * PAGE_SIZE; \ | |
359 | GLOBAL(name) | |
360 | #else | |
361 | #define NEXT_PGD_PAGE(name) NEXT_PAGE(name) | |
362 | #define PTI_USER_PGD_FILL 0 | |
363 | #endif | |
364 | ||
67dcbb6b | 365 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
0e192b99 CG |
366 | #define PMDS(START, PERM, COUNT) \ |
367 | i = 0 ; \ | |
368 | .rept (COUNT) ; \ | |
369 | .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ | |
370 | i = i + 1 ; \ | |
67dcbb6b VG |
371 | .endr |
372 | ||
8170e6be | 373 | __INITDATA |
d9e9a641 | 374 | NEXT_PGD_PAGE(early_top_pgt) |
8170e6be | 375 | .fill 511,8,0 |
032370b9 | 376 | #ifdef CONFIG_X86_5LEVEL |
21729f81 | 377 | .quad level4_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
032370b9 | 378 | #else |
21729f81 | 379 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
032370b9 | 380 | #endif |
d9e9a641 | 381 | .fill PTI_USER_PGD_FILL,8,0 |
8170e6be PA |
382 | |
383 | NEXT_PAGE(early_dynamic_pgts) | |
384 | .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 | |
385 | ||
b9af7c0d | 386 | .data |
8170e6be | 387 | |
4375c299 | 388 | #if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH) |
d9e9a641 | 389 | NEXT_PGD_PAGE(init_top_pgt) |
21729f81 | 390 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
032370b9 | 391 | .org init_top_pgt + PGD_PAGE_OFFSET*8, 0 |
21729f81 | 392 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
032370b9 | 393 | .org init_top_pgt + PGD_START_KERNEL*8, 0 |
cfd243d4 | 394 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ |
21729f81 | 395 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
d9e9a641 | 396 | .fill PTI_USER_PGD_FILL,8,0 |
1da177e4 | 397 | |
f0cf5d1a | 398 | NEXT_PAGE(level3_ident_pgt) |
21729f81 | 399 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
8170e6be PA |
400 | .fill 511, 8, 0 |
401 | NEXT_PAGE(level2_ident_pgt) | |
402 | /* Since I easily can, map the first 1G. | |
403 | * Don't set NX because code runs from these pages. | |
404 | */ | |
405 | PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) | |
4375c299 | 406 | #else |
d9e9a641 | 407 | NEXT_PGD_PAGE(init_top_pgt) |
4375c299 | 408 | .fill 512,8,0 |
d9e9a641 | 409 | .fill PTI_USER_PGD_FILL,8,0 |
8170e6be | 410 | #endif |
1da177e4 | 411 | |
032370b9 KS |
412 | #ifdef CONFIG_X86_5LEVEL |
413 | NEXT_PAGE(level4_kernel_pgt) | |
414 | .fill 511,8,0 | |
21729f81 | 415 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
032370b9 KS |
416 | #endif |
417 | ||
f0cf5d1a | 418 | NEXT_PAGE(level3_kernel_pgt) |
a6523748 | 419 | .fill L3_START_KERNEL,8,0 |
1da177e4 | 420 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ |
21729f81 TL |
421 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
422 | .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC | |
b1c931e3 | 423 | |
f0cf5d1a | 424 | NEXT_PAGE(level2_kernel_pgt) |
88f3aec7 | 425 | /* |
85eb69a1 | 426 | * 512 MB kernel mapping. We spend a full page on this pagetable |
88f3aec7 IM |
427 | * anyway. |
428 | * | |
429 | * The kernel code+data+bss must not be bigger than that. | |
430 | * | |
85eb69a1 | 431 | * (NOTE: at +512MB starts the module area, see MODULES_VADDR. |
88f3aec7 IM |
432 | * If you want to increase this then increase MODULES_VADDR |
433 | * too.) | |
434 | */ | |
8490638c | 435 | PMDS(0, __PAGE_KERNEL_LARGE_EXEC, |
d4afe414 | 436 | KERNEL_IMAGE_SIZE/PMD_SIZE) |
1da177e4 | 437 | |
8170e6be PA |
438 | NEXT_PAGE(level2_fixmap_pgt) |
439 | .fill 506,8,0 | |
21729f81 | 440 | .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
8170e6be PA |
441 | /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ |
442 | .fill 5,8,0 | |
443 | ||
444 | NEXT_PAGE(level1_fixmap_pgt) | |
445 | .fill 512,8,0 | |
1ab60e0f | 446 | |
67dcbb6b | 447 | #undef PMDS |
1da177e4 | 448 | |
f0cf5d1a | 449 | .data |
1da177e4 | 450 | .align 16 |
a939098a GC |
451 | .globl early_gdt_descr |
452 | early_gdt_descr: | |
453 | .word GDT_ENTRIES*8-1 | |
3e5d8f97 | 454 | early_gdt_descr_base: |
2add8e23 | 455 | .quad INIT_PER_CPU_VAR(gdt_page) |
1da177e4 | 456 | |
1ab60e0f VG |
457 | ENTRY(phys_base) |
458 | /* This must match the first entry in level2_kernel_pgt */ | |
459 | .quad 0x0000000000000000 | |
784d5699 | 460 | EXPORT_SYMBOL(phys_base) |
1ab60e0f | 461 | |
8c5e5ac3 | 462 | #include "../../x86/xen/xen-head.S" |
2704fbb6 | 463 | |
02b7da37 | 464 | __PAGE_ALIGNED_BSS |
8170e6be | 465 | NEXT_PAGE(empty_zero_page) |
e57113bc | 466 | .skip PAGE_SIZE |
784d5699 | 467 | EXPORT_SYMBOL(empty_zero_page) |
ef7f0d6a | 468 |