]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
5b171e82 | 2 | * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
5 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
6 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
7 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1ab60e0f | 8 | * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> |
1da177e4 LT |
9 | */ |
10 | ||
11 | ||
12 | #include <linux/linkage.h> | |
13 | #include <linux/threads.h> | |
f6c2e333 | 14 | #include <linux/init.h> |
1da177e4 | 15 | #include <asm/segment.h> |
67dcbb6b | 16 | #include <asm/pgtable.h> |
1da177e4 LT |
17 | #include <asm/page.h> |
18 | #include <asm/msr.h> | |
19 | #include <asm/cache.h> | |
369101da | 20 | #include <asm/processor-flags.h> |
b12d8db8 | 21 | #include <asm/percpu.h> |
9900aa2f | 22 | #include <asm/nops.h> |
7bbcdb1c | 23 | #include "../entry/calling.h" |
784d5699 | 24 | #include <asm/export.h> |
1ab60e0f | 25 | |
49a69787 GOC |
26 | #ifdef CONFIG_PARAVIRT |
27 | #include <asm/asm-offsets.h> | |
28 | #include <asm/paravirt.h> | |
ffc4bc9c | 29 | #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg |
49a69787 | 30 | #else |
ffc4bc9c | 31 | #define GET_CR2_INTO(reg) movq %cr2, reg |
9900aa2f | 32 | #define INTERRUPT_RETURN iretq |
49a69787 GOC |
33 | #endif |
34 | ||
3ad2f3fb | 35 | /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE |
1ab60e0f VG |
36 | * because we need identity-mapped pages. |
37 | * | |
1da177e4 LT |
38 | */ |
39 | ||
a6523748 EH |
40 | #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
41 | ||
021182e5 | 42 | L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE) |
a6523748 EH |
43 | L4_START_KERNEL = pgd_index(__START_KERNEL_map) |
44 | L3_START_KERNEL = pud_index(__START_KERNEL_map) | |
45 | ||
1da177e4 | 46 | .text |
4ae59b91 | 47 | __HEAD |
1ab60e0f VG |
48 | .code64 |
49 | .globl startup_64 | |
50 | startup_64: | |
1da177e4 | 51 | /* |
1256276c | 52 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
53 | * and someone has loaded an identity mapped page table |
54 | * for us. These identity mapped page tables map all of the | |
55 | * kernel pages and possibly all of memory. | |
56 | * | |
8170e6be | 57 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
58 | * |
59 | * We come here either directly from a 64bit bootloader, or from | |
5b171e82 | 60 | * arch/x86/boot/compressed/head_64.S. |
1ab60e0f VG |
61 | * |
62 | * We only come here initially at boot nothing else comes here. | |
63 | * | |
64 | * Since we may be loaded at an address different from what we were | |
65 | * compiled to run at we first fixup the physical addresses in our page | |
66 | * tables and then reload them. | |
1da177e4 LT |
67 | */ |
68 | ||
22dc3918 JP |
69 | /* Set up the stack for verify_cpu(), similar to initial_stack below */ |
70 | leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp | |
91ed140d | 71 | |
04633df0 BP |
72 | /* Sanitize CPU configuration */ |
73 | call verify_cpu | |
74 | ||
8170e6be PA |
75 | /* |
76 | * Compute the delta between the address I am compiled to run at and the | |
1ab60e0f | 77 | * address I am actually running at. |
1da177e4 | 78 | */ |
1ab60e0f VG |
79 | leaq _text(%rip), %rbp |
80 | subq $_text - __START_KERNEL_map, %rbp | |
81 | ||
82 | /* Is the address not 2M aligned? */ | |
a4733143 | 83 | testl $~PMD_PAGE_MASK, %ebp |
1ab60e0f VG |
84 | jnz bad_address |
85 | ||
8170e6be PA |
86 | /* |
87 | * Is the address too large? | |
1da177e4 | 88 | */ |
8170e6be PA |
89 | leaq _text(%rip), %rax |
90 | shrq $MAX_PHYSMEM_BITS, %rax | |
91 | jnz bad_address | |
1ab60e0f | 92 | |
8170e6be PA |
93 | /* |
94 | * Fixup the physical addresses in the page table | |
95 | */ | |
96 | addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip) | |
b1c931e3 | 97 | |
1ab60e0f | 98 | addq %rbp, level3_kernel_pgt + (510*8)(%rip) |
b1c931e3 EB |
99 | addq %rbp, level3_kernel_pgt + (511*8)(%rip) |
100 | ||
101 | addq %rbp, level2_fixmap_pgt + (506*8)(%rip) | |
1ab60e0f | 102 | |
8170e6be PA |
103 | /* |
104 | * Set up the identity mapping for the switchover. These | |
105 | * entries should *NOT* have the global bit set! This also | |
106 | * creates a bunch of nonsense entries but that is fine -- | |
107 | * it avoids problems around wraparound. | |
108 | */ | |
1ab60e0f | 109 | leaq _text(%rip), %rdi |
8170e6be | 110 | leaq early_level4_pgt(%rip), %rbx |
1ab60e0f VG |
111 | |
112 | movq %rdi, %rax | |
8170e6be | 113 | shrq $PGDIR_SHIFT, %rax |
1ab60e0f | 114 | |
9b032d21 | 115 | leaq (PAGE_SIZE + _KERNPG_TABLE)(%rbx), %rdx |
8170e6be PA |
116 | movq %rdx, 0(%rbx,%rax,8) |
117 | movq %rdx, 8(%rbx,%rax,8) | |
1ab60e0f | 118 | |
9b032d21 | 119 | addq $PAGE_SIZE, %rdx |
1ab60e0f | 120 | movq %rdi, %rax |
8170e6be PA |
121 | shrq $PUD_SHIFT, %rax |
122 | andl $(PTRS_PER_PUD-1), %eax | |
9b032d21 | 123 | movq %rdx, PAGE_SIZE(%rbx,%rax,8) |
e9d0626e ZY |
124 | incl %eax |
125 | andl $(PTRS_PER_PUD-1), %eax | |
9b032d21 | 126 | movq %rdx, PAGE_SIZE(%rbx,%rax,8) |
8170e6be | 127 | |
9b032d21 | 128 | addq $PAGE_SIZE * 2, %rbx |
8170e6be PA |
129 | movq %rdi, %rax |
130 | shrq $PMD_SHIFT, %rdi | |
131 | addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax | |
132 | leaq (_end - 1)(%rip), %rcx | |
133 | shrq $PMD_SHIFT, %rcx | |
134 | subq %rdi, %rcx | |
135 | incl %ecx | |
136 | ||
137 | 1: | |
138 | andq $(PTRS_PER_PMD - 1), %rdi | |
139 | movq %rax, (%rbx,%rdi,8) | |
140 | incq %rdi | |
141 | addq $PMD_SIZE, %rax | |
142 | decl %ecx | |
143 | jnz 1b | |
1ab60e0f | 144 | |
6248f456 BP |
145 | test %rbp, %rbp |
146 | jz .Lskip_fixup | |
147 | ||
31eedd82 TG |
148 | /* |
149 | * Fixup the kernel text+data virtual addresses. Note that | |
150 | * we might write invalid pmds, when the kernel is relocated | |
151 | * cleanup_highmap() fixes this up along with the mappings | |
152 | * beyond _end. | |
1ab60e0f VG |
153 | */ |
154 | leaq level2_kernel_pgt(%rip), %rdi | |
6248f456 | 155 | leaq PAGE_SIZE(%rdi), %r8 |
1ab60e0f | 156 | /* See if it is a valid page table entry */ |
6248f456 | 157 | 1: testb $_PAGE_PRESENT, 0(%rdi) |
1ab60e0f VG |
158 | jz 2f |
159 | addq %rbp, 0(%rdi) | |
160 | /* Go to the next page */ | |
161 | 2: addq $8, %rdi | |
162 | cmp %r8, %rdi | |
163 | jne 1b | |
164 | ||
165 | /* Fixup phys_base */ | |
166 | addq %rbp, phys_base(%rip) | |
1da177e4 | 167 | |
6248f456 | 168 | .Lskip_fixup: |
8170e6be PA |
169 | movq $(early_level4_pgt - __START_KERNEL_map), %rax |
170 | jmp 1f | |
90b1c208 | 171 | ENTRY(secondary_startup_64) |
1ab60e0f | 172 | /* |
1256276c | 173 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
174 | * and someone has loaded a mapped page table. |
175 | * | |
8170e6be | 176 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
177 | * |
178 | * We come here either from startup_64 (using physical addresses) | |
179 | * or from trampoline.S (using virtual addresses). | |
180 | * | |
181 | * Using virtual addresses from trampoline.S removes the need | |
182 | * to have any identity mapped pages in the kernel page table | |
183 | * after the boot processor executes this code. | |
1da177e4 LT |
184 | */ |
185 | ||
04633df0 BP |
186 | /* Sanitize CPU configuration */ |
187 | call verify_cpu | |
188 | ||
8170e6be PA |
189 | movq $(init_level4_pgt - __START_KERNEL_map), %rax |
190 | 1: | |
191 | ||
1da177e4 | 192 | /* Enable PAE mode and PGE */ |
8170e6be PA |
193 | movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx |
194 | movq %rcx, %cr4 | |
1da177e4 LT |
195 | |
196 | /* Setup early boot stage 4 level pagetables. */ | |
1ab60e0f | 197 | addq phys_base(%rip), %rax |
1da177e4 LT |
198 | movq %rax, %cr3 |
199 | ||
1ab60e0f VG |
200 | /* Ensure I am executing from virtual addresses */ |
201 | movq $1f, %rax | |
202 | jmp *%rax | |
203 | 1: | |
204 | ||
1da177e4 LT |
205 | /* Check if nx is implemented */ |
206 | movl $0x80000001, %eax | |
207 | cpuid | |
208 | movl %edx,%edi | |
209 | ||
210 | /* Setup EFER (Extended Feature Enable Register) */ | |
211 | movl $MSR_EFER, %ecx | |
212 | rdmsr | |
1ab60e0f VG |
213 | btsl $_EFER_SCE, %eax /* Enable System Call */ |
214 | btl $20,%edi /* No Execute supported? */ | |
1da177e4 LT |
215 | jnc 1f |
216 | btsl $_EFER_NX, %eax | |
78d77df7 | 217 | btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) |
1ab60e0f | 218 | 1: wrmsr /* Make changes effective */ |
1da177e4 LT |
219 | |
220 | /* Setup cr0 */ | |
369101da CG |
221 | #define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ |
222 | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ | |
223 | X86_CR0_PG) | |
224 | movl $CR0_STATE, %eax | |
1da177e4 LT |
225 | /* Make changes effective */ |
226 | movq %rax, %cr0 | |
227 | ||
228 | /* Setup a boot time stack */ | |
b32f96c7 | 229 | movq initial_stack(%rip), %rsp |
1da177e4 LT |
230 | |
231 | /* zero EFLAGS after setting rsp */ | |
232 | pushq $0 | |
233 | popfq | |
234 | ||
235 | /* | |
236 | * We must switch to a new descriptor in kernel space for the GDT | |
237 | * because soon the kernel won't have access anymore to the userspace | |
238 | * addresses where we're currently running on. We have to do that here | |
239 | * because in 32bit we couldn't load a 64bit linear address. | |
240 | */ | |
a939098a | 241 | lgdt early_gdt_descr(%rip) |
1da177e4 | 242 | |
8ec6993d BG |
243 | /* set up data segments */ |
244 | xorl %eax,%eax | |
ffb60175 ZA |
245 | movl %eax,%ds |
246 | movl %eax,%ss | |
247 | movl %eax,%es | |
248 | ||
249 | /* | |
250 | * We don't really need to load %fs or %gs, but load them anyway | |
251 | * to kill any stale realmode selectors. This allows execution | |
252 | * under VT hardware. | |
253 | */ | |
254 | movl %eax,%fs | |
255 | movl %eax,%gs | |
256 | ||
f32ff538 TH |
257 | /* Set up %gs. |
258 | * | |
947e76cd BG |
259 | * The base of %gs always points to the bottom of the irqstack |
260 | * union. If the stack protector canary is enabled, it is | |
261 | * located at %gs:40. Note that, on SMP, the boot cpu uses | |
262 | * init data section till per cpu areas are set up. | |
f32ff538 | 263 | */ |
1da177e4 | 264 | movl $MSR_GS_BASE,%ecx |
650fb439 BG |
265 | movl initial_gs(%rip),%eax |
266 | movl initial_gs+4(%rip),%edx | |
a9468df5 | 267 | wrmsr |
1da177e4 | 268 | |
8170e6be | 269 | /* rsi is pointer to real mode structure with interesting info. |
1da177e4 | 270 | pass it to C */ |
8170e6be | 271 | movq %rsi, %rdi |
a9468df5 | 272 | |
79d243a0 | 273 | .Ljump_to_C_code: |
a9468df5 JP |
274 | /* |
275 | * Jump to run C code and to be on a real kernel address. | |
1da177e4 | 276 | * Since we are running on identity-mapped space we have to jump |
26374c7b EB |
277 | * to the full 64bit address, this is only possible as indirect |
278 | * jump. In addition we need to ensure %cs is set so we make this | |
279 | * a far return. | |
8170e6be PA |
280 | * |
281 | * Note: do not change to far jump indirect with 64bit offset. | |
282 | * | |
283 | * AMD does not support far jump indirect with 64bit offset. | |
284 | * AMD64 Architecture Programmer's Manual, Volume 3: states only | |
285 | * JMP FAR mem16:16 FF /5 Far jump indirect, | |
286 | * with the target specified by a far pointer in memory. | |
287 | * JMP FAR mem16:32 FF /5 Far jump indirect, | |
288 | * with the target specified by a far pointer in memory. | |
289 | * | |
290 | * Intel64 does support 64bit offset. | |
291 | * Software Developer Manual Vol 2: states: | |
292 | * FF /5 JMP m16:16 Jump far, absolute indirect, | |
293 | * address given in m16:16 | |
294 | * FF /5 JMP m16:32 Jump far, absolute indirect, | |
295 | * address given in m16:32. | |
296 | * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, | |
297 | * address given in m16:64. | |
1da177e4 | 298 | */ |
31dcfec1 JP |
299 | pushq $.Lafter_lret # put return address on stack for unwinder |
300 | xorq %rbp, %rbp # clear frame pointer | |
595c1e64 | 301 | movq initial_code(%rip), %rax |
26374c7b EB |
302 | pushq $__KERNEL_CS # set correct cs |
303 | pushq %rax # target address in negative space | |
304 | lretq | |
31dcfec1 | 305 | .Lafter_lret: |
79d243a0 | 306 | ENDPROC(secondary_startup_64) |
1da177e4 | 307 | |
04633df0 BP |
308 | #include "verify_cpu.S" |
309 | ||
42e78e97 FY |
310 | #ifdef CONFIG_HOTPLUG_CPU |
311 | /* | |
312 | * Boot CPU0 entry point. It's called from play_dead(). Everything has been set | |
313 | * up already except stack. We just set up stack here. Then call | |
79d243a0 | 314 | * start_secondary() via .Ljump_to_C_code. |
42e78e97 FY |
315 | */ |
316 | ENTRY(start_cpu0) | |
a9468df5 | 317 | movq initial_stack(%rip), %rsp |
79d243a0 | 318 | jmp .Ljump_to_C_code |
42e78e97 FY |
319 | ENDPROC(start_cpu0) |
320 | #endif | |
321 | ||
b32f96c7 | 322 | /* Both SMP bootup and ACPI suspend change these variables */ |
da5968ae | 323 | __REFDATA |
8170e6be PA |
324 | .balign 8 |
325 | GLOBAL(initial_code) | |
1da177e4 | 326 | .quad x86_64_start_kernel |
8170e6be | 327 | GLOBAL(initial_gs) |
2add8e23 | 328 | .quad INIT_PER_CPU_VAR(irq_stack_union) |
b32f96c7 | 329 | GLOBAL(initial_stack) |
22dc3918 JP |
330 | /* |
331 | * The SIZEOF_PTREGS gap is a convention which helps the in-kernel | |
332 | * unwinder reliably detect the end of the stack. | |
333 | */ | |
334 | .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS | |
b9af7c0d | 335 | __FINITDATA |
1da177e4 | 336 | |
1ab60e0f VG |
337 | bad_address: |
338 | jmp bad_address | |
339 | ||
8170e6be | 340 | __INIT |
cdeb6048 | 341 | ENTRY(early_idt_handler_array) |
9900aa2f PA |
342 | # 104(%rsp) %rflags |
343 | # 96(%rsp) %cs | |
344 | # 88(%rsp) %rip | |
345 | # 80(%rsp) error code | |
749c970a AK |
346 | i = 0 |
347 | .rept NUM_EXCEPTION_VECTORS | |
cdeb6048 | 348 | .ifeq (EXCEPTION_ERRCODE_MASK >> i) & 1 |
9900aa2f PA |
349 | pushq $0 # Dummy error code, to make stack frame uniform |
350 | .endif | |
351 | pushq $i # 72(%rsp) Vector number | |
cdeb6048 | 352 | jmp early_idt_handler_common |
749c970a | 353 | i = i + 1 |
cdeb6048 | 354 | .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc |
749c970a | 355 | .endr |
cdeb6048 | 356 | ENDPROC(early_idt_handler_array) |
8866cd9d | 357 | |
cdeb6048 AL |
358 | early_idt_handler_common: |
359 | /* | |
360 | * The stack is the hardware frame, an error code or zero, and the | |
361 | * vector number. | |
362 | */ | |
9900aa2f PA |
363 | cld |
364 | ||
b957591f | 365 | incl early_recursion_flag(%rip) |
9900aa2f | 366 | |
7bbcdb1c AL |
367 | /* The vector number is currently in the pt_regs->di slot. */ |
368 | pushq %rsi /* pt_regs->si */ | |
369 | movq 8(%rsp), %rsi /* RSI = vector number */ | |
370 | movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ | |
371 | pushq %rdx /* pt_regs->dx */ | |
372 | pushq %rcx /* pt_regs->cx */ | |
373 | pushq %rax /* pt_regs->ax */ | |
374 | pushq %r8 /* pt_regs->r8 */ | |
375 | pushq %r9 /* pt_regs->r9 */ | |
376 | pushq %r10 /* pt_regs->r10 */ | |
377 | pushq %r11 /* pt_regs->r11 */ | |
378 | pushq %rbx /* pt_regs->bx */ | |
379 | pushq %rbp /* pt_regs->bp */ | |
380 | pushq %r12 /* pt_regs->r12 */ | |
381 | pushq %r13 /* pt_regs->r13 */ | |
382 | pushq %r14 /* pt_regs->r14 */ | |
383 | pushq %r15 /* pt_regs->r15 */ | |
384 | ||
7bbcdb1c | 385 | cmpq $14,%rsi /* Page fault? */ |
8170e6be | 386 | jnz 10f |
7bbcdb1c | 387 | GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ |
8170e6be PA |
388 | call early_make_pgtable |
389 | andl %eax,%eax | |
7bbcdb1c | 390 | jz 20f /* All good */ |
9900aa2f | 391 | |
8170e6be | 392 | 10: |
7bbcdb1c | 393 | movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ |
9900aa2f | 394 | call early_fixup_exception |
076f9776 | 395 | |
0e861fbb | 396 | 20: |
9900aa2f | 397 | decl early_recursion_flag(%rip) |
7bbcdb1c | 398 | jmp restore_regs_and_iret |
cdeb6048 | 399 | ENDPROC(early_idt_handler_common) |
9900aa2f | 400 | |
8170e6be PA |
401 | __INITDATA |
402 | ||
9900aa2f | 403 | .balign 4 |
0e861fbb | 404 | GLOBAL(early_recursion_flag) |
b957591f | 405 | .long 0 |
1da177e4 | 406 | |
f0cf5d1a | 407 | #define NEXT_PAGE(name) \ |
67dcbb6b | 408 | .balign PAGE_SIZE; \ |
8170e6be | 409 | GLOBAL(name) |
f0cf5d1a | 410 | |
67dcbb6b | 411 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
0e192b99 CG |
412 | #define PMDS(START, PERM, COUNT) \ |
413 | i = 0 ; \ | |
414 | .rept (COUNT) ; \ | |
415 | .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ | |
416 | i = i + 1 ; \ | |
67dcbb6b VG |
417 | .endr |
418 | ||
8170e6be PA |
419 | __INITDATA |
420 | NEXT_PAGE(early_level4_pgt) | |
421 | .fill 511,8,0 | |
422 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE | |
423 | ||
424 | NEXT_PAGE(early_dynamic_pgts) | |
425 | .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 | |
426 | ||
b9af7c0d | 427 | .data |
8170e6be PA |
428 | |
429 | #ifndef CONFIG_XEN | |
f0cf5d1a | 430 | NEXT_PAGE(init_level4_pgt) |
8170e6be PA |
431 | .fill 512,8,0 |
432 | #else | |
433 | NEXT_PAGE(init_level4_pgt) | |
434 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE | |
435 | .org init_level4_pgt + L4_PAGE_OFFSET*8, 0 | |
436 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE | |
437 | .org init_level4_pgt + L4_START_KERNEL*8, 0 | |
cfd243d4 | 438 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ |
8170e6be | 439 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE |
1da177e4 | 440 | |
f0cf5d1a | 441 | NEXT_PAGE(level3_ident_pgt) |
67dcbb6b | 442 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
8170e6be PA |
443 | .fill 511, 8, 0 |
444 | NEXT_PAGE(level2_ident_pgt) | |
445 | /* Since I easily can, map the first 1G. | |
446 | * Don't set NX because code runs from these pages. | |
447 | */ | |
448 | PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) | |
449 | #endif | |
1da177e4 | 450 | |
f0cf5d1a | 451 | NEXT_PAGE(level3_kernel_pgt) |
a6523748 | 452 | .fill L3_START_KERNEL,8,0 |
1da177e4 | 453 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ |
67dcbb6b | 454 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE |
b1c931e3 EB |
455 | .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE |
456 | ||
f0cf5d1a | 457 | NEXT_PAGE(level2_kernel_pgt) |
88f3aec7 | 458 | /* |
85eb69a1 | 459 | * 512 MB kernel mapping. We spend a full page on this pagetable |
88f3aec7 IM |
460 | * anyway. |
461 | * | |
462 | * The kernel code+data+bss must not be bigger than that. | |
463 | * | |
85eb69a1 | 464 | * (NOTE: at +512MB starts the module area, see MODULES_VADDR. |
88f3aec7 IM |
465 | * If you want to increase this then increase MODULES_VADDR |
466 | * too.) | |
467 | */ | |
8490638c | 468 | PMDS(0, __PAGE_KERNEL_LARGE_EXEC, |
d4afe414 | 469 | KERNEL_IMAGE_SIZE/PMD_SIZE) |
1da177e4 | 470 | |
8170e6be PA |
471 | NEXT_PAGE(level2_fixmap_pgt) |
472 | .fill 506,8,0 | |
473 | .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE | |
474 | /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ | |
475 | .fill 5,8,0 | |
476 | ||
477 | NEXT_PAGE(level1_fixmap_pgt) | |
478 | .fill 512,8,0 | |
1ab60e0f | 479 | |
67dcbb6b | 480 | #undef PMDS |
1da177e4 | 481 | |
f0cf5d1a | 482 | .data |
1da177e4 | 483 | .align 16 |
a939098a GC |
484 | .globl early_gdt_descr |
485 | early_gdt_descr: | |
486 | .word GDT_ENTRIES*8-1 | |
3e5d8f97 | 487 | early_gdt_descr_base: |
2add8e23 | 488 | .quad INIT_PER_CPU_VAR(gdt_page) |
1da177e4 | 489 | |
1ab60e0f VG |
490 | ENTRY(phys_base) |
491 | /* This must match the first entry in level2_kernel_pgt */ | |
492 | .quad 0x0000000000000000 | |
784d5699 | 493 | EXPORT_SYMBOL(phys_base) |
1ab60e0f | 494 | |
8c5e5ac3 | 495 | #include "../../x86/xen/xen-head.S" |
1da177e4 | 496 | |
02b7da37 | 497 | __PAGE_ALIGNED_BSS |
8170e6be | 498 | NEXT_PAGE(empty_zero_page) |
e57113bc | 499 | .skip PAGE_SIZE |
784d5699 | 500 | EXPORT_SYMBOL(empty_zero_page) |
ef7f0d6a | 501 |