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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
5b171e82 | 3 | * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
7 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
8 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1ab60e0f | 9 | * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> |
1da177e4 LT |
10 | */ |
11 | ||
12 | ||
13 | #include <linux/linkage.h> | |
14 | #include <linux/threads.h> | |
f6c2e333 | 15 | #include <linux/init.h> |
ca5999fd | 16 | #include <linux/pgtable.h> |
65fddcfc | 17 | #include <asm/segment.h> |
1da177e4 LT |
18 | #include <asm/page.h> |
19 | #include <asm/msr.h> | |
20 | #include <asm/cache.h> | |
369101da | 21 | #include <asm/processor-flags.h> |
b12d8db8 | 22 | #include <asm/percpu.h> |
9900aa2f | 23 | #include <asm/nops.h> |
7bbcdb1c | 24 | #include "../entry/calling.h" |
784d5699 | 25 | #include <asm/export.h> |
bd89004f | 26 | #include <asm/nospec-branch.h> |
05ab1d8a | 27 | #include <asm/fixmap.h> |
1ab60e0f | 28 | |
75da04f7 TG |
29 | /* |
30 | * We are not able to switch in one step to the final KERNEL ADDRESS SPACE | |
1ab60e0f | 31 | * because we need identity-mapped pages. |
1da177e4 | 32 | */ |
b9952ec7 | 33 | #define l4_index(x) (((x) >> 39) & 511) |
a6523748 EH |
34 | #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
35 | ||
b9952ec7 KS |
36 | L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4) |
37 | L4_START_KERNEL = l4_index(__START_KERNEL_map) | |
38 | ||
a6523748 EH |
39 | L3_START_KERNEL = pud_index(__START_KERNEL_map) |
40 | ||
1da177e4 | 41 | .text |
4ae59b91 | 42 | __HEAD |
1ab60e0f | 43 | .code64 |
37818afd | 44 | SYM_CODE_START_NOALIGN(startup_64) |
2704fbb6 | 45 | UNWIND_HINT_EMPTY |
1da177e4 | 46 | /* |
1256276c | 47 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
48 | * and someone has loaded an identity mapped page table |
49 | * for us. These identity mapped page tables map all of the | |
50 | * kernel pages and possibly all of memory. | |
51 | * | |
8170e6be | 52 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
53 | * |
54 | * We come here either directly from a 64bit bootloader, or from | |
5b171e82 | 55 | * arch/x86/boot/compressed/head_64.S. |
1ab60e0f VG |
56 | * |
57 | * We only come here initially at boot nothing else comes here. | |
58 | * | |
59 | * Since we may be loaded at an address different from what we were | |
60 | * compiled to run at we first fixup the physical addresses in our page | |
61 | * tables and then reload them. | |
1da177e4 LT |
62 | */ |
63 | ||
22dc3918 | 64 | /* Set up the stack for verify_cpu(), similar to initial_stack below */ |
6627eb25 | 65 | leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp |
91ed140d | 66 | |
866b556e JR |
67 | leaq _text(%rip), %rdi |
68 | pushq %rsi | |
69 | call startup_64_setup_env | |
70 | popq %rsi | |
71 | ||
72 | /* Now switch to __KERNEL_CS so IRET works reliably */ | |
73 | pushq $__KERNEL_CS | |
74 | leaq .Lon_kernel_cs(%rip), %rax | |
75 | pushq %rax | |
76 | lretq | |
77 | ||
78 | .Lon_kernel_cs: | |
79 | UNWIND_HINT_EMPTY | |
80 | ||
04633df0 BP |
81 | /* Sanitize CPU configuration */ |
82 | call verify_cpu | |
83 | ||
5868f365 TL |
84 | /* |
85 | * Perform pagetable fixups. Additionally, if SME is active, encrypt | |
86 | * the kernel and retrieve the modifier (SME encryption mask if SME | |
87 | * is active) to be added to the initial pgdir entry that will be | |
88 | * programmed into CR3. | |
89 | */ | |
1ab60e0f | 90 | leaq _text(%rip), %rdi |
c88d7150 KS |
91 | pushq %rsi |
92 | call __startup_64 | |
93 | popq %rsi | |
1da177e4 | 94 | |
5868f365 TL |
95 | /* Form the CR3 value being sure to include the CR3 modifier */ |
96 | addq $(early_top_pgt - __START_KERNEL_map), %rax | |
8170e6be | 97 | jmp 1f |
37818afd JS |
98 | SYM_CODE_END(startup_64) |
99 | ||
bc7b11c0 | 100 | SYM_CODE_START(secondary_startup_64) |
2704fbb6 | 101 | UNWIND_HINT_EMPTY |
1ab60e0f | 102 | /* |
1256276c | 103 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
104 | * and someone has loaded a mapped page table. |
105 | * | |
8170e6be | 106 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
107 | * |
108 | * We come here either from startup_64 (using physical addresses) | |
109 | * or from trampoline.S (using virtual addresses). | |
110 | * | |
111 | * Using virtual addresses from trampoline.S removes the need | |
112 | * to have any identity mapped pages in the kernel page table | |
113 | * after the boot processor executes this code. | |
1da177e4 LT |
114 | */ |
115 | ||
04633df0 BP |
116 | /* Sanitize CPU configuration */ |
117 | call verify_cpu | |
118 | ||
3ecacdbd JR |
119 | /* |
120 | * The secondary_startup_64_no_verify entry point is only used by | |
121 | * SEV-ES guests. In those guests the call to verify_cpu() would cause | |
122 | * #VC exceptions which can not be handled at this stage of secondary | |
123 | * CPU bringup. | |
124 | * | |
125 | * All non SEV-ES systems, especially Intel systems, need to execute | |
126 | * verify_cpu() above to make sure NX is enabled. | |
127 | */ | |
128 | SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) | |
129 | UNWIND_HINT_EMPTY | |
130 | ||
5868f365 TL |
131 | /* |
132 | * Retrieve the modifier (SME encryption mask if SME is active) to be | |
133 | * added to the initial pgdir entry that will be programmed into CR3. | |
134 | */ | |
135 | pushq %rsi | |
136 | call __startup_secondary_64 | |
137 | popq %rsi | |
138 | ||
139 | /* Form the CR3 value being sure to include the CR3 modifier */ | |
140 | addq $(init_top_pgt - __START_KERNEL_map), %rax | |
8170e6be PA |
141 | 1: |
142 | ||
032370b9 | 143 | /* Enable PAE mode, PGE and LA57 */ |
8170e6be | 144 | movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx |
032370b9 | 145 | #ifdef CONFIG_X86_5LEVEL |
39b95522 | 146 | testl $1, __pgtable_l5_enabled(%rip) |
6f9dd329 | 147 | jz 1f |
032370b9 | 148 | orl $X86_CR4_LA57, %ecx |
6f9dd329 | 149 | 1: |
032370b9 | 150 | #endif |
8170e6be | 151 | movq %rcx, %cr4 |
1da177e4 | 152 | |
032370b9 | 153 | /* Setup early boot stage 4-/5-level pagetables. */ |
1ab60e0f | 154 | addq phys_base(%rip), %rax |
c9f09539 JR |
155 | |
156 | /* | |
157 | * For SEV guests: Verify that the C-bit is correct. A malicious | |
158 | * hypervisor could lie about the C-bit position to perform a ROP | |
159 | * attack on the guest by writing to the unencrypted stack and wait for | |
160 | * the next RET instruction. | |
161 | * %rsi carries pointer to realmode data and is callee-clobbered. Save | |
162 | * and restore it. | |
163 | */ | |
164 | pushq %rsi | |
165 | movq %rax, %rdi | |
166 | call sev_verify_cbit | |
167 | popq %rsi | |
168 | ||
169 | /* Switch to new page-table */ | |
1da177e4 LT |
170 | movq %rax, %cr3 |
171 | ||
1ab60e0f VG |
172 | /* Ensure I am executing from virtual addresses */ |
173 | movq $1f, %rax | |
bd89004f | 174 | ANNOTATE_RETPOLINE_SAFE |
1ab60e0f VG |
175 | jmp *%rax |
176 | 1: | |
2704fbb6 | 177 | UNWIND_HINT_EMPTY |
1ab60e0f | 178 | |
e04b8833 JR |
179 | /* |
180 | * We must switch to a new descriptor in kernel space for the GDT | |
181 | * because soon the kernel won't have access anymore to the userspace | |
182 | * addresses where we're currently running on. We have to do that here | |
183 | * because in 32bit we couldn't load a 64bit linear address. | |
184 | */ | |
185 | lgdt early_gdt_descr(%rip) | |
186 | ||
7b99819d JR |
187 | /* set up data segments */ |
188 | xorl %eax,%eax | |
189 | movl %eax,%ds | |
190 | movl %eax,%ss | |
191 | movl %eax,%es | |
192 | ||
193 | /* | |
194 | * We don't really need to load %fs or %gs, but load them anyway | |
195 | * to kill any stale realmode selectors. This allows execution | |
196 | * under VT hardware. | |
197 | */ | |
198 | movl %eax,%fs | |
199 | movl %eax,%gs | |
200 | ||
201 | /* Set up %gs. | |
202 | * | |
203 | * The base of %gs always points to fixed_percpu_data. If the | |
204 | * stack protector canary is enabled, it is located at %gs:40. | |
205 | * Note that, on SMP, the boot cpu uses init data section until | |
206 | * the per cpu areas are set up. | |
207 | */ | |
208 | movl $MSR_GS_BASE,%ecx | |
209 | movl initial_gs(%rip),%eax | |
210 | movl initial_gs+4(%rip),%edx | |
211 | wrmsr | |
212 | ||
3add38cb JR |
213 | /* |
214 | * Setup a boot time stack - Any secondary CPU will have lost its stack | |
215 | * by now because the cr3-switch above unmaps the real-mode stack | |
216 | */ | |
217 | movq initial_stack(%rip), %rsp | |
218 | ||
f5963ba7 JR |
219 | /* Setup and Load IDT */ |
220 | pushq %rsi | |
221 | call early_setup_idt | |
222 | popq %rsi | |
223 | ||
1da177e4 LT |
224 | /* Check if nx is implemented */ |
225 | movl $0x80000001, %eax | |
226 | cpuid | |
227 | movl %edx,%edi | |
228 | ||
229 | /* Setup EFER (Extended Feature Enable Register) */ | |
230 | movl $MSR_EFER, %ecx | |
231 | rdmsr | |
1ab60e0f VG |
232 | btsl $_EFER_SCE, %eax /* Enable System Call */ |
233 | btl $20,%edi /* No Execute supported? */ | |
1da177e4 LT |
234 | jnc 1f |
235 | btsl $_EFER_NX, %eax | |
78d77df7 | 236 | btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) |
1ab60e0f | 237 | 1: wrmsr /* Make changes effective */ |
1da177e4 LT |
238 | |
239 | /* Setup cr0 */ | |
369101da | 240 | movl $CR0_STATE, %eax |
1da177e4 LT |
241 | /* Make changes effective */ |
242 | movq %rax, %cr0 | |
243 | ||
1da177e4 LT |
244 | /* zero EFLAGS after setting rsp */ |
245 | pushq $0 | |
246 | popfq | |
247 | ||
8170e6be | 248 | /* rsi is pointer to real mode structure with interesting info. |
1da177e4 | 249 | pass it to C */ |
8170e6be | 250 | movq %rsi, %rdi |
a9468df5 | 251 | |
79d243a0 | 252 | .Ljump_to_C_code: |
a9468df5 JP |
253 | /* |
254 | * Jump to run C code and to be on a real kernel address. | |
1da177e4 | 255 | * Since we are running on identity-mapped space we have to jump |
26374c7b EB |
256 | * to the full 64bit address, this is only possible as indirect |
257 | * jump. In addition we need to ensure %cs is set so we make this | |
258 | * a far return. | |
8170e6be PA |
259 | * |
260 | * Note: do not change to far jump indirect with 64bit offset. | |
261 | * | |
262 | * AMD does not support far jump indirect with 64bit offset. | |
263 | * AMD64 Architecture Programmer's Manual, Volume 3: states only | |
264 | * JMP FAR mem16:16 FF /5 Far jump indirect, | |
265 | * with the target specified by a far pointer in memory. | |
266 | * JMP FAR mem16:32 FF /5 Far jump indirect, | |
267 | * with the target specified by a far pointer in memory. | |
268 | * | |
269 | * Intel64 does support 64bit offset. | |
270 | * Software Developer Manual Vol 2: states: | |
271 | * FF /5 JMP m16:16 Jump far, absolute indirect, | |
272 | * address given in m16:16 | |
273 | * FF /5 JMP m16:32 Jump far, absolute indirect, | |
274 | * address given in m16:32. | |
275 | * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, | |
276 | * address given in m16:64. | |
1da177e4 | 277 | */ |
31dcfec1 | 278 | pushq $.Lafter_lret # put return address on stack for unwinder |
a7bea830 | 279 | xorl %ebp, %ebp # clear frame pointer |
595c1e64 | 280 | movq initial_code(%rip), %rax |
26374c7b EB |
281 | pushq $__KERNEL_CS # set correct cs |
282 | pushq %rax # target address in negative space | |
283 | lretq | |
31dcfec1 | 284 | .Lafter_lret: |
bc7b11c0 | 285 | SYM_CODE_END(secondary_startup_64) |
1da177e4 | 286 | |
04633df0 | 287 | #include "verify_cpu.S" |
c9f09539 | 288 | #include "sev_verify_cbit.S" |
04633df0 | 289 | |
42e78e97 FY |
290 | #ifdef CONFIG_HOTPLUG_CPU |
291 | /* | |
292 | * Boot CPU0 entry point. It's called from play_dead(). Everything has been set | |
293 | * up already except stack. We just set up stack here. Then call | |
79d243a0 | 294 | * start_secondary() via .Ljump_to_C_code. |
42e78e97 | 295 | */ |
bc7b11c0 | 296 | SYM_CODE_START(start_cpu0) |
2704fbb6 | 297 | UNWIND_HINT_EMPTY |
61a73f5c | 298 | movq initial_stack(%rip), %rsp |
79d243a0 | 299 | jmp .Ljump_to_C_code |
bc7b11c0 | 300 | SYM_CODE_END(start_cpu0) |
1aa9aa8e JR |
301 | #endif |
302 | ||
303 | #ifdef CONFIG_AMD_MEM_ENCRYPT | |
304 | /* | |
305 | * VC Exception handler used during early boot when running on kernel | |
306 | * addresses, but before the switch to the idt_table can be made. | |
307 | * The early_idt_handler_array can't be used here because it calls into a lot | |
308 | * of __init code and this handler is also used during CPU offlining/onlining. | |
309 | * Therefore this handler ends up in the .text section so that it stays around | |
310 | * when .init.text is freed. | |
311 | */ | |
312 | SYM_CODE_START_NOALIGN(vc_boot_ghcb) | |
313 | UNWIND_HINT_IRET_REGS offset=8 | |
314 | ||
315 | /* Build pt_regs */ | |
316 | PUSH_AND_CLEAR_REGS | |
317 | ||
318 | /* Call C handler */ | |
319 | movq %rsp, %rdi | |
320 | movq ORIG_RAX(%rsp), %rsi | |
321 | movq initial_vc_handler(%rip), %rax | |
322 | ANNOTATE_RETPOLINE_SAFE | |
323 | call *%rax | |
324 | ||
325 | /* Unwind pt_regs */ | |
326 | POP_REGS | |
327 | ||
328 | /* Remove Error Code */ | |
329 | addq $8, %rsp | |
330 | ||
331 | /* Pure iret required here - don't use INTERRUPT_RETURN */ | |
332 | iretq | |
333 | SYM_CODE_END(vc_boot_ghcb) | |
42e78e97 FY |
334 | #endif |
335 | ||
b32f96c7 | 336 | /* Both SMP bootup and ACPI suspend change these variables */ |
da5968ae | 337 | __REFDATA |
8170e6be | 338 | .balign 8 |
b1bd27b9 JS |
339 | SYM_DATA(initial_code, .quad x86_64_start_kernel) |
340 | SYM_DATA(initial_gs, .quad INIT_PER_CPU_VAR(fixed_percpu_data)) | |
1aa9aa8e JR |
341 | #ifdef CONFIG_AMD_MEM_ENCRYPT |
342 | SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) | |
343 | #endif | |
b1bd27b9 JS |
344 | |
345 | /* | |
6627eb25 | 346 | * The FRAME_SIZE gap is a convention which helps the in-kernel unwinder |
b1bd27b9 JS |
347 | * reliably detect the end of the stack. |
348 | */ | |
6627eb25 | 349 | SYM_DATA(initial_stack, .quad init_thread_union + THREAD_SIZE - FRAME_SIZE) |
b9af7c0d | 350 | __FINITDATA |
1da177e4 | 351 | |
8170e6be | 352 | __INIT |
bc7b11c0 | 353 | SYM_CODE_START(early_idt_handler_array) |
749c970a AK |
354 | i = 0 |
355 | .rept NUM_EXCEPTION_VECTORS | |
82c62fa0 | 356 | .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 |
2704fbb6 JP |
357 | UNWIND_HINT_IRET_REGS |
358 | pushq $0 # Dummy error code, to make stack frame uniform | |
359 | .else | |
360 | UNWIND_HINT_IRET_REGS offset=8 | |
9900aa2f PA |
361 | .endif |
362 | pushq $i # 72(%rsp) Vector number | |
cdeb6048 | 363 | jmp early_idt_handler_common |
2704fbb6 | 364 | UNWIND_HINT_IRET_REGS |
749c970a | 365 | i = i + 1 |
cdeb6048 | 366 | .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc |
749c970a | 367 | .endr |
2704fbb6 | 368 | UNWIND_HINT_IRET_REGS offset=16 |
bc7b11c0 | 369 | SYM_CODE_END(early_idt_handler_array) |
8866cd9d | 370 | |
ef77e688 | 371 | SYM_CODE_START_LOCAL(early_idt_handler_common) |
cdeb6048 AL |
372 | /* |
373 | * The stack is the hardware frame, an error code or zero, and the | |
374 | * vector number. | |
375 | */ | |
9900aa2f PA |
376 | cld |
377 | ||
b957591f | 378 | incl early_recursion_flag(%rip) |
9900aa2f | 379 | |
7bbcdb1c AL |
380 | /* The vector number is currently in the pt_regs->di slot. */ |
381 | pushq %rsi /* pt_regs->si */ | |
382 | movq 8(%rsp), %rsi /* RSI = vector number */ | |
383 | movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ | |
384 | pushq %rdx /* pt_regs->dx */ | |
385 | pushq %rcx /* pt_regs->cx */ | |
386 | pushq %rax /* pt_regs->ax */ | |
387 | pushq %r8 /* pt_regs->r8 */ | |
388 | pushq %r9 /* pt_regs->r9 */ | |
389 | pushq %r10 /* pt_regs->r10 */ | |
390 | pushq %r11 /* pt_regs->r11 */ | |
391 | pushq %rbx /* pt_regs->bx */ | |
392 | pushq %rbp /* pt_regs->bp */ | |
393 | pushq %r12 /* pt_regs->r12 */ | |
394 | pushq %r13 /* pt_regs->r13 */ | |
395 | pushq %r14 /* pt_regs->r14 */ | |
396 | pushq %r15 /* pt_regs->r15 */ | |
2704fbb6 | 397 | UNWIND_HINT_REGS |
7bbcdb1c | 398 | |
7bbcdb1c | 399 | movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ |
4b47cdbd | 400 | call do_early_exception |
076f9776 | 401 | |
9900aa2f | 402 | decl early_recursion_flag(%rip) |
26c4ef9c | 403 | jmp restore_regs_and_return_to_kernel |
ef77e688 | 404 | SYM_CODE_END(early_idt_handler_common) |
9900aa2f | 405 | |
74d8d9d5 JR |
406 | #ifdef CONFIG_AMD_MEM_ENCRYPT |
407 | /* | |
408 | * VC Exception handler used during very early boot. The | |
409 | * early_idt_handler_array can't be used because it returns via the | |
410 | * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. | |
411 | * | |
412 | * This handler will end up in the .init.text section and not be | |
413 | * available to boot secondary CPUs. | |
414 | */ | |
415 | SYM_CODE_START_NOALIGN(vc_no_ghcb) | |
416 | UNWIND_HINT_IRET_REGS offset=8 | |
417 | ||
418 | /* Build pt_regs */ | |
419 | PUSH_AND_CLEAR_REGS | |
420 | ||
421 | /* Call C handler */ | |
422 | movq %rsp, %rdi | |
423 | movq ORIG_RAX(%rsp), %rsi | |
424 | call do_vc_no_ghcb | |
425 | ||
426 | /* Unwind pt_regs */ | |
427 | POP_REGS | |
428 | ||
429 | /* Remove Error Code */ | |
430 | addq $8, %rsp | |
431 | ||
432 | /* Pure iret required here - don't use INTERRUPT_RETURN */ | |
433 | iretq | |
434 | SYM_CODE_END(vc_no_ghcb) | |
435 | #endif | |
b1bd27b9 JS |
436 | |
437 | #define SYM_DATA_START_PAGE_ALIGNED(name) \ | |
438 | SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE) | |
f0cf5d1a | 439 | |
d9e9a641 DH |
440 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
441 | /* | |
442 | * Each PGD needs to be 8k long and 8k aligned. We do not | |
443 | * ever go out to userspace with these, so we do not | |
444 | * strictly *need* the second page, but this allows us to | |
445 | * have a single set_pgd() implementation that does not | |
446 | * need to worry about whether it has 4k or 8k to work | |
447 | * with. | |
448 | * | |
449 | * This ensures PGDs are 8k long: | |
450 | */ | |
451 | #define PTI_USER_PGD_FILL 512 | |
452 | /* This ensures they are 8k-aligned: */ | |
b1bd27b9 JS |
453 | #define SYM_DATA_START_PTI_ALIGNED(name) \ |
454 | SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) | |
d9e9a641 | 455 | #else |
b1bd27b9 JS |
456 | #define SYM_DATA_START_PTI_ALIGNED(name) \ |
457 | SYM_DATA_START_PAGE_ALIGNED(name) | |
d9e9a641 DH |
458 | #define PTI_USER_PGD_FILL 0 |
459 | #endif | |
460 | ||
67dcbb6b | 461 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
0e192b99 CG |
462 | #define PMDS(START, PERM, COUNT) \ |
463 | i = 0 ; \ | |
464 | .rept (COUNT) ; \ | |
465 | .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ | |
466 | i = i + 1 ; \ | |
67dcbb6b VG |
467 | .endr |
468 | ||
8170e6be | 469 | __INITDATA |
1a8770b7 JS |
470 | .balign 4 |
471 | ||
b1bd27b9 | 472 | SYM_DATA_START_PTI_ALIGNED(early_top_pgt) |
6f9dd329 | 473 | .fill 512,8,0 |
d9e9a641 | 474 | .fill PTI_USER_PGD_FILL,8,0 |
b1bd27b9 | 475 | SYM_DATA_END(early_top_pgt) |
8170e6be | 476 | |
b1bd27b9 | 477 | SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) |
8170e6be | 478 | .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 |
b1bd27b9 | 479 | SYM_DATA_END(early_dynamic_pgts) |
8170e6be | 480 | |
b1bd27b9 | 481 | SYM_DATA(early_recursion_flag, .long 0) |
1a8770b7 | 482 | |
b9af7c0d | 483 | .data |
8170e6be | 484 | |
7733607f | 485 | #if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) |
b1bd27b9 | 486 | SYM_DATA_START_PTI_ALIGNED(init_top_pgt) |
21729f81 | 487 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
b9952ec7 | 488 | .org init_top_pgt + L4_PAGE_OFFSET*8, 0 |
21729f81 | 489 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
b9952ec7 | 490 | .org init_top_pgt + L4_START_KERNEL*8, 0 |
cfd243d4 | 491 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ |
21729f81 | 492 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
d9e9a641 | 493 | .fill PTI_USER_PGD_FILL,8,0 |
b1bd27b9 | 494 | SYM_DATA_END(init_top_pgt) |
1da177e4 | 495 | |
b1bd27b9 | 496 | SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) |
21729f81 | 497 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
8170e6be | 498 | .fill 511, 8, 0 |
b1bd27b9 JS |
499 | SYM_DATA_END(level3_ident_pgt) |
500 | SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) | |
430d4005 DH |
501 | /* |
502 | * Since I easily can, map the first 1G. | |
8170e6be | 503 | * Don't set NX because code runs from these pages. |
430d4005 DH |
504 | * |
505 | * Note: This sets _PAGE_GLOBAL despite whether | |
506 | * the CPU supports it or it is enabled. But, | |
507 | * the CPU should ignore the bit. | |
8170e6be PA |
508 | */ |
509 | PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) | |
b1bd27b9 | 510 | SYM_DATA_END(level2_ident_pgt) |
4375c299 | 511 | #else |
b1bd27b9 | 512 | SYM_DATA_START_PTI_ALIGNED(init_top_pgt) |
4375c299 | 513 | .fill 512,8,0 |
d9e9a641 | 514 | .fill PTI_USER_PGD_FILL,8,0 |
b1bd27b9 | 515 | SYM_DATA_END(init_top_pgt) |
8170e6be | 516 | #endif |
1da177e4 | 517 | |
032370b9 | 518 | #ifdef CONFIG_X86_5LEVEL |
b1bd27b9 | 519 | SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) |
032370b9 | 520 | .fill 511,8,0 |
21729f81 | 521 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC |
b1bd27b9 | 522 | SYM_DATA_END(level4_kernel_pgt) |
032370b9 KS |
523 | #endif |
524 | ||
b1bd27b9 | 525 | SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) |
a6523748 | 526 | .fill L3_START_KERNEL,8,0 |
1da177e4 | 527 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ |
21729f81 TL |
528 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC |
529 | .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC | |
b1bd27b9 | 530 | SYM_DATA_END(level3_kernel_pgt) |
b1c931e3 | 531 | |
b1bd27b9 | 532 | SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) |
88f3aec7 | 533 | /* |
ea3186b9 | 534 | * Kernel high mapping. |
88f3aec7 | 535 | * |
ea3186b9 AS |
536 | * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in |
537 | * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled, | |
538 | * 512 MiB otherwise. | |
88f3aec7 | 539 | * |
ea3186b9 | 540 | * (NOTE: after that starts the module area, see MODULES_VADDR.) |
430d4005 | 541 | * |
ea3186b9 AS |
542 | * This table is eventually used by the kernel during normal runtime. |
543 | * Care must be taken to clear out undesired bits later, like _PAGE_RW | |
544 | * or _PAGE_GLOBAL in some cases. | |
88f3aec7 | 545 | */ |
ea3186b9 | 546 | PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE) |
b1bd27b9 | 547 | SYM_DATA_END(level2_kernel_pgt) |
1da177e4 | 548 | |
b1bd27b9 | 549 | SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) |
05ab1d8a FT |
550 | .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 |
551 | pgtno = 0 | |
552 | .rept (FIXMAP_PMD_NUM) | |
553 | .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ | |
554 | + _PAGE_TABLE_NOENC; | |
555 | pgtno = pgtno + 1 | |
556 | .endr | |
557 | /* 6 MB reserved space + a 2MB hole */ | |
558 | .fill 4,8,0 | |
b1bd27b9 | 559 | SYM_DATA_END(level2_fixmap_pgt) |
8170e6be | 560 | |
b1bd27b9 | 561 | SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) |
05ab1d8a | 562 | .rept (FIXMAP_PMD_NUM) |
8170e6be | 563 | .fill 512,8,0 |
05ab1d8a | 564 | .endr |
b1bd27b9 | 565 | SYM_DATA_END(level1_fixmap_pgt) |
1ab60e0f | 566 | |
67dcbb6b | 567 | #undef PMDS |
1da177e4 | 568 | |
f0cf5d1a | 569 | .data |
1da177e4 | 570 | .align 16 |
b1bd27b9 JS |
571 | |
572 | SYM_DATA(early_gdt_descr, .word GDT_ENTRIES*8-1) | |
573 | SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) | |
574 | ||
575 | .align 16 | |
576 | /* This must match the first entry in level2_kernel_pgt */ | |
577 | SYM_DATA(phys_base, .quad 0x0) | |
784d5699 | 578 | EXPORT_SYMBOL(phys_base) |
1ab60e0f | 579 | |
8c5e5ac3 | 580 | #include "../../x86/xen/xen-head.S" |
2704fbb6 | 581 | |
02b7da37 | 582 | __PAGE_ALIGNED_BSS |
b1bd27b9 | 583 | SYM_DATA_START_PAGE_ALIGNED(empty_zero_page) |
e57113bc | 584 | .skip PAGE_SIZE |
b1bd27b9 | 585 | SYM_DATA_END(empty_zero_page) |
784d5699 | 586 | EXPORT_SYMBOL(empty_zero_page) |
ef7f0d6a | 587 |