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Commit | Line | Data |
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1da177e4 | 1 | /* |
5b171e82 | 2 | * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
5 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
6 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
7 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1ab60e0f | 8 | * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> |
1da177e4 LT |
9 | */ |
10 | ||
11 | ||
12 | #include <linux/linkage.h> | |
13 | #include <linux/threads.h> | |
f6c2e333 | 14 | #include <linux/init.h> |
1da177e4 | 15 | #include <asm/segment.h> |
67dcbb6b | 16 | #include <asm/pgtable.h> |
1da177e4 LT |
17 | #include <asm/page.h> |
18 | #include <asm/msr.h> | |
19 | #include <asm/cache.h> | |
369101da | 20 | #include <asm/processor-flags.h> |
b12d8db8 | 21 | #include <asm/percpu.h> |
9900aa2f | 22 | #include <asm/nops.h> |
7bbcdb1c | 23 | #include "../entry/calling.h" |
784d5699 | 24 | #include <asm/export.h> |
1ab60e0f | 25 | |
49a69787 GOC |
26 | #ifdef CONFIG_PARAVIRT |
27 | #include <asm/asm-offsets.h> | |
28 | #include <asm/paravirt.h> | |
ffc4bc9c | 29 | #define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg |
49a69787 | 30 | #else |
ffc4bc9c | 31 | #define GET_CR2_INTO(reg) movq %cr2, reg |
9900aa2f | 32 | #define INTERRUPT_RETURN iretq |
49a69787 GOC |
33 | #endif |
34 | ||
3ad2f3fb | 35 | /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE |
1ab60e0f VG |
36 | * because we need identity-mapped pages. |
37 | * | |
1da177e4 LT |
38 | */ |
39 | ||
a6523748 EH |
40 | #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) |
41 | ||
a883ee7f | 42 | #if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH) |
032370b9 KS |
43 | PGD_PAGE_OFFSET = pgd_index(__PAGE_OFFSET_BASE) |
44 | PGD_START_KERNEL = pgd_index(__START_KERNEL_map) | |
a883ee7f | 45 | #endif |
a6523748 EH |
46 | L3_START_KERNEL = pud_index(__START_KERNEL_map) |
47 | ||
1da177e4 | 48 | .text |
4ae59b91 | 49 | __HEAD |
1ab60e0f VG |
50 | .code64 |
51 | .globl startup_64 | |
52 | startup_64: | |
b63a868e | 53 | UNWIND_HINT_EMPTY |
1da177e4 | 54 | /* |
1256276c | 55 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
56 | * and someone has loaded an identity mapped page table |
57 | * for us. These identity mapped page tables map all of the | |
58 | * kernel pages and possibly all of memory. | |
59 | * | |
8170e6be | 60 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
61 | * |
62 | * We come here either directly from a 64bit bootloader, or from | |
5b171e82 | 63 | * arch/x86/boot/compressed/head_64.S. |
1ab60e0f VG |
64 | * |
65 | * We only come here initially at boot nothing else comes here. | |
66 | * | |
67 | * Since we may be loaded at an address different from what we were | |
68 | * compiled to run at we first fixup the physical addresses in our page | |
69 | * tables and then reload them. | |
1da177e4 LT |
70 | */ |
71 | ||
22dc3918 JP |
72 | /* Set up the stack for verify_cpu(), similar to initial_stack below */ |
73 | leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp | |
91ed140d | 74 | |
04633df0 BP |
75 | /* Sanitize CPU configuration */ |
76 | call verify_cpu | |
77 | ||
1ab60e0f | 78 | leaq _text(%rip), %rdi |
c88d7150 KS |
79 | pushq %rsi |
80 | call __startup_64 | |
81 | popq %rsi | |
1da177e4 | 82 | |
65ade2f8 | 83 | movq $(early_top_pgt - __START_KERNEL_map), %rax |
8170e6be | 84 | jmp 1f |
90b1c208 | 85 | ENTRY(secondary_startup_64) |
b63a868e | 86 | UNWIND_HINT_EMPTY |
1ab60e0f | 87 | /* |
1256276c | 88 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, |
1ab60e0f VG |
89 | * and someone has loaded a mapped page table. |
90 | * | |
8170e6be | 91 | * %rsi holds a physical pointer to real_mode_data. |
1ab60e0f VG |
92 | * |
93 | * We come here either from startup_64 (using physical addresses) | |
94 | * or from trampoline.S (using virtual addresses). | |
95 | * | |
96 | * Using virtual addresses from trampoline.S removes the need | |
97 | * to have any identity mapped pages in the kernel page table | |
98 | * after the boot processor executes this code. | |
1da177e4 LT |
99 | */ |
100 | ||
04633df0 BP |
101 | /* Sanitize CPU configuration */ |
102 | call verify_cpu | |
103 | ||
65ade2f8 | 104 | movq $(init_top_pgt - __START_KERNEL_map), %rax |
8170e6be PA |
105 | 1: |
106 | ||
032370b9 | 107 | /* Enable PAE mode, PGE and LA57 */ |
8170e6be | 108 | movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx |
032370b9 KS |
109 | #ifdef CONFIG_X86_5LEVEL |
110 | orl $X86_CR4_LA57, %ecx | |
111 | #endif | |
8170e6be | 112 | movq %rcx, %cr4 |
1da177e4 | 113 | |
032370b9 | 114 | /* Setup early boot stage 4-/5-level pagetables. */ |
1ab60e0f | 115 | addq phys_base(%rip), %rax |
1da177e4 LT |
116 | movq %rax, %cr3 |
117 | ||
1ab60e0f VG |
118 | /* Ensure I am executing from virtual addresses */ |
119 | movq $1f, %rax | |
120 | jmp *%rax | |
121 | 1: | |
b63a868e | 122 | UNWIND_HINT_EMPTY |
1ab60e0f | 123 | |
1da177e4 LT |
124 | /* Check if nx is implemented */ |
125 | movl $0x80000001, %eax | |
126 | cpuid | |
127 | movl %edx,%edi | |
128 | ||
129 | /* Setup EFER (Extended Feature Enable Register) */ | |
130 | movl $MSR_EFER, %ecx | |
131 | rdmsr | |
1ab60e0f VG |
132 | btsl $_EFER_SCE, %eax /* Enable System Call */ |
133 | btl $20,%edi /* No Execute supported? */ | |
1da177e4 LT |
134 | jnc 1f |
135 | btsl $_EFER_NX, %eax | |
78d77df7 | 136 | btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) |
1ab60e0f | 137 | 1: wrmsr /* Make changes effective */ |
1da177e4 LT |
138 | |
139 | /* Setup cr0 */ | |
369101da | 140 | movl $CR0_STATE, %eax |
1da177e4 LT |
141 | /* Make changes effective */ |
142 | movq %rax, %cr0 | |
143 | ||
144 | /* Setup a boot time stack */ | |
b32f96c7 | 145 | movq initial_stack(%rip), %rsp |
1da177e4 LT |
146 | |
147 | /* zero EFLAGS after setting rsp */ | |
148 | pushq $0 | |
149 | popfq | |
150 | ||
151 | /* | |
152 | * We must switch to a new descriptor in kernel space for the GDT | |
153 | * because soon the kernel won't have access anymore to the userspace | |
154 | * addresses where we're currently running on. We have to do that here | |
155 | * because in 32bit we couldn't load a 64bit linear address. | |
156 | */ | |
a939098a | 157 | lgdt early_gdt_descr(%rip) |
1da177e4 | 158 | |
8ec6993d BG |
159 | /* set up data segments */ |
160 | xorl %eax,%eax | |
ffb60175 ZA |
161 | movl %eax,%ds |
162 | movl %eax,%ss | |
163 | movl %eax,%es | |
164 | ||
165 | /* | |
166 | * We don't really need to load %fs or %gs, but load them anyway | |
167 | * to kill any stale realmode selectors. This allows execution | |
168 | * under VT hardware. | |
169 | */ | |
170 | movl %eax,%fs | |
171 | movl %eax,%gs | |
172 | ||
f32ff538 TH |
173 | /* Set up %gs. |
174 | * | |
947e76cd BG |
175 | * The base of %gs always points to the bottom of the irqstack |
176 | * union. If the stack protector canary is enabled, it is | |
177 | * located at %gs:40. Note that, on SMP, the boot cpu uses | |
178 | * init data section till per cpu areas are set up. | |
f32ff538 | 179 | */ |
1da177e4 | 180 | movl $MSR_GS_BASE,%ecx |
650fb439 BG |
181 | movl initial_gs(%rip),%eax |
182 | movl initial_gs+4(%rip),%edx | |
a9468df5 | 183 | wrmsr |
1da177e4 | 184 | |
8170e6be | 185 | /* rsi is pointer to real mode structure with interesting info. |
1da177e4 | 186 | pass it to C */ |
8170e6be | 187 | movq %rsi, %rdi |
a9468df5 | 188 | |
79d243a0 | 189 | .Ljump_to_C_code: |
a9468df5 JP |
190 | /* |
191 | * Jump to run C code and to be on a real kernel address. | |
1da177e4 | 192 | * Since we are running on identity-mapped space we have to jump |
26374c7b EB |
193 | * to the full 64bit address, this is only possible as indirect |
194 | * jump. In addition we need to ensure %cs is set so we make this | |
195 | * a far return. | |
8170e6be PA |
196 | * |
197 | * Note: do not change to far jump indirect with 64bit offset. | |
198 | * | |
199 | * AMD does not support far jump indirect with 64bit offset. | |
200 | * AMD64 Architecture Programmer's Manual, Volume 3: states only | |
201 | * JMP FAR mem16:16 FF /5 Far jump indirect, | |
202 | * with the target specified by a far pointer in memory. | |
203 | * JMP FAR mem16:32 FF /5 Far jump indirect, | |
204 | * with the target specified by a far pointer in memory. | |
205 | * | |
206 | * Intel64 does support 64bit offset. | |
207 | * Software Developer Manual Vol 2: states: | |
208 | * FF /5 JMP m16:16 Jump far, absolute indirect, | |
209 | * address given in m16:16 | |
210 | * FF /5 JMP m16:32 Jump far, absolute indirect, | |
211 | * address given in m16:32. | |
212 | * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect, | |
213 | * address given in m16:64. | |
1da177e4 | 214 | */ |
31dcfec1 JP |
215 | pushq $.Lafter_lret # put return address on stack for unwinder |
216 | xorq %rbp, %rbp # clear frame pointer | |
595c1e64 | 217 | movq initial_code(%rip), %rax |
26374c7b EB |
218 | pushq $__KERNEL_CS # set correct cs |
219 | pushq %rax # target address in negative space | |
220 | lretq | |
31dcfec1 | 221 | .Lafter_lret: |
707517a5 | 222 | END(secondary_startup_64) |
1da177e4 | 223 | |
04633df0 BP |
224 | #include "verify_cpu.S" |
225 | ||
42e78e97 FY |
226 | #ifdef CONFIG_HOTPLUG_CPU |
227 | /* | |
228 | * Boot CPU0 entry point. It's called from play_dead(). Everything has been set | |
229 | * up already except stack. We just set up stack here. Then call | |
79d243a0 | 230 | * start_secondary() via .Ljump_to_C_code. |
42e78e97 FY |
231 | */ |
232 | ENTRY(start_cpu0) | |
a9468df5 | 233 | movq initial_stack(%rip), %rsp |
b63a868e | 234 | UNWIND_HINT_EMPTY |
79d243a0 | 235 | jmp .Ljump_to_C_code |
42e78e97 FY |
236 | ENDPROC(start_cpu0) |
237 | #endif | |
238 | ||
b32f96c7 | 239 | /* Both SMP bootup and ACPI suspend change these variables */ |
da5968ae | 240 | __REFDATA |
8170e6be PA |
241 | .balign 8 |
242 | GLOBAL(initial_code) | |
1da177e4 | 243 | .quad x86_64_start_kernel |
8170e6be | 244 | GLOBAL(initial_gs) |
2add8e23 | 245 | .quad INIT_PER_CPU_VAR(irq_stack_union) |
b32f96c7 | 246 | GLOBAL(initial_stack) |
22dc3918 JP |
247 | /* |
248 | * The SIZEOF_PTREGS gap is a convention which helps the in-kernel | |
249 | * unwinder reliably detect the end of the stack. | |
250 | */ | |
251 | .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS | |
b9af7c0d | 252 | __FINITDATA |
1da177e4 | 253 | |
8170e6be | 254 | __INIT |
cdeb6048 | 255 | ENTRY(early_idt_handler_array) |
749c970a AK |
256 | i = 0 |
257 | .rept NUM_EXCEPTION_VECTORS | |
981dedac | 258 | .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 |
b63a868e JP |
259 | UNWIND_HINT_IRET_REGS |
260 | pushq $0 # Dummy error code, to make stack frame uniform | |
261 | .else | |
262 | UNWIND_HINT_IRET_REGS offset=8 | |
9900aa2f PA |
263 | .endif |
264 | pushq $i # 72(%rsp) Vector number | |
cdeb6048 | 265 | jmp early_idt_handler_common |
b63a868e | 266 | UNWIND_HINT_IRET_REGS |
749c970a | 267 | i = i + 1 |
cdeb6048 | 268 | .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc |
749c970a | 269 | .endr |
b63a868e | 270 | UNWIND_HINT_IRET_REGS offset=16 |
707517a5 | 271 | END(early_idt_handler_array) |
8866cd9d | 272 | |
cdeb6048 AL |
273 | early_idt_handler_common: |
274 | /* | |
275 | * The stack is the hardware frame, an error code or zero, and the | |
276 | * vector number. | |
277 | */ | |
9900aa2f PA |
278 | cld |
279 | ||
b957591f | 280 | incl early_recursion_flag(%rip) |
9900aa2f | 281 | |
7bbcdb1c AL |
282 | /* The vector number is currently in the pt_regs->di slot. */ |
283 | pushq %rsi /* pt_regs->si */ | |
284 | movq 8(%rsp), %rsi /* RSI = vector number */ | |
285 | movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ | |
286 | pushq %rdx /* pt_regs->dx */ | |
287 | pushq %rcx /* pt_regs->cx */ | |
288 | pushq %rax /* pt_regs->ax */ | |
289 | pushq %r8 /* pt_regs->r8 */ | |
290 | pushq %r9 /* pt_regs->r9 */ | |
291 | pushq %r10 /* pt_regs->r10 */ | |
292 | pushq %r11 /* pt_regs->r11 */ | |
293 | pushq %rbx /* pt_regs->bx */ | |
294 | pushq %rbp /* pt_regs->bp */ | |
295 | pushq %r12 /* pt_regs->r12 */ | |
296 | pushq %r13 /* pt_regs->r13 */ | |
297 | pushq %r14 /* pt_regs->r14 */ | |
298 | pushq %r15 /* pt_regs->r15 */ | |
b63a868e | 299 | UNWIND_HINT_REGS |
7bbcdb1c | 300 | |
7bbcdb1c | 301 | cmpq $14,%rsi /* Page fault? */ |
8170e6be | 302 | jnz 10f |
7bbcdb1c | 303 | GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */ |
8170e6be PA |
304 | call early_make_pgtable |
305 | andl %eax,%eax | |
7bbcdb1c | 306 | jz 20f /* All good */ |
9900aa2f | 307 | |
8170e6be | 308 | 10: |
7bbcdb1c | 309 | movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ |
9900aa2f | 310 | call early_fixup_exception |
076f9776 | 311 | |
0e861fbb | 312 | 20: |
9900aa2f | 313 | decl early_recursion_flag(%rip) |
64adfba0 | 314 | jmp restore_regs_and_return_to_kernel |
707517a5 | 315 | END(early_idt_handler_common) |
9900aa2f | 316 | |
8170e6be PA |
317 | __INITDATA |
318 | ||
9900aa2f | 319 | .balign 4 |
0e861fbb | 320 | GLOBAL(early_recursion_flag) |
b957591f | 321 | .long 0 |
1da177e4 | 322 | |
f0cf5d1a | 323 | #define NEXT_PAGE(name) \ |
67dcbb6b | 324 | .balign PAGE_SIZE; \ |
8170e6be | 325 | GLOBAL(name) |
f0cf5d1a | 326 | |
0bd4b34e DH |
327 | #ifdef CONFIG_PAGE_TABLE_ISOLATION |
328 | /* | |
329 | * Each PGD needs to be 8k long and 8k aligned. We do not | |
330 | * ever go out to userspace with these, so we do not | |
331 | * strictly *need* the second page, but this allows us to | |
332 | * have a single set_pgd() implementation that does not | |
333 | * need to worry about whether it has 4k or 8k to work | |
334 | * with. | |
335 | * | |
336 | * This ensures PGDs are 8k long: | |
337 | */ | |
338 | #define PTI_USER_PGD_FILL 512 | |
339 | /* This ensures they are 8k-aligned: */ | |
340 | #define NEXT_PGD_PAGE(name) \ | |
341 | .balign 2 * PAGE_SIZE; \ | |
342 | GLOBAL(name) | |
343 | #else | |
344 | #define NEXT_PGD_PAGE(name) NEXT_PAGE(name) | |
345 | #define PTI_USER_PGD_FILL 0 | |
346 | #endif | |
347 | ||
67dcbb6b | 348 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
0e192b99 CG |
349 | #define PMDS(START, PERM, COUNT) \ |
350 | i = 0 ; \ | |
351 | .rept (COUNT) ; \ | |
352 | .quad (START) + (i << PMD_SHIFT) + (PERM) ; \ | |
353 | i = i + 1 ; \ | |
67dcbb6b VG |
354 | .endr |
355 | ||
8170e6be | 356 | __INITDATA |
0bd4b34e | 357 | NEXT_PGD_PAGE(early_top_pgt) |
8170e6be | 358 | .fill 511,8,0 |
032370b9 KS |
359 | #ifdef CONFIG_X86_5LEVEL |
360 | .quad level4_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE | |
361 | #else | |
8170e6be | 362 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE |
032370b9 | 363 | #endif |
0bd4b34e | 364 | .fill PTI_USER_PGD_FILL,8,0 |
8170e6be PA |
365 | |
366 | NEXT_PAGE(early_dynamic_pgts) | |
367 | .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 | |
368 | ||
b9af7c0d | 369 | .data |
8170e6be | 370 | |
a883ee7f | 371 | #if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH) |
0bd4b34e | 372 | NEXT_PGD_PAGE(init_top_pgt) |
8170e6be | 373 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
032370b9 | 374 | .org init_top_pgt + PGD_PAGE_OFFSET*8, 0 |
8170e6be | 375 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
032370b9 | 376 | .org init_top_pgt + PGD_START_KERNEL*8, 0 |
cfd243d4 | 377 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ |
8170e6be | 378 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE |
0bd4b34e | 379 | .fill PTI_USER_PGD_FILL,8,0 |
1da177e4 | 380 | |
f0cf5d1a | 381 | NEXT_PAGE(level3_ident_pgt) |
67dcbb6b | 382 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
8170e6be PA |
383 | .fill 511, 8, 0 |
384 | NEXT_PAGE(level2_ident_pgt) | |
385 | /* Since I easily can, map the first 1G. | |
386 | * Don't set NX because code runs from these pages. | |
387 | */ | |
388 | PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) | |
a883ee7f | 389 | #else |
0bd4b34e | 390 | NEXT_PGD_PAGE(init_top_pgt) |
a883ee7f | 391 | .fill 512,8,0 |
0bd4b34e | 392 | .fill PTI_USER_PGD_FILL,8,0 |
8170e6be | 393 | #endif |
1da177e4 | 394 | |
032370b9 KS |
395 | #ifdef CONFIG_X86_5LEVEL |
396 | NEXT_PAGE(level4_kernel_pgt) | |
397 | .fill 511,8,0 | |
398 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE | |
399 | #endif | |
400 | ||
f0cf5d1a | 401 | NEXT_PAGE(level3_kernel_pgt) |
a6523748 | 402 | .fill L3_START_KERNEL,8,0 |
1da177e4 | 403 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ |
67dcbb6b | 404 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE |
b1c931e3 EB |
405 | .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE |
406 | ||
f0cf5d1a | 407 | NEXT_PAGE(level2_kernel_pgt) |
88f3aec7 | 408 | /* |
85eb69a1 | 409 | * 512 MB kernel mapping. We spend a full page on this pagetable |
88f3aec7 IM |
410 | * anyway. |
411 | * | |
412 | * The kernel code+data+bss must not be bigger than that. | |
413 | * | |
85eb69a1 | 414 | * (NOTE: at +512MB starts the module area, see MODULES_VADDR. |
88f3aec7 IM |
415 | * If you want to increase this then increase MODULES_VADDR |
416 | * too.) | |
417 | */ | |
8490638c | 418 | PMDS(0, __PAGE_KERNEL_LARGE_EXEC, |
d4afe414 | 419 | KERNEL_IMAGE_SIZE/PMD_SIZE) |
1da177e4 | 420 | |
8170e6be PA |
421 | NEXT_PAGE(level2_fixmap_pgt) |
422 | .fill 506,8,0 | |
423 | .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE | |
424 | /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ | |
425 | .fill 5,8,0 | |
426 | ||
427 | NEXT_PAGE(level1_fixmap_pgt) | |
428 | .fill 512,8,0 | |
1ab60e0f | 429 | |
67dcbb6b | 430 | #undef PMDS |
1da177e4 | 431 | |
f0cf5d1a | 432 | .data |
1da177e4 | 433 | .align 16 |
a939098a GC |
434 | .globl early_gdt_descr |
435 | early_gdt_descr: | |
436 | .word GDT_ENTRIES*8-1 | |
3e5d8f97 | 437 | early_gdt_descr_base: |
2add8e23 | 438 | .quad INIT_PER_CPU_VAR(gdt_page) |
1da177e4 | 439 | |
1ab60e0f VG |
440 | ENTRY(phys_base) |
441 | /* This must match the first entry in level2_kernel_pgt */ | |
442 | .quad 0x0000000000000000 | |
784d5699 | 443 | EXPORT_SYMBOL(phys_base) |
1ab60e0f | 444 | |
8c5e5ac3 | 445 | #include "../../x86/xen/xen-head.S" |
b63a868e | 446 | |
02b7da37 | 447 | __PAGE_ALIGNED_BSS |
8170e6be | 448 | NEXT_PAGE(empty_zero_page) |
e57113bc | 449 | .skip PAGE_SIZE |
784d5699 | 450 | EXPORT_SYMBOL(empty_zero_page) |
ef7f0d6a | 451 |