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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit | |
3 | * | |
4 | * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE | |
5 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
6 | * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> | |
7 | * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> | |
1ab60e0f | 8 | * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> |
1da177e4 LT |
9 | */ |
10 | ||
11 | ||
12 | #include <linux/linkage.h> | |
13 | #include <linux/threads.h> | |
f6c2e333 | 14 | #include <linux/init.h> |
1da177e4 LT |
15 | #include <asm/desc.h> |
16 | #include <asm/segment.h> | |
67dcbb6b | 17 | #include <asm/pgtable.h> |
1da177e4 LT |
18 | #include <asm/page.h> |
19 | #include <asm/msr.h> | |
20 | #include <asm/cache.h> | |
1ab60e0f | 21 | |
49a69787 GOC |
22 | #ifdef CONFIG_PARAVIRT |
23 | #include <asm/asm-offsets.h> | |
24 | #include <asm/paravirt.h> | |
25 | #else | |
26 | #define GET_CR2_INTO_RCX movq %cr2, %rcx | |
27 | #endif | |
28 | ||
1da177e4 | 29 | /* we are not able to switch in one step to the final KERNEL ADRESS SPACE |
1ab60e0f VG |
30 | * because we need identity-mapped pages. |
31 | * | |
1da177e4 LT |
32 | */ |
33 | ||
34 | .text | |
92417df0 | 35 | .section .text.head |
1ab60e0f VG |
36 | .code64 |
37 | .globl startup_64 | |
38 | startup_64: | |
39 | ||
1da177e4 | 40 | /* |
1ab60e0f VG |
41 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, |
42 | * and someone has loaded an identity mapped page table | |
43 | * for us. These identity mapped page tables map all of the | |
44 | * kernel pages and possibly all of memory. | |
45 | * | |
46 | * %esi holds a physical pointer to real_mode_data. | |
47 | * | |
48 | * We come here either directly from a 64bit bootloader, or from | |
49 | * arch/x86_64/boot/compressed/head.S. | |
50 | * | |
51 | * We only come here initially at boot nothing else comes here. | |
52 | * | |
53 | * Since we may be loaded at an address different from what we were | |
54 | * compiled to run at we first fixup the physical addresses in our page | |
55 | * tables and then reload them. | |
1da177e4 LT |
56 | */ |
57 | ||
1ab60e0f VG |
58 | /* Compute the delta between the address I am compiled to run at and the |
59 | * address I am actually running at. | |
1da177e4 | 60 | */ |
1ab60e0f VG |
61 | leaq _text(%rip), %rbp |
62 | subq $_text - __START_KERNEL_map, %rbp | |
63 | ||
64 | /* Is the address not 2M aligned? */ | |
65 | movq %rbp, %rax | |
31422c51 | 66 | andl $~PMD_PAGE_MASK, %eax |
1ab60e0f VG |
67 | testl %eax, %eax |
68 | jnz bad_address | |
69 | ||
70 | /* Is the address too large? */ | |
71 | leaq _text(%rip), %rdx | |
72 | movq $PGDIR_SIZE, %rax | |
73 | cmpq %rax, %rdx | |
74 | jae bad_address | |
75 | ||
76 | /* Fixup the physical addresses in the page table | |
1da177e4 | 77 | */ |
1ab60e0f VG |
78 | addq %rbp, init_level4_pgt + 0(%rip) |
79 | addq %rbp, init_level4_pgt + (258*8)(%rip) | |
80 | addq %rbp, init_level4_pgt + (511*8)(%rip) | |
81 | ||
82 | addq %rbp, level3_ident_pgt + 0(%rip) | |
b1c931e3 | 83 | |
1ab60e0f | 84 | addq %rbp, level3_kernel_pgt + (510*8)(%rip) |
b1c931e3 EB |
85 | addq %rbp, level3_kernel_pgt + (511*8)(%rip) |
86 | ||
87 | addq %rbp, level2_fixmap_pgt + (506*8)(%rip) | |
1ab60e0f VG |
88 | |
89 | /* Add an Identity mapping if I am above 1G */ | |
90 | leaq _text(%rip), %rdi | |
31422c51 | 91 | andq $PMD_PAGE_MASK, %rdi |
1ab60e0f VG |
92 | |
93 | movq %rdi, %rax | |
94 | shrq $PUD_SHIFT, %rax | |
95 | andq $(PTRS_PER_PUD - 1), %rax | |
96 | jz ident_complete | |
97 | ||
98 | leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx | |
99 | leaq level3_ident_pgt(%rip), %rbx | |
100 | movq %rdx, 0(%rbx, %rax, 8) | |
101 | ||
102 | movq %rdi, %rax | |
103 | shrq $PMD_SHIFT, %rax | |
104 | andq $(PTRS_PER_PMD - 1), %rax | |
105 | leaq __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx | |
106 | leaq level2_spare_pgt(%rip), %rbx | |
107 | movq %rdx, 0(%rbx, %rax, 8) | |
108 | ident_complete: | |
109 | ||
110 | /* Fixup the kernel text+data virtual addresses | |
111 | */ | |
112 | leaq level2_kernel_pgt(%rip), %rdi | |
113 | leaq 4096(%rdi), %r8 | |
114 | /* See if it is a valid page table entry */ | |
115 | 1: testq $1, 0(%rdi) | |
116 | jz 2f | |
117 | addq %rbp, 0(%rdi) | |
118 | /* Go to the next page */ | |
119 | 2: addq $8, %rdi | |
120 | cmp %r8, %rdi | |
121 | jne 1b | |
122 | ||
123 | /* Fixup phys_base */ | |
124 | addq %rbp, phys_base(%rip) | |
1da177e4 | 125 | |
1ab60e0f VG |
126 | #ifdef CONFIG_SMP |
127 | addq %rbp, trampoline_level4_pgt + 0(%rip) | |
128 | addq %rbp, trampoline_level4_pgt + (511*8)(%rip) | |
129 | #endif | |
673d5b43 | 130 | #ifdef CONFIG_ACPI_SLEEP |
1ab60e0f VG |
131 | addq %rbp, wakeup_level4_pgt + 0(%rip) |
132 | addq %rbp, wakeup_level4_pgt + (511*8)(%rip) | |
133 | #endif | |
1da177e4 | 134 | |
1ab60e0f VG |
135 | /* Due to ENTRY(), sometimes the empty space gets filled with |
136 | * zeros. Better take a jmp than relying on empty space being | |
137 | * filled with 0x90 (nop) | |
1da177e4 | 138 | */ |
1ab60e0f | 139 | jmp secondary_startup_64 |
90b1c208 | 140 | ENTRY(secondary_startup_64) |
1ab60e0f VG |
141 | /* |
142 | * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1, | |
143 | * and someone has loaded a mapped page table. | |
144 | * | |
145 | * %esi holds a physical pointer to real_mode_data. | |
146 | * | |
147 | * We come here either from startup_64 (using physical addresses) | |
148 | * or from trampoline.S (using virtual addresses). | |
149 | * | |
150 | * Using virtual addresses from trampoline.S removes the need | |
151 | * to have any identity mapped pages in the kernel page table | |
152 | * after the boot processor executes this code. | |
1da177e4 LT |
153 | */ |
154 | ||
155 | /* Enable PAE mode and PGE */ | |
156 | xorq %rax, %rax | |
157 | btsq $5, %rax | |
158 | btsq $7, %rax | |
159 | movq %rax, %cr4 | |
160 | ||
161 | /* Setup early boot stage 4 level pagetables. */ | |
cfd243d4 | 162 | movq $(init_level4_pgt - __START_KERNEL_map), %rax |
1ab60e0f | 163 | addq phys_base(%rip), %rax |
1da177e4 LT |
164 | movq %rax, %cr3 |
165 | ||
1ab60e0f VG |
166 | /* Ensure I am executing from virtual addresses */ |
167 | movq $1f, %rax | |
168 | jmp *%rax | |
169 | 1: | |
170 | ||
1da177e4 LT |
171 | /* Check if nx is implemented */ |
172 | movl $0x80000001, %eax | |
173 | cpuid | |
174 | movl %edx,%edi | |
175 | ||
176 | /* Setup EFER (Extended Feature Enable Register) */ | |
177 | movl $MSR_EFER, %ecx | |
178 | rdmsr | |
1ab60e0f VG |
179 | btsl $_EFER_SCE, %eax /* Enable System Call */ |
180 | btl $20,%edi /* No Execute supported? */ | |
1da177e4 LT |
181 | jnc 1f |
182 | btsl $_EFER_NX, %eax | |
1ab60e0f | 183 | 1: wrmsr /* Make changes effective */ |
1da177e4 LT |
184 | |
185 | /* Setup cr0 */ | |
3829ee6b AK |
186 | #define CR0_PM 1 /* protected mode */ |
187 | #define CR0_MP (1<<1) | |
188 | #define CR0_ET (1<<4) | |
189 | #define CR0_NE (1<<5) | |
190 | #define CR0_WP (1<<16) | |
191 | #define CR0_AM (1<<18) | |
192 | #define CR0_PAGING (1<<31) | |
193 | movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax | |
1da177e4 LT |
194 | /* Make changes effective */ |
195 | movq %rax, %cr0 | |
196 | ||
197 | /* Setup a boot time stack */ | |
198 | movq init_rsp(%rip),%rsp | |
199 | ||
200 | /* zero EFLAGS after setting rsp */ | |
201 | pushq $0 | |
202 | popfq | |
203 | ||
204 | /* | |
205 | * We must switch to a new descriptor in kernel space for the GDT | |
206 | * because soon the kernel won't have access anymore to the userspace | |
207 | * addresses where we're currently running on. We have to do that here | |
208 | * because in 32bit we couldn't load a 64bit linear address. | |
209 | */ | |
1ab60e0f | 210 | lgdt cpu_gdt_descr(%rip) |
1da177e4 | 211 | |
ffb60175 ZA |
212 | /* set up data segments. actually 0 would do too */ |
213 | movl $__KERNEL_DS,%eax | |
214 | movl %eax,%ds | |
215 | movl %eax,%ss | |
216 | movl %eax,%es | |
217 | ||
218 | /* | |
219 | * We don't really need to load %fs or %gs, but load them anyway | |
220 | * to kill any stale realmode selectors. This allows execution | |
221 | * under VT hardware. | |
222 | */ | |
223 | movl %eax,%fs | |
224 | movl %eax,%gs | |
225 | ||
1da177e4 LT |
226 | /* |
227 | * Setup up a dummy PDA. this is just for some early bootup code | |
228 | * that does in_interrupt() | |
229 | */ | |
230 | movl $MSR_GS_BASE,%ecx | |
231 | movq $empty_zero_page,%rax | |
232 | movq %rax,%rdx | |
233 | shrq $32,%rdx | |
234 | wrmsr | |
235 | ||
1da177e4 LT |
236 | /* esi is pointer to real mode structure with interesting info. |
237 | pass it to C */ | |
238 | movl %esi, %edi | |
239 | ||
240 | /* Finally jump to run C code and to be on real kernel address | |
241 | * Since we are running on identity-mapped space we have to jump | |
26374c7b EB |
242 | * to the full 64bit address, this is only possible as indirect |
243 | * jump. In addition we need to ensure %cs is set so we make this | |
244 | * a far return. | |
1da177e4 LT |
245 | */ |
246 | movq initial_code(%rip),%rax | |
26374c7b EB |
247 | pushq $0 # fake return address to stop unwinder |
248 | pushq $__KERNEL_CS # set correct cs | |
249 | pushq %rax # target address in negative space | |
250 | lretq | |
1da177e4 | 251 | |
e57113bc | 252 | /* SMP bootup changes these two */ |
f1fbabb3 | 253 | __CPUINITDATA |
e57113bc | 254 | .align 8 |
f1fbabb3 | 255 | ENTRY(initial_code) |
1da177e4 | 256 | .quad x86_64_start_kernel |
f1fbabb3 SR |
257 | __FINITDATA |
258 | ||
259 | ENTRY(init_rsp) | |
1da177e4 LT |
260 | .quad init_thread_union+THREAD_SIZE-8 |
261 | ||
1ab60e0f VG |
262 | bad_address: |
263 | jmp bad_address | |
264 | ||
076f9776 | 265 | #ifdef CONFIG_EARLY_PRINTK |
8866cd9d RM |
266 | .macro early_idt_tramp first, last |
267 | .ifgt \last-\first | |
268 | early_idt_tramp \first, \last-1 | |
269 | .endif | |
270 | movl $\last,%esi | |
271 | jmp early_idt_handler | |
272 | .endm | |
273 | ||
274 | .globl early_idt_handlers | |
275 | early_idt_handlers: | |
276 | early_idt_tramp 0, 63 | |
277 | early_idt_tramp 64, 127 | |
278 | early_idt_tramp 128, 191 | |
279 | early_idt_tramp 192, 255 | |
076f9776 | 280 | #endif |
8866cd9d | 281 | |
1da177e4 | 282 | ENTRY(early_idt_handler) |
076f9776 | 283 | #ifdef CONFIG_EARLY_PRINTK |
b957591f AK |
284 | cmpl $2,early_recursion_flag(%rip) |
285 | jz 1f | |
286 | incl early_recursion_flag(%rip) | |
49a69787 | 287 | GET_CR2_INTO_RCX |
8866cd9d RM |
288 | movq %rcx,%r9 |
289 | xorl %r8d,%r8d # zero for error code | |
290 | movl %esi,%ecx # get vector number | |
291 | # Test %ecx against mask of vectors that push error code. | |
292 | cmpl $31,%ecx | |
293 | ja 0f | |
294 | movl $1,%eax | |
295 | salq %cl,%rax | |
296 | testl $0x27d00,%eax | |
297 | je 0f | |
298 | popq %r8 # get error code | |
299 | 0: movq 0(%rsp),%rcx # get ip | |
300 | movq 8(%rsp),%rdx # get cs | |
301 | xorl %eax,%eax | |
1da177e4 LT |
302 | leaq early_idt_msg(%rip),%rdi |
303 | call early_printk | |
b957591f AK |
304 | cmpl $2,early_recursion_flag(%rip) |
305 | jz 1f | |
306 | call dump_stack | |
6574ffd7 AK |
307 | #ifdef CONFIG_KALLSYMS |
308 | leaq early_idt_ripmsg(%rip),%rdi | |
309 | movq 8(%rsp),%rsi # get rip again | |
310 | call __print_symbol | |
311 | #endif | |
076f9776 | 312 | #endif /* EARLY_PRINTK */ |
1da177e4 LT |
313 | 1: hlt |
314 | jmp 1b | |
076f9776 IM |
315 | |
316 | #ifdef CONFIG_EARLY_PRINTK | |
b957591f AK |
317 | early_recursion_flag: |
318 | .long 0 | |
1da177e4 LT |
319 | |
320 | early_idt_msg: | |
8866cd9d | 321 | .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n" |
6574ffd7 AK |
322 | early_idt_ripmsg: |
323 | .asciz "RIP %s\n" | |
076f9776 | 324 | #endif /* CONFIG_EARLY_PRINTK */ |
1da177e4 | 325 | |
1ab60e0f | 326 | .balign PAGE_SIZE |
1da177e4 | 327 | |
f0cf5d1a | 328 | #define NEXT_PAGE(name) \ |
67dcbb6b | 329 | .balign PAGE_SIZE; \ |
f0cf5d1a JB |
330 | ENTRY(name) |
331 | ||
67dcbb6b VG |
332 | /* Automate the creation of 1 to 1 mapping pmd entries */ |
333 | #define PMDS(START, PERM, COUNT) \ | |
334 | i = 0 ; \ | |
335 | .rept (COUNT) ; \ | |
336 | .quad (START) + (i << 21) + (PERM) ; \ | |
337 | i = i + 1 ; \ | |
338 | .endr | |
339 | ||
cfd243d4 VG |
340 | /* |
341 | * This default setting generates an ident mapping at address 0x100000 | |
342 | * and a mapping for the kernel that precisely maps virtual address | |
343 | * 0xffffffff80000000 to physical address 0x000000. (always using | |
344 | * 2Mbyte large pages provided by PAE mode) | |
345 | */ | |
f0cf5d1a | 346 | NEXT_PAGE(init_level4_pgt) |
cfd243d4 VG |
347 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
348 | .fill 257,8,0 | |
349 | .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE | |
350 | .fill 252,8,0 | |
351 | /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ | |
352 | .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE | |
1da177e4 | 353 | |
f0cf5d1a | 354 | NEXT_PAGE(level3_ident_pgt) |
67dcbb6b | 355 | .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE |
1da177e4 LT |
356 | .fill 511,8,0 |
357 | ||
f0cf5d1a | 358 | NEXT_PAGE(level3_kernel_pgt) |
1da177e4 LT |
359 | .fill 510,8,0 |
360 | /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ | |
67dcbb6b | 361 | .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE |
b1c931e3 EB |
362 | .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE |
363 | ||
364 | NEXT_PAGE(level2_fixmap_pgt) | |
365 | .fill 506,8,0 | |
366 | .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE | |
367 | /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */ | |
368 | .fill 5,8,0 | |
369 | ||
370 | NEXT_PAGE(level1_fixmap_pgt) | |
371 | .fill 512,8,0 | |
1da177e4 | 372 | |
f0cf5d1a | 373 | NEXT_PAGE(level2_ident_pgt) |
67dcbb6b VG |
374 | /* Since I easily can, map the first 1G. |
375 | * Don't set NX because code runs from these pages. | |
376 | */ | |
377 | PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD) | |
1ab60e0f | 378 | |
f0cf5d1a | 379 | NEXT_PAGE(level2_kernel_pgt) |
1da177e4 LT |
380 | /* 40MB kernel mapping. The kernel code cannot be bigger than that. |
381 | When you change this change KERNEL_TEXT_SIZE in page.h too. */ | |
382 | /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */ | |
6e351535 | 383 | PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL, KERNEL_TEXT_SIZE/PMD_SIZE) |
1da177e4 | 384 | /* Module mapping starts here */ |
67dcbb6b | 385 | .fill (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0 |
1da177e4 | 386 | |
1ab60e0f VG |
387 | NEXT_PAGE(level2_spare_pgt) |
388 | .fill 512,8,0 | |
389 | ||
67dcbb6b | 390 | #undef PMDS |
f0cf5d1a | 391 | #undef NEXT_PAGE |
1da177e4 | 392 | |
f0cf5d1a | 393 | .data |
1da177e4 LT |
394 | .align 16 |
395 | .globl cpu_gdt_descr | |
396 | cpu_gdt_descr: | |
e57113bc | 397 | .word gdt_end-cpu_gdt_table-1 |
1da177e4 LT |
398 | gdt: |
399 | .quad cpu_gdt_table | |
400 | #ifdef CONFIG_SMP | |
401 | .rept NR_CPUS-1 | |
402 | .word 0 | |
403 | .quad 0 | |
404 | .endr | |
405 | #endif | |
406 | ||
1ab60e0f VG |
407 | ENTRY(phys_base) |
408 | /* This must match the first entry in level2_kernel_pgt */ | |
409 | .quad 0x0000000000000000 | |
410 | ||
1da177e4 LT |
411 | /* We need valid kernel segments for data and code in long mode too |
412 | * IRET will check the segment types kkeil 2000/10/28 | |
413 | * Also sysret mandates a special GDT layout | |
414 | */ | |
415 | ||
e57113bc JB |
416 | .section .data.page_aligned, "aw" |
417 | .align PAGE_SIZE | |
1da177e4 LT |
418 | |
419 | /* The TLS descriptors are currently at a different place compared to i386. | |
420 | Hopefully nobody expects them at a fixed place (Wine?) */ | |
421 | ||
422 | ENTRY(cpu_gdt_table) | |
423 | .quad 0x0000000000000000 /* NULL descriptor */ | |
30f47289 VG |
424 | .quad 0x00cf9b000000ffff /* __KERNEL32_CS */ |
425 | .quad 0x00af9b000000ffff /* __KERNEL_CS */ | |
426 | .quad 0x00cf93000000ffff /* __KERNEL_DS */ | |
427 | .quad 0x00cffb000000ffff /* __USER32_CS */ | |
428 | .quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */ | |
429 | .quad 0x00affb000000ffff /* __USER_CS */ | |
cdc4b9c0 | 430 | .quad 0x0 /* unused */ |
1da177e4 LT |
431 | .quad 0,0 /* TSS */ |
432 | .quad 0,0 /* LDT */ | |
433 | .quad 0,0,0 /* three TLS descriptors */ | |
c08c8205 | 434 | .quad 0x0000f40000000000 /* node/CPU stored in limit */ |
1da177e4 LT |
435 | gdt_end: |
436 | /* asm/segment.h:GDT_ENTRIES must match this */ | |
437 | /* This should be a multiple of the cache line size */ | |
c11efdf9 RT |
438 | /* GDTs of other CPUs are now dynamically allocated */ |
439 | ||
440 | /* zero the remaining page */ | |
441 | .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0 | |
1da177e4 | 442 | |
e57113bc JB |
443 | .section .bss, "aw", @nobits |
444 | .align L1_CACHE_BYTES | |
445 | ENTRY(idt_table) | |
446 | .skip 256 * 16 | |
1da177e4 | 447 | |
e57113bc JB |
448 | .section .bss.page_aligned, "aw", @nobits |
449 | .align PAGE_SIZE | |
450 | ENTRY(empty_zero_page) | |
451 | .skip PAGE_SIZE |