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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 IM |
3 | #include <linux/interrupt.h> |
4 | #include <linux/sysdev.h> | |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 | 6 | #include <linux/errno.h> |
334955ef | 7 | #include <linux/i8253.h> |
5a0e3ad6 | 8 | #include <linux/slab.h> |
5d0cf410 JS |
9 | #include <linux/hpet.h> |
10 | #include <linux/init.h> | |
58ac1e76 | 11 | #include <linux/cpu.h> |
4588c1f0 IM |
12 | #include <linux/pm.h> |
13 | #include <linux/io.h> | |
5d0cf410 | 14 | |
28769149 | 15 | #include <asm/fixmap.h> |
4588c1f0 | 16 | #include <asm/hpet.h> |
16f871bc | 17 | #include <asm/time.h> |
5d0cf410 | 18 | |
4588c1f0 | 19 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 20 | |
b10db7f0 PM |
21 | /* FSEC = 10^-15 |
22 | NSEC = 10^-9 */ | |
4588c1f0 | 23 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 24 | |
26afe5f2 | 25 | #define HPET_DEV_USED_BIT 2 |
26 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
27 | #define HPET_DEV_VALID 0x8 | |
28 | #define HPET_DEV_FSB_CAP 0x1000 | |
29 | #define HPET_DEV_PERI_CAP 0x2000 | |
30 | ||
f1c18071 TG |
31 | #define HPET_MIN_CYCLES 128 |
32 | #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) | |
33 | ||
26afe5f2 | 34 | #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) |
35 | ||
e9e2cdb4 TG |
36 | /* |
37 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
38 | */ | |
4588c1f0 | 39 | unsigned long hpet_address; |
c8bc6f3c | 40 | u8 hpet_blockid; /* OS timer block num */ |
73472a46 PV |
41 | u8 hpet_msi_disable; |
42 | ||
e951e4af | 43 | #ifdef CONFIG_PCI_MSI |
3b71e9e3 | 44 | static unsigned long hpet_num_timers; |
e951e4af | 45 | #endif |
4588c1f0 | 46 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 47 | |
58ac1e76 | 48 | struct hpet_dev { |
4588c1f0 IM |
49 | struct clock_event_device evt; |
50 | unsigned int num; | |
51 | int cpu; | |
52 | unsigned int irq; | |
53 | unsigned int flags; | |
54 | char name[10]; | |
58ac1e76 | 55 | }; |
56 | ||
5946fa3d | 57 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
58 | { |
59 | return readl(hpet_virt_address + a); | |
60 | } | |
61 | ||
5946fa3d | 62 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
63 | { |
64 | writel(d, hpet_virt_address + a); | |
65 | } | |
66 | ||
28769149 | 67 | #ifdef CONFIG_X86_64 |
28769149 | 68 | #include <asm/pgtable.h> |
2387ce57 | 69 | #endif |
28769149 | 70 | |
06a24dec TG |
71 | static inline void hpet_set_mapping(void) |
72 | { | |
73 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 | 74 | #ifdef CONFIG_X86_64 |
d319bb79 | 75 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE); |
2387ce57 | 76 | #endif |
06a24dec TG |
77 | } |
78 | ||
79 | static inline void hpet_clear_mapping(void) | |
80 | { | |
81 | iounmap(hpet_virt_address); | |
82 | hpet_virt_address = NULL; | |
83 | } | |
84 | ||
e9e2cdb4 TG |
85 | /* |
86 | * HPET command line enable / disable | |
87 | */ | |
88 | static int boot_hpet_disable; | |
b17530bd | 89 | int hpet_force_user; |
b98103a5 | 90 | static int hpet_verbose; |
e9e2cdb4 | 91 | |
4588c1f0 | 92 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
93 | { |
94 | if (str) { | |
95 | if (!strncmp("disable", str, 7)) | |
96 | boot_hpet_disable = 1; | |
b17530bd TG |
97 | if (!strncmp("force", str, 5)) |
98 | hpet_force_user = 1; | |
b98103a5 AH |
99 | if (!strncmp("verbose", str, 7)) |
100 | hpet_verbose = 1; | |
e9e2cdb4 TG |
101 | } |
102 | return 1; | |
103 | } | |
104 | __setup("hpet=", hpet_setup); | |
105 | ||
28769149 TG |
106 | static int __init disable_hpet(char *str) |
107 | { | |
108 | boot_hpet_disable = 1; | |
109 | return 1; | |
110 | } | |
111 | __setup("nohpet", disable_hpet); | |
112 | ||
e9e2cdb4 TG |
113 | static inline int is_hpet_capable(void) |
114 | { | |
4588c1f0 | 115 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
116 | } |
117 | ||
118 | /* | |
119 | * HPET timer interrupt enable / disable | |
120 | */ | |
121 | static int hpet_legacy_int_enabled; | |
122 | ||
123 | /** | |
124 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
125 | */ | |
126 | int is_hpet_enabled(void) | |
127 | { | |
128 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
129 | } | |
1bdbdaac | 130 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 131 | |
b98103a5 AH |
132 | static void _hpet_print_config(const char *function, int line) |
133 | { | |
134 | u32 i, timers, l, h; | |
135 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
136 | l = hpet_readl(HPET_ID); | |
137 | h = hpet_readl(HPET_PERIOD); | |
138 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
139 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
140 | l = hpet_readl(HPET_CFG); | |
141 | h = hpet_readl(HPET_STATUS); | |
142 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
143 | l = hpet_readl(HPET_COUNTER); | |
144 | h = hpet_readl(HPET_COUNTER+4); | |
145 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
146 | ||
147 | for (i = 0; i < timers; i++) { | |
148 | l = hpet_readl(HPET_Tn_CFG(i)); | |
149 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
150 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
151 | i, l, h); | |
152 | l = hpet_readl(HPET_Tn_CMP(i)); | |
153 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
154 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
155 | i, l, h); | |
156 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
157 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
158 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
159 | i, l, h); | |
160 | } | |
161 | } | |
162 | ||
163 | #define hpet_print_config() \ | |
164 | do { \ | |
165 | if (hpet_verbose) \ | |
166 | _hpet_print_config(__FUNCTION__, __LINE__); \ | |
167 | } while (0) | |
168 | ||
e9e2cdb4 TG |
169 | /* |
170 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
171 | * timer 0 and timer 1 in case of RTC emulation. | |
172 | */ | |
173 | #ifdef CONFIG_HPET | |
f0ed4e69 | 174 | |
5f79f2f2 | 175 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 176 | |
5946fa3d | 177 | static void hpet_reserve_platform_timers(unsigned int id) |
e9e2cdb4 TG |
178 | { |
179 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
180 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
181 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
182 | struct hpet_data hd; |
183 | ||
184 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
185 | ||
4588c1f0 IM |
186 | memset(&hd, 0, sizeof(hd)); |
187 | hd.hd_phys_address = hpet_address; | |
188 | hd.hd_address = hpet; | |
189 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
190 | hpet_reserve_timer(&hd, 0); |
191 | ||
192 | #ifdef CONFIG_HPET_EMULATE_RTC | |
193 | hpet_reserve_timer(&hd, 1); | |
194 | #endif | |
5761d64b | 195 | |
64a76f66 DB |
196 | /* |
197 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
198 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
199 | * don't bother configuring *any* comparator interrupts. | |
200 | */ | |
e9e2cdb4 TG |
201 | hd.hd_irq[0] = HPET_LEGACY_8254; |
202 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
203 | ||
fc3fbc45 | 204 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
205 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
206 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 207 | } |
5761d64b | 208 | |
f0ed4e69 | 209 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 210 | |
e9e2cdb4 | 211 | hpet_alloc(&hd); |
5761d64b | 212 | |
e9e2cdb4 TG |
213 | } |
214 | #else | |
5946fa3d | 215 | static void hpet_reserve_platform_timers(unsigned int id) { } |
e9e2cdb4 TG |
216 | #endif |
217 | ||
218 | /* | |
219 | * Common hpet info | |
220 | */ | |
ab0e08f1 | 221 | static unsigned long hpet_freq; |
e9e2cdb4 | 222 | |
610bf2f1 | 223 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 224 | struct clock_event_device *evt); |
610bf2f1 | 225 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
226 | struct clock_event_device *evt); |
227 | ||
228 | /* | |
229 | * The hpet clock event device | |
230 | */ | |
231 | static struct clock_event_device hpet_clockevent = { | |
232 | .name = "hpet", | |
233 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
234 | .set_mode = hpet_legacy_set_mode, |
235 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 | 236 | .irq = 0, |
59c69f2a | 237 | .rating = 50, |
e9e2cdb4 TG |
238 | }; |
239 | ||
8d6f0c82 | 240 | static void hpet_stop_counter(void) |
e9e2cdb4 TG |
241 | { |
242 | unsigned long cfg = hpet_readl(HPET_CFG); | |
e9e2cdb4 TG |
243 | cfg &= ~HPET_CFG_ENABLE; |
244 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
245 | } |
246 | ||
247 | static void hpet_reset_counter(void) | |
248 | { | |
e9e2cdb4 TG |
249 | hpet_writel(0, HPET_COUNTER); |
250 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
251 | } |
252 | ||
253 | static void hpet_start_counter(void) | |
254 | { | |
5946fa3d | 255 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
256 | cfg |= HPET_CFG_ENABLE; |
257 | hpet_writel(cfg, HPET_CFG); | |
258 | } | |
259 | ||
8d6f0c82 AH |
260 | static void hpet_restart_counter(void) |
261 | { | |
262 | hpet_stop_counter(); | |
7a6f9cbb | 263 | hpet_reset_counter(); |
8d6f0c82 AH |
264 | hpet_start_counter(); |
265 | } | |
266 | ||
59c69f2a VP |
267 | static void hpet_resume_device(void) |
268 | { | |
bfe0c1cc | 269 | force_hpet_resume(); |
59c69f2a VP |
270 | } |
271 | ||
17622339 | 272 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
273 | { |
274 | hpet_resume_device(); | |
8d6f0c82 | 275 | hpet_restart_counter(); |
59c69f2a VP |
276 | } |
277 | ||
610bf2f1 | 278 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 279 | { |
5946fa3d | 280 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
281 | |
282 | cfg |= HPET_CFG_LEGACY; | |
283 | hpet_writel(cfg, HPET_CFG); | |
284 | hpet_legacy_int_enabled = 1; | |
285 | } | |
286 | ||
610bf2f1 VP |
287 | static void hpet_legacy_clockevent_register(void) |
288 | { | |
610bf2f1 VP |
289 | /* Start HPET legacy interrupts */ |
290 | hpet_enable_legacy_int(); | |
291 | ||
610bf2f1 VP |
292 | /* |
293 | * Start hpet with the boot cpu mask and make it | |
294 | * global after the IO_APIC has been initialized. | |
295 | */ | |
320ab2b0 | 296 | hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); |
ab0e08f1 TG |
297 | clockevents_config_and_register(&hpet_clockevent, hpet_freq, |
298 | HPET_MIN_PROG_DELTA, 0x7FFFFFFF); | |
610bf2f1 VP |
299 | global_clock_event = &hpet_clockevent; |
300 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
301 | } | |
302 | ||
26afe5f2 | 303 | static int hpet_setup_msi_irq(unsigned int irq); |
304 | ||
b40d575b | 305 | static void hpet_set_mode(enum clock_event_mode mode, |
306 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 307 | { |
5946fa3d | 308 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
309 | uint64_t delta; |
310 | ||
4588c1f0 | 311 | switch (mode) { |
e9e2cdb4 | 312 | case CLOCK_EVT_MODE_PERIODIC: |
c23e253e | 313 | hpet_stop_counter(); |
b40d575b | 314 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
315 | delta >>= evt->shift; | |
7a6f9cbb | 316 | now = hpet_readl(HPET_COUNTER); |
5946fa3d | 317 | cmp = now + (unsigned int) delta; |
b40d575b | 318 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
b13e2464 JS |
319 | /* Make sure we use edge triggered interrupts */ |
320 | cfg &= ~HPET_TN_LEVEL; | |
e9e2cdb4 TG |
321 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
322 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 323 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
7a6f9cbb AH |
324 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
325 | udelay(1); | |
326 | /* | |
327 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
328 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
329 | * bit is automatically cleared after the first write. | |
330 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
331 | * Publication # 24674) | |
332 | */ | |
5946fa3d | 333 | hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); |
c23e253e | 334 | hpet_start_counter(); |
b98103a5 | 335 | hpet_print_config(); |
e9e2cdb4 TG |
336 | break; |
337 | ||
338 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 339 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
340 | cfg &= ~HPET_TN_PERIODIC; |
341 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 342 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
343 | break; |
344 | ||
345 | case CLOCK_EVT_MODE_UNUSED: | |
346 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 347 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 348 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 349 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 350 | break; |
18de5bc4 TG |
351 | |
352 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 353 | if (timer == 0) { |
354 | hpet_enable_legacy_int(); | |
355 | } else { | |
356 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
357 | hpet_setup_msi_irq(hdev->irq); | |
358 | disable_irq(hdev->irq); | |
0de26520 | 359 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
26afe5f2 | 360 | enable_irq(hdev->irq); |
361 | } | |
b98103a5 | 362 | hpet_print_config(); |
18de5bc4 | 363 | break; |
e9e2cdb4 TG |
364 | } |
365 | } | |
366 | ||
b40d575b | 367 | static int hpet_next_event(unsigned long delta, |
368 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 369 | { |
f7676254 | 370 | u32 cnt; |
995bd3bb | 371 | s32 res; |
e9e2cdb4 TG |
372 | |
373 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 374 | cnt += (u32) delta; |
b40d575b | 375 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 376 | |
72d43d9b | 377 | /* |
995bd3bb TG |
378 | * HPETs are a complete disaster. The compare register is |
379 | * based on a equal comparison and neither provides a less | |
380 | * than or equal functionality (which would require to take | |
381 | * the wraparound into account) nor a simple count down event | |
382 | * mode. Further the write to the comparator register is | |
383 | * delayed internally up to two HPET clock cycles in certain | |
f1c18071 TG |
384 | * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even |
385 | * longer delays. We worked around that by reading back the | |
386 | * compare register, but that required another workaround for | |
387 | * ICH9,10 chips where the first readout after write can | |
388 | * return the old stale value. We already had a minimum | |
389 | * programming delta of 5us enforced, but a NMI or SMI hitting | |
995bd3bb TG |
390 | * between the counter readout and the comparator write can |
391 | * move us behind that point easily. Now instead of reading | |
392 | * the compare register back several times, we make the ETIME | |
393 | * decision based on the following: Return ETIME if the | |
f1c18071 | 394 | * counter value after the write is less than HPET_MIN_CYCLES |
995bd3bb | 395 | * away from the event or if the counter is already ahead of |
f1c18071 TG |
396 | * the event. The minimum programming delta for the generic |
397 | * clockevents code is set to 1.5 * HPET_MIN_CYCLES. | |
72d43d9b | 398 | */ |
995bd3bb | 399 | res = (s32)(cnt - hpet_readl(HPET_COUNTER)); |
72d43d9b | 400 | |
f1c18071 | 401 | return res < HPET_MIN_CYCLES ? -ETIME : 0; |
e9e2cdb4 TG |
402 | } |
403 | ||
b40d575b | 404 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
405 | struct clock_event_device *evt) | |
406 | { | |
407 | hpet_set_mode(mode, evt, 0); | |
408 | } | |
409 | ||
410 | static int hpet_legacy_next_event(unsigned long delta, | |
411 | struct clock_event_device *evt) | |
412 | { | |
413 | return hpet_next_event(delta, evt, 0); | |
414 | } | |
415 | ||
58ac1e76 | 416 | /* |
417 | * HPET MSI Support | |
418 | */ | |
26afe5f2 | 419 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
420 | |
421 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
422 | static struct hpet_dev *hpet_devs; | |
423 | ||
d0fbca8f | 424 | void hpet_msi_unmask(struct irq_data *data) |
58ac1e76 | 425 | { |
d0fbca8f | 426 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 427 | unsigned int cfg; |
58ac1e76 | 428 | |
429 | /* unmask it */ | |
430 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
431 | cfg |= HPET_TN_FSB; | |
432 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
433 | } | |
434 | ||
d0fbca8f | 435 | void hpet_msi_mask(struct irq_data *data) |
58ac1e76 | 436 | { |
d0fbca8f | 437 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 438 | unsigned int cfg; |
58ac1e76 | 439 | |
440 | /* mask it */ | |
441 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
442 | cfg &= ~HPET_TN_FSB; | |
443 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
444 | } | |
445 | ||
d0fbca8f | 446 | void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 447 | { |
58ac1e76 | 448 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); |
449 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
450 | } | |
451 | ||
d0fbca8f | 452 | void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 453 | { |
58ac1e76 | 454 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); |
455 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
456 | msg->address_hi = 0; | |
457 | } | |
458 | ||
26afe5f2 | 459 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
460 | struct clock_event_device *evt) | |
461 | { | |
462 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
463 | hpet_set_mode(mode, evt, hdev->num); | |
464 | } | |
465 | ||
466 | static int hpet_msi_next_event(unsigned long delta, | |
467 | struct clock_event_device *evt) | |
468 | { | |
469 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
470 | return hpet_next_event(delta, evt, hdev->num); | |
471 | } | |
472 | ||
473 | static int hpet_setup_msi_irq(unsigned int irq) | |
474 | { | |
c8bc6f3c | 475 | if (arch_setup_hpet_msi(irq, hpet_blockid)) { |
26afe5f2 | 476 | destroy_irq(irq); |
477 | return -EINVAL; | |
478 | } | |
479 | return 0; | |
480 | } | |
481 | ||
482 | static int hpet_assign_irq(struct hpet_dev *dev) | |
483 | { | |
484 | unsigned int irq; | |
485 | ||
02198962 | 486 | irq = create_irq_nr(0, -1); |
26afe5f2 | 487 | if (!irq) |
488 | return -EINVAL; | |
489 | ||
2c778651 | 490 | irq_set_handler_data(irq, dev); |
26afe5f2 | 491 | |
492 | if (hpet_setup_msi_irq(irq)) | |
493 | return -EINVAL; | |
494 | ||
495 | dev->irq = irq; | |
496 | return 0; | |
497 | } | |
498 | ||
499 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
500 | { | |
501 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
502 | struct clock_event_device *hevt = &dev->evt; | |
503 | ||
504 | if (!hevt->event_handler) { | |
505 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
506 | dev->num); | |
507 | return IRQ_HANDLED; | |
508 | } | |
509 | ||
510 | hevt->event_handler(hevt); | |
511 | return IRQ_HANDLED; | |
512 | } | |
513 | ||
514 | static int hpet_setup_irq(struct hpet_dev *dev) | |
515 | { | |
516 | ||
517 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
507fa3a3 TG |
518 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, |
519 | dev->name, dev)) | |
26afe5f2 | 520 | return -1; |
521 | ||
522 | disable_irq(dev->irq); | |
0de26520 | 523 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 524 | enable_irq(dev->irq); |
525 | ||
c81bba49 YL |
526 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
527 | dev->name, dev->irq); | |
528 | ||
26afe5f2 | 529 | return 0; |
530 | } | |
531 | ||
532 | /* This should be called in specific @cpu */ | |
533 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
534 | { | |
535 | struct clock_event_device *evt = &hdev->evt; | |
26afe5f2 | 536 | |
537 | WARN_ON(cpu != smp_processor_id()); | |
538 | if (!(hdev->flags & HPET_DEV_VALID)) | |
539 | return; | |
540 | ||
541 | if (hpet_setup_msi_irq(hdev->irq)) | |
542 | return; | |
543 | ||
544 | hdev->cpu = cpu; | |
545 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
546 | evt->name = hdev->name; | |
547 | hpet_setup_irq(hdev); | |
548 | evt->irq = hdev->irq; | |
549 | ||
550 | evt->rating = 110; | |
551 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
552 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
553 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
554 | ||
555 | evt->set_mode = hpet_msi_set_mode; | |
556 | evt->set_next_event = hpet_msi_next_event; | |
320ab2b0 | 557 | evt->cpumask = cpumask_of(hdev->cpu); |
ab0e08f1 TG |
558 | |
559 | clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, | |
560 | 0x7FFFFFFF); | |
26afe5f2 | 561 | } |
562 | ||
563 | #ifdef CONFIG_HPET | |
564 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
565 | #define RESERVE_TIMERS 1 | |
566 | #else | |
567 | #define RESERVE_TIMERS 0 | |
568 | #endif | |
5f79f2f2 VP |
569 | |
570 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 571 | { |
572 | unsigned int id; | |
573 | unsigned int num_timers; | |
574 | unsigned int num_timers_used = 0; | |
575 | int i; | |
576 | ||
73472a46 PV |
577 | if (hpet_msi_disable) |
578 | return; | |
579 | ||
39fe05e5 SL |
580 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
581 | return; | |
26afe5f2 | 582 | id = hpet_readl(HPET_ID); |
583 | ||
584 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
585 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 586 | hpet_print_config(); |
26afe5f2 | 587 | |
588 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
589 | if (!hpet_devs) | |
590 | return; | |
591 | ||
592 | hpet_num_timers = num_timers; | |
593 | ||
594 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
595 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
5946fa3d | 596 | unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); |
26afe5f2 | 597 | |
598 | /* Only consider HPET timer with MSI support */ | |
599 | if (!(cfg & HPET_TN_FSB_CAP)) | |
600 | continue; | |
601 | ||
602 | hdev->flags = 0; | |
603 | if (cfg & HPET_TN_PERIODIC_CAP) | |
604 | hdev->flags |= HPET_DEV_PERI_CAP; | |
605 | hdev->num = i; | |
606 | ||
607 | sprintf(hdev->name, "hpet%d", i); | |
608 | if (hpet_assign_irq(hdev)) | |
609 | continue; | |
610 | ||
611 | hdev->flags |= HPET_DEV_FSB_CAP; | |
612 | hdev->flags |= HPET_DEV_VALID; | |
613 | num_timers_used++; | |
614 | if (num_timers_used == num_possible_cpus()) | |
615 | break; | |
616 | } | |
617 | ||
618 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
619 | num_timers, num_timers_used); | |
620 | } | |
621 | ||
5f79f2f2 VP |
622 | #ifdef CONFIG_HPET |
623 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
624 | { | |
625 | int i; | |
626 | ||
627 | if (!hpet_devs) | |
628 | return; | |
629 | ||
630 | for (i = 0; i < hpet_num_timers; i++) { | |
631 | struct hpet_dev *hdev = &hpet_devs[i]; | |
632 | ||
633 | if (!(hdev->flags & HPET_DEV_VALID)) | |
634 | continue; | |
635 | ||
636 | hd->hd_irq[hdev->num] = hdev->irq; | |
637 | hpet_reserve_timer(hd, hdev->num); | |
638 | } | |
639 | } | |
640 | #endif | |
641 | ||
26afe5f2 | 642 | static struct hpet_dev *hpet_get_unused_timer(void) |
643 | { | |
644 | int i; | |
645 | ||
646 | if (!hpet_devs) | |
647 | return NULL; | |
648 | ||
649 | for (i = 0; i < hpet_num_timers; i++) { | |
650 | struct hpet_dev *hdev = &hpet_devs[i]; | |
651 | ||
652 | if (!(hdev->flags & HPET_DEV_VALID)) | |
653 | continue; | |
654 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
655 | (unsigned long *)&hdev->flags)) | |
656 | continue; | |
657 | return hdev; | |
658 | } | |
659 | return NULL; | |
660 | } | |
661 | ||
662 | struct hpet_work_struct { | |
663 | struct delayed_work work; | |
664 | struct completion complete; | |
665 | }; | |
666 | ||
667 | static void hpet_work(struct work_struct *w) | |
668 | { | |
669 | struct hpet_dev *hdev; | |
670 | int cpu = smp_processor_id(); | |
671 | struct hpet_work_struct *hpet_work; | |
672 | ||
673 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
674 | ||
675 | hdev = hpet_get_unused_timer(); | |
676 | if (hdev) | |
677 | init_one_hpet_msi_clockevent(hdev, cpu); | |
678 | ||
679 | complete(&hpet_work->complete); | |
680 | } | |
681 | ||
682 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
683 | unsigned long action, void *hcpu) | |
684 | { | |
685 | unsigned long cpu = (unsigned long)hcpu; | |
686 | struct hpet_work_struct work; | |
687 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
688 | ||
689 | switch (action & 0xf) { | |
690 | case CPU_ONLINE: | |
ca1cab37 | 691 | INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); |
26afe5f2 | 692 | init_completion(&work.complete); |
693 | /* FIXME: add schedule_work_on() */ | |
694 | schedule_delayed_work_on(cpu, &work.work, 0); | |
695 | wait_for_completion(&work.complete); | |
336f6c32 | 696 | destroy_timer_on_stack(&work.work.timer); |
26afe5f2 | 697 | break; |
698 | case CPU_DEAD: | |
699 | if (hdev) { | |
700 | free_irq(hdev->irq, hdev); | |
701 | hdev->flags &= ~HPET_DEV_USED; | |
702 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
703 | } | |
704 | break; | |
705 | } | |
706 | return NOTIFY_OK; | |
707 | } | |
708 | #else | |
709 | ||
ba374c9b SN |
710 | static int hpet_setup_msi_irq(unsigned int irq) |
711 | { | |
712 | return 0; | |
713 | } | |
5f79f2f2 VP |
714 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
715 | { | |
716 | return; | |
717 | } | |
718 | ||
719 | #ifdef CONFIG_HPET | |
720 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 721 | { |
722 | return; | |
723 | } | |
5f79f2f2 | 724 | #endif |
26afe5f2 | 725 | |
726 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
727 | unsigned long action, void *hcpu) | |
728 | { | |
729 | return NOTIFY_OK; | |
730 | } | |
731 | ||
732 | #endif | |
733 | ||
6bb74df4 JS |
734 | /* |
735 | * Clock source related code | |
736 | */ | |
8e19608e | 737 | static cycle_t read_hpet(struct clocksource *cs) |
6bb74df4 JS |
738 | { |
739 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
740 | } | |
741 | ||
742 | static struct clocksource clocksource_hpet = { | |
743 | .name = "hpet", | |
744 | .rating = 250, | |
745 | .read = read_hpet, | |
746 | .mask = HPET_MASK, | |
6bb74df4 | 747 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8d6f0c82 | 748 | .resume = hpet_resume_counter, |
28769149 | 749 | #ifdef CONFIG_X86_64 |
98d0ac38 | 750 | .archdata = { .vclock_mode = VCLOCK_HPET }, |
28769149 | 751 | #endif |
6bb74df4 JS |
752 | }; |
753 | ||
610bf2f1 | 754 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 755 | { |
6fd592da | 756 | u64 start, now; |
075bcd1f | 757 | cycle_t t1; |
e9e2cdb4 | 758 | |
e9e2cdb4 | 759 | /* Start the counter */ |
8d6f0c82 | 760 | hpet_restart_counter(); |
e9e2cdb4 | 761 | |
075bcd1f | 762 | /* Verify whether hpet counter works */ |
8e19608e | 763 | t1 = hpet_readl(HPET_COUNTER); |
075bcd1f TG |
764 | rdtscll(start); |
765 | ||
766 | /* | |
767 | * We don't know the TSC frequency yet, but waiting for | |
768 | * 200000 TSC cycles is safe: | |
769 | * 4 GHz == 50us | |
770 | * 1 GHz == 200us | |
771 | */ | |
772 | do { | |
773 | rep_nop(); | |
774 | rdtscll(now); | |
775 | } while ((now - start) < 200000UL); | |
776 | ||
8e19608e | 777 | if (t1 == hpet_readl(HPET_COUNTER)) { |
075bcd1f TG |
778 | printk(KERN_WARNING |
779 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 780 | return -ENODEV; |
075bcd1f TG |
781 | } |
782 | ||
f12a15be | 783 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); |
610bf2f1 VP |
784 | return 0; |
785 | } | |
786 | ||
b02a7f22 PM |
787 | /** |
788 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
789 | */ |
790 | int __init hpet_enable(void) | |
791 | { | |
ab0e08f1 | 792 | unsigned long hpet_period; |
5946fa3d | 793 | unsigned int id; |
ab0e08f1 | 794 | u64 freq; |
a6825f1c | 795 | int i; |
610bf2f1 VP |
796 | |
797 | if (!is_hpet_capable()) | |
798 | return 0; | |
799 | ||
800 | hpet_set_mapping(); | |
801 | ||
802 | /* | |
803 | * Read the period and check for a sane value: | |
804 | */ | |
805 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
806 | |
807 | /* | |
808 | * AMD SB700 based systems with spread spectrum enabled use a | |
809 | * SMM based HPET emulation to provide proper frequency | |
810 | * setting. The SMM code is initialized with the first HPET | |
811 | * register access and takes some time to complete. During | |
812 | * this time the config register reads 0xffffffff. We check | |
813 | * for max. 1000 loops whether the config register reads a non | |
814 | * 0xffffffff value to make sure that HPET is up and running | |
815 | * before we go further. A counting loop is safe, as the HPET | |
816 | * access takes thousands of CPU cycles. On non SB700 based | |
817 | * machines this check is only done once and has no side | |
818 | * effects. | |
819 | */ | |
820 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
821 | if (i == 1000) { | |
822 | printk(KERN_WARNING | |
823 | "HPET config register value = 0xFFFFFFFF. " | |
824 | "Disabling HPET\n"); | |
825 | goto out_nohpet; | |
826 | } | |
827 | } | |
828 | ||
610bf2f1 VP |
829 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
830 | goto out_nohpet; | |
831 | ||
ab0e08f1 TG |
832 | /* |
833 | * The period is a femto seconds value. Convert it to a | |
834 | * frequency. | |
835 | */ | |
836 | freq = FSEC_PER_SEC; | |
837 | do_div(freq, hpet_period); | |
838 | hpet_freq = freq; | |
839 | ||
610bf2f1 VP |
840 | /* |
841 | * Read the HPET ID register to retrieve the IRQ routing | |
842 | * information and the number of channels | |
843 | */ | |
844 | id = hpet_readl(HPET_ID); | |
b98103a5 | 845 | hpet_print_config(); |
610bf2f1 VP |
846 | |
847 | #ifdef CONFIG_HPET_EMULATE_RTC | |
848 | /* | |
849 | * The legacy routing mode needs at least two channels, tick timer | |
850 | * and the rtc emulation channel. | |
851 | */ | |
852 | if (!(id & HPET_ID_NUMBER)) | |
853 | goto out_nohpet; | |
854 | #endif | |
855 | ||
856 | if (hpet_clocksource_register()) | |
857 | goto out_nohpet; | |
858 | ||
e9e2cdb4 | 859 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 860 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
861 | return 1; |
862 | } | |
863 | return 0; | |
5d0cf410 | 864 | |
e9e2cdb4 | 865 | out_nohpet: |
06a24dec | 866 | hpet_clear_mapping(); |
bacbe999 | 867 | hpet_address = 0; |
e9e2cdb4 TG |
868 | return 0; |
869 | } | |
870 | ||
28769149 TG |
871 | /* |
872 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
873 | * | |
874 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
875 | * but on x86_64 it is necessary ! | |
876 | */ | |
877 | static __init int hpet_late_init(void) | |
878 | { | |
26afe5f2 | 879 | int cpu; |
880 | ||
59c69f2a | 881 | if (boot_hpet_disable) |
28769149 TG |
882 | return -ENODEV; |
883 | ||
59c69f2a VP |
884 | if (!hpet_address) { |
885 | if (!force_hpet_address) | |
886 | return -ENODEV; | |
887 | ||
888 | hpet_address = force_hpet_address; | |
889 | hpet_enable(); | |
59c69f2a VP |
890 | } |
891 | ||
39c04b55 JF |
892 | if (!hpet_virt_address) |
893 | return -ENODEV; | |
894 | ||
39fe05e5 SL |
895 | if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) |
896 | hpet_msi_capability_lookup(2); | |
897 | else | |
898 | hpet_msi_capability_lookup(0); | |
899 | ||
28769149 | 900 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 901 | hpet_print_config(); |
59c69f2a | 902 | |
73472a46 PV |
903 | if (hpet_msi_disable) |
904 | return 0; | |
905 | ||
39fe05e5 SL |
906 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
907 | return 0; | |
908 | ||
26afe5f2 | 909 | for_each_online_cpu(cpu) { |
910 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
911 | } | |
912 | ||
913 | /* This notifier should be called after workqueue is ready */ | |
914 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
915 | ||
28769149 TG |
916 | return 0; |
917 | } | |
918 | fs_initcall(hpet_late_init); | |
919 | ||
c86c7fbc OH |
920 | void hpet_disable(void) |
921 | { | |
ff487808 | 922 | if (is_hpet_capable() && hpet_virt_address) { |
5946fa3d | 923 | unsigned int cfg = hpet_readl(HPET_CFG); |
c86c7fbc OH |
924 | |
925 | if (hpet_legacy_int_enabled) { | |
926 | cfg &= ~HPET_CFG_LEGACY; | |
927 | hpet_legacy_int_enabled = 0; | |
928 | } | |
929 | cfg &= ~HPET_CFG_ENABLE; | |
930 | hpet_writel(cfg, HPET_CFG); | |
931 | } | |
932 | } | |
933 | ||
e9e2cdb4 TG |
934 | #ifdef CONFIG_HPET_EMULATE_RTC |
935 | ||
936 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
937 | * is enabled, we support RTC interrupt functionality in software. | |
938 | * RTC has 3 kinds of interrupts: | |
939 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
940 | * is updated | |
941 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
942 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
943 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
944 | * (1) and (2) above are implemented using polling at a frequency of | |
945 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
946 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
947 | * For (3), we use interrupts at 64Hz or user specified periodic | |
948 | * frequency, whichever is higher. | |
949 | */ | |
950 | #include <linux/mc146818rtc.h> | |
951 | #include <linux/rtc.h> | |
1bdbdaac | 952 | #include <asm/rtc.h> |
e9e2cdb4 TG |
953 | |
954 | #define DEFAULT_RTC_INT_FREQ 64 | |
955 | #define DEFAULT_RTC_SHIFT 6 | |
956 | #define RTC_NUM_INTS 1 | |
957 | ||
958 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 959 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
960 | static struct rtc_time hpet_alarm_time; |
961 | static unsigned long hpet_pie_count; | |
ff08f76d | 962 | static u32 hpet_t1_cmp; |
5946fa3d JB |
963 | static u32 hpet_default_delta; |
964 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
965 | static unsigned long hpet_pie_limit; |
966 | ||
1bdbdaac BW |
967 | static rtc_irq_handler irq_handler; |
968 | ||
ff08f76d PE |
969 | /* |
970 | * Check that the hpet counter c1 is ahead of the c2 | |
971 | */ | |
972 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
973 | { | |
974 | return (s32)(c2 - c1) < 0; | |
975 | } | |
976 | ||
1bdbdaac BW |
977 | /* |
978 | * Registers a IRQ handler. | |
979 | */ | |
980 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
981 | { | |
982 | if (!is_hpet_enabled()) | |
983 | return -ENODEV; | |
984 | if (irq_handler) | |
985 | return -EBUSY; | |
986 | ||
987 | irq_handler = handler; | |
988 | ||
989 | return 0; | |
990 | } | |
991 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
992 | ||
993 | /* | |
994 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
995 | * and does cleanup. | |
996 | */ | |
997 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
998 | { | |
999 | if (!is_hpet_enabled()) | |
1000 | return; | |
1001 | ||
1002 | irq_handler = NULL; | |
1003 | hpet_rtc_flags = 0; | |
1004 | } | |
1005 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1006 | ||
e9e2cdb4 TG |
1007 | /* |
1008 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
1009 | * is not supported by all HPET implementations for timer 1. | |
1010 | * | |
1011 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1012 | */ | |
1013 | int hpet_rtc_timer_init(void) | |
1014 | { | |
5946fa3d JB |
1015 | unsigned int cfg, cnt, delta; |
1016 | unsigned long flags; | |
e9e2cdb4 TG |
1017 | |
1018 | if (!is_hpet_enabled()) | |
1019 | return 0; | |
1020 | ||
1021 | if (!hpet_default_delta) { | |
1022 | uint64_t clc; | |
1023 | ||
1024 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1025 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1026 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1027 | } |
1028 | ||
1029 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1030 | delta = hpet_default_delta; | |
1031 | else | |
1032 | delta = hpet_pie_delta; | |
1033 | ||
1034 | local_irq_save(flags); | |
1035 | ||
1036 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1037 | hpet_writel(cnt, HPET_T1_CMP); | |
1038 | hpet_t1_cmp = cnt; | |
1039 | ||
1040 | cfg = hpet_readl(HPET_T1_CFG); | |
1041 | cfg &= ~HPET_TN_PERIODIC; | |
1042 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1043 | hpet_writel(cfg, HPET_T1_CFG); | |
1044 | ||
1045 | local_irq_restore(flags); | |
1046 | ||
1047 | return 1; | |
1048 | } | |
1bdbdaac | 1049 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
1050 | |
1051 | /* | |
1052 | * The functions below are called from rtc driver. | |
1053 | * Return 0 if HPET is not being used. | |
1054 | * Otherwise do the necessary changes and return 1. | |
1055 | */ | |
1056 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1057 | { | |
1058 | if (!is_hpet_enabled()) | |
1059 | return 0; | |
1060 | ||
1061 | hpet_rtc_flags &= ~bit_mask; | |
1062 | return 1; | |
1063 | } | |
1bdbdaac | 1064 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1065 | |
1066 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1067 | { | |
1068 | unsigned long oldbits = hpet_rtc_flags; | |
1069 | ||
1070 | if (!is_hpet_enabled()) | |
1071 | return 0; | |
1072 | ||
1073 | hpet_rtc_flags |= bit_mask; | |
1074 | ||
7e2a31da DB |
1075 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1076 | hpet_prev_update_sec = -1; | |
1077 | ||
e9e2cdb4 TG |
1078 | if (!oldbits) |
1079 | hpet_rtc_timer_init(); | |
1080 | ||
1081 | return 1; | |
1082 | } | |
1bdbdaac | 1083 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1084 | |
1085 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1086 | unsigned char sec) | |
1087 | { | |
1088 | if (!is_hpet_enabled()) | |
1089 | return 0; | |
1090 | ||
1091 | hpet_alarm_time.tm_hour = hrs; | |
1092 | hpet_alarm_time.tm_min = min; | |
1093 | hpet_alarm_time.tm_sec = sec; | |
1094 | ||
1095 | return 1; | |
1096 | } | |
1bdbdaac | 1097 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1098 | |
1099 | int hpet_set_periodic_freq(unsigned long freq) | |
1100 | { | |
1101 | uint64_t clc; | |
1102 | ||
1103 | if (!is_hpet_enabled()) | |
1104 | return 0; | |
1105 | ||
1106 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1107 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1108 | else { | |
1109 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1110 | do_div(clc, freq); | |
1111 | clc >>= hpet_clockevent.shift; | |
5946fa3d | 1112 | hpet_pie_delta = clc; |
b4a5e8a1 | 1113 | hpet_pie_limit = 0; |
e9e2cdb4 TG |
1114 | } |
1115 | return 1; | |
1116 | } | |
1bdbdaac | 1117 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1118 | |
1119 | int hpet_rtc_dropped_irq(void) | |
1120 | { | |
1121 | return is_hpet_enabled(); | |
1122 | } | |
1bdbdaac | 1123 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1124 | |
1125 | static void hpet_rtc_timer_reinit(void) | |
1126 | { | |
5946fa3d | 1127 | unsigned int cfg, delta; |
e9e2cdb4 TG |
1128 | int lost_ints = -1; |
1129 | ||
1130 | if (unlikely(!hpet_rtc_flags)) { | |
1131 | cfg = hpet_readl(HPET_T1_CFG); | |
1132 | cfg &= ~HPET_TN_ENABLE; | |
1133 | hpet_writel(cfg, HPET_T1_CFG); | |
1134 | return; | |
1135 | } | |
1136 | ||
1137 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1138 | delta = hpet_default_delta; | |
1139 | else | |
1140 | delta = hpet_pie_delta; | |
1141 | ||
1142 | /* | |
1143 | * Increment the comparator value until we are ahead of the | |
1144 | * current count. | |
1145 | */ | |
1146 | do { | |
1147 | hpet_t1_cmp += delta; | |
1148 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1149 | lost_ints++; | |
ff08f76d | 1150 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1151 | |
1152 | if (lost_ints) { | |
1153 | if (hpet_rtc_flags & RTC_PIE) | |
1154 | hpet_pie_count += lost_ints; | |
1155 | if (printk_ratelimit()) | |
7e2a31da | 1156 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1157 | lost_ints); |
1158 | } | |
1159 | } | |
1160 | ||
1161 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1162 | { | |
1163 | struct rtc_time curr_time; | |
1164 | unsigned long rtc_int_flag = 0; | |
1165 | ||
1166 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1167 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1168 | |
1169 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1170 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1171 | |
1172 | if (hpet_rtc_flags & RTC_UIE && | |
1173 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1174 | if (hpet_prev_update_sec >= 0) |
1175 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1176 | hpet_prev_update_sec = curr_time.tm_sec; |
1177 | } | |
1178 | ||
1179 | if (hpet_rtc_flags & RTC_PIE && | |
1180 | ++hpet_pie_count >= hpet_pie_limit) { | |
1181 | rtc_int_flag |= RTC_PF; | |
1182 | hpet_pie_count = 0; | |
1183 | } | |
1184 | ||
8ee291f8 | 1185 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1186 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1187 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1188 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1189 | rtc_int_flag |= RTC_AF; | |
1190 | ||
1191 | if (rtc_int_flag) { | |
1192 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1193 | if (irq_handler) |
1194 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1195 | } |
1196 | return IRQ_HANDLED; | |
1197 | } | |
1bdbdaac | 1198 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1199 | #endif |