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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 | 3 | #include <linux/interrupt.h> |
69c60c88 | 4 | #include <linux/export.h> |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 | 6 | #include <linux/errno.h> |
334955ef | 7 | #include <linux/i8253.h> |
5a0e3ad6 | 8 | #include <linux/slab.h> |
5d0cf410 JS |
9 | #include <linux/hpet.h> |
10 | #include <linux/init.h> | |
58ac1e76 | 11 | #include <linux/cpu.h> |
4588c1f0 IM |
12 | #include <linux/pm.h> |
13 | #include <linux/io.h> | |
5d0cf410 | 14 | |
28769149 | 15 | #include <asm/fixmap.h> |
4588c1f0 | 16 | #include <asm/hpet.h> |
16f871bc | 17 | #include <asm/time.h> |
5d0cf410 | 18 | |
4588c1f0 | 19 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 20 | |
b10db7f0 PM |
21 | /* FSEC = 10^-15 |
22 | NSEC = 10^-9 */ | |
4588c1f0 | 23 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 24 | |
26afe5f2 | 25 | #define HPET_DEV_USED_BIT 2 |
26 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
27 | #define HPET_DEV_VALID 0x8 | |
28 | #define HPET_DEV_FSB_CAP 0x1000 | |
29 | #define HPET_DEV_PERI_CAP 0x2000 | |
30 | ||
f1c18071 TG |
31 | #define HPET_MIN_CYCLES 128 |
32 | #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) | |
33 | ||
e9e2cdb4 TG |
34 | /* |
35 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
36 | */ | |
4588c1f0 | 37 | unsigned long hpet_address; |
c8bc6f3c | 38 | u8 hpet_blockid; /* OS timer block num */ |
73472a46 PV |
39 | u8 hpet_msi_disable; |
40 | ||
e951e4af | 41 | #ifdef CONFIG_PCI_MSI |
3b71e9e3 | 42 | static unsigned long hpet_num_timers; |
e951e4af | 43 | #endif |
4588c1f0 | 44 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 45 | |
58ac1e76 | 46 | struct hpet_dev { |
4588c1f0 IM |
47 | struct clock_event_device evt; |
48 | unsigned int num; | |
49 | int cpu; | |
50 | unsigned int irq; | |
51 | unsigned int flags; | |
52 | char name[10]; | |
58ac1e76 | 53 | }; |
54 | ||
3f7787b3 FW |
55 | inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev) |
56 | { | |
57 | return container_of(evtdev, struct hpet_dev, evt); | |
58 | } | |
59 | ||
5946fa3d | 60 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
61 | { |
62 | return readl(hpet_virt_address + a); | |
63 | } | |
64 | ||
5946fa3d | 65 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
66 | { |
67 | writel(d, hpet_virt_address + a); | |
68 | } | |
69 | ||
28769149 | 70 | #ifdef CONFIG_X86_64 |
28769149 | 71 | #include <asm/pgtable.h> |
2387ce57 | 72 | #endif |
28769149 | 73 | |
06a24dec TG |
74 | static inline void hpet_set_mapping(void) |
75 | { | |
76 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 | 77 | #ifdef CONFIG_X86_64 |
d319bb79 | 78 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE); |
2387ce57 | 79 | #endif |
06a24dec TG |
80 | } |
81 | ||
82 | static inline void hpet_clear_mapping(void) | |
83 | { | |
84 | iounmap(hpet_virt_address); | |
85 | hpet_virt_address = NULL; | |
86 | } | |
87 | ||
e9e2cdb4 TG |
88 | /* |
89 | * HPET command line enable / disable | |
90 | */ | |
91 | static int boot_hpet_disable; | |
b17530bd | 92 | int hpet_force_user; |
b98103a5 | 93 | static int hpet_verbose; |
e9e2cdb4 | 94 | |
4588c1f0 | 95 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
96 | { |
97 | if (str) { | |
98 | if (!strncmp("disable", str, 7)) | |
99 | boot_hpet_disable = 1; | |
b17530bd TG |
100 | if (!strncmp("force", str, 5)) |
101 | hpet_force_user = 1; | |
b98103a5 AH |
102 | if (!strncmp("verbose", str, 7)) |
103 | hpet_verbose = 1; | |
e9e2cdb4 TG |
104 | } |
105 | return 1; | |
106 | } | |
107 | __setup("hpet=", hpet_setup); | |
108 | ||
28769149 TG |
109 | static int __init disable_hpet(char *str) |
110 | { | |
111 | boot_hpet_disable = 1; | |
112 | return 1; | |
113 | } | |
114 | __setup("nohpet", disable_hpet); | |
115 | ||
e9e2cdb4 TG |
116 | static inline int is_hpet_capable(void) |
117 | { | |
4588c1f0 | 118 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
119 | } |
120 | ||
121 | /* | |
122 | * HPET timer interrupt enable / disable | |
123 | */ | |
124 | static int hpet_legacy_int_enabled; | |
125 | ||
126 | /** | |
127 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
128 | */ | |
129 | int is_hpet_enabled(void) | |
130 | { | |
131 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
132 | } | |
1bdbdaac | 133 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 134 | |
b98103a5 AH |
135 | static void _hpet_print_config(const char *function, int line) |
136 | { | |
137 | u32 i, timers, l, h; | |
138 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
139 | l = hpet_readl(HPET_ID); | |
140 | h = hpet_readl(HPET_PERIOD); | |
141 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
142 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
143 | l = hpet_readl(HPET_CFG); | |
144 | h = hpet_readl(HPET_STATUS); | |
145 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
146 | l = hpet_readl(HPET_COUNTER); | |
147 | h = hpet_readl(HPET_COUNTER+4); | |
148 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
149 | ||
150 | for (i = 0; i < timers; i++) { | |
151 | l = hpet_readl(HPET_Tn_CFG(i)); | |
152 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
153 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
154 | i, l, h); | |
155 | l = hpet_readl(HPET_Tn_CMP(i)); | |
156 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
157 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
158 | i, l, h); | |
159 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
160 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
161 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
162 | i, l, h); | |
163 | } | |
164 | } | |
165 | ||
166 | #define hpet_print_config() \ | |
167 | do { \ | |
168 | if (hpet_verbose) \ | |
169 | _hpet_print_config(__FUNCTION__, __LINE__); \ | |
170 | } while (0) | |
171 | ||
e9e2cdb4 TG |
172 | /* |
173 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
174 | * timer 0 and timer 1 in case of RTC emulation. | |
175 | */ | |
176 | #ifdef CONFIG_HPET | |
f0ed4e69 | 177 | |
5f79f2f2 | 178 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 179 | |
5946fa3d | 180 | static void hpet_reserve_platform_timers(unsigned int id) |
e9e2cdb4 TG |
181 | { |
182 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
183 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
184 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
185 | struct hpet_data hd; |
186 | ||
187 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
188 | ||
4588c1f0 IM |
189 | memset(&hd, 0, sizeof(hd)); |
190 | hd.hd_phys_address = hpet_address; | |
191 | hd.hd_address = hpet; | |
192 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
193 | hpet_reserve_timer(&hd, 0); |
194 | ||
195 | #ifdef CONFIG_HPET_EMULATE_RTC | |
196 | hpet_reserve_timer(&hd, 1); | |
197 | #endif | |
5761d64b | 198 | |
64a76f66 DB |
199 | /* |
200 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
201 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
202 | * don't bother configuring *any* comparator interrupts. | |
203 | */ | |
e9e2cdb4 TG |
204 | hd.hd_irq[0] = HPET_LEGACY_8254; |
205 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
206 | ||
fc3fbc45 | 207 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
208 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
209 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 210 | } |
5761d64b | 211 | |
f0ed4e69 | 212 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 213 | |
e9e2cdb4 | 214 | hpet_alloc(&hd); |
5761d64b | 215 | |
e9e2cdb4 TG |
216 | } |
217 | #else | |
5946fa3d | 218 | static void hpet_reserve_platform_timers(unsigned int id) { } |
e9e2cdb4 TG |
219 | #endif |
220 | ||
221 | /* | |
222 | * Common hpet info | |
223 | */ | |
ab0e08f1 | 224 | static unsigned long hpet_freq; |
e9e2cdb4 | 225 | |
610bf2f1 | 226 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 227 | struct clock_event_device *evt); |
610bf2f1 | 228 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
229 | struct clock_event_device *evt); |
230 | ||
231 | /* | |
232 | * The hpet clock event device | |
233 | */ | |
234 | static struct clock_event_device hpet_clockevent = { | |
235 | .name = "hpet", | |
236 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
237 | .set_mode = hpet_legacy_set_mode, |
238 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 | 239 | .irq = 0, |
59c69f2a | 240 | .rating = 50, |
e9e2cdb4 TG |
241 | }; |
242 | ||
8d6f0c82 | 243 | static void hpet_stop_counter(void) |
e9e2cdb4 TG |
244 | { |
245 | unsigned long cfg = hpet_readl(HPET_CFG); | |
e9e2cdb4 TG |
246 | cfg &= ~HPET_CFG_ENABLE; |
247 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
248 | } |
249 | ||
250 | static void hpet_reset_counter(void) | |
251 | { | |
e9e2cdb4 TG |
252 | hpet_writel(0, HPET_COUNTER); |
253 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
254 | } |
255 | ||
256 | static void hpet_start_counter(void) | |
257 | { | |
5946fa3d | 258 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
259 | cfg |= HPET_CFG_ENABLE; |
260 | hpet_writel(cfg, HPET_CFG); | |
261 | } | |
262 | ||
8d6f0c82 AH |
263 | static void hpet_restart_counter(void) |
264 | { | |
265 | hpet_stop_counter(); | |
7a6f9cbb | 266 | hpet_reset_counter(); |
8d6f0c82 AH |
267 | hpet_start_counter(); |
268 | } | |
269 | ||
59c69f2a VP |
270 | static void hpet_resume_device(void) |
271 | { | |
bfe0c1cc | 272 | force_hpet_resume(); |
59c69f2a VP |
273 | } |
274 | ||
17622339 | 275 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
276 | { |
277 | hpet_resume_device(); | |
8d6f0c82 | 278 | hpet_restart_counter(); |
59c69f2a VP |
279 | } |
280 | ||
610bf2f1 | 281 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 282 | { |
5946fa3d | 283 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
284 | |
285 | cfg |= HPET_CFG_LEGACY; | |
286 | hpet_writel(cfg, HPET_CFG); | |
287 | hpet_legacy_int_enabled = 1; | |
288 | } | |
289 | ||
610bf2f1 VP |
290 | static void hpet_legacy_clockevent_register(void) |
291 | { | |
610bf2f1 VP |
292 | /* Start HPET legacy interrupts */ |
293 | hpet_enable_legacy_int(); | |
294 | ||
610bf2f1 VP |
295 | /* |
296 | * Start hpet with the boot cpu mask and make it | |
297 | * global after the IO_APIC has been initialized. | |
298 | */ | |
320ab2b0 | 299 | hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); |
ab0e08f1 TG |
300 | clockevents_config_and_register(&hpet_clockevent, hpet_freq, |
301 | HPET_MIN_PROG_DELTA, 0x7FFFFFFF); | |
610bf2f1 VP |
302 | global_clock_event = &hpet_clockevent; |
303 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
304 | } | |
305 | ||
26afe5f2 | 306 | static int hpet_setup_msi_irq(unsigned int irq); |
307 | ||
b40d575b | 308 | static void hpet_set_mode(enum clock_event_mode mode, |
309 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 310 | { |
5946fa3d | 311 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
312 | uint64_t delta; |
313 | ||
4588c1f0 | 314 | switch (mode) { |
e9e2cdb4 | 315 | case CLOCK_EVT_MODE_PERIODIC: |
c23e253e | 316 | hpet_stop_counter(); |
b40d575b | 317 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
318 | delta >>= evt->shift; | |
7a6f9cbb | 319 | now = hpet_readl(HPET_COUNTER); |
5946fa3d | 320 | cmp = now + (unsigned int) delta; |
b40d575b | 321 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
322 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
323 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 324 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
7a6f9cbb AH |
325 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
326 | udelay(1); | |
327 | /* | |
328 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
329 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
330 | * bit is automatically cleared after the first write. | |
331 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
332 | * Publication # 24674) | |
333 | */ | |
5946fa3d | 334 | hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); |
c23e253e | 335 | hpet_start_counter(); |
b98103a5 | 336 | hpet_print_config(); |
e9e2cdb4 TG |
337 | break; |
338 | ||
339 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 340 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
341 | cfg &= ~HPET_TN_PERIODIC; |
342 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 343 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
344 | break; |
345 | ||
346 | case CLOCK_EVT_MODE_UNUSED: | |
347 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 348 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 349 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 350 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 351 | break; |
18de5bc4 TG |
352 | |
353 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 354 | if (timer == 0) { |
355 | hpet_enable_legacy_int(); | |
356 | } else { | |
357 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
358 | hpet_setup_msi_irq(hdev->irq); | |
359 | disable_irq(hdev->irq); | |
0de26520 | 360 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
26afe5f2 | 361 | enable_irq(hdev->irq); |
362 | } | |
b98103a5 | 363 | hpet_print_config(); |
18de5bc4 | 364 | break; |
e9e2cdb4 TG |
365 | } |
366 | } | |
367 | ||
b40d575b | 368 | static int hpet_next_event(unsigned long delta, |
369 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 370 | { |
f7676254 | 371 | u32 cnt; |
995bd3bb | 372 | s32 res; |
e9e2cdb4 TG |
373 | |
374 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 375 | cnt += (u32) delta; |
b40d575b | 376 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 377 | |
72d43d9b | 378 | /* |
995bd3bb TG |
379 | * HPETs are a complete disaster. The compare register is |
380 | * based on a equal comparison and neither provides a less | |
381 | * than or equal functionality (which would require to take | |
382 | * the wraparound into account) nor a simple count down event | |
383 | * mode. Further the write to the comparator register is | |
384 | * delayed internally up to two HPET clock cycles in certain | |
f1c18071 TG |
385 | * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even |
386 | * longer delays. We worked around that by reading back the | |
387 | * compare register, but that required another workaround for | |
388 | * ICH9,10 chips where the first readout after write can | |
389 | * return the old stale value. We already had a minimum | |
390 | * programming delta of 5us enforced, but a NMI or SMI hitting | |
995bd3bb TG |
391 | * between the counter readout and the comparator write can |
392 | * move us behind that point easily. Now instead of reading | |
393 | * the compare register back several times, we make the ETIME | |
394 | * decision based on the following: Return ETIME if the | |
f1c18071 | 395 | * counter value after the write is less than HPET_MIN_CYCLES |
995bd3bb | 396 | * away from the event or if the counter is already ahead of |
f1c18071 TG |
397 | * the event. The minimum programming delta for the generic |
398 | * clockevents code is set to 1.5 * HPET_MIN_CYCLES. | |
72d43d9b | 399 | */ |
995bd3bb | 400 | res = (s32)(cnt - hpet_readl(HPET_COUNTER)); |
72d43d9b | 401 | |
f1c18071 | 402 | return res < HPET_MIN_CYCLES ? -ETIME : 0; |
e9e2cdb4 TG |
403 | } |
404 | ||
b40d575b | 405 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
406 | struct clock_event_device *evt) | |
407 | { | |
408 | hpet_set_mode(mode, evt, 0); | |
409 | } | |
410 | ||
411 | static int hpet_legacy_next_event(unsigned long delta, | |
412 | struct clock_event_device *evt) | |
413 | { | |
414 | return hpet_next_event(delta, evt, 0); | |
415 | } | |
416 | ||
58ac1e76 | 417 | /* |
418 | * HPET MSI Support | |
419 | */ | |
26afe5f2 | 420 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
421 | |
422 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
423 | static struct hpet_dev *hpet_devs; | |
424 | ||
d0fbca8f | 425 | void hpet_msi_unmask(struct irq_data *data) |
58ac1e76 | 426 | { |
d0fbca8f | 427 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 428 | unsigned int cfg; |
58ac1e76 | 429 | |
430 | /* unmask it */ | |
431 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
432 | cfg |= HPET_TN_FSB; | |
433 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
434 | } | |
435 | ||
d0fbca8f | 436 | void hpet_msi_mask(struct irq_data *data) |
58ac1e76 | 437 | { |
d0fbca8f | 438 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 439 | unsigned int cfg; |
58ac1e76 | 440 | |
441 | /* mask it */ | |
442 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
443 | cfg &= ~HPET_TN_FSB; | |
444 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
445 | } | |
446 | ||
d0fbca8f | 447 | void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 448 | { |
58ac1e76 | 449 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); |
450 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
451 | } | |
452 | ||
d0fbca8f | 453 | void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 454 | { |
58ac1e76 | 455 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); |
456 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
457 | msg->address_hi = 0; | |
458 | } | |
459 | ||
26afe5f2 | 460 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
461 | struct clock_event_device *evt) | |
462 | { | |
463 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
464 | hpet_set_mode(mode, evt, hdev->num); | |
465 | } | |
466 | ||
467 | static int hpet_msi_next_event(unsigned long delta, | |
468 | struct clock_event_device *evt) | |
469 | { | |
470 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
471 | return hpet_next_event(delta, evt, hdev->num); | |
472 | } | |
473 | ||
474 | static int hpet_setup_msi_irq(unsigned int irq) | |
475 | { | |
c8bc6f3c | 476 | if (arch_setup_hpet_msi(irq, hpet_blockid)) { |
26afe5f2 | 477 | destroy_irq(irq); |
478 | return -EINVAL; | |
479 | } | |
480 | return 0; | |
481 | } | |
482 | ||
483 | static int hpet_assign_irq(struct hpet_dev *dev) | |
484 | { | |
485 | unsigned int irq; | |
486 | ||
02198962 | 487 | irq = create_irq_nr(0, -1); |
26afe5f2 | 488 | if (!irq) |
489 | return -EINVAL; | |
490 | ||
2c778651 | 491 | irq_set_handler_data(irq, dev); |
26afe5f2 | 492 | |
493 | if (hpet_setup_msi_irq(irq)) | |
494 | return -EINVAL; | |
495 | ||
496 | dev->irq = irq; | |
497 | return 0; | |
498 | } | |
499 | ||
500 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
501 | { | |
502 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
503 | struct clock_event_device *hevt = &dev->evt; | |
504 | ||
505 | if (!hevt->event_handler) { | |
506 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
507 | dev->num); | |
508 | return IRQ_HANDLED; | |
509 | } | |
510 | ||
511 | hevt->event_handler(hevt); | |
512 | return IRQ_HANDLED; | |
513 | } | |
514 | ||
515 | static int hpet_setup_irq(struct hpet_dev *dev) | |
516 | { | |
517 | ||
518 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
507fa3a3 TG |
519 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, |
520 | dev->name, dev)) | |
26afe5f2 | 521 | return -1; |
522 | ||
523 | disable_irq(dev->irq); | |
0de26520 | 524 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 525 | enable_irq(dev->irq); |
526 | ||
c81bba49 YL |
527 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
528 | dev->name, dev->irq); | |
529 | ||
26afe5f2 | 530 | return 0; |
531 | } | |
532 | ||
533 | /* This should be called in specific @cpu */ | |
534 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
535 | { | |
536 | struct clock_event_device *evt = &hdev->evt; | |
26afe5f2 | 537 | |
538 | WARN_ON(cpu != smp_processor_id()); | |
539 | if (!(hdev->flags & HPET_DEV_VALID)) | |
540 | return; | |
541 | ||
542 | if (hpet_setup_msi_irq(hdev->irq)) | |
543 | return; | |
544 | ||
545 | hdev->cpu = cpu; | |
546 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
547 | evt->name = hdev->name; | |
548 | hpet_setup_irq(hdev); | |
549 | evt->irq = hdev->irq; | |
550 | ||
551 | evt->rating = 110; | |
552 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
553 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
554 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
555 | ||
556 | evt->set_mode = hpet_msi_set_mode; | |
557 | evt->set_next_event = hpet_msi_next_event; | |
320ab2b0 | 558 | evt->cpumask = cpumask_of(hdev->cpu); |
ab0e08f1 TG |
559 | |
560 | clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, | |
561 | 0x7FFFFFFF); | |
26afe5f2 | 562 | } |
563 | ||
564 | #ifdef CONFIG_HPET | |
565 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
566 | #define RESERVE_TIMERS 1 | |
567 | #else | |
568 | #define RESERVE_TIMERS 0 | |
569 | #endif | |
5f79f2f2 VP |
570 | |
571 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 572 | { |
573 | unsigned int id; | |
574 | unsigned int num_timers; | |
575 | unsigned int num_timers_used = 0; | |
576 | int i; | |
577 | ||
73472a46 PV |
578 | if (hpet_msi_disable) |
579 | return; | |
580 | ||
39fe05e5 SL |
581 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
582 | return; | |
26afe5f2 | 583 | id = hpet_readl(HPET_ID); |
584 | ||
585 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
586 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 587 | hpet_print_config(); |
26afe5f2 | 588 | |
589 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
590 | if (!hpet_devs) | |
591 | return; | |
592 | ||
593 | hpet_num_timers = num_timers; | |
594 | ||
595 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
596 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
5946fa3d | 597 | unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); |
26afe5f2 | 598 | |
599 | /* Only consider HPET timer with MSI support */ | |
600 | if (!(cfg & HPET_TN_FSB_CAP)) | |
601 | continue; | |
602 | ||
603 | hdev->flags = 0; | |
604 | if (cfg & HPET_TN_PERIODIC_CAP) | |
605 | hdev->flags |= HPET_DEV_PERI_CAP; | |
606 | hdev->num = i; | |
607 | ||
608 | sprintf(hdev->name, "hpet%d", i); | |
609 | if (hpet_assign_irq(hdev)) | |
610 | continue; | |
611 | ||
612 | hdev->flags |= HPET_DEV_FSB_CAP; | |
613 | hdev->flags |= HPET_DEV_VALID; | |
614 | num_timers_used++; | |
615 | if (num_timers_used == num_possible_cpus()) | |
616 | break; | |
617 | } | |
618 | ||
619 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
620 | num_timers, num_timers_used); | |
621 | } | |
622 | ||
5f79f2f2 VP |
623 | #ifdef CONFIG_HPET |
624 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
625 | { | |
626 | int i; | |
627 | ||
628 | if (!hpet_devs) | |
629 | return; | |
630 | ||
631 | for (i = 0; i < hpet_num_timers; i++) { | |
632 | struct hpet_dev *hdev = &hpet_devs[i]; | |
633 | ||
634 | if (!(hdev->flags & HPET_DEV_VALID)) | |
635 | continue; | |
636 | ||
637 | hd->hd_irq[hdev->num] = hdev->irq; | |
638 | hpet_reserve_timer(hd, hdev->num); | |
639 | } | |
640 | } | |
641 | #endif | |
642 | ||
26afe5f2 | 643 | static struct hpet_dev *hpet_get_unused_timer(void) |
644 | { | |
645 | int i; | |
646 | ||
647 | if (!hpet_devs) | |
648 | return NULL; | |
649 | ||
650 | for (i = 0; i < hpet_num_timers; i++) { | |
651 | struct hpet_dev *hdev = &hpet_devs[i]; | |
652 | ||
653 | if (!(hdev->flags & HPET_DEV_VALID)) | |
654 | continue; | |
655 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
656 | (unsigned long *)&hdev->flags)) | |
657 | continue; | |
658 | return hdev; | |
659 | } | |
660 | return NULL; | |
661 | } | |
662 | ||
663 | struct hpet_work_struct { | |
664 | struct delayed_work work; | |
665 | struct completion complete; | |
666 | }; | |
667 | ||
668 | static void hpet_work(struct work_struct *w) | |
669 | { | |
670 | struct hpet_dev *hdev; | |
671 | int cpu = smp_processor_id(); | |
672 | struct hpet_work_struct *hpet_work; | |
673 | ||
674 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
675 | ||
676 | hdev = hpet_get_unused_timer(); | |
677 | if (hdev) | |
678 | init_one_hpet_msi_clockevent(hdev, cpu); | |
679 | ||
680 | complete(&hpet_work->complete); | |
681 | } | |
682 | ||
683 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
684 | unsigned long action, void *hcpu) | |
685 | { | |
686 | unsigned long cpu = (unsigned long)hcpu; | |
687 | struct hpet_work_struct work; | |
688 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
689 | ||
690 | switch (action & 0xf) { | |
691 | case CPU_ONLINE: | |
ca1cab37 | 692 | INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); |
26afe5f2 | 693 | init_completion(&work.complete); |
694 | /* FIXME: add schedule_work_on() */ | |
695 | schedule_delayed_work_on(cpu, &work.work, 0); | |
696 | wait_for_completion(&work.complete); | |
336f6c32 | 697 | destroy_timer_on_stack(&work.work.timer); |
26afe5f2 | 698 | break; |
699 | case CPU_DEAD: | |
700 | if (hdev) { | |
701 | free_irq(hdev->irq, hdev); | |
702 | hdev->flags &= ~HPET_DEV_USED; | |
703 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
704 | } | |
705 | break; | |
706 | } | |
707 | return NOTIFY_OK; | |
708 | } | |
709 | #else | |
710 | ||
ba374c9b SN |
711 | static int hpet_setup_msi_irq(unsigned int irq) |
712 | { | |
713 | return 0; | |
714 | } | |
5f79f2f2 VP |
715 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
716 | { | |
717 | return; | |
718 | } | |
719 | ||
720 | #ifdef CONFIG_HPET | |
721 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 722 | { |
723 | return; | |
724 | } | |
5f79f2f2 | 725 | #endif |
26afe5f2 | 726 | |
727 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
728 | unsigned long action, void *hcpu) | |
729 | { | |
730 | return NOTIFY_OK; | |
731 | } | |
732 | ||
733 | #endif | |
734 | ||
6bb74df4 JS |
735 | /* |
736 | * Clock source related code | |
737 | */ | |
8e19608e | 738 | static cycle_t read_hpet(struct clocksource *cs) |
6bb74df4 JS |
739 | { |
740 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
741 | } | |
742 | ||
743 | static struct clocksource clocksource_hpet = { | |
744 | .name = "hpet", | |
745 | .rating = 250, | |
746 | .read = read_hpet, | |
747 | .mask = HPET_MASK, | |
6bb74df4 | 748 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8d6f0c82 | 749 | .resume = hpet_resume_counter, |
28769149 | 750 | #ifdef CONFIG_X86_64 |
98d0ac38 | 751 | .archdata = { .vclock_mode = VCLOCK_HPET }, |
28769149 | 752 | #endif |
6bb74df4 JS |
753 | }; |
754 | ||
610bf2f1 | 755 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 756 | { |
6fd592da | 757 | u64 start, now; |
075bcd1f | 758 | cycle_t t1; |
e9e2cdb4 | 759 | |
e9e2cdb4 | 760 | /* Start the counter */ |
8d6f0c82 | 761 | hpet_restart_counter(); |
e9e2cdb4 | 762 | |
075bcd1f | 763 | /* Verify whether hpet counter works */ |
8e19608e | 764 | t1 = hpet_readl(HPET_COUNTER); |
075bcd1f TG |
765 | rdtscll(start); |
766 | ||
767 | /* | |
768 | * We don't know the TSC frequency yet, but waiting for | |
769 | * 200000 TSC cycles is safe: | |
770 | * 4 GHz == 50us | |
771 | * 1 GHz == 200us | |
772 | */ | |
773 | do { | |
774 | rep_nop(); | |
775 | rdtscll(now); | |
776 | } while ((now - start) < 200000UL); | |
777 | ||
8e19608e | 778 | if (t1 == hpet_readl(HPET_COUNTER)) { |
075bcd1f TG |
779 | printk(KERN_WARNING |
780 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 781 | return -ENODEV; |
075bcd1f TG |
782 | } |
783 | ||
f12a15be | 784 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); |
610bf2f1 VP |
785 | return 0; |
786 | } | |
787 | ||
396e2c6f JB |
788 | static u32 *hpet_boot_cfg; |
789 | ||
b02a7f22 PM |
790 | /** |
791 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
792 | */ |
793 | int __init hpet_enable(void) | |
794 | { | |
396e2c6f | 795 | u32 hpet_period, cfg, id; |
ab0e08f1 | 796 | u64 freq; |
396e2c6f | 797 | unsigned int i, last; |
610bf2f1 VP |
798 | |
799 | if (!is_hpet_capable()) | |
800 | return 0; | |
801 | ||
802 | hpet_set_mapping(); | |
803 | ||
804 | /* | |
805 | * Read the period and check for a sane value: | |
806 | */ | |
807 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
808 | |
809 | /* | |
810 | * AMD SB700 based systems with spread spectrum enabled use a | |
811 | * SMM based HPET emulation to provide proper frequency | |
812 | * setting. The SMM code is initialized with the first HPET | |
813 | * register access and takes some time to complete. During | |
814 | * this time the config register reads 0xffffffff. We check | |
815 | * for max. 1000 loops whether the config register reads a non | |
816 | * 0xffffffff value to make sure that HPET is up and running | |
817 | * before we go further. A counting loop is safe, as the HPET | |
818 | * access takes thousands of CPU cycles. On non SB700 based | |
819 | * machines this check is only done once and has no side | |
820 | * effects. | |
821 | */ | |
822 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
823 | if (i == 1000) { | |
824 | printk(KERN_WARNING | |
825 | "HPET config register value = 0xFFFFFFFF. " | |
826 | "Disabling HPET\n"); | |
827 | goto out_nohpet; | |
828 | } | |
829 | } | |
830 | ||
610bf2f1 VP |
831 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
832 | goto out_nohpet; | |
833 | ||
ab0e08f1 TG |
834 | /* |
835 | * The period is a femto seconds value. Convert it to a | |
836 | * frequency. | |
837 | */ | |
838 | freq = FSEC_PER_SEC; | |
839 | do_div(freq, hpet_period); | |
840 | hpet_freq = freq; | |
841 | ||
610bf2f1 VP |
842 | /* |
843 | * Read the HPET ID register to retrieve the IRQ routing | |
844 | * information and the number of channels | |
845 | */ | |
846 | id = hpet_readl(HPET_ID); | |
b98103a5 | 847 | hpet_print_config(); |
610bf2f1 | 848 | |
396e2c6f JB |
849 | last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; |
850 | ||
610bf2f1 VP |
851 | #ifdef CONFIG_HPET_EMULATE_RTC |
852 | /* | |
853 | * The legacy routing mode needs at least two channels, tick timer | |
854 | * and the rtc emulation channel. | |
855 | */ | |
396e2c6f | 856 | if (!last) |
610bf2f1 VP |
857 | goto out_nohpet; |
858 | #endif | |
859 | ||
396e2c6f JB |
860 | cfg = hpet_readl(HPET_CFG); |
861 | hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg), | |
862 | GFP_KERNEL); | |
863 | if (hpet_boot_cfg) | |
864 | *hpet_boot_cfg = cfg; | |
865 | else | |
866 | pr_warn("HPET initial state will not be saved\n"); | |
867 | cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); | |
868 | hpet_writel(cfg, HPET_Tn_CFG(i)); | |
869 | if (cfg) | |
870 | pr_warn("HPET: Unrecognized bits %#x set in global cfg\n", | |
871 | cfg); | |
872 | ||
873 | for (i = 0; i <= last; ++i) { | |
874 | cfg = hpet_readl(HPET_Tn_CFG(i)); | |
875 | if (hpet_boot_cfg) | |
876 | hpet_boot_cfg[i + 1] = cfg; | |
877 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); | |
878 | hpet_writel(cfg, HPET_Tn_CFG(i)); | |
879 | cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP | |
880 | | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE | |
881 | | HPET_TN_FSB | HPET_TN_FSB_CAP); | |
882 | if (cfg) | |
883 | pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n", | |
884 | cfg, i); | |
885 | } | |
886 | hpet_print_config(); | |
887 | ||
610bf2f1 VP |
888 | if (hpet_clocksource_register()) |
889 | goto out_nohpet; | |
890 | ||
e9e2cdb4 | 891 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 892 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
893 | return 1; |
894 | } | |
895 | return 0; | |
5d0cf410 | 896 | |
e9e2cdb4 | 897 | out_nohpet: |
06a24dec | 898 | hpet_clear_mapping(); |
bacbe999 | 899 | hpet_address = 0; |
e9e2cdb4 TG |
900 | return 0; |
901 | } | |
902 | ||
28769149 TG |
903 | /* |
904 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
905 | * | |
906 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
907 | * but on x86_64 it is necessary ! | |
908 | */ | |
909 | static __init int hpet_late_init(void) | |
910 | { | |
26afe5f2 | 911 | int cpu; |
912 | ||
59c69f2a | 913 | if (boot_hpet_disable) |
28769149 TG |
914 | return -ENODEV; |
915 | ||
59c69f2a VP |
916 | if (!hpet_address) { |
917 | if (!force_hpet_address) | |
918 | return -ENODEV; | |
919 | ||
920 | hpet_address = force_hpet_address; | |
921 | hpet_enable(); | |
59c69f2a VP |
922 | } |
923 | ||
39c04b55 JF |
924 | if (!hpet_virt_address) |
925 | return -ENODEV; | |
926 | ||
39fe05e5 SL |
927 | if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) |
928 | hpet_msi_capability_lookup(2); | |
929 | else | |
930 | hpet_msi_capability_lookup(0); | |
931 | ||
28769149 | 932 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 933 | hpet_print_config(); |
59c69f2a | 934 | |
73472a46 PV |
935 | if (hpet_msi_disable) |
936 | return 0; | |
937 | ||
39fe05e5 SL |
938 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
939 | return 0; | |
940 | ||
26afe5f2 | 941 | for_each_online_cpu(cpu) { |
942 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
943 | } | |
944 | ||
945 | /* This notifier should be called after workqueue is ready */ | |
946 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
947 | ||
28769149 TG |
948 | return 0; |
949 | } | |
950 | fs_initcall(hpet_late_init); | |
951 | ||
c86c7fbc OH |
952 | void hpet_disable(void) |
953 | { | |
ff487808 | 954 | if (is_hpet_capable() && hpet_virt_address) { |
396e2c6f | 955 | unsigned int cfg = hpet_readl(HPET_CFG), id, last; |
c86c7fbc | 956 | |
396e2c6f JB |
957 | if (hpet_boot_cfg) |
958 | cfg = *hpet_boot_cfg; | |
959 | else if (hpet_legacy_int_enabled) { | |
c86c7fbc OH |
960 | cfg &= ~HPET_CFG_LEGACY; |
961 | hpet_legacy_int_enabled = 0; | |
962 | } | |
963 | cfg &= ~HPET_CFG_ENABLE; | |
964 | hpet_writel(cfg, HPET_CFG); | |
396e2c6f JB |
965 | |
966 | if (!hpet_boot_cfg) | |
967 | return; | |
968 | ||
969 | id = hpet_readl(HPET_ID); | |
970 | last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
971 | ||
972 | for (id = 0; id <= last; ++id) | |
973 | hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id)); | |
974 | ||
975 | if (*hpet_boot_cfg & HPET_CFG_ENABLE) | |
976 | hpet_writel(*hpet_boot_cfg, HPET_CFG); | |
c86c7fbc OH |
977 | } |
978 | } | |
979 | ||
e9e2cdb4 TG |
980 | #ifdef CONFIG_HPET_EMULATE_RTC |
981 | ||
982 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
983 | * is enabled, we support RTC interrupt functionality in software. | |
984 | * RTC has 3 kinds of interrupts: | |
985 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
986 | * is updated | |
987 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
988 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
989 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
990 | * (1) and (2) above are implemented using polling at a frequency of | |
991 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
992 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
993 | * For (3), we use interrupts at 64Hz or user specified periodic | |
994 | * frequency, whichever is higher. | |
995 | */ | |
996 | #include <linux/mc146818rtc.h> | |
997 | #include <linux/rtc.h> | |
1bdbdaac | 998 | #include <asm/rtc.h> |
e9e2cdb4 TG |
999 | |
1000 | #define DEFAULT_RTC_INT_FREQ 64 | |
1001 | #define DEFAULT_RTC_SHIFT 6 | |
1002 | #define RTC_NUM_INTS 1 | |
1003 | ||
1004 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 1005 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
1006 | static struct rtc_time hpet_alarm_time; |
1007 | static unsigned long hpet_pie_count; | |
ff08f76d | 1008 | static u32 hpet_t1_cmp; |
5946fa3d JB |
1009 | static u32 hpet_default_delta; |
1010 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
1011 | static unsigned long hpet_pie_limit; |
1012 | ||
1bdbdaac BW |
1013 | static rtc_irq_handler irq_handler; |
1014 | ||
ff08f76d PE |
1015 | /* |
1016 | * Check that the hpet counter c1 is ahead of the c2 | |
1017 | */ | |
1018 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
1019 | { | |
1020 | return (s32)(c2 - c1) < 0; | |
1021 | } | |
1022 | ||
1bdbdaac BW |
1023 | /* |
1024 | * Registers a IRQ handler. | |
1025 | */ | |
1026 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
1027 | { | |
1028 | if (!is_hpet_enabled()) | |
1029 | return -ENODEV; | |
1030 | if (irq_handler) | |
1031 | return -EBUSY; | |
1032 | ||
1033 | irq_handler = handler; | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
1038 | ||
1039 | /* | |
1040 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
1041 | * and does cleanup. | |
1042 | */ | |
1043 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
1044 | { | |
1045 | if (!is_hpet_enabled()) | |
1046 | return; | |
1047 | ||
1048 | irq_handler = NULL; | |
1049 | hpet_rtc_flags = 0; | |
1050 | } | |
1051 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1052 | ||
e9e2cdb4 TG |
1053 | /* |
1054 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
1055 | * is not supported by all HPET implementations for timer 1. | |
1056 | * | |
1057 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1058 | */ | |
1059 | int hpet_rtc_timer_init(void) | |
1060 | { | |
5946fa3d JB |
1061 | unsigned int cfg, cnt, delta; |
1062 | unsigned long flags; | |
e9e2cdb4 TG |
1063 | |
1064 | if (!is_hpet_enabled()) | |
1065 | return 0; | |
1066 | ||
1067 | if (!hpet_default_delta) { | |
1068 | uint64_t clc; | |
1069 | ||
1070 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1071 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1072 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1073 | } |
1074 | ||
1075 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1076 | delta = hpet_default_delta; | |
1077 | else | |
1078 | delta = hpet_pie_delta; | |
1079 | ||
1080 | local_irq_save(flags); | |
1081 | ||
1082 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1083 | hpet_writel(cnt, HPET_T1_CMP); | |
1084 | hpet_t1_cmp = cnt; | |
1085 | ||
1086 | cfg = hpet_readl(HPET_T1_CFG); | |
1087 | cfg &= ~HPET_TN_PERIODIC; | |
1088 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1089 | hpet_writel(cfg, HPET_T1_CFG); | |
1090 | ||
1091 | local_irq_restore(flags); | |
1092 | ||
1093 | return 1; | |
1094 | } | |
1bdbdaac | 1095 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 | 1096 | |
2ded6e6a ML |
1097 | static void hpet_disable_rtc_channel(void) |
1098 | { | |
1099 | unsigned long cfg; | |
1100 | cfg = hpet_readl(HPET_T1_CFG); | |
1101 | cfg &= ~HPET_TN_ENABLE; | |
1102 | hpet_writel(cfg, HPET_T1_CFG); | |
1103 | } | |
1104 | ||
e9e2cdb4 TG |
1105 | /* |
1106 | * The functions below are called from rtc driver. | |
1107 | * Return 0 if HPET is not being used. | |
1108 | * Otherwise do the necessary changes and return 1. | |
1109 | */ | |
1110 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1111 | { | |
1112 | if (!is_hpet_enabled()) | |
1113 | return 0; | |
1114 | ||
1115 | hpet_rtc_flags &= ~bit_mask; | |
2ded6e6a ML |
1116 | if (unlikely(!hpet_rtc_flags)) |
1117 | hpet_disable_rtc_channel(); | |
1118 | ||
e9e2cdb4 TG |
1119 | return 1; |
1120 | } | |
1bdbdaac | 1121 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1122 | |
1123 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1124 | { | |
1125 | unsigned long oldbits = hpet_rtc_flags; | |
1126 | ||
1127 | if (!is_hpet_enabled()) | |
1128 | return 0; | |
1129 | ||
1130 | hpet_rtc_flags |= bit_mask; | |
1131 | ||
7e2a31da DB |
1132 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1133 | hpet_prev_update_sec = -1; | |
1134 | ||
e9e2cdb4 TG |
1135 | if (!oldbits) |
1136 | hpet_rtc_timer_init(); | |
1137 | ||
1138 | return 1; | |
1139 | } | |
1bdbdaac | 1140 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1141 | |
1142 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1143 | unsigned char sec) | |
1144 | { | |
1145 | if (!is_hpet_enabled()) | |
1146 | return 0; | |
1147 | ||
1148 | hpet_alarm_time.tm_hour = hrs; | |
1149 | hpet_alarm_time.tm_min = min; | |
1150 | hpet_alarm_time.tm_sec = sec; | |
1151 | ||
1152 | return 1; | |
1153 | } | |
1bdbdaac | 1154 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1155 | |
1156 | int hpet_set_periodic_freq(unsigned long freq) | |
1157 | { | |
1158 | uint64_t clc; | |
1159 | ||
1160 | if (!is_hpet_enabled()) | |
1161 | return 0; | |
1162 | ||
1163 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1164 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1165 | else { | |
1166 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1167 | do_div(clc, freq); | |
1168 | clc >>= hpet_clockevent.shift; | |
5946fa3d | 1169 | hpet_pie_delta = clc; |
b4a5e8a1 | 1170 | hpet_pie_limit = 0; |
e9e2cdb4 TG |
1171 | } |
1172 | return 1; | |
1173 | } | |
1bdbdaac | 1174 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1175 | |
1176 | int hpet_rtc_dropped_irq(void) | |
1177 | { | |
1178 | return is_hpet_enabled(); | |
1179 | } | |
1bdbdaac | 1180 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1181 | |
1182 | static void hpet_rtc_timer_reinit(void) | |
1183 | { | |
2ded6e6a | 1184 | unsigned int delta; |
e9e2cdb4 TG |
1185 | int lost_ints = -1; |
1186 | ||
2ded6e6a ML |
1187 | if (unlikely(!hpet_rtc_flags)) |
1188 | hpet_disable_rtc_channel(); | |
e9e2cdb4 TG |
1189 | |
1190 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1191 | delta = hpet_default_delta; | |
1192 | else | |
1193 | delta = hpet_pie_delta; | |
1194 | ||
1195 | /* | |
1196 | * Increment the comparator value until we are ahead of the | |
1197 | * current count. | |
1198 | */ | |
1199 | do { | |
1200 | hpet_t1_cmp += delta; | |
1201 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1202 | lost_ints++; | |
ff08f76d | 1203 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1204 | |
1205 | if (lost_ints) { | |
1206 | if (hpet_rtc_flags & RTC_PIE) | |
1207 | hpet_pie_count += lost_ints; | |
1208 | if (printk_ratelimit()) | |
7e2a31da | 1209 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1210 | lost_ints); |
1211 | } | |
1212 | } | |
1213 | ||
1214 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1215 | { | |
1216 | struct rtc_time curr_time; | |
1217 | unsigned long rtc_int_flag = 0; | |
1218 | ||
1219 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1220 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1221 | |
1222 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1223 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1224 | |
1225 | if (hpet_rtc_flags & RTC_UIE && | |
1226 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1227 | if (hpet_prev_update_sec >= 0) |
1228 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1229 | hpet_prev_update_sec = curr_time.tm_sec; |
1230 | } | |
1231 | ||
1232 | if (hpet_rtc_flags & RTC_PIE && | |
1233 | ++hpet_pie_count >= hpet_pie_limit) { | |
1234 | rtc_int_flag |= RTC_PF; | |
1235 | hpet_pie_count = 0; | |
1236 | } | |
1237 | ||
8ee291f8 | 1238 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1239 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1240 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1241 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1242 | rtc_int_flag |= RTC_AF; | |
1243 | ||
1244 | if (rtc_int_flag) { | |
1245 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1246 | if (irq_handler) |
1247 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1248 | } |
1249 | return IRQ_HANDLED; | |
1250 | } | |
1bdbdaac | 1251 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1252 | #endif |