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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 IM |
3 | #include <linux/interrupt.h> |
4 | #include <linux/sysdev.h> | |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 JS |
6 | #include <linux/errno.h> |
7 | #include <linux/hpet.h> | |
8 | #include <linux/init.h> | |
58ac1e76 | 9 | #include <linux/cpu.h> |
4588c1f0 IM |
10 | #include <linux/pm.h> |
11 | #include <linux/io.h> | |
5d0cf410 | 12 | |
28769149 | 13 | #include <asm/fixmap.h> |
06a24dec | 14 | #include <asm/i8253.h> |
4588c1f0 | 15 | #include <asm/hpet.h> |
5d0cf410 | 16 | |
4588c1f0 IM |
17 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
18 | #define HPET_SHIFT 22 | |
5d0cf410 | 19 | |
b10db7f0 PM |
20 | /* FSEC = 10^-15 |
21 | NSEC = 10^-9 */ | |
4588c1f0 | 22 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 23 | |
e9e2cdb4 TG |
24 | /* |
25 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
26 | */ | |
4588c1f0 IM |
27 | unsigned long hpet_address; |
28 | static void __iomem *hpet_virt_address; | |
e9e2cdb4 | 29 | |
58ac1e76 | 30 | struct hpet_dev { |
4588c1f0 IM |
31 | struct clock_event_device evt; |
32 | unsigned int num; | |
33 | int cpu; | |
34 | unsigned int irq; | |
35 | unsigned int flags; | |
36 | char name[10]; | |
58ac1e76 | 37 | }; |
38 | ||
31c435d7 | 39 | unsigned long hpet_readl(unsigned long a) |
e9e2cdb4 TG |
40 | { |
41 | return readl(hpet_virt_address + a); | |
42 | } | |
43 | ||
44 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
45 | { | |
46 | writel(d, hpet_virt_address + a); | |
47 | } | |
48 | ||
28769149 | 49 | #ifdef CONFIG_X86_64 |
28769149 | 50 | #include <asm/pgtable.h> |
2387ce57 | 51 | #endif |
28769149 | 52 | |
06a24dec TG |
53 | static inline void hpet_set_mapping(void) |
54 | { | |
55 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 YL |
56 | #ifdef CONFIG_X86_64 |
57 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
58 | #endif | |
06a24dec TG |
59 | } |
60 | ||
61 | static inline void hpet_clear_mapping(void) | |
62 | { | |
63 | iounmap(hpet_virt_address); | |
64 | hpet_virt_address = NULL; | |
65 | } | |
66 | ||
e9e2cdb4 TG |
67 | /* |
68 | * HPET command line enable / disable | |
69 | */ | |
70 | static int boot_hpet_disable; | |
b17530bd | 71 | int hpet_force_user; |
e9e2cdb4 | 72 | |
4588c1f0 | 73 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
74 | { |
75 | if (str) { | |
76 | if (!strncmp("disable", str, 7)) | |
77 | boot_hpet_disable = 1; | |
b17530bd TG |
78 | if (!strncmp("force", str, 5)) |
79 | hpet_force_user = 1; | |
e9e2cdb4 TG |
80 | } |
81 | return 1; | |
82 | } | |
83 | __setup("hpet=", hpet_setup); | |
84 | ||
28769149 TG |
85 | static int __init disable_hpet(char *str) |
86 | { | |
87 | boot_hpet_disable = 1; | |
88 | return 1; | |
89 | } | |
90 | __setup("nohpet", disable_hpet); | |
91 | ||
e9e2cdb4 TG |
92 | static inline int is_hpet_capable(void) |
93 | { | |
4588c1f0 | 94 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
95 | } |
96 | ||
97 | /* | |
98 | * HPET timer interrupt enable / disable | |
99 | */ | |
100 | static int hpet_legacy_int_enabled; | |
101 | ||
102 | /** | |
103 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
104 | */ | |
105 | int is_hpet_enabled(void) | |
106 | { | |
107 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
108 | } | |
1bdbdaac | 109 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 TG |
110 | |
111 | /* | |
112 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
113 | * timer 0 and timer 1 in case of RTC emulation. | |
114 | */ | |
115 | #ifdef CONFIG_HPET | |
116 | static void hpet_reserve_platform_timers(unsigned long id) | |
117 | { | |
118 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
119 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
120 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
121 | struct hpet_data hd; |
122 | ||
123 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
124 | ||
4588c1f0 IM |
125 | memset(&hd, 0, sizeof(hd)); |
126 | hd.hd_phys_address = hpet_address; | |
127 | hd.hd_address = hpet; | |
128 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
129 | hpet_reserve_timer(&hd, 0); |
130 | ||
131 | #ifdef CONFIG_HPET_EMULATE_RTC | |
132 | hpet_reserve_timer(&hd, 1); | |
133 | #endif | |
5761d64b | 134 | |
64a76f66 DB |
135 | /* |
136 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
137 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
138 | * don't bother configuring *any* comparator interrupts. | |
139 | */ | |
e9e2cdb4 TG |
140 | hd.hd_irq[0] = HPET_LEGACY_8254; |
141 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
142 | ||
fc3fbc45 | 143 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
144 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
145 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 146 | } |
5761d64b | 147 | |
e9e2cdb4 | 148 | hpet_alloc(&hd); |
5761d64b | 149 | |
e9e2cdb4 TG |
150 | } |
151 | #else | |
152 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
153 | #endif | |
154 | ||
155 | /* | |
156 | * Common hpet info | |
157 | */ | |
158 | static unsigned long hpet_period; | |
159 | ||
610bf2f1 | 160 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 161 | struct clock_event_device *evt); |
610bf2f1 | 162 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
163 | struct clock_event_device *evt); |
164 | ||
165 | /* | |
166 | * The hpet clock event device | |
167 | */ | |
168 | static struct clock_event_device hpet_clockevent = { | |
169 | .name = "hpet", | |
170 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
171 | .set_mode = hpet_legacy_set_mode, |
172 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 TG |
173 | .shift = 32, |
174 | .irq = 0, | |
59c69f2a | 175 | .rating = 50, |
e9e2cdb4 TG |
176 | }; |
177 | ||
178 | static void hpet_start_counter(void) | |
179 | { | |
180 | unsigned long cfg = hpet_readl(HPET_CFG); | |
181 | ||
182 | cfg &= ~HPET_CFG_ENABLE; | |
183 | hpet_writel(cfg, HPET_CFG); | |
184 | hpet_writel(0, HPET_COUNTER); | |
185 | hpet_writel(0, HPET_COUNTER + 4); | |
186 | cfg |= HPET_CFG_ENABLE; | |
187 | hpet_writel(cfg, HPET_CFG); | |
188 | } | |
189 | ||
59c69f2a VP |
190 | static void hpet_resume_device(void) |
191 | { | |
bfe0c1cc | 192 | force_hpet_resume(); |
59c69f2a VP |
193 | } |
194 | ||
195 | static void hpet_restart_counter(void) | |
196 | { | |
197 | hpet_resume_device(); | |
198 | hpet_start_counter(); | |
199 | } | |
200 | ||
610bf2f1 | 201 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 TG |
202 | { |
203 | unsigned long cfg = hpet_readl(HPET_CFG); | |
204 | ||
205 | cfg |= HPET_CFG_LEGACY; | |
206 | hpet_writel(cfg, HPET_CFG); | |
207 | hpet_legacy_int_enabled = 1; | |
208 | } | |
209 | ||
610bf2f1 VP |
210 | static void hpet_legacy_clockevent_register(void) |
211 | { | |
610bf2f1 VP |
212 | /* Start HPET legacy interrupts */ |
213 | hpet_enable_legacy_int(); | |
214 | ||
215 | /* | |
6fd592da CM |
216 | * The mult factor is defined as (include/linux/clockchips.h) |
217 | * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) | |
218 | * hpet_period is in units of femtoseconds (per cycle), so | |
219 | * mult/2^shift = cyc/ns = 10^6/hpet_period | |
220 | * mult = (10^6 * 2^shift)/hpet_period | |
221 | * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period | |
610bf2f1 | 222 | */ |
6fd592da CM |
223 | hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, |
224 | hpet_period, hpet_clockevent.shift); | |
610bf2f1 VP |
225 | /* Calculate the min / max delta */ |
226 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
227 | &hpet_clockevent); | |
7cfb0435 TG |
228 | /* 5 usec minimum reprogramming delta. */ |
229 | hpet_clockevent.min_delta_ns = 5000; | |
610bf2f1 VP |
230 | |
231 | /* | |
232 | * Start hpet with the boot cpu mask and make it | |
233 | * global after the IO_APIC has been initialized. | |
234 | */ | |
235 | hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); | |
236 | clockevents_register_device(&hpet_clockevent); | |
237 | global_clock_event = &hpet_clockevent; | |
238 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
239 | } | |
240 | ||
b40d575b | 241 | static void hpet_set_mode(enum clock_event_mode mode, |
242 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 TG |
243 | { |
244 | unsigned long cfg, cmp, now; | |
245 | uint64_t delta; | |
246 | ||
4588c1f0 | 247 | switch (mode) { |
e9e2cdb4 | 248 | case CLOCK_EVT_MODE_PERIODIC: |
b40d575b | 249 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
250 | delta >>= evt->shift; | |
e9e2cdb4 TG |
251 | now = hpet_readl(HPET_COUNTER); |
252 | cmp = now + (unsigned long) delta; | |
b40d575b | 253 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
254 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
255 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 256 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
257 | /* |
258 | * The first write after writing TN_SETVAL to the | |
259 | * config register sets the counter value, the second | |
260 | * write sets the period. | |
261 | */ | |
b40d575b | 262 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 263 | udelay(1); |
b40d575b | 264 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); |
e9e2cdb4 TG |
265 | break; |
266 | ||
267 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 268 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
269 | cfg &= ~HPET_TN_PERIODIC; |
270 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 271 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
272 | break; |
273 | ||
274 | case CLOCK_EVT_MODE_UNUSED: | |
275 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 276 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 277 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 278 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 279 | break; |
18de5bc4 TG |
280 | |
281 | case CLOCK_EVT_MODE_RESUME: | |
610bf2f1 | 282 | hpet_enable_legacy_int(); |
18de5bc4 | 283 | break; |
e9e2cdb4 TG |
284 | } |
285 | } | |
286 | ||
b40d575b | 287 | static int hpet_next_event(unsigned long delta, |
288 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 289 | { |
f7676254 | 290 | u32 cnt; |
e9e2cdb4 TG |
291 | |
292 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 293 | cnt += (u32) delta; |
b40d575b | 294 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 295 | |
72d43d9b TG |
296 | /* |
297 | * We need to read back the CMP register to make sure that | |
298 | * what we wrote hit the chip before we compare it to the | |
299 | * counter. | |
300 | */ | |
301 | WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt); | |
302 | ||
f7676254 | 303 | return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; |
e9e2cdb4 TG |
304 | } |
305 | ||
b40d575b | 306 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
307 | struct clock_event_device *evt) | |
308 | { | |
309 | hpet_set_mode(mode, evt, 0); | |
310 | } | |
311 | ||
312 | static int hpet_legacy_next_event(unsigned long delta, | |
313 | struct clock_event_device *evt) | |
314 | { | |
315 | return hpet_next_event(delta, evt, 0); | |
316 | } | |
317 | ||
58ac1e76 | 318 | /* |
319 | * HPET MSI Support | |
320 | */ | |
321 | ||
322 | void hpet_msi_unmask(unsigned int irq) | |
323 | { | |
324 | struct hpet_dev *hdev = get_irq_data(irq); | |
325 | unsigned long cfg; | |
326 | ||
327 | /* unmask it */ | |
328 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
329 | cfg |= HPET_TN_FSB; | |
330 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
331 | } | |
332 | ||
333 | void hpet_msi_mask(unsigned int irq) | |
334 | { | |
335 | unsigned long cfg; | |
336 | struct hpet_dev *hdev = get_irq_data(irq); | |
337 | ||
338 | /* mask it */ | |
339 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
340 | cfg &= ~HPET_TN_FSB; | |
341 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
342 | } | |
343 | ||
344 | void hpet_msi_write(unsigned int irq, struct msi_msg *msg) | |
345 | { | |
346 | struct hpet_dev *hdev = get_irq_data(irq); | |
347 | ||
348 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); | |
349 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
350 | } | |
351 | ||
352 | void hpet_msi_read(unsigned int irq, struct msi_msg *msg) | |
353 | { | |
354 | struct hpet_dev *hdev = get_irq_data(irq); | |
355 | ||
356 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); | |
357 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
358 | msg->address_hi = 0; | |
359 | } | |
360 | ||
6bb74df4 JS |
361 | /* |
362 | * Clock source related code | |
363 | */ | |
364 | static cycle_t read_hpet(void) | |
365 | { | |
366 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
367 | } | |
368 | ||
28769149 TG |
369 | #ifdef CONFIG_X86_64 |
370 | static cycle_t __vsyscall_fn vread_hpet(void) | |
371 | { | |
372 | return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); | |
373 | } | |
374 | #endif | |
375 | ||
6bb74df4 JS |
376 | static struct clocksource clocksource_hpet = { |
377 | .name = "hpet", | |
378 | .rating = 250, | |
379 | .read = read_hpet, | |
380 | .mask = HPET_MASK, | |
381 | .shift = HPET_SHIFT, | |
382 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
59c69f2a | 383 | .resume = hpet_restart_counter, |
28769149 TG |
384 | #ifdef CONFIG_X86_64 |
385 | .vread = vread_hpet, | |
386 | #endif | |
6bb74df4 JS |
387 | }; |
388 | ||
610bf2f1 | 389 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 390 | { |
6fd592da | 391 | u64 start, now; |
075bcd1f | 392 | cycle_t t1; |
e9e2cdb4 | 393 | |
e9e2cdb4 TG |
394 | /* Start the counter */ |
395 | hpet_start_counter(); | |
396 | ||
075bcd1f TG |
397 | /* Verify whether hpet counter works */ |
398 | t1 = read_hpet(); | |
399 | rdtscll(start); | |
400 | ||
401 | /* | |
402 | * We don't know the TSC frequency yet, but waiting for | |
403 | * 200000 TSC cycles is safe: | |
404 | * 4 GHz == 50us | |
405 | * 1 GHz == 200us | |
406 | */ | |
407 | do { | |
408 | rep_nop(); | |
409 | rdtscll(now); | |
410 | } while ((now - start) < 200000UL); | |
411 | ||
412 | if (t1 == read_hpet()) { | |
413 | printk(KERN_WARNING | |
414 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 415 | return -ENODEV; |
075bcd1f TG |
416 | } |
417 | ||
6fd592da CM |
418 | /* |
419 | * The definition of mult is (include/linux/clocksource.h) | |
420 | * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc | |
421 | * so we first need to convert hpet_period to ns/cyc units: | |
422 | * mult/2^shift = ns/cyc = hpet_period/10^6 | |
423 | * mult = (hpet_period * 2^shift)/10^6 | |
424 | * mult = (hpet_period << shift)/FSEC_PER_NSEC | |
6bb74df4 | 425 | */ |
6fd592da | 426 | clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT); |
6bb74df4 JS |
427 | |
428 | clocksource_register(&clocksource_hpet); | |
429 | ||
610bf2f1 VP |
430 | return 0; |
431 | } | |
432 | ||
b02a7f22 PM |
433 | /** |
434 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
435 | */ |
436 | int __init hpet_enable(void) | |
437 | { | |
438 | unsigned long id; | |
a6825f1c | 439 | int i; |
610bf2f1 VP |
440 | |
441 | if (!is_hpet_capable()) | |
442 | return 0; | |
443 | ||
444 | hpet_set_mapping(); | |
445 | ||
446 | /* | |
447 | * Read the period and check for a sane value: | |
448 | */ | |
449 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
450 | |
451 | /* | |
452 | * AMD SB700 based systems with spread spectrum enabled use a | |
453 | * SMM based HPET emulation to provide proper frequency | |
454 | * setting. The SMM code is initialized with the first HPET | |
455 | * register access and takes some time to complete. During | |
456 | * this time the config register reads 0xffffffff. We check | |
457 | * for max. 1000 loops whether the config register reads a non | |
458 | * 0xffffffff value to make sure that HPET is up and running | |
459 | * before we go further. A counting loop is safe, as the HPET | |
460 | * access takes thousands of CPU cycles. On non SB700 based | |
461 | * machines this check is only done once and has no side | |
462 | * effects. | |
463 | */ | |
464 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
465 | if (i == 1000) { | |
466 | printk(KERN_WARNING | |
467 | "HPET config register value = 0xFFFFFFFF. " | |
468 | "Disabling HPET\n"); | |
469 | goto out_nohpet; | |
470 | } | |
471 | } | |
472 | ||
610bf2f1 VP |
473 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
474 | goto out_nohpet; | |
475 | ||
476 | /* | |
477 | * Read the HPET ID register to retrieve the IRQ routing | |
478 | * information and the number of channels | |
479 | */ | |
480 | id = hpet_readl(HPET_ID); | |
481 | ||
482 | #ifdef CONFIG_HPET_EMULATE_RTC | |
483 | /* | |
484 | * The legacy routing mode needs at least two channels, tick timer | |
485 | * and the rtc emulation channel. | |
486 | */ | |
487 | if (!(id & HPET_ID_NUMBER)) | |
488 | goto out_nohpet; | |
489 | #endif | |
490 | ||
491 | if (hpet_clocksource_register()) | |
492 | goto out_nohpet; | |
493 | ||
e9e2cdb4 | 494 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 495 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
496 | return 1; |
497 | } | |
498 | return 0; | |
5d0cf410 | 499 | |
e9e2cdb4 | 500 | out_nohpet: |
06a24dec | 501 | hpet_clear_mapping(); |
399afa4f | 502 | boot_hpet_disable = 1; |
e9e2cdb4 TG |
503 | return 0; |
504 | } | |
505 | ||
28769149 TG |
506 | /* |
507 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
508 | * | |
509 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
510 | * but on x86_64 it is necessary ! | |
511 | */ | |
512 | static __init int hpet_late_init(void) | |
513 | { | |
59c69f2a | 514 | if (boot_hpet_disable) |
28769149 TG |
515 | return -ENODEV; |
516 | ||
59c69f2a VP |
517 | if (!hpet_address) { |
518 | if (!force_hpet_address) | |
519 | return -ENODEV; | |
520 | ||
521 | hpet_address = force_hpet_address; | |
522 | hpet_enable(); | |
523 | if (!hpet_virt_address) | |
524 | return -ENODEV; | |
525 | } | |
526 | ||
28769149 | 527 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
59c69f2a | 528 | |
28769149 TG |
529 | return 0; |
530 | } | |
531 | fs_initcall(hpet_late_init); | |
532 | ||
c86c7fbc OH |
533 | void hpet_disable(void) |
534 | { | |
535 | if (is_hpet_capable()) { | |
536 | unsigned long cfg = hpet_readl(HPET_CFG); | |
537 | ||
538 | if (hpet_legacy_int_enabled) { | |
539 | cfg &= ~HPET_CFG_LEGACY; | |
540 | hpet_legacy_int_enabled = 0; | |
541 | } | |
542 | cfg &= ~HPET_CFG_ENABLE; | |
543 | hpet_writel(cfg, HPET_CFG); | |
544 | } | |
545 | } | |
546 | ||
e9e2cdb4 TG |
547 | #ifdef CONFIG_HPET_EMULATE_RTC |
548 | ||
549 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
550 | * is enabled, we support RTC interrupt functionality in software. | |
551 | * RTC has 3 kinds of interrupts: | |
552 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
553 | * is updated | |
554 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
555 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
556 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
557 | * (1) and (2) above are implemented using polling at a frequency of | |
558 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
559 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
560 | * For (3), we use interrupts at 64Hz or user specified periodic | |
561 | * frequency, whichever is higher. | |
562 | */ | |
563 | #include <linux/mc146818rtc.h> | |
564 | #include <linux/rtc.h> | |
1bdbdaac | 565 | #include <asm/rtc.h> |
e9e2cdb4 TG |
566 | |
567 | #define DEFAULT_RTC_INT_FREQ 64 | |
568 | #define DEFAULT_RTC_SHIFT 6 | |
569 | #define RTC_NUM_INTS 1 | |
570 | ||
571 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 572 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
573 | static struct rtc_time hpet_alarm_time; |
574 | static unsigned long hpet_pie_count; | |
575 | static unsigned long hpet_t1_cmp; | |
576 | static unsigned long hpet_default_delta; | |
577 | static unsigned long hpet_pie_delta; | |
578 | static unsigned long hpet_pie_limit; | |
579 | ||
1bdbdaac BW |
580 | static rtc_irq_handler irq_handler; |
581 | ||
582 | /* | |
583 | * Registers a IRQ handler. | |
584 | */ | |
585 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
586 | { | |
587 | if (!is_hpet_enabled()) | |
588 | return -ENODEV; | |
589 | if (irq_handler) | |
590 | return -EBUSY; | |
591 | ||
592 | irq_handler = handler; | |
593 | ||
594 | return 0; | |
595 | } | |
596 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
597 | ||
598 | /* | |
599 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
600 | * and does cleanup. | |
601 | */ | |
602 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
603 | { | |
604 | if (!is_hpet_enabled()) | |
605 | return; | |
606 | ||
607 | irq_handler = NULL; | |
608 | hpet_rtc_flags = 0; | |
609 | } | |
610 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
611 | ||
e9e2cdb4 TG |
612 | /* |
613 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
614 | * is not supported by all HPET implementations for timer 1. | |
615 | * | |
616 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
617 | */ | |
618 | int hpet_rtc_timer_init(void) | |
619 | { | |
620 | unsigned long cfg, cnt, delta, flags; | |
621 | ||
622 | if (!is_hpet_enabled()) | |
623 | return 0; | |
624 | ||
625 | if (!hpet_default_delta) { | |
626 | uint64_t clc; | |
627 | ||
628 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
629 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
630 | hpet_default_delta = (unsigned long) clc; | |
631 | } | |
632 | ||
633 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
634 | delta = hpet_default_delta; | |
635 | else | |
636 | delta = hpet_pie_delta; | |
637 | ||
638 | local_irq_save(flags); | |
639 | ||
640 | cnt = delta + hpet_readl(HPET_COUNTER); | |
641 | hpet_writel(cnt, HPET_T1_CMP); | |
642 | hpet_t1_cmp = cnt; | |
643 | ||
644 | cfg = hpet_readl(HPET_T1_CFG); | |
645 | cfg &= ~HPET_TN_PERIODIC; | |
646 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
647 | hpet_writel(cfg, HPET_T1_CFG); | |
648 | ||
649 | local_irq_restore(flags); | |
650 | ||
651 | return 1; | |
652 | } | |
1bdbdaac | 653 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
654 | |
655 | /* | |
656 | * The functions below are called from rtc driver. | |
657 | * Return 0 if HPET is not being used. | |
658 | * Otherwise do the necessary changes and return 1. | |
659 | */ | |
660 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
661 | { | |
662 | if (!is_hpet_enabled()) | |
663 | return 0; | |
664 | ||
665 | hpet_rtc_flags &= ~bit_mask; | |
666 | return 1; | |
667 | } | |
1bdbdaac | 668 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
669 | |
670 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
671 | { | |
672 | unsigned long oldbits = hpet_rtc_flags; | |
673 | ||
674 | if (!is_hpet_enabled()) | |
675 | return 0; | |
676 | ||
677 | hpet_rtc_flags |= bit_mask; | |
678 | ||
7e2a31da DB |
679 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
680 | hpet_prev_update_sec = -1; | |
681 | ||
e9e2cdb4 TG |
682 | if (!oldbits) |
683 | hpet_rtc_timer_init(); | |
684 | ||
685 | return 1; | |
686 | } | |
1bdbdaac | 687 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
688 | |
689 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
690 | unsigned char sec) | |
691 | { | |
692 | if (!is_hpet_enabled()) | |
693 | return 0; | |
694 | ||
695 | hpet_alarm_time.tm_hour = hrs; | |
696 | hpet_alarm_time.tm_min = min; | |
697 | hpet_alarm_time.tm_sec = sec; | |
698 | ||
699 | return 1; | |
700 | } | |
1bdbdaac | 701 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
702 | |
703 | int hpet_set_periodic_freq(unsigned long freq) | |
704 | { | |
705 | uint64_t clc; | |
706 | ||
707 | if (!is_hpet_enabled()) | |
708 | return 0; | |
709 | ||
710 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
711 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
712 | else { | |
713 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
714 | do_div(clc, freq); | |
715 | clc >>= hpet_clockevent.shift; | |
716 | hpet_pie_delta = (unsigned long) clc; | |
717 | } | |
718 | return 1; | |
719 | } | |
1bdbdaac | 720 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
721 | |
722 | int hpet_rtc_dropped_irq(void) | |
723 | { | |
724 | return is_hpet_enabled(); | |
725 | } | |
1bdbdaac | 726 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
727 | |
728 | static void hpet_rtc_timer_reinit(void) | |
729 | { | |
730 | unsigned long cfg, delta; | |
731 | int lost_ints = -1; | |
732 | ||
733 | if (unlikely(!hpet_rtc_flags)) { | |
734 | cfg = hpet_readl(HPET_T1_CFG); | |
735 | cfg &= ~HPET_TN_ENABLE; | |
736 | hpet_writel(cfg, HPET_T1_CFG); | |
737 | return; | |
738 | } | |
739 | ||
740 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
741 | delta = hpet_default_delta; | |
742 | else | |
743 | delta = hpet_pie_delta; | |
744 | ||
745 | /* | |
746 | * Increment the comparator value until we are ahead of the | |
747 | * current count. | |
748 | */ | |
749 | do { | |
750 | hpet_t1_cmp += delta; | |
751 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
752 | lost_ints++; | |
753 | } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); | |
754 | ||
755 | if (lost_ints) { | |
756 | if (hpet_rtc_flags & RTC_PIE) | |
757 | hpet_pie_count += lost_ints; | |
758 | if (printk_ratelimit()) | |
7e2a31da | 759 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
760 | lost_ints); |
761 | } | |
762 | } | |
763 | ||
764 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
765 | { | |
766 | struct rtc_time curr_time; | |
767 | unsigned long rtc_int_flag = 0; | |
768 | ||
769 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 770 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
771 | |
772 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 773 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
774 | |
775 | if (hpet_rtc_flags & RTC_UIE && | |
776 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
777 | if (hpet_prev_update_sec >= 0) |
778 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
779 | hpet_prev_update_sec = curr_time.tm_sec; |
780 | } | |
781 | ||
782 | if (hpet_rtc_flags & RTC_PIE && | |
783 | ++hpet_pie_count >= hpet_pie_limit) { | |
784 | rtc_int_flag |= RTC_PF; | |
785 | hpet_pie_count = 0; | |
786 | } | |
787 | ||
8ee291f8 | 788 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
789 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
790 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
791 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
792 | rtc_int_flag |= RTC_AF; | |
793 | ||
794 | if (rtc_int_flag) { | |
795 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
796 | if (irq_handler) |
797 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
798 | } |
799 | return IRQ_HANDLED; | |
800 | } | |
1bdbdaac | 801 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 802 | #endif |