[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kernel / hpet.c

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/hpet.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/pm.h>
#include <linux/delay.h>

#include <asm/fixmap.h>
#include <asm/hpet.h>
#include <asm/i8253.h>
#include <asm/io.h>

#define HPET_MASK	CLOCKSOURCE_MASK(32)
#define HPET_SHIFT	22

/* FSEC = 10^-15 NSEC = 10^-9 */
#define FSEC_PER_NSEC	1000000

/*
 * HPET address is set in acpi/boot.c, when an ACPI entry exists
 */
unsigned long hpet_address;
static void __iomem *hpet_virt_address;

unsigned long hpet_readl(unsigned long a)
{
	return readl(hpet_virt_address + a);
}

static inline void hpet_writel(unsigned long d, unsigned long a)
{
	writel(d, hpet_virt_address + a);
}

#ifdef CONFIG_X86_64

#include <asm/pgtable.h>

static inline void hpet_set_mapping(void)
{
	set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
	__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
	hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
}

static inline void hpet_clear_mapping(void)
{
	hpet_virt_address = NULL;
}

#else

static inline void hpet_set_mapping(void)
{
	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
}

static inline void hpet_clear_mapping(void)
{
	iounmap(hpet_virt_address);
	hpet_virt_address = NULL;
}
#endif

/*
 * HPET command line enable / disable
 */
static int boot_hpet_disable;
int hpet_force_user;

static int __init hpet_setup(char* str)
{
	if (str) {
		if (!strncmp("disable", str, 7))
			boot_hpet_disable = 1;
		if (!strncmp("force", str, 5))
			hpet_force_user = 1;
	}
	return 1;
}
__setup("hpet=", hpet_setup);

static int __init disable_hpet(char *str)
{
	boot_hpet_disable = 1;
	return 1;
}
__setup("nohpet", disable_hpet);

static inline int is_hpet_capable(void)
{
	return (!boot_hpet_disable && hpet_address);
}

/*
 * HPET timer interrupt enable / disable
 */
static int hpet_legacy_int_enabled;

/**
 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 */
int is_hpet_enabled(void)
{
	return is_hpet_capable() && hpet_legacy_int_enabled;
}

/*
 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 * timer 0 and timer 1 in case of RTC emulation.
 */
#ifdef CONFIG_HPET
static void hpet_reserve_platform_timers(unsigned long id)
{
	struct hpet __iomem *hpet = hpet_virt_address;
	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
	unsigned int nrtimers, i;
	struct hpet_data hd;

	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;

	memset(&hd, 0, sizeof (hd));
	hd.hd_phys_address = hpet_address;
	hd.hd_address = hpet;
	hd.hd_nirqs = nrtimers;
	hd.hd_flags = HPET_DATA_PLATFORM;
	hpet_reserve_timer(&hd, 0);

#ifdef CONFIG_HPET_EMULATE_RTC
	hpet_reserve_timer(&hd, 1);
#endif

	hd.hd_irq[0] = HPET_LEGACY_8254;
	hd.hd_irq[1] = HPET_LEGACY_RTC;

	for (i = 2; i < nrtimers; timer++, i++)
		hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
			Tn_INT_ROUTE_CNF_SHIFT;

	hpet_alloc(&hd);

}
#else
static void hpet_reserve_platform_timers(unsigned long id) { }
#endif

/*
 * Common hpet info
 */
static unsigned long hpet_period;

static void hpet_legacy_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt);
static int hpet_legacy_next_event(unsigned long delta,
			   struct clock_event_device *evt);

/*
 * The hpet clock event device
 */
static struct clock_event_device hpet_clockevent = {
	.name		= "hpet",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= hpet_legacy_set_mode,
	.set_next_event = hpet_legacy_next_event,
	.shift		= 32,
	.irq		= 0,
	.rating		= 50,
};

static void hpet_start_counter(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg &= ~HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
	hpet_writel(0, HPET_COUNTER);
	hpet_writel(0, HPET_COUNTER + 4);
	cfg |= HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
}

static void hpet_resume_device(void)
{
	force_hpet_resume();
}

static void hpet_restart_counter(void)
{
	hpet_resume_device();
	hpet_start_counter();
}

static void hpet_enable_legacy_int(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg |= HPET_CFG_LEGACY;
	hpet_writel(cfg, HPET_CFG);
	hpet_legacy_int_enabled = 1;
}

static void hpet_legacy_clockevent_register(void)
{
	uint64_t hpet_freq;

	/* Start HPET legacy interrupts */
	hpet_enable_legacy_int();

	/*
	 * The period is a femto seconds value. We need to calculate the
	 * scaled math multiplication factor for nanosecond to hpet tick
	 * conversion.
	 */
	hpet_freq = 1000000000000000ULL;
	do_div(hpet_freq, hpet_period);
	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
				      NSEC_PER_SEC, 32);
	/* Calculate the min / max delta */
	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
							   &hpet_clockevent);
	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
							   &hpet_clockevent);

	/*
	 * Start hpet with the boot cpu mask and make it
	 * global after the IO_APIC has been initialized.
	 */
	hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
	clockevents_register_device(&hpet_clockevent);
	global_clock_event = &hpet_clockevent;
	printk(KERN_DEBUG "hpet clockevent registered\n");
}

static void hpet_legacy_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt)
{
	unsigned long cfg, cmp, now;
	uint64_t delta;

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
		delta >>= hpet_clockevent.shift;
		now = hpet_readl(HPET_COUNTER);
		cmp = now + (unsigned long) delta;
		cfg = hpet_readl(HPET_T0_CFG);
		cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
		       HPET_TN_SETVAL | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		/*
		 * The first write after writing TN_SETVAL to the
		 * config register sets the counter value, the second
		 * write sets the period.
		 */
		hpet_writel(cmp, HPET_T0_CMP);
		udelay(1);
		hpet_writel((unsigned long) delta, HPET_T0_CMP);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_PERIODIC;
		cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_RESUME:
		hpet_enable_legacy_int();
		break;
	}
}

static int hpet_legacy_next_event(unsigned long delta,
			   struct clock_event_device *evt)
{
	unsigned long cnt;

	cnt = hpet_readl(HPET_COUNTER);
	cnt += delta;
	hpet_writel(cnt, HPET_T0_CMP);

	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
}

/*
 * Clock source related code
 */
static cycle_t read_hpet(void)
{
	return (cycle_t)hpet_readl(HPET_COUNTER);
}

#ifdef CONFIG_X86_64
static cycle_t __vsyscall_fn vread_hpet(void)
{
	return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
}
#endif

static struct clocksource clocksource_hpet = {
	.name		= "hpet",
	.rating		= 250,
	.read		= read_hpet,
	.mask		= HPET_MASK,
	.shift		= HPET_SHIFT,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= hpet_restart_counter,
#ifdef CONFIG_X86_64
	.vread		= vread_hpet,
#endif
};

static int hpet_clocksource_register(void)
{
	u64 tmp, start, now;
	cycle_t t1;

	/* Start the counter */
	hpet_start_counter();

	/* Verify whether hpet counter works */
	t1 = read_hpet();
	rdtscll(start);

	/*
	 * We don't know the TSC frequency yet, but waiting for
	 * 200000 TSC cycles is safe:
	 * 4 GHz == 50us
	 * 1 GHz == 200us
	 */
	do {
		rep_nop();
		rdtscll(now);
	} while ((now - start) < 200000UL);

	if (t1 == read_hpet()) {
		printk(KERN_WARNING
		       "HPET counter not counting. HPET disabled\n");
		return -ENODEV;
	}

	/* Initialize and register HPET clocksource
	 *
	 * hpet period is in femto seconds per cycle
	 * so we need to convert this to ns/cyc units
	 * approximated by mult/2^shift
	 *
	 *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	 *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	 *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	 *  (fsec/cyc << shift)/1000000 = mult
	 *  (hpet_period << shift)/FSEC_PER_NSEC = mult
	 */
	tmp = (u64)hpet_period << HPET_SHIFT;
	do_div(tmp, FSEC_PER_NSEC);
	clocksource_hpet.mult = (u32)tmp;

	clocksource_register(&clocksource_hpet);

	return 0;
}

/*
 * Try to setup the HPET timer
 */
int __init hpet_enable(void)
{
	unsigned long id;

	if (!is_hpet_capable())
		return 0;

	hpet_set_mapping();

	/*
	 * Read the period and check for a sane value:
	 */
	hpet_period = hpet_readl(HPET_PERIOD);
	if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
		goto out_nohpet;

	/*
	 * Read the HPET ID register to retrieve the IRQ routing
	 * information and the number of channels
	 */
	id = hpet_readl(HPET_ID);

#ifdef CONFIG_HPET_EMULATE_RTC
	/*
	 * The legacy routing mode needs at least two channels, tick timer
	 * and the rtc emulation channel.
	 */
	if (!(id & HPET_ID_NUMBER))
		goto out_nohpet;
#endif

	if (hpet_clocksource_register())
		goto out_nohpet;

	if (id & HPET_ID_LEGSUP) {
		hpet_legacy_clockevent_register();
		return 1;
	}
	return 0;

out_nohpet:
	hpet_clear_mapping();
	boot_hpet_disable = 1;
	return 0;
}

/*
 * Needs to be late, as the reserve_timer code calls kalloc !
 *
 * Not a problem on i386 as hpet_enable is called from late_time_init,
 * but on x86_64 it is necessary !
 */
static __init int hpet_late_init(void)
{
	if (boot_hpet_disable)
		return -ENODEV;

	if (!hpet_address) {
		if (!force_hpet_address)
			return -ENODEV;

		hpet_address = force_hpet_address;
		hpet_enable();
		if (!hpet_virt_address)
			return -ENODEV;
	}

	hpet_reserve_platform_timers(hpet_readl(HPET_ID));

	return 0;
}
fs_initcall(hpet_late_init);

void hpet_disable(void)
{
	if (is_hpet_capable()) {
		unsigned long cfg = hpet_readl(HPET_CFG);

		if (hpet_legacy_int_enabled) {
			cfg &= ~HPET_CFG_LEGACY;
			hpet_legacy_int_enabled = 0;
		}
		cfg &= ~HPET_CFG_ENABLE;
		hpet_writel(cfg, HPET_CFG);
	}
}

#ifdef CONFIG_HPET_EMULATE_RTC

/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 * is enabled, we support RTC interrupt functionality in software.
 * RTC has 3 kinds of interrupts:
 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 *    is updated
 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 * (1) and (2) above are implemented using polling at a frequency of
 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 * overhead. (DEFAULT_RTC_INT_FREQ)
 * For (3), we use interrupts at 64Hz or user specified periodic
 * frequency, whichever is higher.
 */
#include <linux/mc146818rtc.h>
#include <linux/rtc.h>

#define DEFAULT_RTC_INT_FREQ	64
#define DEFAULT_RTC_SHIFT	6
#define RTC_NUM_INTS		1

static unsigned long hpet_rtc_flags;
static unsigned long hpet_prev_update_sec;
static struct rtc_time hpet_alarm_time;
static unsigned long hpet_pie_count;
static unsigned long hpet_t1_cmp;
static unsigned long hpet_default_delta;
static unsigned long hpet_pie_delta;
static unsigned long hpet_pie_limit;

/*
 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 * is not supported by all HPET implementations for timer 1.
 *
 * hpet_rtc_timer_init() is called when the rtc is initialized.
 */
int hpet_rtc_timer_init(void)
{
	unsigned long cfg, cnt, delta, flags;

	if (!is_hpet_enabled())
		return 0;

	if (!hpet_default_delta) {
		uint64_t clc;

		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
		hpet_default_delta = (unsigned long) clc;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	local_irq_save(flags);

	cnt = delta + hpet_readl(HPET_COUNTER);
	hpet_writel(cnt, HPET_T1_CMP);
	hpet_t1_cmp = cnt;

	cfg = hpet_readl(HPET_T1_CFG);
	cfg &= ~HPET_TN_PERIODIC;
	cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
	hpet_writel(cfg, HPET_T1_CFG);

	local_irq_restore(flags);

	return 1;
}

/*
 * The functions below are called from rtc driver.
 * Return 0 if HPET is not being used.
 * Otherwise do the necessary changes and return 1.
 */
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags &= ~bit_mask;
	return 1;
}

int hpet_set_rtc_irq_bit(unsigned long bit_mask)
{
	unsigned long oldbits = hpet_rtc_flags;

	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags |= bit_mask;

	if (!oldbits)
		hpet_rtc_timer_init();

	return 1;
}

int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
			unsigned char sec)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_alarm_time.tm_hour = hrs;
	hpet_alarm_time.tm_min = min;
	hpet_alarm_time.tm_sec = sec;

	return 1;
}

int hpet_set_periodic_freq(unsigned long freq)
{
	uint64_t clc;

	if (!is_hpet_enabled())
		return 0;

	if (freq <= DEFAULT_RTC_INT_FREQ)
		hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
	else {
		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		do_div(clc, freq);
		clc >>= hpet_clockevent.shift;
		hpet_pie_delta = (unsigned long) clc;
	}
	return 1;
}

int hpet_rtc_dropped_irq(void)
{
	return is_hpet_enabled();
}

static void hpet_rtc_timer_reinit(void)
{
	unsigned long cfg, delta;
	int lost_ints = -1;

	if (unlikely(!hpet_rtc_flags)) {
		cfg = hpet_readl(HPET_T1_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T1_CFG);
		return;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	/*
	 * Increment the comparator value until we are ahead of the
	 * current count.
	 */
	do {
		hpet_t1_cmp += delta;
		hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
		lost_ints++;
	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);

	if (lost_ints) {
		if (hpet_rtc_flags & RTC_PIE)
			hpet_pie_count += lost_ints;
		if (printk_ratelimit())
			printk(KERN_WARNING "rtc: lost %d interrupts\n",
				lost_ints);
	}
}

irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
{
	struct rtc_time curr_time;
	unsigned long rtc_int_flag = 0;

	hpet_rtc_timer_reinit();

	if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
		rtc_get_rtc_time(&curr_time);

	if (hpet_rtc_flags & RTC_UIE &&
	    curr_time.tm_sec != hpet_prev_update_sec) {
		rtc_int_flag = RTC_UF;
		hpet_prev_update_sec = curr_time.tm_sec;
	}

	if (hpet_rtc_flags & RTC_PIE &&
	    ++hpet_pie_count >= hpet_pie_limit) {
		rtc_int_flag |= RTC_PF;
		hpet_pie_count = 0;
	}

	if (hpet_rtc_flags & RTC_AIE &&
	    (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
	    (curr_time.tm_min == hpet_alarm_time.tm_min) &&
	    (curr_time.tm_hour == hpet_alarm_time.tm_hour))
			rtc_int_flag |= RTC_AF;

	if (rtc_int_flag) {
		rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
		rtc_interrupt(rtc_int_flag, dev_id);
	}
	return IRQ_HANDLED;
}
#endif
Commit	Line	Data
5d0cf410	1	#include <linux/clocksource.h>
e9e2cdb4	2	#include <linux/clockchips.h>
28769149	3	#include <linux/delay.h>
5d0cf410 JS	4	#include <linux/errno.h>
	5	#include <linux/hpet.h>
	6	#include <linux/init.h>
399afa4f ML	7	#include <linux/sysdev.h>
399afa4f ML	8	#include <linux/pm.h>
0655d7c3	9	#include <linux/delay.h>
5d0cf410	10
28769149	11	#include <asm/fixmap.h>
5d0cf410	12	#include <asm/hpet.h>
06a24dec	13	#include <asm/i8253.h>
5d0cf410 JS	14	#include <asm/io.h>
5d0cf410 JS	15
7f9f303a	16	#define HPET_MASK CLOCKSOURCE_MASK(32)
5d0cf410 JS	17	#define HPET_SHIFT 22
	18
	19	/* FSEC = 10^-15 NSEC = 10^-9 */
	20	#define FSEC_PER_NSEC 1000000
	21
e9e2cdb4 TG	22	/*
	23	* HPET address is set in acpi/boot.c, when an ACPI entry exists
	24	*/
	25	unsigned long hpet_address;
06a24dec	26	static void __iomem *hpet_virt_address;
e9e2cdb4	27
31c435d7	28	unsigned long hpet_readl(unsigned long a)
e9e2cdb4 TG	29	{
	30	return readl(hpet_virt_address + a);
	31	}
	32
	33	static inline void hpet_writel(unsigned long d, unsigned long a)
	34	{
	35	writel(d, hpet_virt_address + a);
	36	}
	37
28769149 TG	38	#ifdef CONFIG_X86_64
	39
	40	#include <asm/pgtable.h>
	41
	42	static inline void hpet_set_mapping(void)
	43	{
	44	set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
	45	__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
	46	hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
	47	}
	48
	49	static inline void hpet_clear_mapping(void)
	50	{
	51	hpet_virt_address = NULL;
	52	}
	53
	54	#else
	55
06a24dec TG	56	static inline void hpet_set_mapping(void)
	57	{
	58	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
	59	}
	60
	61	static inline void hpet_clear_mapping(void)
	62	{
	63	iounmap(hpet_virt_address);
	64	hpet_virt_address = NULL;
	65	}
28769149	66	#endif
06a24dec	67
e9e2cdb4 TG	68	/*
	69	* HPET command line enable / disable
	70	*/
	71	static int boot_hpet_disable;
b17530bd	72	int hpet_force_user;
e9e2cdb4 TG	73
	74	static int __init hpet_setup(char* str)
	75	{
	76	if (str) {
	77	if (!strncmp("disable", str, 7))
	78	boot_hpet_disable = 1;
b17530bd TG	79	if (!strncmp("force", str, 5))
b17530bd TG	80	hpet_force_user = 1;
e9e2cdb4 TG	81	}
	82	return 1;
	83	}
	84	__setup("hpet=", hpet_setup);
	85
28769149 TG	86	static int __init disable_hpet(char *str)
	87	{
	88	boot_hpet_disable = 1;
	89	return 1;
	90	}
	91	__setup("nohpet", disable_hpet);
	92
e9e2cdb4 TG	93	static inline int is_hpet_capable(void)
	94	{
	95	return (!boot_hpet_disable && hpet_address);
	96	}
	97
	98	/*
	99	* HPET timer interrupt enable / disable
	100	*/
	101	static int hpet_legacy_int_enabled;
	102
	103	/**
	104	* is_hpet_enabled - check whether the hpet timer interrupt is enabled
	105	*/
	106	int is_hpet_enabled(void)
	107	{
	108	return is_hpet_capable() && hpet_legacy_int_enabled;
	109	}
	110
	111	/*
	112	* When the hpet driver (/dev/hpet) is enabled, we need to reserve
	113	* timer 0 and timer 1 in case of RTC emulation.
	114	*/
	115	#ifdef CONFIG_HPET
	116	static void hpet_reserve_platform_timers(unsigned long id)
	117	{
	118	struct hpet __iomem *hpet = hpet_virt_address;
	119	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
	120	unsigned int nrtimers, i;
	121	struct hpet_data hd;
	122
	123	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
	124
	125	memset(&hd, 0, sizeof (hd));
	126	hd.hd_phys_address = hpet_address;
06a24dec	127	hd.hd_address = hpet;
e9e2cdb4 TG	128	hd.hd_nirqs = nrtimers;
	129	hd.hd_flags = HPET_DATA_PLATFORM;
	130	hpet_reserve_timer(&hd, 0);
	131
	132	#ifdef CONFIG_HPET_EMULATE_RTC
	133	hpet_reserve_timer(&hd, 1);
	134	#endif
	135
	136	hd.hd_irq[0] = HPET_LEGACY_8254;
	137	hd.hd_irq[1] = HPET_LEGACY_RTC;
	138
	139	for (i = 2; i < nrtimers; timer++, i++)
	140	hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
	141	Tn_INT_ROUTE_CNF_SHIFT;
	142
	143	hpet_alloc(&hd);
	144
	145	}
	146	#else
	147	static void hpet_reserve_platform_timers(unsigned long id) { }
	148	#endif
	149
	150	/*
	151	* Common hpet info
	152	*/
	153	static unsigned long hpet_period;
	154
610bf2f1	155	static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4	156	struct clock_event_device *evt);
610bf2f1	157	static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4 TG	158	struct clock_event_device *evt);
	159
	160	/*
	161	* The hpet clock event device
	162	*/
	163	static struct clock_event_device hpet_clockevent = {
	164	.name = "hpet",
	165	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
610bf2f1 VP	166	.set_mode = hpet_legacy_set_mode,
610bf2f1 VP	167	.set_next_event = hpet_legacy_next_event,
e9e2cdb4 TG	168	.shift = 32,
e9e2cdb4 TG	169	.irq = 0,
59c69f2a	170	.rating = 50,
e9e2cdb4 TG	171	};
	172
	173	static void hpet_start_counter(void)
	174	{
	175	unsigned long cfg = hpet_readl(HPET_CFG);
	176
	177	cfg &= ~HPET_CFG_ENABLE;
	178	hpet_writel(cfg, HPET_CFG);
	179	hpet_writel(0, HPET_COUNTER);
	180	hpet_writel(0, HPET_COUNTER + 4);
	181	cfg \|= HPET_CFG_ENABLE;
	182	hpet_writel(cfg, HPET_CFG);
	183	}
	184
59c69f2a VP	185	static void hpet_resume_device(void)
59c69f2a VP	186	{
bfe0c1cc	187	force_hpet_resume();
59c69f2a VP	188	}
	189
	190	static void hpet_restart_counter(void)
	191	{
	192	hpet_resume_device();
	193	hpet_start_counter();
	194	}
	195
610bf2f1	196	static void hpet_enable_legacy_int(void)
e9e2cdb4 TG	197	{
	198	unsigned long cfg = hpet_readl(HPET_CFG);
	199
	200	cfg \|= HPET_CFG_LEGACY;
	201	hpet_writel(cfg, HPET_CFG);
	202	hpet_legacy_int_enabled = 1;
	203	}
	204
610bf2f1 VP	205	static void hpet_legacy_clockevent_register(void)
	206	{
	207	uint64_t hpet_freq;
	208
	209	/* Start HPET legacy interrupts */
	210	hpet_enable_legacy_int();
	211
	212	/*
	213	* The period is a femto seconds value. We need to calculate the
	214	* scaled math multiplication factor for nanosecond to hpet tick
	215	* conversion.
	216	*/
	217	hpet_freq = 1000000000000000ULL;
	218	do_div(hpet_freq, hpet_period);
	219	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
	220	NSEC_PER_SEC, 32);
	221	/* Calculate the min / max delta */
	222	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
	223	&hpet_clockevent);
	224	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
	225	&hpet_clockevent);
	226
	227	/*
	228	* Start hpet with the boot cpu mask and make it
	229	* global after the IO_APIC has been initialized.
	230	*/
	231	hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
	232	clockevents_register_device(&hpet_clockevent);
	233	global_clock_event = &hpet_clockevent;
	234	printk(KERN_DEBUG "hpet clockevent registered\n");
	235	}
	236
	237	static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4 TG	238	struct clock_event_device *evt)
	239	{
	240	unsigned long cfg, cmp, now;
	241	uint64_t delta;
	242
	243	switch(mode) {
	244	case CLOCK_EVT_MODE_PERIODIC:
	245	delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
	246	delta >>= hpet_clockevent.shift;
	247	now = hpet_readl(HPET_COUNTER);
	248	cmp = now + (unsigned long) delta;
	249	cfg = hpet_readl(HPET_T0_CFG);
	250	cfg \|= HPET_TN_ENABLE \| HPET_TN_PERIODIC \|
	251	HPET_TN_SETVAL \| HPET_TN_32BIT;
	252	hpet_writel(cfg, HPET_T0_CFG);
	253	/*
	254	* The first write after writing TN_SETVAL to the
	255	* config register sets the counter value, the second
	256	* write sets the period.
	257	*/
	258	hpet_writel(cmp, HPET_T0_CMP);
	259	udelay(1);
	260	hpet_writel((unsigned long) delta, HPET_T0_CMP);
	261	break;
	262
	263	case CLOCK_EVT_MODE_ONESHOT:
	264	cfg = hpet_readl(HPET_T0_CFG);
	265	cfg &= ~HPET_TN_PERIODIC;
	266	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
	267	hpet_writel(cfg, HPET_T0_CFG);
	268	break;
	269
	270	case CLOCK_EVT_MODE_UNUSED:
	271	case CLOCK_EVT_MODE_SHUTDOWN:
	272	cfg = hpet_readl(HPET_T0_CFG);
	273	cfg &= ~HPET_TN_ENABLE;
	274	hpet_writel(cfg, HPET_T0_CFG);
	275	break;
18de5bc4 TG	276
18de5bc4 TG	277	case CLOCK_EVT_MODE_RESUME:
610bf2f1	278	hpet_enable_legacy_int();
18de5bc4	279	break;
e9e2cdb4 TG	280	}
	281	}
	282
610bf2f1	283	static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4 TG	284	struct clock_event_device *evt)
	285	{
	286	unsigned long cnt;
	287
	288	cnt = hpet_readl(HPET_COUNTER);
	289	cnt += delta;
	290	hpet_writel(cnt, HPET_T0_CMP);
	291
c7f6d15f	292	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
e9e2cdb4 TG	293	}
e9e2cdb4 TG	294
6bb74df4 JS	295	/*
	296	* Clock source related code
	297	*/
	298	static cycle_t read_hpet(void)
	299	{
	300	return (cycle_t)hpet_readl(HPET_COUNTER);
	301	}
	302
28769149 TG	303	#ifdef CONFIG_X86_64
	304	static cycle_t __vsyscall_fn vread_hpet(void)
	305	{
	306	return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
	307	}
	308	#endif
	309
6bb74df4 JS	310	static struct clocksource clocksource_hpet = {
	311	.name = "hpet",
	312	.rating = 250,
	313	.read = read_hpet,
	314	.mask = HPET_MASK,
	315	.shift = HPET_SHIFT,
	316	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
59c69f2a	317	.resume = hpet_restart_counter,
28769149 TG	318	#ifdef CONFIG_X86_64
	319	.vread = vread_hpet,
	320	#endif
6bb74df4 JS	321	};
6bb74df4 JS	322
610bf2f1	323	static int hpet_clocksource_register(void)
e9e2cdb4	324	{
075bcd1f TG	325	u64 tmp, start, now;
075bcd1f TG	326	cycle_t t1;
e9e2cdb4	327
e9e2cdb4 TG	328	/* Start the counter */
	329	hpet_start_counter();
	330
075bcd1f TG	331	/* Verify whether hpet counter works */
	332	t1 = read_hpet();
	333	rdtscll(start);
	334
	335	/*
	336	* We don't know the TSC frequency yet, but waiting for
	337	* 200000 TSC cycles is safe:
	338	* 4 GHz == 50us
	339	* 1 GHz == 200us
	340	*/
	341	do {
	342	rep_nop();
	343	rdtscll(now);
	344	} while ((now - start) < 200000UL);
	345
	346	if (t1 == read_hpet()) {
	347	printk(KERN_WARNING
	348	"HPET counter not counting. HPET disabled\n");
610bf2f1	349	return -ENODEV;
075bcd1f TG	350	}
075bcd1f TG	351
6bb74df4 JS	352	/* Initialize and register HPET clocksource
	353	*
	354	* hpet period is in femto seconds per cycle
	355	* so we need to convert this to ns/cyc units
27b46d76	356	* approximated by mult/2^shift
6bb74df4 JS	357	*
	358	* fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	359	* fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	360	* fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	361	* (fsec/cyc << shift)/1000000 = mult
	362	* (hpet_period << shift)/FSEC_PER_NSEC = mult
	363	*/
	364	tmp = (u64)hpet_period << HPET_SHIFT;
	365	do_div(tmp, FSEC_PER_NSEC);
	366	clocksource_hpet.mult = (u32)tmp;
	367
	368	clocksource_register(&clocksource_hpet);
	369
610bf2f1 VP	370	return 0;
	371	}
	372
	373	/*
	374	* Try to setup the HPET timer
	375	*/
	376	int __init hpet_enable(void)
	377	{
	378	unsigned long id;
	379
	380	if (!is_hpet_capable())
	381	return 0;
	382
	383	hpet_set_mapping();
	384
	385	/*
	386	* Read the period and check for a sane value:
	387	*/
	388	hpet_period = hpet_readl(HPET_PERIOD);
	389	if (hpet_period < HPET_MIN_PERIOD \|\| hpet_period > HPET_MAX_PERIOD)
	390	goto out_nohpet;
	391
	392	/*
	393	* Read the HPET ID register to retrieve the IRQ routing
	394	* information and the number of channels
	395	*/
	396	id = hpet_readl(HPET_ID);
	397
	398	#ifdef CONFIG_HPET_EMULATE_RTC
	399	/*
	400	* The legacy routing mode needs at least two channels, tick timer
	401	* and the rtc emulation channel.
	402	*/
	403	if (!(id & HPET_ID_NUMBER))
	404	goto out_nohpet;
	405	#endif
	406
	407	if (hpet_clocksource_register())
	408	goto out_nohpet;
	409
e9e2cdb4	410	if (id & HPET_ID_LEGSUP) {
610bf2f1	411	hpet_legacy_clockevent_register();
e9e2cdb4 TG	412	return 1;
	413	}
	414	return 0;
5d0cf410	415
e9e2cdb4	416	out_nohpet:
06a24dec	417	hpet_clear_mapping();
399afa4f	418	boot_hpet_disable = 1;
e9e2cdb4 TG	419	return 0;
	420	}
	421
28769149 TG	422	/*
	423	* Needs to be late, as the reserve_timer code calls kalloc !
	424	*
	425	* Not a problem on i386 as hpet_enable is called from late_time_init,
	426	* but on x86_64 it is necessary !
	427	*/
	428	static __init int hpet_late_init(void)
	429	{
59c69f2a	430	if (boot_hpet_disable)
28769149 TG	431	return -ENODEV;
28769149 TG	432
59c69f2a VP	433	if (!hpet_address) {
	434	if (!force_hpet_address)
	435	return -ENODEV;
	436
	437	hpet_address = force_hpet_address;
	438	hpet_enable();
	439	if (!hpet_virt_address)
	440	return -ENODEV;
	441	}
	442
28769149	443	hpet_reserve_platform_timers(hpet_readl(HPET_ID));
59c69f2a	444
28769149 TG	445	return 0;
	446	}
	447	fs_initcall(hpet_late_init);
	448
c86c7fbc OH	449	void hpet_disable(void)
	450	{
	451	if (is_hpet_capable()) {
	452	unsigned long cfg = hpet_readl(HPET_CFG);
	453
	454	if (hpet_legacy_int_enabled) {
	455	cfg &= ~HPET_CFG_LEGACY;
	456	hpet_legacy_int_enabled = 0;
	457	}
	458	cfg &= ~HPET_CFG_ENABLE;
	459	hpet_writel(cfg, HPET_CFG);
	460	}
	461	}
	462
e9e2cdb4 TG	463	#ifdef CONFIG_HPET_EMULATE_RTC
	464
	465	/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
	466	* is enabled, we support RTC interrupt functionality in software.
	467	* RTC has 3 kinds of interrupts:
	468	* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
	469	* is updated
	470	* 2) Alarm Interrupt - generate an interrupt at a specific time of day
	471	* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
	472	* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
	473	* (1) and (2) above are implemented using polling at a frequency of
	474	* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
	475	* overhead. (DEFAULT_RTC_INT_FREQ)
	476	* For (3), we use interrupts at 64Hz or user specified periodic
	477	* frequency, whichever is higher.
	478	*/
	479	#include <linux/mc146818rtc.h>
	480	#include <linux/rtc.h>
	481
	482	#define DEFAULT_RTC_INT_FREQ 64
	483	#define DEFAULT_RTC_SHIFT 6
	484	#define RTC_NUM_INTS 1
	485
	486	static unsigned long hpet_rtc_flags;
	487	static unsigned long hpet_prev_update_sec;
	488	static struct rtc_time hpet_alarm_time;
	489	static unsigned long hpet_pie_count;
	490	static unsigned long hpet_t1_cmp;
	491	static unsigned long hpet_default_delta;
	492	static unsigned long hpet_pie_delta;
	493	static unsigned long hpet_pie_limit;
	494
	495	/*
	496	* Timer 1 for RTC emulation. We use one shot mode, as periodic mode
	497	* is not supported by all HPET implementations for timer 1.
	498	*
	499	* hpet_rtc_timer_init() is called when the rtc is initialized.
	500	*/
	501	int hpet_rtc_timer_init(void)
	502	{
	503	unsigned long cfg, cnt, delta, flags;
	504
	505	if (!is_hpet_enabled())
	506	return 0;
	507
	508	if (!hpet_default_delta) {
	509	uint64_t clc;
	510
	511	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
	512	clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
	513	hpet_default_delta = (unsigned long) clc;
	514	}
	515
	516	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
	517	delta = hpet_default_delta;
	518	else
	519	delta = hpet_pie_delta;
	520
	521	local_irq_save(flags);
	522
	523	cnt = delta + hpet_readl(HPET_COUNTER);
	524	hpet_writel(cnt, HPET_T1_CMP);
	525	hpet_t1_cmp = cnt;
	526
527	cfg = hpet_readl(HPET_T1_CFG);
528	cfg &= ~HPET_TN_PERIODIC;
529	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
530	hpet_writel(cfg, HPET_T1_CFG);
531
532	local_irq_restore(flags);
533
534	return 1;
535	}
536
537	/*
538	* The functions below are called from rtc driver.
539	* Return 0 if HPET is not being used.
540	* Otherwise do the necessary changes and return 1.
541	*/
542	int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
543	{
544	if (!is_hpet_enabled())
545	return 0;
546
547	hpet_rtc_flags &= ~bit_mask;
548	return 1;
549	}
550
551	int hpet_set_rtc_irq_bit(unsigned long bit_mask)
552	{
553	unsigned long oldbits = hpet_rtc_flags;
554
555	if (!is_hpet_enabled())
556	return 0;
557
558	hpet_rtc_flags \|= bit_mask;
559
560	if (!oldbits)
561	hpet_rtc_timer_init();
562
563	return 1;
564	}
565
566	int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
567	unsigned char sec)
568	{
569	if (!is_hpet_enabled())
570	return 0;
571
572	hpet_alarm_time.tm_hour = hrs;
573	hpet_alarm_time.tm_min = min;
574	hpet_alarm_time.tm_sec = sec;
575
576	return 1;
577	}
578
579	int hpet_set_periodic_freq(unsigned long freq)
580	{
581	uint64_t clc;
582
583	if (!is_hpet_enabled())
584	return 0;
585
586	if (freq <= DEFAULT_RTC_INT_FREQ)
587	hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
588	else {
589	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
590	do_div(clc, freq);
591	clc >>= hpet_clockevent.shift;
592	hpet_pie_delta = (unsigned long) clc;
593	}
594	return 1;
595	}
596
597	int hpet_rtc_dropped_irq(void)
598	{
599	return is_hpet_enabled();
600	}
601
602	static void hpet_rtc_timer_reinit(void)
603	{
604	unsigned long cfg, delta;
605	int lost_ints = -1;
606
607	if (unlikely(!hpet_rtc_flags)) {
608	cfg = hpet_readl(HPET_T1_CFG);
609	cfg &= ~HPET_TN_ENABLE;
610	hpet_writel(cfg, HPET_T1_CFG);
611	return;
612	}
613
614	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
615	delta = hpet_default_delta;
616	else
617	delta = hpet_pie_delta;
618
619	/*
620	* Increment the comparator value until we are ahead of the
621	* current count.
622	*/
623	do {
624	hpet_t1_cmp += delta;
625	hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
626	lost_ints++;
627	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
628
629	if (lost_ints) {
630	if (hpet_rtc_flags & RTC_PIE)
631	hpet_pie_count += lost_ints;
632	if (printk_ratelimit())
633	printk(KERN_WARNING "rtc: lost %d interrupts\n",
634	lost_ints);
635	}
636	}
637
638	irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
639	{
640	struct rtc_time curr_time;
641	unsigned long rtc_int_flag = 0;
642
643	hpet_rtc_timer_reinit();
644
645	if (hpet_rtc_flags & (RTC_UIE \| RTC_AIE))
646	rtc_get_rtc_time(&curr_time);
647
648	if (hpet_rtc_flags & RTC_UIE &&
649	curr_time.tm_sec != hpet_prev_update_sec) {
650	rtc_int_flag = RTC_UF;
651	hpet_prev_update_sec = curr_time.tm_sec;
652	}
653
654	if (hpet_rtc_flags & RTC_PIE &&
655	++hpet_pie_count >= hpet_pie_limit) {
656	rtc_int_flag \|= RTC_PF;
657	hpet_pie_count = 0;
658	}
659
8ee291f8	660	if (hpet_rtc_flags & RTC_AIE &&
e9e2cdb4 TG	661	(curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
	662	(curr_time.tm_min == hpet_alarm_time.tm_min) &&
	663	(curr_time.tm_hour == hpet_alarm_time.tm_hour))
	664	rtc_int_flag \|= RTC_AF;
	665
	666	if (rtc_int_flag) {
	667	rtc_int_flag \|= (RTC_IRQF \| (RTC_NUM_INTS << 8));
	668	rtc_interrupt(rtc_int_flag, dev_id);
	669	}
	670	return IRQ_HANDLED;
	671	}
	672	#endif