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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 | 3 | #include <linux/interrupt.h> |
69c60c88 | 4 | #include <linux/export.h> |
4588c1f0 | 5 | #include <linux/sysdev.h> |
28769149 | 6 | #include <linux/delay.h> |
5d0cf410 | 7 | #include <linux/errno.h> |
334955ef | 8 | #include <linux/i8253.h> |
5a0e3ad6 | 9 | #include <linux/slab.h> |
5d0cf410 JS |
10 | #include <linux/hpet.h> |
11 | #include <linux/init.h> | |
58ac1e76 | 12 | #include <linux/cpu.h> |
4588c1f0 IM |
13 | #include <linux/pm.h> |
14 | #include <linux/io.h> | |
5d0cf410 | 15 | |
28769149 | 16 | #include <asm/fixmap.h> |
4588c1f0 | 17 | #include <asm/hpet.h> |
16f871bc | 18 | #include <asm/time.h> |
5d0cf410 | 19 | |
4588c1f0 | 20 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 21 | |
b10db7f0 PM |
22 | /* FSEC = 10^-15 |
23 | NSEC = 10^-9 */ | |
4588c1f0 | 24 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 25 | |
26afe5f2 | 26 | #define HPET_DEV_USED_BIT 2 |
27 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
28 | #define HPET_DEV_VALID 0x8 | |
29 | #define HPET_DEV_FSB_CAP 0x1000 | |
30 | #define HPET_DEV_PERI_CAP 0x2000 | |
31 | ||
f1c18071 TG |
32 | #define HPET_MIN_CYCLES 128 |
33 | #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) | |
34 | ||
26afe5f2 | 35 | #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) |
36 | ||
e9e2cdb4 TG |
37 | /* |
38 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
39 | */ | |
4588c1f0 | 40 | unsigned long hpet_address; |
c8bc6f3c | 41 | u8 hpet_blockid; /* OS timer block num */ |
73472a46 PV |
42 | u8 hpet_msi_disable; |
43 | ||
e951e4af | 44 | #ifdef CONFIG_PCI_MSI |
3b71e9e3 | 45 | static unsigned long hpet_num_timers; |
e951e4af | 46 | #endif |
4588c1f0 | 47 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 48 | |
58ac1e76 | 49 | struct hpet_dev { |
4588c1f0 IM |
50 | struct clock_event_device evt; |
51 | unsigned int num; | |
52 | int cpu; | |
53 | unsigned int irq; | |
54 | unsigned int flags; | |
55 | char name[10]; | |
58ac1e76 | 56 | }; |
57 | ||
5946fa3d | 58 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
59 | { |
60 | return readl(hpet_virt_address + a); | |
61 | } | |
62 | ||
5946fa3d | 63 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
64 | { |
65 | writel(d, hpet_virt_address + a); | |
66 | } | |
67 | ||
28769149 | 68 | #ifdef CONFIG_X86_64 |
28769149 | 69 | #include <asm/pgtable.h> |
2387ce57 | 70 | #endif |
28769149 | 71 | |
06a24dec TG |
72 | static inline void hpet_set_mapping(void) |
73 | { | |
74 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 | 75 | #ifdef CONFIG_X86_64 |
d319bb79 | 76 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE); |
2387ce57 | 77 | #endif |
06a24dec TG |
78 | } |
79 | ||
80 | static inline void hpet_clear_mapping(void) | |
81 | { | |
82 | iounmap(hpet_virt_address); | |
83 | hpet_virt_address = NULL; | |
84 | } | |
85 | ||
e9e2cdb4 TG |
86 | /* |
87 | * HPET command line enable / disable | |
88 | */ | |
89 | static int boot_hpet_disable; | |
b17530bd | 90 | int hpet_force_user; |
b98103a5 | 91 | static int hpet_verbose; |
e9e2cdb4 | 92 | |
4588c1f0 | 93 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
94 | { |
95 | if (str) { | |
96 | if (!strncmp("disable", str, 7)) | |
97 | boot_hpet_disable = 1; | |
b17530bd TG |
98 | if (!strncmp("force", str, 5)) |
99 | hpet_force_user = 1; | |
b98103a5 AH |
100 | if (!strncmp("verbose", str, 7)) |
101 | hpet_verbose = 1; | |
e9e2cdb4 TG |
102 | } |
103 | return 1; | |
104 | } | |
105 | __setup("hpet=", hpet_setup); | |
106 | ||
28769149 TG |
107 | static int __init disable_hpet(char *str) |
108 | { | |
109 | boot_hpet_disable = 1; | |
110 | return 1; | |
111 | } | |
112 | __setup("nohpet", disable_hpet); | |
113 | ||
e9e2cdb4 TG |
114 | static inline int is_hpet_capable(void) |
115 | { | |
4588c1f0 | 116 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
117 | } |
118 | ||
119 | /* | |
120 | * HPET timer interrupt enable / disable | |
121 | */ | |
122 | static int hpet_legacy_int_enabled; | |
123 | ||
124 | /** | |
125 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
126 | */ | |
127 | int is_hpet_enabled(void) | |
128 | { | |
129 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
130 | } | |
1bdbdaac | 131 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 132 | |
b98103a5 AH |
133 | static void _hpet_print_config(const char *function, int line) |
134 | { | |
135 | u32 i, timers, l, h; | |
136 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
137 | l = hpet_readl(HPET_ID); | |
138 | h = hpet_readl(HPET_PERIOD); | |
139 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
140 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
141 | l = hpet_readl(HPET_CFG); | |
142 | h = hpet_readl(HPET_STATUS); | |
143 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
144 | l = hpet_readl(HPET_COUNTER); | |
145 | h = hpet_readl(HPET_COUNTER+4); | |
146 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
147 | ||
148 | for (i = 0; i < timers; i++) { | |
149 | l = hpet_readl(HPET_Tn_CFG(i)); | |
150 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
151 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
152 | i, l, h); | |
153 | l = hpet_readl(HPET_Tn_CMP(i)); | |
154 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
155 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
156 | i, l, h); | |
157 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
158 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
159 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
160 | i, l, h); | |
161 | } | |
162 | } | |
163 | ||
164 | #define hpet_print_config() \ | |
165 | do { \ | |
166 | if (hpet_verbose) \ | |
167 | _hpet_print_config(__FUNCTION__, __LINE__); \ | |
168 | } while (0) | |
169 | ||
e9e2cdb4 TG |
170 | /* |
171 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
172 | * timer 0 and timer 1 in case of RTC emulation. | |
173 | */ | |
174 | #ifdef CONFIG_HPET | |
f0ed4e69 | 175 | |
5f79f2f2 | 176 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 177 | |
5946fa3d | 178 | static void hpet_reserve_platform_timers(unsigned int id) |
e9e2cdb4 TG |
179 | { |
180 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
181 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
182 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
183 | struct hpet_data hd; |
184 | ||
185 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
186 | ||
4588c1f0 IM |
187 | memset(&hd, 0, sizeof(hd)); |
188 | hd.hd_phys_address = hpet_address; | |
189 | hd.hd_address = hpet; | |
190 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
191 | hpet_reserve_timer(&hd, 0); |
192 | ||
193 | #ifdef CONFIG_HPET_EMULATE_RTC | |
194 | hpet_reserve_timer(&hd, 1); | |
195 | #endif | |
5761d64b | 196 | |
64a76f66 DB |
197 | /* |
198 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
199 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
200 | * don't bother configuring *any* comparator interrupts. | |
201 | */ | |
e9e2cdb4 TG |
202 | hd.hd_irq[0] = HPET_LEGACY_8254; |
203 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
204 | ||
fc3fbc45 | 205 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
206 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
207 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 208 | } |
5761d64b | 209 | |
f0ed4e69 | 210 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 211 | |
e9e2cdb4 | 212 | hpet_alloc(&hd); |
5761d64b | 213 | |
e9e2cdb4 TG |
214 | } |
215 | #else | |
5946fa3d | 216 | static void hpet_reserve_platform_timers(unsigned int id) { } |
e9e2cdb4 TG |
217 | #endif |
218 | ||
219 | /* | |
220 | * Common hpet info | |
221 | */ | |
ab0e08f1 | 222 | static unsigned long hpet_freq; |
e9e2cdb4 | 223 | |
610bf2f1 | 224 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 225 | struct clock_event_device *evt); |
610bf2f1 | 226 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
227 | struct clock_event_device *evt); |
228 | ||
229 | /* | |
230 | * The hpet clock event device | |
231 | */ | |
232 | static struct clock_event_device hpet_clockevent = { | |
233 | .name = "hpet", | |
234 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
235 | .set_mode = hpet_legacy_set_mode, |
236 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 | 237 | .irq = 0, |
59c69f2a | 238 | .rating = 50, |
e9e2cdb4 TG |
239 | }; |
240 | ||
8d6f0c82 | 241 | static void hpet_stop_counter(void) |
e9e2cdb4 TG |
242 | { |
243 | unsigned long cfg = hpet_readl(HPET_CFG); | |
e9e2cdb4 TG |
244 | cfg &= ~HPET_CFG_ENABLE; |
245 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
246 | } |
247 | ||
248 | static void hpet_reset_counter(void) | |
249 | { | |
e9e2cdb4 TG |
250 | hpet_writel(0, HPET_COUNTER); |
251 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
252 | } |
253 | ||
254 | static void hpet_start_counter(void) | |
255 | { | |
5946fa3d | 256 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
257 | cfg |= HPET_CFG_ENABLE; |
258 | hpet_writel(cfg, HPET_CFG); | |
259 | } | |
260 | ||
8d6f0c82 AH |
261 | static void hpet_restart_counter(void) |
262 | { | |
263 | hpet_stop_counter(); | |
7a6f9cbb | 264 | hpet_reset_counter(); |
8d6f0c82 AH |
265 | hpet_start_counter(); |
266 | } | |
267 | ||
59c69f2a VP |
268 | static void hpet_resume_device(void) |
269 | { | |
bfe0c1cc | 270 | force_hpet_resume(); |
59c69f2a VP |
271 | } |
272 | ||
17622339 | 273 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
274 | { |
275 | hpet_resume_device(); | |
8d6f0c82 | 276 | hpet_restart_counter(); |
59c69f2a VP |
277 | } |
278 | ||
610bf2f1 | 279 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 280 | { |
5946fa3d | 281 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
282 | |
283 | cfg |= HPET_CFG_LEGACY; | |
284 | hpet_writel(cfg, HPET_CFG); | |
285 | hpet_legacy_int_enabled = 1; | |
286 | } | |
287 | ||
610bf2f1 VP |
288 | static void hpet_legacy_clockevent_register(void) |
289 | { | |
610bf2f1 VP |
290 | /* Start HPET legacy interrupts */ |
291 | hpet_enable_legacy_int(); | |
292 | ||
610bf2f1 VP |
293 | /* |
294 | * Start hpet with the boot cpu mask and make it | |
295 | * global after the IO_APIC has been initialized. | |
296 | */ | |
320ab2b0 | 297 | hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); |
ab0e08f1 TG |
298 | clockevents_config_and_register(&hpet_clockevent, hpet_freq, |
299 | HPET_MIN_PROG_DELTA, 0x7FFFFFFF); | |
610bf2f1 VP |
300 | global_clock_event = &hpet_clockevent; |
301 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
302 | } | |
303 | ||
26afe5f2 | 304 | static int hpet_setup_msi_irq(unsigned int irq); |
305 | ||
b40d575b | 306 | static void hpet_set_mode(enum clock_event_mode mode, |
307 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 308 | { |
5946fa3d | 309 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
310 | uint64_t delta; |
311 | ||
4588c1f0 | 312 | switch (mode) { |
e9e2cdb4 | 313 | case CLOCK_EVT_MODE_PERIODIC: |
c23e253e | 314 | hpet_stop_counter(); |
b40d575b | 315 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
316 | delta >>= evt->shift; | |
7a6f9cbb | 317 | now = hpet_readl(HPET_COUNTER); |
5946fa3d | 318 | cmp = now + (unsigned int) delta; |
b40d575b | 319 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
b13e2464 JS |
320 | /* Make sure we use edge triggered interrupts */ |
321 | cfg &= ~HPET_TN_LEVEL; | |
e9e2cdb4 TG |
322 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
323 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 324 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
7a6f9cbb AH |
325 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
326 | udelay(1); | |
327 | /* | |
328 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
329 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
330 | * bit is automatically cleared after the first write. | |
331 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
332 | * Publication # 24674) | |
333 | */ | |
5946fa3d | 334 | hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); |
c23e253e | 335 | hpet_start_counter(); |
b98103a5 | 336 | hpet_print_config(); |
e9e2cdb4 TG |
337 | break; |
338 | ||
339 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 340 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
341 | cfg &= ~HPET_TN_PERIODIC; |
342 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 343 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
344 | break; |
345 | ||
346 | case CLOCK_EVT_MODE_UNUSED: | |
347 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 348 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 349 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 350 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 351 | break; |
18de5bc4 TG |
352 | |
353 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 354 | if (timer == 0) { |
355 | hpet_enable_legacy_int(); | |
356 | } else { | |
357 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
358 | hpet_setup_msi_irq(hdev->irq); | |
359 | disable_irq(hdev->irq); | |
0de26520 | 360 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
26afe5f2 | 361 | enable_irq(hdev->irq); |
362 | } | |
b98103a5 | 363 | hpet_print_config(); |
18de5bc4 | 364 | break; |
e9e2cdb4 TG |
365 | } |
366 | } | |
367 | ||
b40d575b | 368 | static int hpet_next_event(unsigned long delta, |
369 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 370 | { |
f7676254 | 371 | u32 cnt; |
995bd3bb | 372 | s32 res; |
e9e2cdb4 TG |
373 | |
374 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 375 | cnt += (u32) delta; |
b40d575b | 376 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 377 | |
72d43d9b | 378 | /* |
995bd3bb TG |
379 | * HPETs are a complete disaster. The compare register is |
380 | * based on a equal comparison and neither provides a less | |
381 | * than or equal functionality (which would require to take | |
382 | * the wraparound into account) nor a simple count down event | |
383 | * mode. Further the write to the comparator register is | |
384 | * delayed internally up to two HPET clock cycles in certain | |
f1c18071 TG |
385 | * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even |
386 | * longer delays. We worked around that by reading back the | |
387 | * compare register, but that required another workaround for | |
388 | * ICH9,10 chips where the first readout after write can | |
389 | * return the old stale value. We already had a minimum | |
390 | * programming delta of 5us enforced, but a NMI or SMI hitting | |
995bd3bb TG |
391 | * between the counter readout and the comparator write can |
392 | * move us behind that point easily. Now instead of reading | |
393 | * the compare register back several times, we make the ETIME | |
394 | * decision based on the following: Return ETIME if the | |
f1c18071 | 395 | * counter value after the write is less than HPET_MIN_CYCLES |
995bd3bb | 396 | * away from the event or if the counter is already ahead of |
f1c18071 TG |
397 | * the event. The minimum programming delta for the generic |
398 | * clockevents code is set to 1.5 * HPET_MIN_CYCLES. | |
72d43d9b | 399 | */ |
995bd3bb | 400 | res = (s32)(cnt - hpet_readl(HPET_COUNTER)); |
72d43d9b | 401 | |
f1c18071 | 402 | return res < HPET_MIN_CYCLES ? -ETIME : 0; |
e9e2cdb4 TG |
403 | } |
404 | ||
b40d575b | 405 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
406 | struct clock_event_device *evt) | |
407 | { | |
408 | hpet_set_mode(mode, evt, 0); | |
409 | } | |
410 | ||
411 | static int hpet_legacy_next_event(unsigned long delta, | |
412 | struct clock_event_device *evt) | |
413 | { | |
414 | return hpet_next_event(delta, evt, 0); | |
415 | } | |
416 | ||
58ac1e76 | 417 | /* |
418 | * HPET MSI Support | |
419 | */ | |
26afe5f2 | 420 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
421 | |
422 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
423 | static struct hpet_dev *hpet_devs; | |
424 | ||
d0fbca8f | 425 | void hpet_msi_unmask(struct irq_data *data) |
58ac1e76 | 426 | { |
d0fbca8f | 427 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 428 | unsigned int cfg; |
58ac1e76 | 429 | |
430 | /* unmask it */ | |
431 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
432 | cfg |= HPET_TN_FSB; | |
433 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
434 | } | |
435 | ||
d0fbca8f | 436 | void hpet_msi_mask(struct irq_data *data) |
58ac1e76 | 437 | { |
d0fbca8f | 438 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 439 | unsigned int cfg; |
58ac1e76 | 440 | |
441 | /* mask it */ | |
442 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
443 | cfg &= ~HPET_TN_FSB; | |
444 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
445 | } | |
446 | ||
d0fbca8f | 447 | void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 448 | { |
58ac1e76 | 449 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); |
450 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
451 | } | |
452 | ||
d0fbca8f | 453 | void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 454 | { |
58ac1e76 | 455 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); |
456 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
457 | msg->address_hi = 0; | |
458 | } | |
459 | ||
26afe5f2 | 460 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
461 | struct clock_event_device *evt) | |
462 | { | |
463 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
464 | hpet_set_mode(mode, evt, hdev->num); | |
465 | } | |
466 | ||
467 | static int hpet_msi_next_event(unsigned long delta, | |
468 | struct clock_event_device *evt) | |
469 | { | |
470 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
471 | return hpet_next_event(delta, evt, hdev->num); | |
472 | } | |
473 | ||
474 | static int hpet_setup_msi_irq(unsigned int irq) | |
475 | { | |
c8bc6f3c | 476 | if (arch_setup_hpet_msi(irq, hpet_blockid)) { |
26afe5f2 | 477 | destroy_irq(irq); |
478 | return -EINVAL; | |
479 | } | |
480 | return 0; | |
481 | } | |
482 | ||
483 | static int hpet_assign_irq(struct hpet_dev *dev) | |
484 | { | |
485 | unsigned int irq; | |
486 | ||
02198962 | 487 | irq = create_irq_nr(0, -1); |
26afe5f2 | 488 | if (!irq) |
489 | return -EINVAL; | |
490 | ||
2c778651 | 491 | irq_set_handler_data(irq, dev); |
26afe5f2 | 492 | |
493 | if (hpet_setup_msi_irq(irq)) | |
494 | return -EINVAL; | |
495 | ||
496 | dev->irq = irq; | |
497 | return 0; | |
498 | } | |
499 | ||
500 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
501 | { | |
502 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
503 | struct clock_event_device *hevt = &dev->evt; | |
504 | ||
505 | if (!hevt->event_handler) { | |
506 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
507 | dev->num); | |
508 | return IRQ_HANDLED; | |
509 | } | |
510 | ||
511 | hevt->event_handler(hevt); | |
512 | return IRQ_HANDLED; | |
513 | } | |
514 | ||
515 | static int hpet_setup_irq(struct hpet_dev *dev) | |
516 | { | |
517 | ||
518 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
507fa3a3 TG |
519 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, |
520 | dev->name, dev)) | |
26afe5f2 | 521 | return -1; |
522 | ||
523 | disable_irq(dev->irq); | |
0de26520 | 524 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 525 | enable_irq(dev->irq); |
526 | ||
c81bba49 YL |
527 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
528 | dev->name, dev->irq); | |
529 | ||
26afe5f2 | 530 | return 0; |
531 | } | |
532 | ||
533 | /* This should be called in specific @cpu */ | |
534 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
535 | { | |
536 | struct clock_event_device *evt = &hdev->evt; | |
26afe5f2 | 537 | |
538 | WARN_ON(cpu != smp_processor_id()); | |
539 | if (!(hdev->flags & HPET_DEV_VALID)) | |
540 | return; | |
541 | ||
542 | if (hpet_setup_msi_irq(hdev->irq)) | |
543 | return; | |
544 | ||
545 | hdev->cpu = cpu; | |
546 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
547 | evt->name = hdev->name; | |
548 | hpet_setup_irq(hdev); | |
549 | evt->irq = hdev->irq; | |
550 | ||
551 | evt->rating = 110; | |
552 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
553 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
554 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
555 | ||
556 | evt->set_mode = hpet_msi_set_mode; | |
557 | evt->set_next_event = hpet_msi_next_event; | |
320ab2b0 | 558 | evt->cpumask = cpumask_of(hdev->cpu); |
ab0e08f1 TG |
559 | |
560 | clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, | |
561 | 0x7FFFFFFF); | |
26afe5f2 | 562 | } |
563 | ||
564 | #ifdef CONFIG_HPET | |
565 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
566 | #define RESERVE_TIMERS 1 | |
567 | #else | |
568 | #define RESERVE_TIMERS 0 | |
569 | #endif | |
5f79f2f2 VP |
570 | |
571 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 572 | { |
573 | unsigned int id; | |
574 | unsigned int num_timers; | |
575 | unsigned int num_timers_used = 0; | |
576 | int i; | |
577 | ||
73472a46 PV |
578 | if (hpet_msi_disable) |
579 | return; | |
580 | ||
39fe05e5 SL |
581 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
582 | return; | |
26afe5f2 | 583 | id = hpet_readl(HPET_ID); |
584 | ||
585 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
586 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 587 | hpet_print_config(); |
26afe5f2 | 588 | |
589 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
590 | if (!hpet_devs) | |
591 | return; | |
592 | ||
593 | hpet_num_timers = num_timers; | |
594 | ||
595 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
596 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
5946fa3d | 597 | unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); |
26afe5f2 | 598 | |
599 | /* Only consider HPET timer with MSI support */ | |
600 | if (!(cfg & HPET_TN_FSB_CAP)) | |
601 | continue; | |
602 | ||
603 | hdev->flags = 0; | |
604 | if (cfg & HPET_TN_PERIODIC_CAP) | |
605 | hdev->flags |= HPET_DEV_PERI_CAP; | |
606 | hdev->num = i; | |
607 | ||
608 | sprintf(hdev->name, "hpet%d", i); | |
609 | if (hpet_assign_irq(hdev)) | |
610 | continue; | |
611 | ||
612 | hdev->flags |= HPET_DEV_FSB_CAP; | |
613 | hdev->flags |= HPET_DEV_VALID; | |
614 | num_timers_used++; | |
615 | if (num_timers_used == num_possible_cpus()) | |
616 | break; | |
617 | } | |
618 | ||
619 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
620 | num_timers, num_timers_used); | |
621 | } | |
622 | ||
5f79f2f2 VP |
623 | #ifdef CONFIG_HPET |
624 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
625 | { | |
626 | int i; | |
627 | ||
628 | if (!hpet_devs) | |
629 | return; | |
630 | ||
631 | for (i = 0; i < hpet_num_timers; i++) { | |
632 | struct hpet_dev *hdev = &hpet_devs[i]; | |
633 | ||
634 | if (!(hdev->flags & HPET_DEV_VALID)) | |
635 | continue; | |
636 | ||
637 | hd->hd_irq[hdev->num] = hdev->irq; | |
638 | hpet_reserve_timer(hd, hdev->num); | |
639 | } | |
640 | } | |
641 | #endif | |
642 | ||
26afe5f2 | 643 | static struct hpet_dev *hpet_get_unused_timer(void) |
644 | { | |
645 | int i; | |
646 | ||
647 | if (!hpet_devs) | |
648 | return NULL; | |
649 | ||
650 | for (i = 0; i < hpet_num_timers; i++) { | |
651 | struct hpet_dev *hdev = &hpet_devs[i]; | |
652 | ||
653 | if (!(hdev->flags & HPET_DEV_VALID)) | |
654 | continue; | |
655 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
656 | (unsigned long *)&hdev->flags)) | |
657 | continue; | |
658 | return hdev; | |
659 | } | |
660 | return NULL; | |
661 | } | |
662 | ||
663 | struct hpet_work_struct { | |
664 | struct delayed_work work; | |
665 | struct completion complete; | |
666 | }; | |
667 | ||
668 | static void hpet_work(struct work_struct *w) | |
669 | { | |
670 | struct hpet_dev *hdev; | |
671 | int cpu = smp_processor_id(); | |
672 | struct hpet_work_struct *hpet_work; | |
673 | ||
674 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
675 | ||
676 | hdev = hpet_get_unused_timer(); | |
677 | if (hdev) | |
678 | init_one_hpet_msi_clockevent(hdev, cpu); | |
679 | ||
680 | complete(&hpet_work->complete); | |
681 | } | |
682 | ||
683 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
684 | unsigned long action, void *hcpu) | |
685 | { | |
686 | unsigned long cpu = (unsigned long)hcpu; | |
687 | struct hpet_work_struct work; | |
688 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
689 | ||
690 | switch (action & 0xf) { | |
691 | case CPU_ONLINE: | |
ca1cab37 | 692 | INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); |
26afe5f2 | 693 | init_completion(&work.complete); |
694 | /* FIXME: add schedule_work_on() */ | |
695 | schedule_delayed_work_on(cpu, &work.work, 0); | |
696 | wait_for_completion(&work.complete); | |
336f6c32 | 697 | destroy_timer_on_stack(&work.work.timer); |
26afe5f2 | 698 | break; |
699 | case CPU_DEAD: | |
700 | if (hdev) { | |
701 | free_irq(hdev->irq, hdev); | |
702 | hdev->flags &= ~HPET_DEV_USED; | |
703 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
704 | } | |
705 | break; | |
706 | } | |
707 | return NOTIFY_OK; | |
708 | } | |
709 | #else | |
710 | ||
ba374c9b SN |
711 | static int hpet_setup_msi_irq(unsigned int irq) |
712 | { | |
713 | return 0; | |
714 | } | |
5f79f2f2 VP |
715 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
716 | { | |
717 | return; | |
718 | } | |
719 | ||
720 | #ifdef CONFIG_HPET | |
721 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 722 | { |
723 | return; | |
724 | } | |
5f79f2f2 | 725 | #endif |
26afe5f2 | 726 | |
727 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
728 | unsigned long action, void *hcpu) | |
729 | { | |
730 | return NOTIFY_OK; | |
731 | } | |
732 | ||
733 | #endif | |
734 | ||
6bb74df4 JS |
735 | /* |
736 | * Clock source related code | |
737 | */ | |
8e19608e | 738 | static cycle_t read_hpet(struct clocksource *cs) |
6bb74df4 JS |
739 | { |
740 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
741 | } | |
742 | ||
743 | static struct clocksource clocksource_hpet = { | |
744 | .name = "hpet", | |
745 | .rating = 250, | |
746 | .read = read_hpet, | |
747 | .mask = HPET_MASK, | |
6bb74df4 | 748 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8d6f0c82 | 749 | .resume = hpet_resume_counter, |
28769149 | 750 | #ifdef CONFIG_X86_64 |
98d0ac38 | 751 | .archdata = { .vclock_mode = VCLOCK_HPET }, |
28769149 | 752 | #endif |
6bb74df4 JS |
753 | }; |
754 | ||
610bf2f1 | 755 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 756 | { |
6fd592da | 757 | u64 start, now; |
075bcd1f | 758 | cycle_t t1; |
e9e2cdb4 | 759 | |
e9e2cdb4 | 760 | /* Start the counter */ |
8d6f0c82 | 761 | hpet_restart_counter(); |
e9e2cdb4 | 762 | |
075bcd1f | 763 | /* Verify whether hpet counter works */ |
8e19608e | 764 | t1 = hpet_readl(HPET_COUNTER); |
075bcd1f TG |
765 | rdtscll(start); |
766 | ||
767 | /* | |
768 | * We don't know the TSC frequency yet, but waiting for | |
769 | * 200000 TSC cycles is safe: | |
770 | * 4 GHz == 50us | |
771 | * 1 GHz == 200us | |
772 | */ | |
773 | do { | |
774 | rep_nop(); | |
775 | rdtscll(now); | |
776 | } while ((now - start) < 200000UL); | |
777 | ||
8e19608e | 778 | if (t1 == hpet_readl(HPET_COUNTER)) { |
075bcd1f TG |
779 | printk(KERN_WARNING |
780 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 781 | return -ENODEV; |
075bcd1f TG |
782 | } |
783 | ||
f12a15be | 784 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); |
610bf2f1 VP |
785 | return 0; |
786 | } | |
787 | ||
b02a7f22 PM |
788 | /** |
789 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
790 | */ |
791 | int __init hpet_enable(void) | |
792 | { | |
ab0e08f1 | 793 | unsigned long hpet_period; |
5946fa3d | 794 | unsigned int id; |
ab0e08f1 | 795 | u64 freq; |
a6825f1c | 796 | int i; |
610bf2f1 VP |
797 | |
798 | if (!is_hpet_capable()) | |
799 | return 0; | |
800 | ||
801 | hpet_set_mapping(); | |
802 | ||
803 | /* | |
804 | * Read the period and check for a sane value: | |
805 | */ | |
806 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
807 | |
808 | /* | |
809 | * AMD SB700 based systems with spread spectrum enabled use a | |
810 | * SMM based HPET emulation to provide proper frequency | |
811 | * setting. The SMM code is initialized with the first HPET | |
812 | * register access and takes some time to complete. During | |
813 | * this time the config register reads 0xffffffff. We check | |
814 | * for max. 1000 loops whether the config register reads a non | |
815 | * 0xffffffff value to make sure that HPET is up and running | |
816 | * before we go further. A counting loop is safe, as the HPET | |
817 | * access takes thousands of CPU cycles. On non SB700 based | |
818 | * machines this check is only done once and has no side | |
819 | * effects. | |
820 | */ | |
821 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
822 | if (i == 1000) { | |
823 | printk(KERN_WARNING | |
824 | "HPET config register value = 0xFFFFFFFF. " | |
825 | "Disabling HPET\n"); | |
826 | goto out_nohpet; | |
827 | } | |
828 | } | |
829 | ||
610bf2f1 VP |
830 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
831 | goto out_nohpet; | |
832 | ||
ab0e08f1 TG |
833 | /* |
834 | * The period is a femto seconds value. Convert it to a | |
835 | * frequency. | |
836 | */ | |
837 | freq = FSEC_PER_SEC; | |
838 | do_div(freq, hpet_period); | |
839 | hpet_freq = freq; | |
840 | ||
610bf2f1 VP |
841 | /* |
842 | * Read the HPET ID register to retrieve the IRQ routing | |
843 | * information and the number of channels | |
844 | */ | |
845 | id = hpet_readl(HPET_ID); | |
b98103a5 | 846 | hpet_print_config(); |
610bf2f1 VP |
847 | |
848 | #ifdef CONFIG_HPET_EMULATE_RTC | |
849 | /* | |
850 | * The legacy routing mode needs at least two channels, tick timer | |
851 | * and the rtc emulation channel. | |
852 | */ | |
853 | if (!(id & HPET_ID_NUMBER)) | |
854 | goto out_nohpet; | |
855 | #endif | |
856 | ||
857 | if (hpet_clocksource_register()) | |
858 | goto out_nohpet; | |
859 | ||
e9e2cdb4 | 860 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 861 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
862 | return 1; |
863 | } | |
864 | return 0; | |
5d0cf410 | 865 | |
e9e2cdb4 | 866 | out_nohpet: |
06a24dec | 867 | hpet_clear_mapping(); |
bacbe999 | 868 | hpet_address = 0; |
e9e2cdb4 TG |
869 | return 0; |
870 | } | |
871 | ||
28769149 TG |
872 | /* |
873 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
874 | * | |
875 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
876 | * but on x86_64 it is necessary ! | |
877 | */ | |
878 | static __init int hpet_late_init(void) | |
879 | { | |
26afe5f2 | 880 | int cpu; |
881 | ||
59c69f2a | 882 | if (boot_hpet_disable) |
28769149 TG |
883 | return -ENODEV; |
884 | ||
59c69f2a VP |
885 | if (!hpet_address) { |
886 | if (!force_hpet_address) | |
887 | return -ENODEV; | |
888 | ||
889 | hpet_address = force_hpet_address; | |
890 | hpet_enable(); | |
59c69f2a VP |
891 | } |
892 | ||
39c04b55 JF |
893 | if (!hpet_virt_address) |
894 | return -ENODEV; | |
895 | ||
39fe05e5 SL |
896 | if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) |
897 | hpet_msi_capability_lookup(2); | |
898 | else | |
899 | hpet_msi_capability_lookup(0); | |
900 | ||
28769149 | 901 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 902 | hpet_print_config(); |
59c69f2a | 903 | |
73472a46 PV |
904 | if (hpet_msi_disable) |
905 | return 0; | |
906 | ||
39fe05e5 SL |
907 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
908 | return 0; | |
909 | ||
26afe5f2 | 910 | for_each_online_cpu(cpu) { |
911 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
912 | } | |
913 | ||
914 | /* This notifier should be called after workqueue is ready */ | |
915 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
916 | ||
28769149 TG |
917 | return 0; |
918 | } | |
919 | fs_initcall(hpet_late_init); | |
920 | ||
c86c7fbc OH |
921 | void hpet_disable(void) |
922 | { | |
ff487808 | 923 | if (is_hpet_capable() && hpet_virt_address) { |
5946fa3d | 924 | unsigned int cfg = hpet_readl(HPET_CFG); |
c86c7fbc OH |
925 | |
926 | if (hpet_legacy_int_enabled) { | |
927 | cfg &= ~HPET_CFG_LEGACY; | |
928 | hpet_legacy_int_enabled = 0; | |
929 | } | |
930 | cfg &= ~HPET_CFG_ENABLE; | |
931 | hpet_writel(cfg, HPET_CFG); | |
932 | } | |
933 | } | |
934 | ||
e9e2cdb4 TG |
935 | #ifdef CONFIG_HPET_EMULATE_RTC |
936 | ||
937 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
938 | * is enabled, we support RTC interrupt functionality in software. | |
939 | * RTC has 3 kinds of interrupts: | |
940 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
941 | * is updated | |
942 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
943 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
944 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
945 | * (1) and (2) above are implemented using polling at a frequency of | |
946 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
947 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
948 | * For (3), we use interrupts at 64Hz or user specified periodic | |
949 | * frequency, whichever is higher. | |
950 | */ | |
951 | #include <linux/mc146818rtc.h> | |
952 | #include <linux/rtc.h> | |
1bdbdaac | 953 | #include <asm/rtc.h> |
e9e2cdb4 TG |
954 | |
955 | #define DEFAULT_RTC_INT_FREQ 64 | |
956 | #define DEFAULT_RTC_SHIFT 6 | |
957 | #define RTC_NUM_INTS 1 | |
958 | ||
959 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 960 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
961 | static struct rtc_time hpet_alarm_time; |
962 | static unsigned long hpet_pie_count; | |
ff08f76d | 963 | static u32 hpet_t1_cmp; |
5946fa3d JB |
964 | static u32 hpet_default_delta; |
965 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
966 | static unsigned long hpet_pie_limit; |
967 | ||
1bdbdaac BW |
968 | static rtc_irq_handler irq_handler; |
969 | ||
ff08f76d PE |
970 | /* |
971 | * Check that the hpet counter c1 is ahead of the c2 | |
972 | */ | |
973 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
974 | { | |
975 | return (s32)(c2 - c1) < 0; | |
976 | } | |
977 | ||
1bdbdaac BW |
978 | /* |
979 | * Registers a IRQ handler. | |
980 | */ | |
981 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
982 | { | |
983 | if (!is_hpet_enabled()) | |
984 | return -ENODEV; | |
985 | if (irq_handler) | |
986 | return -EBUSY; | |
987 | ||
988 | irq_handler = handler; | |
989 | ||
990 | return 0; | |
991 | } | |
992 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
993 | ||
994 | /* | |
995 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
996 | * and does cleanup. | |
997 | */ | |
998 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
999 | { | |
1000 | if (!is_hpet_enabled()) | |
1001 | return; | |
1002 | ||
1003 | irq_handler = NULL; | |
1004 | hpet_rtc_flags = 0; | |
1005 | } | |
1006 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1007 | ||
e9e2cdb4 TG |
1008 | /* |
1009 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
1010 | * is not supported by all HPET implementations for timer 1. | |
1011 | * | |
1012 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1013 | */ | |
1014 | int hpet_rtc_timer_init(void) | |
1015 | { | |
5946fa3d JB |
1016 | unsigned int cfg, cnt, delta; |
1017 | unsigned long flags; | |
e9e2cdb4 TG |
1018 | |
1019 | if (!is_hpet_enabled()) | |
1020 | return 0; | |
1021 | ||
1022 | if (!hpet_default_delta) { | |
1023 | uint64_t clc; | |
1024 | ||
1025 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1026 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1027 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1028 | } |
1029 | ||
1030 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1031 | delta = hpet_default_delta; | |
1032 | else | |
1033 | delta = hpet_pie_delta; | |
1034 | ||
1035 | local_irq_save(flags); | |
1036 | ||
1037 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1038 | hpet_writel(cnt, HPET_T1_CMP); | |
1039 | hpet_t1_cmp = cnt; | |
1040 | ||
1041 | cfg = hpet_readl(HPET_T1_CFG); | |
1042 | cfg &= ~HPET_TN_PERIODIC; | |
1043 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1044 | hpet_writel(cfg, HPET_T1_CFG); | |
1045 | ||
1046 | local_irq_restore(flags); | |
1047 | ||
1048 | return 1; | |
1049 | } | |
1bdbdaac | 1050 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
1051 | |
1052 | /* | |
1053 | * The functions below are called from rtc driver. | |
1054 | * Return 0 if HPET is not being used. | |
1055 | * Otherwise do the necessary changes and return 1. | |
1056 | */ | |
1057 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1058 | { | |
1059 | if (!is_hpet_enabled()) | |
1060 | return 0; | |
1061 | ||
1062 | hpet_rtc_flags &= ~bit_mask; | |
1063 | return 1; | |
1064 | } | |
1bdbdaac | 1065 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1066 | |
1067 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1068 | { | |
1069 | unsigned long oldbits = hpet_rtc_flags; | |
1070 | ||
1071 | if (!is_hpet_enabled()) | |
1072 | return 0; | |
1073 | ||
1074 | hpet_rtc_flags |= bit_mask; | |
1075 | ||
7e2a31da DB |
1076 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1077 | hpet_prev_update_sec = -1; | |
1078 | ||
e9e2cdb4 TG |
1079 | if (!oldbits) |
1080 | hpet_rtc_timer_init(); | |
1081 | ||
1082 | return 1; | |
1083 | } | |
1bdbdaac | 1084 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1085 | |
1086 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1087 | unsigned char sec) | |
1088 | { | |
1089 | if (!is_hpet_enabled()) | |
1090 | return 0; | |
1091 | ||
1092 | hpet_alarm_time.tm_hour = hrs; | |
1093 | hpet_alarm_time.tm_min = min; | |
1094 | hpet_alarm_time.tm_sec = sec; | |
1095 | ||
1096 | return 1; | |
1097 | } | |
1bdbdaac | 1098 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1099 | |
1100 | int hpet_set_periodic_freq(unsigned long freq) | |
1101 | { | |
1102 | uint64_t clc; | |
1103 | ||
1104 | if (!is_hpet_enabled()) | |
1105 | return 0; | |
1106 | ||
1107 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1108 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1109 | else { | |
1110 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1111 | do_div(clc, freq); | |
1112 | clc >>= hpet_clockevent.shift; | |
5946fa3d | 1113 | hpet_pie_delta = clc; |
b4a5e8a1 | 1114 | hpet_pie_limit = 0; |
e9e2cdb4 TG |
1115 | } |
1116 | return 1; | |
1117 | } | |
1bdbdaac | 1118 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1119 | |
1120 | int hpet_rtc_dropped_irq(void) | |
1121 | { | |
1122 | return is_hpet_enabled(); | |
1123 | } | |
1bdbdaac | 1124 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1125 | |
1126 | static void hpet_rtc_timer_reinit(void) | |
1127 | { | |
5946fa3d | 1128 | unsigned int cfg, delta; |
e9e2cdb4 TG |
1129 | int lost_ints = -1; |
1130 | ||
1131 | if (unlikely(!hpet_rtc_flags)) { | |
1132 | cfg = hpet_readl(HPET_T1_CFG); | |
1133 | cfg &= ~HPET_TN_ENABLE; | |
1134 | hpet_writel(cfg, HPET_T1_CFG); | |
1135 | return; | |
1136 | } | |
1137 | ||
1138 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1139 | delta = hpet_default_delta; | |
1140 | else | |
1141 | delta = hpet_pie_delta; | |
1142 | ||
1143 | /* | |
1144 | * Increment the comparator value until we are ahead of the | |
1145 | * current count. | |
1146 | */ | |
1147 | do { | |
1148 | hpet_t1_cmp += delta; | |
1149 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1150 | lost_ints++; | |
ff08f76d | 1151 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1152 | |
1153 | if (lost_ints) { | |
1154 | if (hpet_rtc_flags & RTC_PIE) | |
1155 | hpet_pie_count += lost_ints; | |
1156 | if (printk_ratelimit()) | |
7e2a31da | 1157 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1158 | lost_ints); |
1159 | } | |
1160 | } | |
1161 | ||
1162 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1163 | { | |
1164 | struct rtc_time curr_time; | |
1165 | unsigned long rtc_int_flag = 0; | |
1166 | ||
1167 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1168 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1169 | |
1170 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1171 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1172 | |
1173 | if (hpet_rtc_flags & RTC_UIE && | |
1174 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1175 | if (hpet_prev_update_sec >= 0) |
1176 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1177 | hpet_prev_update_sec = curr_time.tm_sec; |
1178 | } | |
1179 | ||
1180 | if (hpet_rtc_flags & RTC_PIE && | |
1181 | ++hpet_pie_count >= hpet_pie_limit) { | |
1182 | rtc_int_flag |= RTC_PF; | |
1183 | hpet_pie_count = 0; | |
1184 | } | |
1185 | ||
8ee291f8 | 1186 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1187 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1188 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1189 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1190 | rtc_int_flag |= RTC_AF; | |
1191 | ||
1192 | if (rtc_int_flag) { | |
1193 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1194 | if (irq_handler) |
1195 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1196 | } |
1197 | return IRQ_HANDLED; | |
1198 | } | |
1bdbdaac | 1199 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1200 | #endif |