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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
28769149 | 3 | #include <linux/delay.h> |
5d0cf410 JS |
4 | #include <linux/errno.h> |
5 | #include <linux/hpet.h> | |
6 | #include <linux/init.h> | |
399afa4f ML |
7 | #include <linux/sysdev.h> |
8 | #include <linux/pm.h> | |
0655d7c3 | 9 | #include <linux/delay.h> |
5d0cf410 | 10 | |
28769149 | 11 | #include <asm/fixmap.h> |
5d0cf410 | 12 | #include <asm/hpet.h> |
06a24dec | 13 | #include <asm/i8253.h> |
5d0cf410 JS |
14 | #include <asm/io.h> |
15 | ||
7f9f303a | 16 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 JS |
17 | #define HPET_SHIFT 22 |
18 | ||
19 | /* FSEC = 10^-15 NSEC = 10^-9 */ | |
20 | #define FSEC_PER_NSEC 1000000 | |
21 | ||
e9e2cdb4 TG |
22 | /* |
23 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
24 | */ | |
25 | unsigned long hpet_address; | |
06a24dec | 26 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 27 | |
31c435d7 | 28 | unsigned long hpet_readl(unsigned long a) |
e9e2cdb4 TG |
29 | { |
30 | return readl(hpet_virt_address + a); | |
31 | } | |
32 | ||
33 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
34 | { | |
35 | writel(d, hpet_virt_address + a); | |
36 | } | |
37 | ||
28769149 TG |
38 | #ifdef CONFIG_X86_64 |
39 | ||
40 | #include <asm/pgtable.h> | |
41 | ||
42 | static inline void hpet_set_mapping(void) | |
43 | { | |
44 | set_fixmap_nocache(FIX_HPET_BASE, hpet_address); | |
45 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
46 | hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE); | |
47 | } | |
48 | ||
49 | static inline void hpet_clear_mapping(void) | |
50 | { | |
51 | hpet_virt_address = NULL; | |
52 | } | |
53 | ||
54 | #else | |
55 | ||
06a24dec TG |
56 | static inline void hpet_set_mapping(void) |
57 | { | |
58 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
59 | } | |
60 | ||
61 | static inline void hpet_clear_mapping(void) | |
62 | { | |
63 | iounmap(hpet_virt_address); | |
64 | hpet_virt_address = NULL; | |
65 | } | |
28769149 | 66 | #endif |
06a24dec | 67 | |
e9e2cdb4 TG |
68 | /* |
69 | * HPET command line enable / disable | |
70 | */ | |
71 | static int boot_hpet_disable; | |
72 | ||
73 | static int __init hpet_setup(char* str) | |
74 | { | |
75 | if (str) { | |
76 | if (!strncmp("disable", str, 7)) | |
77 | boot_hpet_disable = 1; | |
78 | } | |
79 | return 1; | |
80 | } | |
81 | __setup("hpet=", hpet_setup); | |
82 | ||
28769149 TG |
83 | static int __init disable_hpet(char *str) |
84 | { | |
85 | boot_hpet_disable = 1; | |
86 | return 1; | |
87 | } | |
88 | __setup("nohpet", disable_hpet); | |
89 | ||
e9e2cdb4 TG |
90 | static inline int is_hpet_capable(void) |
91 | { | |
92 | return (!boot_hpet_disable && hpet_address); | |
93 | } | |
94 | ||
95 | /* | |
96 | * HPET timer interrupt enable / disable | |
97 | */ | |
98 | static int hpet_legacy_int_enabled; | |
99 | ||
100 | /** | |
101 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
102 | */ | |
103 | int is_hpet_enabled(void) | |
104 | { | |
105 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
106 | } | |
107 | ||
108 | /* | |
109 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
110 | * timer 0 and timer 1 in case of RTC emulation. | |
111 | */ | |
112 | #ifdef CONFIG_HPET | |
113 | static void hpet_reserve_platform_timers(unsigned long id) | |
114 | { | |
115 | struct hpet __iomem *hpet = hpet_virt_address; | |
116 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; | |
117 | unsigned int nrtimers, i; | |
118 | struct hpet_data hd; | |
119 | ||
120 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
121 | ||
122 | memset(&hd, 0, sizeof (hd)); | |
123 | hd.hd_phys_address = hpet_address; | |
06a24dec | 124 | hd.hd_address = hpet; |
e9e2cdb4 TG |
125 | hd.hd_nirqs = nrtimers; |
126 | hd.hd_flags = HPET_DATA_PLATFORM; | |
127 | hpet_reserve_timer(&hd, 0); | |
128 | ||
129 | #ifdef CONFIG_HPET_EMULATE_RTC | |
130 | hpet_reserve_timer(&hd, 1); | |
131 | #endif | |
132 | ||
133 | hd.hd_irq[0] = HPET_LEGACY_8254; | |
134 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
135 | ||
136 | for (i = 2; i < nrtimers; timer++, i++) | |
137 | hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> | |
138 | Tn_INT_ROUTE_CNF_SHIFT; | |
139 | ||
140 | hpet_alloc(&hd); | |
141 | ||
142 | } | |
143 | #else | |
144 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
145 | #endif | |
146 | ||
147 | /* | |
148 | * Common hpet info | |
149 | */ | |
150 | static unsigned long hpet_period; | |
151 | ||
610bf2f1 | 152 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 153 | struct clock_event_device *evt); |
610bf2f1 | 154 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
155 | struct clock_event_device *evt); |
156 | ||
157 | /* | |
158 | * The hpet clock event device | |
159 | */ | |
160 | static struct clock_event_device hpet_clockevent = { | |
161 | .name = "hpet", | |
162 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
163 | .set_mode = hpet_legacy_set_mode, |
164 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 TG |
165 | .shift = 32, |
166 | .irq = 0, | |
59c69f2a | 167 | .rating = 50, |
e9e2cdb4 TG |
168 | }; |
169 | ||
170 | static void hpet_start_counter(void) | |
171 | { | |
172 | unsigned long cfg = hpet_readl(HPET_CFG); | |
173 | ||
174 | cfg &= ~HPET_CFG_ENABLE; | |
175 | hpet_writel(cfg, HPET_CFG); | |
176 | hpet_writel(0, HPET_COUNTER); | |
177 | hpet_writel(0, HPET_COUNTER + 4); | |
178 | cfg |= HPET_CFG_ENABLE; | |
179 | hpet_writel(cfg, HPET_CFG); | |
180 | } | |
181 | ||
59c69f2a VP |
182 | static void hpet_resume_device(void) |
183 | { | |
184 | ich_force_hpet_resume(); | |
185 | } | |
186 | ||
187 | static void hpet_restart_counter(void) | |
188 | { | |
189 | hpet_resume_device(); | |
190 | hpet_start_counter(); | |
191 | } | |
192 | ||
610bf2f1 | 193 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 TG |
194 | { |
195 | unsigned long cfg = hpet_readl(HPET_CFG); | |
196 | ||
197 | cfg |= HPET_CFG_LEGACY; | |
198 | hpet_writel(cfg, HPET_CFG); | |
199 | hpet_legacy_int_enabled = 1; | |
200 | } | |
201 | ||
610bf2f1 VP |
202 | static void hpet_legacy_clockevent_register(void) |
203 | { | |
204 | uint64_t hpet_freq; | |
205 | ||
206 | /* Start HPET legacy interrupts */ | |
207 | hpet_enable_legacy_int(); | |
208 | ||
209 | /* | |
210 | * The period is a femto seconds value. We need to calculate the | |
211 | * scaled math multiplication factor for nanosecond to hpet tick | |
212 | * conversion. | |
213 | */ | |
214 | hpet_freq = 1000000000000000ULL; | |
215 | do_div(hpet_freq, hpet_period); | |
216 | hpet_clockevent.mult = div_sc((unsigned long) hpet_freq, | |
217 | NSEC_PER_SEC, 32); | |
218 | /* Calculate the min / max delta */ | |
219 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
220 | &hpet_clockevent); | |
221 | hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30, | |
222 | &hpet_clockevent); | |
223 | ||
224 | /* | |
225 | * Start hpet with the boot cpu mask and make it | |
226 | * global after the IO_APIC has been initialized. | |
227 | */ | |
228 | hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); | |
229 | clockevents_register_device(&hpet_clockevent); | |
230 | global_clock_event = &hpet_clockevent; | |
231 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
232 | } | |
233 | ||
234 | static void hpet_legacy_set_mode(enum clock_event_mode mode, | |
e9e2cdb4 TG |
235 | struct clock_event_device *evt) |
236 | { | |
237 | unsigned long cfg, cmp, now; | |
238 | uint64_t delta; | |
239 | ||
240 | switch(mode) { | |
241 | case CLOCK_EVT_MODE_PERIODIC: | |
242 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult; | |
243 | delta >>= hpet_clockevent.shift; | |
244 | now = hpet_readl(HPET_COUNTER); | |
245 | cmp = now + (unsigned long) delta; | |
246 | cfg = hpet_readl(HPET_T0_CFG); | |
247 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | | |
248 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
249 | hpet_writel(cfg, HPET_T0_CFG); | |
250 | /* | |
251 | * The first write after writing TN_SETVAL to the | |
252 | * config register sets the counter value, the second | |
253 | * write sets the period. | |
254 | */ | |
255 | hpet_writel(cmp, HPET_T0_CMP); | |
256 | udelay(1); | |
257 | hpet_writel((unsigned long) delta, HPET_T0_CMP); | |
258 | break; | |
259 | ||
260 | case CLOCK_EVT_MODE_ONESHOT: | |
261 | cfg = hpet_readl(HPET_T0_CFG); | |
262 | cfg &= ~HPET_TN_PERIODIC; | |
263 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
264 | hpet_writel(cfg, HPET_T0_CFG); | |
265 | break; | |
266 | ||
267 | case CLOCK_EVT_MODE_UNUSED: | |
268 | case CLOCK_EVT_MODE_SHUTDOWN: | |
269 | cfg = hpet_readl(HPET_T0_CFG); | |
270 | cfg &= ~HPET_TN_ENABLE; | |
271 | hpet_writel(cfg, HPET_T0_CFG); | |
272 | break; | |
18de5bc4 TG |
273 | |
274 | case CLOCK_EVT_MODE_RESUME: | |
610bf2f1 | 275 | hpet_enable_legacy_int(); |
18de5bc4 | 276 | break; |
e9e2cdb4 TG |
277 | } |
278 | } | |
279 | ||
610bf2f1 | 280 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
281 | struct clock_event_device *evt) |
282 | { | |
283 | unsigned long cnt; | |
284 | ||
285 | cnt = hpet_readl(HPET_COUNTER); | |
286 | cnt += delta; | |
287 | hpet_writel(cnt, HPET_T0_CMP); | |
288 | ||
c7f6d15f | 289 | return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0; |
e9e2cdb4 TG |
290 | } |
291 | ||
6bb74df4 JS |
292 | /* |
293 | * Clock source related code | |
294 | */ | |
295 | static cycle_t read_hpet(void) | |
296 | { | |
297 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
298 | } | |
299 | ||
28769149 TG |
300 | #ifdef CONFIG_X86_64 |
301 | static cycle_t __vsyscall_fn vread_hpet(void) | |
302 | { | |
303 | return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); | |
304 | } | |
305 | #endif | |
306 | ||
6bb74df4 JS |
307 | static struct clocksource clocksource_hpet = { |
308 | .name = "hpet", | |
309 | .rating = 250, | |
310 | .read = read_hpet, | |
311 | .mask = HPET_MASK, | |
312 | .shift = HPET_SHIFT, | |
313 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
59c69f2a | 314 | .resume = hpet_restart_counter, |
28769149 TG |
315 | #ifdef CONFIG_X86_64 |
316 | .vread = vread_hpet, | |
317 | #endif | |
6bb74df4 JS |
318 | }; |
319 | ||
610bf2f1 | 320 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 321 | { |
075bcd1f TG |
322 | u64 tmp, start, now; |
323 | cycle_t t1; | |
e9e2cdb4 | 324 | |
e9e2cdb4 TG |
325 | /* Start the counter */ |
326 | hpet_start_counter(); | |
327 | ||
075bcd1f TG |
328 | /* Verify whether hpet counter works */ |
329 | t1 = read_hpet(); | |
330 | rdtscll(start); | |
331 | ||
332 | /* | |
333 | * We don't know the TSC frequency yet, but waiting for | |
334 | * 200000 TSC cycles is safe: | |
335 | * 4 GHz == 50us | |
336 | * 1 GHz == 200us | |
337 | */ | |
338 | do { | |
339 | rep_nop(); | |
340 | rdtscll(now); | |
341 | } while ((now - start) < 200000UL); | |
342 | ||
343 | if (t1 == read_hpet()) { | |
344 | printk(KERN_WARNING | |
345 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 346 | return -ENODEV; |
075bcd1f TG |
347 | } |
348 | ||
6bb74df4 JS |
349 | /* Initialize and register HPET clocksource |
350 | * | |
351 | * hpet period is in femto seconds per cycle | |
352 | * so we need to convert this to ns/cyc units | |
353 | * aproximated by mult/2^shift | |
354 | * | |
355 | * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift | |
356 | * fsec/cyc * 1ns/1000000fsec * 2^shift = mult | |
357 | * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult | |
358 | * (fsec/cyc << shift)/1000000 = mult | |
359 | * (hpet_period << shift)/FSEC_PER_NSEC = mult | |
360 | */ | |
361 | tmp = (u64)hpet_period << HPET_SHIFT; | |
362 | do_div(tmp, FSEC_PER_NSEC); | |
363 | clocksource_hpet.mult = (u32)tmp; | |
364 | ||
365 | clocksource_register(&clocksource_hpet); | |
366 | ||
610bf2f1 VP |
367 | return 0; |
368 | } | |
369 | ||
370 | /* | |
371 | * Try to setup the HPET timer | |
372 | */ | |
373 | int __init hpet_enable(void) | |
374 | { | |
375 | unsigned long id; | |
376 | ||
377 | if (!is_hpet_capable()) | |
378 | return 0; | |
379 | ||
380 | hpet_set_mapping(); | |
381 | ||
382 | /* | |
383 | * Read the period and check for a sane value: | |
384 | */ | |
385 | hpet_period = hpet_readl(HPET_PERIOD); | |
386 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) | |
387 | goto out_nohpet; | |
388 | ||
389 | /* | |
390 | * Read the HPET ID register to retrieve the IRQ routing | |
391 | * information and the number of channels | |
392 | */ | |
393 | id = hpet_readl(HPET_ID); | |
394 | ||
395 | #ifdef CONFIG_HPET_EMULATE_RTC | |
396 | /* | |
397 | * The legacy routing mode needs at least two channels, tick timer | |
398 | * and the rtc emulation channel. | |
399 | */ | |
400 | if (!(id & HPET_ID_NUMBER)) | |
401 | goto out_nohpet; | |
402 | #endif | |
403 | ||
404 | if (hpet_clocksource_register()) | |
405 | goto out_nohpet; | |
406 | ||
e9e2cdb4 | 407 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 408 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
409 | return 1; |
410 | } | |
411 | return 0; | |
5d0cf410 | 412 | |
e9e2cdb4 | 413 | out_nohpet: |
06a24dec | 414 | hpet_clear_mapping(); |
399afa4f | 415 | boot_hpet_disable = 1; |
e9e2cdb4 TG |
416 | return 0; |
417 | } | |
418 | ||
28769149 TG |
419 | /* |
420 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
421 | * | |
422 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
423 | * but on x86_64 it is necessary ! | |
424 | */ | |
425 | static __init int hpet_late_init(void) | |
426 | { | |
59c69f2a | 427 | if (boot_hpet_disable) |
28769149 TG |
428 | return -ENODEV; |
429 | ||
59c69f2a VP |
430 | if (!hpet_address) { |
431 | if (!force_hpet_address) | |
432 | return -ENODEV; | |
433 | ||
434 | hpet_address = force_hpet_address; | |
435 | hpet_enable(); | |
436 | if (!hpet_virt_address) | |
437 | return -ENODEV; | |
438 | } | |
439 | ||
28769149 | 440 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
59c69f2a | 441 | |
28769149 TG |
442 | return 0; |
443 | } | |
444 | fs_initcall(hpet_late_init); | |
445 | ||
e9e2cdb4 TG |
446 | #ifdef CONFIG_HPET_EMULATE_RTC |
447 | ||
448 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
449 | * is enabled, we support RTC interrupt functionality in software. | |
450 | * RTC has 3 kinds of interrupts: | |
451 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
452 | * is updated | |
453 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
454 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
455 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
456 | * (1) and (2) above are implemented using polling at a frequency of | |
457 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
458 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
459 | * For (3), we use interrupts at 64Hz or user specified periodic | |
460 | * frequency, whichever is higher. | |
461 | */ | |
462 | #include <linux/mc146818rtc.h> | |
463 | #include <linux/rtc.h> | |
464 | ||
465 | #define DEFAULT_RTC_INT_FREQ 64 | |
466 | #define DEFAULT_RTC_SHIFT 6 | |
467 | #define RTC_NUM_INTS 1 | |
468 | ||
469 | static unsigned long hpet_rtc_flags; | |
470 | static unsigned long hpet_prev_update_sec; | |
471 | static struct rtc_time hpet_alarm_time; | |
472 | static unsigned long hpet_pie_count; | |
473 | static unsigned long hpet_t1_cmp; | |
474 | static unsigned long hpet_default_delta; | |
475 | static unsigned long hpet_pie_delta; | |
476 | static unsigned long hpet_pie_limit; | |
477 | ||
478 | /* | |
479 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
480 | * is not supported by all HPET implementations for timer 1. | |
481 | * | |
482 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
483 | */ | |
484 | int hpet_rtc_timer_init(void) | |
485 | { | |
486 | unsigned long cfg, cnt, delta, flags; | |
487 | ||
488 | if (!is_hpet_enabled()) | |
489 | return 0; | |
490 | ||
491 | if (!hpet_default_delta) { | |
492 | uint64_t clc; | |
493 | ||
494 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
495 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
496 | hpet_default_delta = (unsigned long) clc; | |
497 | } | |
498 | ||
499 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
500 | delta = hpet_default_delta; | |
501 | else | |
502 | delta = hpet_pie_delta; | |
503 | ||
504 | local_irq_save(flags); | |
505 | ||
506 | cnt = delta + hpet_readl(HPET_COUNTER); | |
507 | hpet_writel(cnt, HPET_T1_CMP); | |
508 | hpet_t1_cmp = cnt; | |
509 | ||
510 | cfg = hpet_readl(HPET_T1_CFG); | |
511 | cfg &= ~HPET_TN_PERIODIC; | |
512 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
513 | hpet_writel(cfg, HPET_T1_CFG); | |
514 | ||
515 | local_irq_restore(flags); | |
516 | ||
517 | return 1; | |
518 | } | |
519 | ||
520 | /* | |
521 | * The functions below are called from rtc driver. | |
522 | * Return 0 if HPET is not being used. | |
523 | * Otherwise do the necessary changes and return 1. | |
524 | */ | |
525 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
526 | { | |
527 | if (!is_hpet_enabled()) | |
528 | return 0; | |
529 | ||
530 | hpet_rtc_flags &= ~bit_mask; | |
531 | return 1; | |
532 | } | |
533 | ||
534 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
535 | { | |
536 | unsigned long oldbits = hpet_rtc_flags; | |
537 | ||
538 | if (!is_hpet_enabled()) | |
539 | return 0; | |
540 | ||
541 | hpet_rtc_flags |= bit_mask; | |
542 | ||
543 | if (!oldbits) | |
544 | hpet_rtc_timer_init(); | |
545 | ||
546 | return 1; | |
547 | } | |
548 | ||
549 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
550 | unsigned char sec) | |
551 | { | |
552 | if (!is_hpet_enabled()) | |
553 | return 0; | |
554 | ||
555 | hpet_alarm_time.tm_hour = hrs; | |
556 | hpet_alarm_time.tm_min = min; | |
557 | hpet_alarm_time.tm_sec = sec; | |
558 | ||
559 | return 1; | |
560 | } | |
561 | ||
562 | int hpet_set_periodic_freq(unsigned long freq) | |
563 | { | |
564 | uint64_t clc; | |
565 | ||
566 | if (!is_hpet_enabled()) | |
567 | return 0; | |
568 | ||
569 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
570 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
571 | else { | |
572 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
573 | do_div(clc, freq); | |
574 | clc >>= hpet_clockevent.shift; | |
575 | hpet_pie_delta = (unsigned long) clc; | |
576 | } | |
577 | return 1; | |
578 | } | |
579 | ||
580 | int hpet_rtc_dropped_irq(void) | |
581 | { | |
582 | return is_hpet_enabled(); | |
583 | } | |
584 | ||
585 | static void hpet_rtc_timer_reinit(void) | |
586 | { | |
587 | unsigned long cfg, delta; | |
588 | int lost_ints = -1; | |
589 | ||
590 | if (unlikely(!hpet_rtc_flags)) { | |
591 | cfg = hpet_readl(HPET_T1_CFG); | |
592 | cfg &= ~HPET_TN_ENABLE; | |
593 | hpet_writel(cfg, HPET_T1_CFG); | |
594 | return; | |
595 | } | |
596 | ||
597 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
598 | delta = hpet_default_delta; | |
599 | else | |
600 | delta = hpet_pie_delta; | |
601 | ||
602 | /* | |
603 | * Increment the comparator value until we are ahead of the | |
604 | * current count. | |
605 | */ | |
606 | do { | |
607 | hpet_t1_cmp += delta; | |
608 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
609 | lost_ints++; | |
610 | } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); | |
611 | ||
612 | if (lost_ints) { | |
613 | if (hpet_rtc_flags & RTC_PIE) | |
614 | hpet_pie_count += lost_ints; | |
615 | if (printk_ratelimit()) | |
616 | printk(KERN_WARNING "rtc: lost %d interrupts\n", | |
617 | lost_ints); | |
618 | } | |
619 | } | |
620 | ||
621 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
622 | { | |
623 | struct rtc_time curr_time; | |
624 | unsigned long rtc_int_flag = 0; | |
625 | ||
626 | hpet_rtc_timer_reinit(); | |
627 | ||
628 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
629 | rtc_get_rtc_time(&curr_time); | |
630 | ||
631 | if (hpet_rtc_flags & RTC_UIE && | |
632 | curr_time.tm_sec != hpet_prev_update_sec) { | |
633 | rtc_int_flag = RTC_UF; | |
634 | hpet_prev_update_sec = curr_time.tm_sec; | |
635 | } | |
636 | ||
637 | if (hpet_rtc_flags & RTC_PIE && | |
638 | ++hpet_pie_count >= hpet_pie_limit) { | |
639 | rtc_int_flag |= RTC_PF; | |
640 | hpet_pie_count = 0; | |
641 | } | |
642 | ||
643 | if (hpet_rtc_flags & RTC_PIE && | |
644 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && | |
645 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
646 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
647 | rtc_int_flag |= RTC_AF; | |
648 | ||
649 | if (rtc_int_flag) { | |
650 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
651 | rtc_interrupt(rtc_int_flag, dev_id); | |
652 | } | |
653 | return IRQ_HANDLED; | |
654 | } | |
655 | #endif |