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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 IM |
3 | #include <linux/interrupt.h> |
4 | #include <linux/sysdev.h> | |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 JS |
6 | #include <linux/errno.h> |
7 | #include <linux/hpet.h> | |
8 | #include <linux/init.h> | |
58ac1e76 | 9 | #include <linux/cpu.h> |
4588c1f0 IM |
10 | #include <linux/pm.h> |
11 | #include <linux/io.h> | |
5d0cf410 | 12 | |
28769149 | 13 | #include <asm/fixmap.h> |
06a24dec | 14 | #include <asm/i8253.h> |
4588c1f0 | 15 | #include <asm/hpet.h> |
5d0cf410 | 16 | |
4588c1f0 IM |
17 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
18 | #define HPET_SHIFT 22 | |
5d0cf410 | 19 | |
b10db7f0 PM |
20 | /* FSEC = 10^-15 |
21 | NSEC = 10^-9 */ | |
4588c1f0 | 22 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 23 | |
26afe5f2 | 24 | #define HPET_DEV_USED_BIT 2 |
25 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
26 | #define HPET_DEV_VALID 0x8 | |
27 | #define HPET_DEV_FSB_CAP 0x1000 | |
28 | #define HPET_DEV_PERI_CAP 0x2000 | |
29 | ||
30 | #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) | |
31 | ||
e9e2cdb4 TG |
32 | /* |
33 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
34 | */ | |
4588c1f0 | 35 | unsigned long hpet_address; |
c8bc6f3c | 36 | u8 hpet_blockid; /* OS timer block num */ |
73472a46 PV |
37 | u8 hpet_msi_disable; |
38 | ||
e951e4af | 39 | #ifdef CONFIG_PCI_MSI |
3b71e9e3 | 40 | static unsigned long hpet_num_timers; |
e951e4af | 41 | #endif |
4588c1f0 | 42 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 43 | |
58ac1e76 | 44 | struct hpet_dev { |
4588c1f0 IM |
45 | struct clock_event_device evt; |
46 | unsigned int num; | |
47 | int cpu; | |
48 | unsigned int irq; | |
49 | unsigned int flags; | |
50 | char name[10]; | |
58ac1e76 | 51 | }; |
52 | ||
5946fa3d | 53 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
54 | { |
55 | return readl(hpet_virt_address + a); | |
56 | } | |
57 | ||
5946fa3d | 58 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
59 | { |
60 | writel(d, hpet_virt_address + a); | |
61 | } | |
62 | ||
28769149 | 63 | #ifdef CONFIG_X86_64 |
28769149 | 64 | #include <asm/pgtable.h> |
2387ce57 | 65 | #endif |
28769149 | 66 | |
06a24dec TG |
67 | static inline void hpet_set_mapping(void) |
68 | { | |
69 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 YL |
70 | #ifdef CONFIG_X86_64 |
71 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
72 | #endif | |
06a24dec TG |
73 | } |
74 | ||
75 | static inline void hpet_clear_mapping(void) | |
76 | { | |
77 | iounmap(hpet_virt_address); | |
78 | hpet_virt_address = NULL; | |
79 | } | |
80 | ||
e9e2cdb4 TG |
81 | /* |
82 | * HPET command line enable / disable | |
83 | */ | |
84 | static int boot_hpet_disable; | |
b17530bd | 85 | int hpet_force_user; |
b98103a5 | 86 | static int hpet_verbose; |
e9e2cdb4 | 87 | |
4588c1f0 | 88 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
89 | { |
90 | if (str) { | |
91 | if (!strncmp("disable", str, 7)) | |
92 | boot_hpet_disable = 1; | |
b17530bd TG |
93 | if (!strncmp("force", str, 5)) |
94 | hpet_force_user = 1; | |
b98103a5 AH |
95 | if (!strncmp("verbose", str, 7)) |
96 | hpet_verbose = 1; | |
e9e2cdb4 TG |
97 | } |
98 | return 1; | |
99 | } | |
100 | __setup("hpet=", hpet_setup); | |
101 | ||
28769149 TG |
102 | static int __init disable_hpet(char *str) |
103 | { | |
104 | boot_hpet_disable = 1; | |
105 | return 1; | |
106 | } | |
107 | __setup("nohpet", disable_hpet); | |
108 | ||
e9e2cdb4 TG |
109 | static inline int is_hpet_capable(void) |
110 | { | |
4588c1f0 | 111 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
112 | } |
113 | ||
114 | /* | |
115 | * HPET timer interrupt enable / disable | |
116 | */ | |
117 | static int hpet_legacy_int_enabled; | |
118 | ||
119 | /** | |
120 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
121 | */ | |
122 | int is_hpet_enabled(void) | |
123 | { | |
124 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
125 | } | |
1bdbdaac | 126 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 127 | |
b98103a5 AH |
128 | static void _hpet_print_config(const char *function, int line) |
129 | { | |
130 | u32 i, timers, l, h; | |
131 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
132 | l = hpet_readl(HPET_ID); | |
133 | h = hpet_readl(HPET_PERIOD); | |
134 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
135 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
136 | l = hpet_readl(HPET_CFG); | |
137 | h = hpet_readl(HPET_STATUS); | |
138 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
139 | l = hpet_readl(HPET_COUNTER); | |
140 | h = hpet_readl(HPET_COUNTER+4); | |
141 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
142 | ||
143 | for (i = 0; i < timers; i++) { | |
144 | l = hpet_readl(HPET_Tn_CFG(i)); | |
145 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
146 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
147 | i, l, h); | |
148 | l = hpet_readl(HPET_Tn_CMP(i)); | |
149 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
150 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
151 | i, l, h); | |
152 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
153 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
154 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
155 | i, l, h); | |
156 | } | |
157 | } | |
158 | ||
159 | #define hpet_print_config() \ | |
160 | do { \ | |
161 | if (hpet_verbose) \ | |
162 | _hpet_print_config(__FUNCTION__, __LINE__); \ | |
163 | } while (0) | |
164 | ||
e9e2cdb4 TG |
165 | /* |
166 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
167 | * timer 0 and timer 1 in case of RTC emulation. | |
168 | */ | |
169 | #ifdef CONFIG_HPET | |
f0ed4e69 | 170 | |
5f79f2f2 | 171 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 172 | |
5946fa3d | 173 | static void hpet_reserve_platform_timers(unsigned int id) |
e9e2cdb4 TG |
174 | { |
175 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
176 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
177 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
178 | struct hpet_data hd; |
179 | ||
180 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
181 | ||
4588c1f0 IM |
182 | memset(&hd, 0, sizeof(hd)); |
183 | hd.hd_phys_address = hpet_address; | |
184 | hd.hd_address = hpet; | |
185 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
186 | hpet_reserve_timer(&hd, 0); |
187 | ||
188 | #ifdef CONFIG_HPET_EMULATE_RTC | |
189 | hpet_reserve_timer(&hd, 1); | |
190 | #endif | |
5761d64b | 191 | |
64a76f66 DB |
192 | /* |
193 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
194 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
195 | * don't bother configuring *any* comparator interrupts. | |
196 | */ | |
e9e2cdb4 TG |
197 | hd.hd_irq[0] = HPET_LEGACY_8254; |
198 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
199 | ||
fc3fbc45 | 200 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
201 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
202 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 203 | } |
5761d64b | 204 | |
f0ed4e69 | 205 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 206 | |
e9e2cdb4 | 207 | hpet_alloc(&hd); |
5761d64b | 208 | |
e9e2cdb4 TG |
209 | } |
210 | #else | |
5946fa3d | 211 | static void hpet_reserve_platform_timers(unsigned int id) { } |
e9e2cdb4 TG |
212 | #endif |
213 | ||
214 | /* | |
215 | * Common hpet info | |
216 | */ | |
217 | static unsigned long hpet_period; | |
218 | ||
610bf2f1 | 219 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 220 | struct clock_event_device *evt); |
610bf2f1 | 221 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
222 | struct clock_event_device *evt); |
223 | ||
224 | /* | |
225 | * The hpet clock event device | |
226 | */ | |
227 | static struct clock_event_device hpet_clockevent = { | |
228 | .name = "hpet", | |
229 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
230 | .set_mode = hpet_legacy_set_mode, |
231 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 TG |
232 | .shift = 32, |
233 | .irq = 0, | |
59c69f2a | 234 | .rating = 50, |
e9e2cdb4 TG |
235 | }; |
236 | ||
8d6f0c82 | 237 | static void hpet_stop_counter(void) |
e9e2cdb4 TG |
238 | { |
239 | unsigned long cfg = hpet_readl(HPET_CFG); | |
e9e2cdb4 TG |
240 | cfg &= ~HPET_CFG_ENABLE; |
241 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
242 | } |
243 | ||
244 | static void hpet_reset_counter(void) | |
245 | { | |
e9e2cdb4 TG |
246 | hpet_writel(0, HPET_COUNTER); |
247 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
248 | } |
249 | ||
250 | static void hpet_start_counter(void) | |
251 | { | |
5946fa3d | 252 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
253 | cfg |= HPET_CFG_ENABLE; |
254 | hpet_writel(cfg, HPET_CFG); | |
255 | } | |
256 | ||
8d6f0c82 AH |
257 | static void hpet_restart_counter(void) |
258 | { | |
259 | hpet_stop_counter(); | |
7a6f9cbb | 260 | hpet_reset_counter(); |
8d6f0c82 AH |
261 | hpet_start_counter(); |
262 | } | |
263 | ||
59c69f2a VP |
264 | static void hpet_resume_device(void) |
265 | { | |
bfe0c1cc | 266 | force_hpet_resume(); |
59c69f2a VP |
267 | } |
268 | ||
17622339 | 269 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
270 | { |
271 | hpet_resume_device(); | |
8d6f0c82 | 272 | hpet_restart_counter(); |
59c69f2a VP |
273 | } |
274 | ||
610bf2f1 | 275 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 276 | { |
5946fa3d | 277 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
278 | |
279 | cfg |= HPET_CFG_LEGACY; | |
280 | hpet_writel(cfg, HPET_CFG); | |
281 | hpet_legacy_int_enabled = 1; | |
282 | } | |
283 | ||
610bf2f1 VP |
284 | static void hpet_legacy_clockevent_register(void) |
285 | { | |
610bf2f1 VP |
286 | /* Start HPET legacy interrupts */ |
287 | hpet_enable_legacy_int(); | |
288 | ||
289 | /* | |
6fd592da CM |
290 | * The mult factor is defined as (include/linux/clockchips.h) |
291 | * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) | |
292 | * hpet_period is in units of femtoseconds (per cycle), so | |
293 | * mult/2^shift = cyc/ns = 10^6/hpet_period | |
294 | * mult = (10^6 * 2^shift)/hpet_period | |
295 | * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period | |
610bf2f1 | 296 | */ |
6fd592da CM |
297 | hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, |
298 | hpet_period, hpet_clockevent.shift); | |
610bf2f1 VP |
299 | /* Calculate the min / max delta */ |
300 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
301 | &hpet_clockevent); | |
7cfb0435 TG |
302 | /* 5 usec minimum reprogramming delta. */ |
303 | hpet_clockevent.min_delta_ns = 5000; | |
610bf2f1 VP |
304 | |
305 | /* | |
306 | * Start hpet with the boot cpu mask and make it | |
307 | * global after the IO_APIC has been initialized. | |
308 | */ | |
320ab2b0 | 309 | hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); |
610bf2f1 VP |
310 | clockevents_register_device(&hpet_clockevent); |
311 | global_clock_event = &hpet_clockevent; | |
312 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
313 | } | |
314 | ||
26afe5f2 | 315 | static int hpet_setup_msi_irq(unsigned int irq); |
316 | ||
b40d575b | 317 | static void hpet_set_mode(enum clock_event_mode mode, |
318 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 319 | { |
5946fa3d | 320 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
321 | uint64_t delta; |
322 | ||
4588c1f0 | 323 | switch (mode) { |
e9e2cdb4 | 324 | case CLOCK_EVT_MODE_PERIODIC: |
c23e253e | 325 | hpet_stop_counter(); |
b40d575b | 326 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
327 | delta >>= evt->shift; | |
7a6f9cbb | 328 | now = hpet_readl(HPET_COUNTER); |
5946fa3d | 329 | cmp = now + (unsigned int) delta; |
b40d575b | 330 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
b13e2464 JS |
331 | /* Make sure we use edge triggered interrupts */ |
332 | cfg &= ~HPET_TN_LEVEL; | |
e9e2cdb4 TG |
333 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
334 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 335 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
7a6f9cbb AH |
336 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
337 | udelay(1); | |
338 | /* | |
339 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
340 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
341 | * bit is automatically cleared after the first write. | |
342 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
343 | * Publication # 24674) | |
344 | */ | |
5946fa3d | 345 | hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); |
c23e253e | 346 | hpet_start_counter(); |
b98103a5 | 347 | hpet_print_config(); |
e9e2cdb4 TG |
348 | break; |
349 | ||
350 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 351 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
352 | cfg &= ~HPET_TN_PERIODIC; |
353 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 354 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
355 | break; |
356 | ||
357 | case CLOCK_EVT_MODE_UNUSED: | |
358 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 359 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 360 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 361 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 362 | break; |
18de5bc4 TG |
363 | |
364 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 365 | if (timer == 0) { |
366 | hpet_enable_legacy_int(); | |
367 | } else { | |
368 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
369 | hpet_setup_msi_irq(hdev->irq); | |
370 | disable_irq(hdev->irq); | |
0de26520 | 371 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
26afe5f2 | 372 | enable_irq(hdev->irq); |
373 | } | |
b98103a5 | 374 | hpet_print_config(); |
18de5bc4 | 375 | break; |
e9e2cdb4 TG |
376 | } |
377 | } | |
378 | ||
b40d575b | 379 | static int hpet_next_event(unsigned long delta, |
380 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 381 | { |
f7676254 | 382 | u32 cnt; |
e9e2cdb4 TG |
383 | |
384 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 385 | cnt += (u32) delta; |
b40d575b | 386 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 387 | |
72d43d9b | 388 | /* |
18ed61da TG |
389 | * We need to read back the CMP register on certain HPET |
390 | * implementations (ATI chipsets) which seem to delay the | |
391 | * transfer of the compare register into the internal compare | |
392 | * logic. With small deltas this might actually be too late as | |
393 | * the counter could already be higher than the compare value | |
394 | * at that point and we would wait for the next hpet interrupt | |
395 | * forever. We found out that reading the CMP register back | |
396 | * forces the transfer so we can rely on the comparison with | |
397 | * the counter register below. If the read back from the | |
398 | * compare register does not match the value we programmed | |
399 | * then we might have a real hardware problem. We can not do | |
400 | * much about it here, but at least alert the user/admin with | |
401 | * a prominent warning. | |
8da854cb PV |
402 | * An erratum on some chipsets (ICH9,..), results in comparator read |
403 | * immediately following a write returning old value. Workaround | |
404 | * for this is to read this value second time, when first | |
405 | * read returns old value. | |
72d43d9b | 406 | */ |
8da854cb PV |
407 | if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) { |
408 | WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt, | |
18ed61da | 409 | KERN_WARNING "hpet: compare register read back failed.\n"); |
8da854cb | 410 | } |
72d43d9b | 411 | |
5946fa3d | 412 | return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; |
e9e2cdb4 TG |
413 | } |
414 | ||
b40d575b | 415 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
416 | struct clock_event_device *evt) | |
417 | { | |
418 | hpet_set_mode(mode, evt, 0); | |
419 | } | |
420 | ||
421 | static int hpet_legacy_next_event(unsigned long delta, | |
422 | struct clock_event_device *evt) | |
423 | { | |
424 | return hpet_next_event(delta, evt, 0); | |
425 | } | |
426 | ||
58ac1e76 | 427 | /* |
428 | * HPET MSI Support | |
429 | */ | |
26afe5f2 | 430 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
431 | |
432 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
433 | static struct hpet_dev *hpet_devs; | |
434 | ||
58ac1e76 | 435 | void hpet_msi_unmask(unsigned int irq) |
436 | { | |
437 | struct hpet_dev *hdev = get_irq_data(irq); | |
5946fa3d | 438 | unsigned int cfg; |
58ac1e76 | 439 | |
440 | /* unmask it */ | |
441 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
442 | cfg |= HPET_TN_FSB; | |
443 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
444 | } | |
445 | ||
446 | void hpet_msi_mask(unsigned int irq) | |
447 | { | |
5946fa3d | 448 | unsigned int cfg; |
58ac1e76 | 449 | struct hpet_dev *hdev = get_irq_data(irq); |
450 | ||
451 | /* mask it */ | |
452 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
453 | cfg &= ~HPET_TN_FSB; | |
454 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
455 | } | |
456 | ||
457 | void hpet_msi_write(unsigned int irq, struct msi_msg *msg) | |
458 | { | |
459 | struct hpet_dev *hdev = get_irq_data(irq); | |
460 | ||
461 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); | |
462 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
463 | } | |
464 | ||
465 | void hpet_msi_read(unsigned int irq, struct msi_msg *msg) | |
466 | { | |
467 | struct hpet_dev *hdev = get_irq_data(irq); | |
468 | ||
469 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); | |
470 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
471 | msg->address_hi = 0; | |
472 | } | |
473 | ||
26afe5f2 | 474 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
475 | struct clock_event_device *evt) | |
476 | { | |
477 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
478 | hpet_set_mode(mode, evt, hdev->num); | |
479 | } | |
480 | ||
481 | static int hpet_msi_next_event(unsigned long delta, | |
482 | struct clock_event_device *evt) | |
483 | { | |
484 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
485 | return hpet_next_event(delta, evt, hdev->num); | |
486 | } | |
487 | ||
488 | static int hpet_setup_msi_irq(unsigned int irq) | |
489 | { | |
c8bc6f3c | 490 | if (arch_setup_hpet_msi(irq, hpet_blockid)) { |
26afe5f2 | 491 | destroy_irq(irq); |
492 | return -EINVAL; | |
493 | } | |
494 | return 0; | |
495 | } | |
496 | ||
497 | static int hpet_assign_irq(struct hpet_dev *dev) | |
498 | { | |
499 | unsigned int irq; | |
500 | ||
501 | irq = create_irq(); | |
502 | if (!irq) | |
503 | return -EINVAL; | |
504 | ||
505 | set_irq_data(irq, dev); | |
506 | ||
507 | if (hpet_setup_msi_irq(irq)) | |
508 | return -EINVAL; | |
509 | ||
510 | dev->irq = irq; | |
511 | return 0; | |
512 | } | |
513 | ||
514 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
515 | { | |
516 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
517 | struct clock_event_device *hevt = &dev->evt; | |
518 | ||
519 | if (!hevt->event_handler) { | |
520 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
521 | dev->num); | |
522 | return IRQ_HANDLED; | |
523 | } | |
524 | ||
525 | hevt->event_handler(hevt); | |
526 | return IRQ_HANDLED; | |
527 | } | |
528 | ||
529 | static int hpet_setup_irq(struct hpet_dev *dev) | |
530 | { | |
531 | ||
532 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
507fa3a3 TG |
533 | IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING, |
534 | dev->name, dev)) | |
26afe5f2 | 535 | return -1; |
536 | ||
537 | disable_irq(dev->irq); | |
0de26520 | 538 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 539 | enable_irq(dev->irq); |
540 | ||
c81bba49 YL |
541 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
542 | dev->name, dev->irq); | |
543 | ||
26afe5f2 | 544 | return 0; |
545 | } | |
546 | ||
547 | /* This should be called in specific @cpu */ | |
548 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
549 | { | |
550 | struct clock_event_device *evt = &hdev->evt; | |
551 | uint64_t hpet_freq; | |
552 | ||
553 | WARN_ON(cpu != smp_processor_id()); | |
554 | if (!(hdev->flags & HPET_DEV_VALID)) | |
555 | return; | |
556 | ||
557 | if (hpet_setup_msi_irq(hdev->irq)) | |
558 | return; | |
559 | ||
560 | hdev->cpu = cpu; | |
561 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
562 | evt->name = hdev->name; | |
563 | hpet_setup_irq(hdev); | |
564 | evt->irq = hdev->irq; | |
565 | ||
566 | evt->rating = 110; | |
567 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
568 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
569 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
570 | ||
571 | evt->set_mode = hpet_msi_set_mode; | |
572 | evt->set_next_event = hpet_msi_next_event; | |
573 | evt->shift = 32; | |
574 | ||
575 | /* | |
576 | * The period is a femto seconds value. We need to calculate the | |
577 | * scaled math multiplication factor for nanosecond to hpet tick | |
578 | * conversion. | |
579 | */ | |
580 | hpet_freq = 1000000000000000ULL; | |
581 | do_div(hpet_freq, hpet_period); | |
582 | evt->mult = div_sc((unsigned long) hpet_freq, | |
583 | NSEC_PER_SEC, evt->shift); | |
584 | /* Calculate the max delta */ | |
585 | evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); | |
586 | /* 5 usec minimum reprogramming delta. */ | |
587 | evt->min_delta_ns = 5000; | |
588 | ||
320ab2b0 | 589 | evt->cpumask = cpumask_of(hdev->cpu); |
26afe5f2 | 590 | clockevents_register_device(evt); |
591 | } | |
592 | ||
593 | #ifdef CONFIG_HPET | |
594 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
595 | #define RESERVE_TIMERS 1 | |
596 | #else | |
597 | #define RESERVE_TIMERS 0 | |
598 | #endif | |
5f79f2f2 VP |
599 | |
600 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 601 | { |
602 | unsigned int id; | |
603 | unsigned int num_timers; | |
604 | unsigned int num_timers_used = 0; | |
605 | int i; | |
606 | ||
73472a46 PV |
607 | if (hpet_msi_disable) |
608 | return; | |
609 | ||
39fe05e5 SL |
610 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
611 | return; | |
26afe5f2 | 612 | id = hpet_readl(HPET_ID); |
613 | ||
614 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
615 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 616 | hpet_print_config(); |
26afe5f2 | 617 | |
618 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
619 | if (!hpet_devs) | |
620 | return; | |
621 | ||
622 | hpet_num_timers = num_timers; | |
623 | ||
624 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
625 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
5946fa3d | 626 | unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); |
26afe5f2 | 627 | |
628 | /* Only consider HPET timer with MSI support */ | |
629 | if (!(cfg & HPET_TN_FSB_CAP)) | |
630 | continue; | |
631 | ||
632 | hdev->flags = 0; | |
633 | if (cfg & HPET_TN_PERIODIC_CAP) | |
634 | hdev->flags |= HPET_DEV_PERI_CAP; | |
635 | hdev->num = i; | |
636 | ||
637 | sprintf(hdev->name, "hpet%d", i); | |
638 | if (hpet_assign_irq(hdev)) | |
639 | continue; | |
640 | ||
641 | hdev->flags |= HPET_DEV_FSB_CAP; | |
642 | hdev->flags |= HPET_DEV_VALID; | |
643 | num_timers_used++; | |
644 | if (num_timers_used == num_possible_cpus()) | |
645 | break; | |
646 | } | |
647 | ||
648 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
649 | num_timers, num_timers_used); | |
650 | } | |
651 | ||
5f79f2f2 VP |
652 | #ifdef CONFIG_HPET |
653 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
654 | { | |
655 | int i; | |
656 | ||
657 | if (!hpet_devs) | |
658 | return; | |
659 | ||
660 | for (i = 0; i < hpet_num_timers; i++) { | |
661 | struct hpet_dev *hdev = &hpet_devs[i]; | |
662 | ||
663 | if (!(hdev->flags & HPET_DEV_VALID)) | |
664 | continue; | |
665 | ||
666 | hd->hd_irq[hdev->num] = hdev->irq; | |
667 | hpet_reserve_timer(hd, hdev->num); | |
668 | } | |
669 | } | |
670 | #endif | |
671 | ||
26afe5f2 | 672 | static struct hpet_dev *hpet_get_unused_timer(void) |
673 | { | |
674 | int i; | |
675 | ||
676 | if (!hpet_devs) | |
677 | return NULL; | |
678 | ||
679 | for (i = 0; i < hpet_num_timers; i++) { | |
680 | struct hpet_dev *hdev = &hpet_devs[i]; | |
681 | ||
682 | if (!(hdev->flags & HPET_DEV_VALID)) | |
683 | continue; | |
684 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
685 | (unsigned long *)&hdev->flags)) | |
686 | continue; | |
687 | return hdev; | |
688 | } | |
689 | return NULL; | |
690 | } | |
691 | ||
692 | struct hpet_work_struct { | |
693 | struct delayed_work work; | |
694 | struct completion complete; | |
695 | }; | |
696 | ||
697 | static void hpet_work(struct work_struct *w) | |
698 | { | |
699 | struct hpet_dev *hdev; | |
700 | int cpu = smp_processor_id(); | |
701 | struct hpet_work_struct *hpet_work; | |
702 | ||
703 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
704 | ||
705 | hdev = hpet_get_unused_timer(); | |
706 | if (hdev) | |
707 | init_one_hpet_msi_clockevent(hdev, cpu); | |
708 | ||
709 | complete(&hpet_work->complete); | |
710 | } | |
711 | ||
712 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
713 | unsigned long action, void *hcpu) | |
714 | { | |
715 | unsigned long cpu = (unsigned long)hcpu; | |
716 | struct hpet_work_struct work; | |
717 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
718 | ||
719 | switch (action & 0xf) { | |
720 | case CPU_ONLINE: | |
336f6c32 | 721 | INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work); |
26afe5f2 | 722 | init_completion(&work.complete); |
723 | /* FIXME: add schedule_work_on() */ | |
724 | schedule_delayed_work_on(cpu, &work.work, 0); | |
725 | wait_for_completion(&work.complete); | |
336f6c32 | 726 | destroy_timer_on_stack(&work.work.timer); |
26afe5f2 | 727 | break; |
728 | case CPU_DEAD: | |
729 | if (hdev) { | |
730 | free_irq(hdev->irq, hdev); | |
731 | hdev->flags &= ~HPET_DEV_USED; | |
732 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
733 | } | |
734 | break; | |
735 | } | |
736 | return NOTIFY_OK; | |
737 | } | |
738 | #else | |
739 | ||
ba374c9b SN |
740 | static int hpet_setup_msi_irq(unsigned int irq) |
741 | { | |
742 | return 0; | |
743 | } | |
5f79f2f2 VP |
744 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
745 | { | |
746 | return; | |
747 | } | |
748 | ||
749 | #ifdef CONFIG_HPET | |
750 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 751 | { |
752 | return; | |
753 | } | |
5f79f2f2 | 754 | #endif |
26afe5f2 | 755 | |
756 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
757 | unsigned long action, void *hcpu) | |
758 | { | |
759 | return NOTIFY_OK; | |
760 | } | |
761 | ||
762 | #endif | |
763 | ||
6bb74df4 JS |
764 | /* |
765 | * Clock source related code | |
766 | */ | |
8e19608e | 767 | static cycle_t read_hpet(struct clocksource *cs) |
6bb74df4 JS |
768 | { |
769 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
770 | } | |
771 | ||
28769149 TG |
772 | #ifdef CONFIG_X86_64 |
773 | static cycle_t __vsyscall_fn vread_hpet(void) | |
774 | { | |
775 | return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); | |
776 | } | |
777 | #endif | |
778 | ||
6bb74df4 JS |
779 | static struct clocksource clocksource_hpet = { |
780 | .name = "hpet", | |
781 | .rating = 250, | |
782 | .read = read_hpet, | |
783 | .mask = HPET_MASK, | |
784 | .shift = HPET_SHIFT, | |
785 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
8d6f0c82 | 786 | .resume = hpet_resume_counter, |
28769149 TG |
787 | #ifdef CONFIG_X86_64 |
788 | .vread = vread_hpet, | |
789 | #endif | |
6bb74df4 JS |
790 | }; |
791 | ||
610bf2f1 | 792 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 793 | { |
6fd592da | 794 | u64 start, now; |
075bcd1f | 795 | cycle_t t1; |
e9e2cdb4 | 796 | |
e9e2cdb4 | 797 | /* Start the counter */ |
8d6f0c82 | 798 | hpet_restart_counter(); |
e9e2cdb4 | 799 | |
075bcd1f | 800 | /* Verify whether hpet counter works */ |
8e19608e | 801 | t1 = hpet_readl(HPET_COUNTER); |
075bcd1f TG |
802 | rdtscll(start); |
803 | ||
804 | /* | |
805 | * We don't know the TSC frequency yet, but waiting for | |
806 | * 200000 TSC cycles is safe: | |
807 | * 4 GHz == 50us | |
808 | * 1 GHz == 200us | |
809 | */ | |
810 | do { | |
811 | rep_nop(); | |
812 | rdtscll(now); | |
813 | } while ((now - start) < 200000UL); | |
814 | ||
8e19608e | 815 | if (t1 == hpet_readl(HPET_COUNTER)) { |
075bcd1f TG |
816 | printk(KERN_WARNING |
817 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 818 | return -ENODEV; |
075bcd1f TG |
819 | } |
820 | ||
6fd592da CM |
821 | /* |
822 | * The definition of mult is (include/linux/clocksource.h) | |
823 | * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc | |
824 | * so we first need to convert hpet_period to ns/cyc units: | |
825 | * mult/2^shift = ns/cyc = hpet_period/10^6 | |
826 | * mult = (hpet_period * 2^shift)/10^6 | |
827 | * mult = (hpet_period << shift)/FSEC_PER_NSEC | |
6bb74df4 | 828 | */ |
6fd592da | 829 | clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT); |
6bb74df4 JS |
830 | |
831 | clocksource_register(&clocksource_hpet); | |
832 | ||
610bf2f1 VP |
833 | return 0; |
834 | } | |
835 | ||
b02a7f22 PM |
836 | /** |
837 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
838 | */ |
839 | int __init hpet_enable(void) | |
840 | { | |
5946fa3d | 841 | unsigned int id; |
a6825f1c | 842 | int i; |
610bf2f1 VP |
843 | |
844 | if (!is_hpet_capable()) | |
845 | return 0; | |
846 | ||
847 | hpet_set_mapping(); | |
848 | ||
849 | /* | |
850 | * Read the period and check for a sane value: | |
851 | */ | |
852 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
853 | |
854 | /* | |
855 | * AMD SB700 based systems with spread spectrum enabled use a | |
856 | * SMM based HPET emulation to provide proper frequency | |
857 | * setting. The SMM code is initialized with the first HPET | |
858 | * register access and takes some time to complete. During | |
859 | * this time the config register reads 0xffffffff. We check | |
860 | * for max. 1000 loops whether the config register reads a non | |
861 | * 0xffffffff value to make sure that HPET is up and running | |
862 | * before we go further. A counting loop is safe, as the HPET | |
863 | * access takes thousands of CPU cycles. On non SB700 based | |
864 | * machines this check is only done once and has no side | |
865 | * effects. | |
866 | */ | |
867 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
868 | if (i == 1000) { | |
869 | printk(KERN_WARNING | |
870 | "HPET config register value = 0xFFFFFFFF. " | |
871 | "Disabling HPET\n"); | |
872 | goto out_nohpet; | |
873 | } | |
874 | } | |
875 | ||
610bf2f1 VP |
876 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
877 | goto out_nohpet; | |
878 | ||
879 | /* | |
880 | * Read the HPET ID register to retrieve the IRQ routing | |
881 | * information and the number of channels | |
882 | */ | |
883 | id = hpet_readl(HPET_ID); | |
b98103a5 | 884 | hpet_print_config(); |
610bf2f1 VP |
885 | |
886 | #ifdef CONFIG_HPET_EMULATE_RTC | |
887 | /* | |
888 | * The legacy routing mode needs at least two channels, tick timer | |
889 | * and the rtc emulation channel. | |
890 | */ | |
891 | if (!(id & HPET_ID_NUMBER)) | |
892 | goto out_nohpet; | |
893 | #endif | |
894 | ||
895 | if (hpet_clocksource_register()) | |
896 | goto out_nohpet; | |
897 | ||
e9e2cdb4 | 898 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 899 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
900 | return 1; |
901 | } | |
902 | return 0; | |
5d0cf410 | 903 | |
e9e2cdb4 | 904 | out_nohpet: |
06a24dec | 905 | hpet_clear_mapping(); |
bacbe999 | 906 | hpet_address = 0; |
e9e2cdb4 TG |
907 | return 0; |
908 | } | |
909 | ||
28769149 TG |
910 | /* |
911 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
912 | * | |
913 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
914 | * but on x86_64 it is necessary ! | |
915 | */ | |
916 | static __init int hpet_late_init(void) | |
917 | { | |
26afe5f2 | 918 | int cpu; |
919 | ||
59c69f2a | 920 | if (boot_hpet_disable) |
28769149 TG |
921 | return -ENODEV; |
922 | ||
59c69f2a VP |
923 | if (!hpet_address) { |
924 | if (!force_hpet_address) | |
925 | return -ENODEV; | |
926 | ||
927 | hpet_address = force_hpet_address; | |
928 | hpet_enable(); | |
59c69f2a VP |
929 | } |
930 | ||
39c04b55 JF |
931 | if (!hpet_virt_address) |
932 | return -ENODEV; | |
933 | ||
39fe05e5 SL |
934 | if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) |
935 | hpet_msi_capability_lookup(2); | |
936 | else | |
937 | hpet_msi_capability_lookup(0); | |
938 | ||
28769149 | 939 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 940 | hpet_print_config(); |
59c69f2a | 941 | |
73472a46 PV |
942 | if (hpet_msi_disable) |
943 | return 0; | |
944 | ||
39fe05e5 SL |
945 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
946 | return 0; | |
947 | ||
26afe5f2 | 948 | for_each_online_cpu(cpu) { |
949 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
950 | } | |
951 | ||
952 | /* This notifier should be called after workqueue is ready */ | |
953 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
954 | ||
28769149 TG |
955 | return 0; |
956 | } | |
957 | fs_initcall(hpet_late_init); | |
958 | ||
c86c7fbc OH |
959 | void hpet_disable(void) |
960 | { | |
961 | if (is_hpet_capable()) { | |
5946fa3d | 962 | unsigned int cfg = hpet_readl(HPET_CFG); |
c86c7fbc OH |
963 | |
964 | if (hpet_legacy_int_enabled) { | |
965 | cfg &= ~HPET_CFG_LEGACY; | |
966 | hpet_legacy_int_enabled = 0; | |
967 | } | |
968 | cfg &= ~HPET_CFG_ENABLE; | |
969 | hpet_writel(cfg, HPET_CFG); | |
970 | } | |
971 | } | |
972 | ||
e9e2cdb4 TG |
973 | #ifdef CONFIG_HPET_EMULATE_RTC |
974 | ||
975 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
976 | * is enabled, we support RTC interrupt functionality in software. | |
977 | * RTC has 3 kinds of interrupts: | |
978 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
979 | * is updated | |
980 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
981 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
982 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
983 | * (1) and (2) above are implemented using polling at a frequency of | |
984 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
985 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
986 | * For (3), we use interrupts at 64Hz or user specified periodic | |
987 | * frequency, whichever is higher. | |
988 | */ | |
989 | #include <linux/mc146818rtc.h> | |
990 | #include <linux/rtc.h> | |
1bdbdaac | 991 | #include <asm/rtc.h> |
e9e2cdb4 TG |
992 | |
993 | #define DEFAULT_RTC_INT_FREQ 64 | |
994 | #define DEFAULT_RTC_SHIFT 6 | |
995 | #define RTC_NUM_INTS 1 | |
996 | ||
997 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 998 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
999 | static struct rtc_time hpet_alarm_time; |
1000 | static unsigned long hpet_pie_count; | |
ff08f76d | 1001 | static u32 hpet_t1_cmp; |
5946fa3d JB |
1002 | static u32 hpet_default_delta; |
1003 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
1004 | static unsigned long hpet_pie_limit; |
1005 | ||
1bdbdaac BW |
1006 | static rtc_irq_handler irq_handler; |
1007 | ||
ff08f76d PE |
1008 | /* |
1009 | * Check that the hpet counter c1 is ahead of the c2 | |
1010 | */ | |
1011 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
1012 | { | |
1013 | return (s32)(c2 - c1) < 0; | |
1014 | } | |
1015 | ||
1bdbdaac BW |
1016 | /* |
1017 | * Registers a IRQ handler. | |
1018 | */ | |
1019 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
1020 | { | |
1021 | if (!is_hpet_enabled()) | |
1022 | return -ENODEV; | |
1023 | if (irq_handler) | |
1024 | return -EBUSY; | |
1025 | ||
1026 | irq_handler = handler; | |
1027 | ||
1028 | return 0; | |
1029 | } | |
1030 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
1031 | ||
1032 | /* | |
1033 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
1034 | * and does cleanup. | |
1035 | */ | |
1036 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
1037 | { | |
1038 | if (!is_hpet_enabled()) | |
1039 | return; | |
1040 | ||
1041 | irq_handler = NULL; | |
1042 | hpet_rtc_flags = 0; | |
1043 | } | |
1044 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1045 | ||
e9e2cdb4 TG |
1046 | /* |
1047 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
1048 | * is not supported by all HPET implementations for timer 1. | |
1049 | * | |
1050 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1051 | */ | |
1052 | int hpet_rtc_timer_init(void) | |
1053 | { | |
5946fa3d JB |
1054 | unsigned int cfg, cnt, delta; |
1055 | unsigned long flags; | |
e9e2cdb4 TG |
1056 | |
1057 | if (!is_hpet_enabled()) | |
1058 | return 0; | |
1059 | ||
1060 | if (!hpet_default_delta) { | |
1061 | uint64_t clc; | |
1062 | ||
1063 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1064 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1065 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1066 | } |
1067 | ||
1068 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1069 | delta = hpet_default_delta; | |
1070 | else | |
1071 | delta = hpet_pie_delta; | |
1072 | ||
1073 | local_irq_save(flags); | |
1074 | ||
1075 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1076 | hpet_writel(cnt, HPET_T1_CMP); | |
1077 | hpet_t1_cmp = cnt; | |
1078 | ||
1079 | cfg = hpet_readl(HPET_T1_CFG); | |
1080 | cfg &= ~HPET_TN_PERIODIC; | |
1081 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1082 | hpet_writel(cfg, HPET_T1_CFG); | |
1083 | ||
1084 | local_irq_restore(flags); | |
1085 | ||
1086 | return 1; | |
1087 | } | |
1bdbdaac | 1088 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
1089 | |
1090 | /* | |
1091 | * The functions below are called from rtc driver. | |
1092 | * Return 0 if HPET is not being used. | |
1093 | * Otherwise do the necessary changes and return 1. | |
1094 | */ | |
1095 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1096 | { | |
1097 | if (!is_hpet_enabled()) | |
1098 | return 0; | |
1099 | ||
1100 | hpet_rtc_flags &= ~bit_mask; | |
1101 | return 1; | |
1102 | } | |
1bdbdaac | 1103 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1104 | |
1105 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1106 | { | |
1107 | unsigned long oldbits = hpet_rtc_flags; | |
1108 | ||
1109 | if (!is_hpet_enabled()) | |
1110 | return 0; | |
1111 | ||
1112 | hpet_rtc_flags |= bit_mask; | |
1113 | ||
7e2a31da DB |
1114 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1115 | hpet_prev_update_sec = -1; | |
1116 | ||
e9e2cdb4 TG |
1117 | if (!oldbits) |
1118 | hpet_rtc_timer_init(); | |
1119 | ||
1120 | return 1; | |
1121 | } | |
1bdbdaac | 1122 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1123 | |
1124 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1125 | unsigned char sec) | |
1126 | { | |
1127 | if (!is_hpet_enabled()) | |
1128 | return 0; | |
1129 | ||
1130 | hpet_alarm_time.tm_hour = hrs; | |
1131 | hpet_alarm_time.tm_min = min; | |
1132 | hpet_alarm_time.tm_sec = sec; | |
1133 | ||
1134 | return 1; | |
1135 | } | |
1bdbdaac | 1136 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1137 | |
1138 | int hpet_set_periodic_freq(unsigned long freq) | |
1139 | { | |
1140 | uint64_t clc; | |
1141 | ||
1142 | if (!is_hpet_enabled()) | |
1143 | return 0; | |
1144 | ||
1145 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1146 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1147 | else { | |
1148 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1149 | do_div(clc, freq); | |
1150 | clc >>= hpet_clockevent.shift; | |
5946fa3d | 1151 | hpet_pie_delta = clc; |
e9e2cdb4 TG |
1152 | } |
1153 | return 1; | |
1154 | } | |
1bdbdaac | 1155 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1156 | |
1157 | int hpet_rtc_dropped_irq(void) | |
1158 | { | |
1159 | return is_hpet_enabled(); | |
1160 | } | |
1bdbdaac | 1161 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1162 | |
1163 | static void hpet_rtc_timer_reinit(void) | |
1164 | { | |
5946fa3d | 1165 | unsigned int cfg, delta; |
e9e2cdb4 TG |
1166 | int lost_ints = -1; |
1167 | ||
1168 | if (unlikely(!hpet_rtc_flags)) { | |
1169 | cfg = hpet_readl(HPET_T1_CFG); | |
1170 | cfg &= ~HPET_TN_ENABLE; | |
1171 | hpet_writel(cfg, HPET_T1_CFG); | |
1172 | return; | |
1173 | } | |
1174 | ||
1175 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1176 | delta = hpet_default_delta; | |
1177 | else | |
1178 | delta = hpet_pie_delta; | |
1179 | ||
1180 | /* | |
1181 | * Increment the comparator value until we are ahead of the | |
1182 | * current count. | |
1183 | */ | |
1184 | do { | |
1185 | hpet_t1_cmp += delta; | |
1186 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1187 | lost_ints++; | |
ff08f76d | 1188 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1189 | |
1190 | if (lost_ints) { | |
1191 | if (hpet_rtc_flags & RTC_PIE) | |
1192 | hpet_pie_count += lost_ints; | |
1193 | if (printk_ratelimit()) | |
7e2a31da | 1194 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1195 | lost_ints); |
1196 | } | |
1197 | } | |
1198 | ||
1199 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1200 | { | |
1201 | struct rtc_time curr_time; | |
1202 | unsigned long rtc_int_flag = 0; | |
1203 | ||
1204 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1205 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1206 | |
1207 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1208 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1209 | |
1210 | if (hpet_rtc_flags & RTC_UIE && | |
1211 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1212 | if (hpet_prev_update_sec >= 0) |
1213 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1214 | hpet_prev_update_sec = curr_time.tm_sec; |
1215 | } | |
1216 | ||
1217 | if (hpet_rtc_flags & RTC_PIE && | |
1218 | ++hpet_pie_count >= hpet_pie_limit) { | |
1219 | rtc_int_flag |= RTC_PF; | |
1220 | hpet_pie_count = 0; | |
1221 | } | |
1222 | ||
8ee291f8 | 1223 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1224 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1225 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1226 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1227 | rtc_int_flag |= RTC_AF; | |
1228 | ||
1229 | if (rtc_int_flag) { | |
1230 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1231 | if (irq_handler) |
1232 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1233 | } |
1234 | return IRQ_HANDLED; | |
1235 | } | |
1bdbdaac | 1236 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1237 | #endif |