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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 IM |
3 | #include <linux/interrupt.h> |
4 | #include <linux/sysdev.h> | |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 JS |
6 | #include <linux/errno.h> |
7 | #include <linux/hpet.h> | |
8 | #include <linux/init.h> | |
58ac1e76 | 9 | #include <linux/cpu.h> |
4588c1f0 IM |
10 | #include <linux/pm.h> |
11 | #include <linux/io.h> | |
5d0cf410 | 12 | |
28769149 | 13 | #include <asm/fixmap.h> |
06a24dec | 14 | #include <asm/i8253.h> |
4588c1f0 | 15 | #include <asm/hpet.h> |
5d0cf410 | 16 | |
4588c1f0 IM |
17 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
18 | #define HPET_SHIFT 22 | |
5d0cf410 | 19 | |
b10db7f0 PM |
20 | /* FSEC = 10^-15 |
21 | NSEC = 10^-9 */ | |
4588c1f0 | 22 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 23 | |
26afe5f2 | 24 | #define HPET_DEV_USED_BIT 2 |
25 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
26 | #define HPET_DEV_VALID 0x8 | |
27 | #define HPET_DEV_FSB_CAP 0x1000 | |
28 | #define HPET_DEV_PERI_CAP 0x2000 | |
29 | ||
30 | #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) | |
31 | ||
e9e2cdb4 TG |
32 | /* |
33 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
34 | */ | |
4588c1f0 | 35 | unsigned long hpet_address; |
e951e4af | 36 | #ifdef CONFIG_PCI_MSI |
3b71e9e3 | 37 | static unsigned long hpet_num_timers; |
e951e4af | 38 | #endif |
4588c1f0 | 39 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 40 | |
58ac1e76 | 41 | struct hpet_dev { |
4588c1f0 IM |
42 | struct clock_event_device evt; |
43 | unsigned int num; | |
44 | int cpu; | |
45 | unsigned int irq; | |
46 | unsigned int flags; | |
47 | char name[10]; | |
58ac1e76 | 48 | }; |
49 | ||
31c435d7 | 50 | unsigned long hpet_readl(unsigned long a) |
e9e2cdb4 TG |
51 | { |
52 | return readl(hpet_virt_address + a); | |
53 | } | |
54 | ||
55 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
56 | { | |
57 | writel(d, hpet_virt_address + a); | |
58 | } | |
59 | ||
28769149 | 60 | #ifdef CONFIG_X86_64 |
28769149 | 61 | #include <asm/pgtable.h> |
2387ce57 | 62 | #endif |
28769149 | 63 | |
06a24dec TG |
64 | static inline void hpet_set_mapping(void) |
65 | { | |
66 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 YL |
67 | #ifdef CONFIG_X86_64 |
68 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
69 | #endif | |
06a24dec TG |
70 | } |
71 | ||
72 | static inline void hpet_clear_mapping(void) | |
73 | { | |
74 | iounmap(hpet_virt_address); | |
75 | hpet_virt_address = NULL; | |
76 | } | |
77 | ||
e9e2cdb4 TG |
78 | /* |
79 | * HPET command line enable / disable | |
80 | */ | |
81 | static int boot_hpet_disable; | |
b17530bd | 82 | int hpet_force_user; |
b98103a5 | 83 | static int hpet_verbose; |
e9e2cdb4 | 84 | |
4588c1f0 | 85 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
86 | { |
87 | if (str) { | |
88 | if (!strncmp("disable", str, 7)) | |
89 | boot_hpet_disable = 1; | |
b17530bd TG |
90 | if (!strncmp("force", str, 5)) |
91 | hpet_force_user = 1; | |
b98103a5 AH |
92 | if (!strncmp("verbose", str, 7)) |
93 | hpet_verbose = 1; | |
e9e2cdb4 TG |
94 | } |
95 | return 1; | |
96 | } | |
97 | __setup("hpet=", hpet_setup); | |
98 | ||
28769149 TG |
99 | static int __init disable_hpet(char *str) |
100 | { | |
101 | boot_hpet_disable = 1; | |
102 | return 1; | |
103 | } | |
104 | __setup("nohpet", disable_hpet); | |
105 | ||
e9e2cdb4 TG |
106 | static inline int is_hpet_capable(void) |
107 | { | |
4588c1f0 | 108 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
109 | } |
110 | ||
111 | /* | |
112 | * HPET timer interrupt enable / disable | |
113 | */ | |
114 | static int hpet_legacy_int_enabled; | |
115 | ||
116 | /** | |
117 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
118 | */ | |
119 | int is_hpet_enabled(void) | |
120 | { | |
121 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
122 | } | |
1bdbdaac | 123 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 124 | |
b98103a5 AH |
125 | static void _hpet_print_config(const char *function, int line) |
126 | { | |
127 | u32 i, timers, l, h; | |
128 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
129 | l = hpet_readl(HPET_ID); | |
130 | h = hpet_readl(HPET_PERIOD); | |
131 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
132 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
133 | l = hpet_readl(HPET_CFG); | |
134 | h = hpet_readl(HPET_STATUS); | |
135 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
136 | l = hpet_readl(HPET_COUNTER); | |
137 | h = hpet_readl(HPET_COUNTER+4); | |
138 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
139 | ||
140 | for (i = 0; i < timers; i++) { | |
141 | l = hpet_readl(HPET_Tn_CFG(i)); | |
142 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
143 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
144 | i, l, h); | |
145 | l = hpet_readl(HPET_Tn_CMP(i)); | |
146 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
147 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
148 | i, l, h); | |
149 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
150 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
151 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
152 | i, l, h); | |
153 | } | |
154 | } | |
155 | ||
156 | #define hpet_print_config() \ | |
157 | do { \ | |
158 | if (hpet_verbose) \ | |
159 | _hpet_print_config(__FUNCTION__, __LINE__); \ | |
160 | } while (0) | |
161 | ||
e9e2cdb4 TG |
162 | /* |
163 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
164 | * timer 0 and timer 1 in case of RTC emulation. | |
165 | */ | |
166 | #ifdef CONFIG_HPET | |
f0ed4e69 | 167 | |
5f79f2f2 | 168 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 169 | |
e9e2cdb4 TG |
170 | static void hpet_reserve_platform_timers(unsigned long id) |
171 | { | |
172 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
173 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
174 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
175 | struct hpet_data hd; |
176 | ||
177 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
178 | ||
4588c1f0 IM |
179 | memset(&hd, 0, sizeof(hd)); |
180 | hd.hd_phys_address = hpet_address; | |
181 | hd.hd_address = hpet; | |
182 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
183 | hpet_reserve_timer(&hd, 0); |
184 | ||
185 | #ifdef CONFIG_HPET_EMULATE_RTC | |
186 | hpet_reserve_timer(&hd, 1); | |
187 | #endif | |
5761d64b | 188 | |
64a76f66 DB |
189 | /* |
190 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
191 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
192 | * don't bother configuring *any* comparator interrupts. | |
193 | */ | |
e9e2cdb4 TG |
194 | hd.hd_irq[0] = HPET_LEGACY_8254; |
195 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
196 | ||
fc3fbc45 | 197 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
198 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
199 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 200 | } |
5761d64b | 201 | |
f0ed4e69 | 202 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 203 | |
e9e2cdb4 | 204 | hpet_alloc(&hd); |
5761d64b | 205 | |
e9e2cdb4 TG |
206 | } |
207 | #else | |
208 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
209 | #endif | |
210 | ||
211 | /* | |
212 | * Common hpet info | |
213 | */ | |
214 | static unsigned long hpet_period; | |
215 | ||
610bf2f1 | 216 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 217 | struct clock_event_device *evt); |
610bf2f1 | 218 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
219 | struct clock_event_device *evt); |
220 | ||
221 | /* | |
222 | * The hpet clock event device | |
223 | */ | |
224 | static struct clock_event_device hpet_clockevent = { | |
225 | .name = "hpet", | |
226 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
227 | .set_mode = hpet_legacy_set_mode, |
228 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 TG |
229 | .shift = 32, |
230 | .irq = 0, | |
59c69f2a | 231 | .rating = 50, |
e9e2cdb4 TG |
232 | }; |
233 | ||
234 | static void hpet_start_counter(void) | |
235 | { | |
236 | unsigned long cfg = hpet_readl(HPET_CFG); | |
237 | ||
238 | cfg &= ~HPET_CFG_ENABLE; | |
239 | hpet_writel(cfg, HPET_CFG); | |
240 | hpet_writel(0, HPET_COUNTER); | |
241 | hpet_writel(0, HPET_COUNTER + 4); | |
242 | cfg |= HPET_CFG_ENABLE; | |
243 | hpet_writel(cfg, HPET_CFG); | |
244 | } | |
245 | ||
59c69f2a VP |
246 | static void hpet_resume_device(void) |
247 | { | |
bfe0c1cc | 248 | force_hpet_resume(); |
59c69f2a VP |
249 | } |
250 | ||
251 | static void hpet_restart_counter(void) | |
252 | { | |
253 | hpet_resume_device(); | |
254 | hpet_start_counter(); | |
255 | } | |
256 | ||
610bf2f1 | 257 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 TG |
258 | { |
259 | unsigned long cfg = hpet_readl(HPET_CFG); | |
260 | ||
261 | cfg |= HPET_CFG_LEGACY; | |
262 | hpet_writel(cfg, HPET_CFG); | |
263 | hpet_legacy_int_enabled = 1; | |
264 | } | |
265 | ||
610bf2f1 VP |
266 | static void hpet_legacy_clockevent_register(void) |
267 | { | |
610bf2f1 VP |
268 | /* Start HPET legacy interrupts */ |
269 | hpet_enable_legacy_int(); | |
270 | ||
271 | /* | |
6fd592da CM |
272 | * The mult factor is defined as (include/linux/clockchips.h) |
273 | * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) | |
274 | * hpet_period is in units of femtoseconds (per cycle), so | |
275 | * mult/2^shift = cyc/ns = 10^6/hpet_period | |
276 | * mult = (10^6 * 2^shift)/hpet_period | |
277 | * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period | |
610bf2f1 | 278 | */ |
6fd592da CM |
279 | hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, |
280 | hpet_period, hpet_clockevent.shift); | |
610bf2f1 VP |
281 | /* Calculate the min / max delta */ |
282 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
283 | &hpet_clockevent); | |
7cfb0435 TG |
284 | /* 5 usec minimum reprogramming delta. */ |
285 | hpet_clockevent.min_delta_ns = 5000; | |
610bf2f1 VP |
286 | |
287 | /* | |
288 | * Start hpet with the boot cpu mask and make it | |
289 | * global after the IO_APIC has been initialized. | |
290 | */ | |
320ab2b0 | 291 | hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); |
610bf2f1 VP |
292 | clockevents_register_device(&hpet_clockevent); |
293 | global_clock_event = &hpet_clockevent; | |
294 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
295 | } | |
296 | ||
26afe5f2 | 297 | static int hpet_setup_msi_irq(unsigned int irq); |
298 | ||
b40d575b | 299 | static void hpet_set_mode(enum clock_event_mode mode, |
300 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 TG |
301 | { |
302 | unsigned long cfg, cmp, now; | |
303 | uint64_t delta; | |
304 | ||
4588c1f0 | 305 | switch (mode) { |
e9e2cdb4 | 306 | case CLOCK_EVT_MODE_PERIODIC: |
b40d575b | 307 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
308 | delta >>= evt->shift; | |
e9e2cdb4 TG |
309 | now = hpet_readl(HPET_COUNTER); |
310 | cmp = now + (unsigned long) delta; | |
b40d575b | 311 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
b13e2464 JS |
312 | /* Make sure we use edge triggered interrupts */ |
313 | cfg &= ~HPET_TN_LEVEL; | |
e9e2cdb4 TG |
314 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
315 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 316 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
317 | /* |
318 | * The first write after writing TN_SETVAL to the | |
319 | * config register sets the counter value, the second | |
320 | * write sets the period. | |
321 | */ | |
b40d575b | 322 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 323 | udelay(1); |
b40d575b | 324 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); |
b98103a5 | 325 | hpet_print_config(); |
e9e2cdb4 TG |
326 | break; |
327 | ||
328 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 329 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
330 | cfg &= ~HPET_TN_PERIODIC; |
331 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 332 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
333 | break; |
334 | ||
335 | case CLOCK_EVT_MODE_UNUSED: | |
336 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 337 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 338 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 339 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 340 | break; |
18de5bc4 TG |
341 | |
342 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 343 | if (timer == 0) { |
344 | hpet_enable_legacy_int(); | |
345 | } else { | |
346 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
347 | hpet_setup_msi_irq(hdev->irq); | |
348 | disable_irq(hdev->irq); | |
0de26520 | 349 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
26afe5f2 | 350 | enable_irq(hdev->irq); |
351 | } | |
b98103a5 | 352 | hpet_print_config(); |
18de5bc4 | 353 | break; |
e9e2cdb4 TG |
354 | } |
355 | } | |
356 | ||
b40d575b | 357 | static int hpet_next_event(unsigned long delta, |
358 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 359 | { |
f7676254 | 360 | u32 cnt; |
e9e2cdb4 TG |
361 | |
362 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 363 | cnt += (u32) delta; |
b40d575b | 364 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 365 | |
72d43d9b TG |
366 | /* |
367 | * We need to read back the CMP register to make sure that | |
368 | * what we wrote hit the chip before we compare it to the | |
369 | * counter. | |
370 | */ | |
89d77a1e | 371 | WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt); |
72d43d9b | 372 | |
f7676254 | 373 | return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; |
e9e2cdb4 TG |
374 | } |
375 | ||
b40d575b | 376 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
377 | struct clock_event_device *evt) | |
378 | { | |
379 | hpet_set_mode(mode, evt, 0); | |
380 | } | |
381 | ||
382 | static int hpet_legacy_next_event(unsigned long delta, | |
383 | struct clock_event_device *evt) | |
384 | { | |
385 | return hpet_next_event(delta, evt, 0); | |
386 | } | |
387 | ||
58ac1e76 | 388 | /* |
389 | * HPET MSI Support | |
390 | */ | |
26afe5f2 | 391 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
392 | |
393 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
394 | static struct hpet_dev *hpet_devs; | |
395 | ||
58ac1e76 | 396 | void hpet_msi_unmask(unsigned int irq) |
397 | { | |
398 | struct hpet_dev *hdev = get_irq_data(irq); | |
399 | unsigned long cfg; | |
400 | ||
401 | /* unmask it */ | |
402 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
403 | cfg |= HPET_TN_FSB; | |
404 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
405 | } | |
406 | ||
407 | void hpet_msi_mask(unsigned int irq) | |
408 | { | |
409 | unsigned long cfg; | |
410 | struct hpet_dev *hdev = get_irq_data(irq); | |
411 | ||
412 | /* mask it */ | |
413 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
414 | cfg &= ~HPET_TN_FSB; | |
415 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
416 | } | |
417 | ||
418 | void hpet_msi_write(unsigned int irq, struct msi_msg *msg) | |
419 | { | |
420 | struct hpet_dev *hdev = get_irq_data(irq); | |
421 | ||
422 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); | |
423 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
424 | } | |
425 | ||
426 | void hpet_msi_read(unsigned int irq, struct msi_msg *msg) | |
427 | { | |
428 | struct hpet_dev *hdev = get_irq_data(irq); | |
429 | ||
430 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); | |
431 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
432 | msg->address_hi = 0; | |
433 | } | |
434 | ||
26afe5f2 | 435 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
436 | struct clock_event_device *evt) | |
437 | { | |
438 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
439 | hpet_set_mode(mode, evt, hdev->num); | |
440 | } | |
441 | ||
442 | static int hpet_msi_next_event(unsigned long delta, | |
443 | struct clock_event_device *evt) | |
444 | { | |
445 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
446 | return hpet_next_event(delta, evt, hdev->num); | |
447 | } | |
448 | ||
449 | static int hpet_setup_msi_irq(unsigned int irq) | |
450 | { | |
451 | if (arch_setup_hpet_msi(irq)) { | |
452 | destroy_irq(irq); | |
453 | return -EINVAL; | |
454 | } | |
455 | return 0; | |
456 | } | |
457 | ||
458 | static int hpet_assign_irq(struct hpet_dev *dev) | |
459 | { | |
460 | unsigned int irq; | |
461 | ||
462 | irq = create_irq(); | |
463 | if (!irq) | |
464 | return -EINVAL; | |
465 | ||
466 | set_irq_data(irq, dev); | |
467 | ||
468 | if (hpet_setup_msi_irq(irq)) | |
469 | return -EINVAL; | |
470 | ||
471 | dev->irq = irq; | |
472 | return 0; | |
473 | } | |
474 | ||
475 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
476 | { | |
477 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
478 | struct clock_event_device *hevt = &dev->evt; | |
479 | ||
480 | if (!hevt->event_handler) { | |
481 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
482 | dev->num); | |
483 | return IRQ_HANDLED; | |
484 | } | |
485 | ||
486 | hevt->event_handler(hevt); | |
487 | return IRQ_HANDLED; | |
488 | } | |
489 | ||
490 | static int hpet_setup_irq(struct hpet_dev *dev) | |
491 | { | |
492 | ||
493 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
5ceb1a04 | 494 | IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev)) |
26afe5f2 | 495 | return -1; |
496 | ||
497 | disable_irq(dev->irq); | |
0de26520 | 498 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 499 | enable_irq(dev->irq); |
500 | ||
c81bba49 YL |
501 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
502 | dev->name, dev->irq); | |
503 | ||
26afe5f2 | 504 | return 0; |
505 | } | |
506 | ||
507 | /* This should be called in specific @cpu */ | |
508 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
509 | { | |
510 | struct clock_event_device *evt = &hdev->evt; | |
511 | uint64_t hpet_freq; | |
512 | ||
513 | WARN_ON(cpu != smp_processor_id()); | |
514 | if (!(hdev->flags & HPET_DEV_VALID)) | |
515 | return; | |
516 | ||
517 | if (hpet_setup_msi_irq(hdev->irq)) | |
518 | return; | |
519 | ||
520 | hdev->cpu = cpu; | |
521 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
522 | evt->name = hdev->name; | |
523 | hpet_setup_irq(hdev); | |
524 | evt->irq = hdev->irq; | |
525 | ||
526 | evt->rating = 110; | |
527 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
528 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
529 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
530 | ||
531 | evt->set_mode = hpet_msi_set_mode; | |
532 | evt->set_next_event = hpet_msi_next_event; | |
533 | evt->shift = 32; | |
534 | ||
535 | /* | |
536 | * The period is a femto seconds value. We need to calculate the | |
537 | * scaled math multiplication factor for nanosecond to hpet tick | |
538 | * conversion. | |
539 | */ | |
540 | hpet_freq = 1000000000000000ULL; | |
541 | do_div(hpet_freq, hpet_period); | |
542 | evt->mult = div_sc((unsigned long) hpet_freq, | |
543 | NSEC_PER_SEC, evt->shift); | |
544 | /* Calculate the max delta */ | |
545 | evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); | |
546 | /* 5 usec minimum reprogramming delta. */ | |
547 | evt->min_delta_ns = 5000; | |
548 | ||
320ab2b0 | 549 | evt->cpumask = cpumask_of(hdev->cpu); |
26afe5f2 | 550 | clockevents_register_device(evt); |
551 | } | |
552 | ||
553 | #ifdef CONFIG_HPET | |
554 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
555 | #define RESERVE_TIMERS 1 | |
556 | #else | |
557 | #define RESERVE_TIMERS 0 | |
558 | #endif | |
5f79f2f2 VP |
559 | |
560 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 561 | { |
562 | unsigned int id; | |
563 | unsigned int num_timers; | |
564 | unsigned int num_timers_used = 0; | |
565 | int i; | |
566 | ||
567 | id = hpet_readl(HPET_ID); | |
568 | ||
569 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
570 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 571 | hpet_print_config(); |
26afe5f2 | 572 | |
573 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
574 | if (!hpet_devs) | |
575 | return; | |
576 | ||
577 | hpet_num_timers = num_timers; | |
578 | ||
579 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
580 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
581 | unsigned long cfg = hpet_readl(HPET_Tn_CFG(i)); | |
582 | ||
583 | /* Only consider HPET timer with MSI support */ | |
584 | if (!(cfg & HPET_TN_FSB_CAP)) | |
585 | continue; | |
586 | ||
587 | hdev->flags = 0; | |
588 | if (cfg & HPET_TN_PERIODIC_CAP) | |
589 | hdev->flags |= HPET_DEV_PERI_CAP; | |
590 | hdev->num = i; | |
591 | ||
592 | sprintf(hdev->name, "hpet%d", i); | |
593 | if (hpet_assign_irq(hdev)) | |
594 | continue; | |
595 | ||
596 | hdev->flags |= HPET_DEV_FSB_CAP; | |
597 | hdev->flags |= HPET_DEV_VALID; | |
598 | num_timers_used++; | |
599 | if (num_timers_used == num_possible_cpus()) | |
600 | break; | |
601 | } | |
602 | ||
603 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
604 | num_timers, num_timers_used); | |
605 | } | |
606 | ||
5f79f2f2 VP |
607 | #ifdef CONFIG_HPET |
608 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
609 | { | |
610 | int i; | |
611 | ||
612 | if (!hpet_devs) | |
613 | return; | |
614 | ||
615 | for (i = 0; i < hpet_num_timers; i++) { | |
616 | struct hpet_dev *hdev = &hpet_devs[i]; | |
617 | ||
618 | if (!(hdev->flags & HPET_DEV_VALID)) | |
619 | continue; | |
620 | ||
621 | hd->hd_irq[hdev->num] = hdev->irq; | |
622 | hpet_reserve_timer(hd, hdev->num); | |
623 | } | |
624 | } | |
625 | #endif | |
626 | ||
26afe5f2 | 627 | static struct hpet_dev *hpet_get_unused_timer(void) |
628 | { | |
629 | int i; | |
630 | ||
631 | if (!hpet_devs) | |
632 | return NULL; | |
633 | ||
634 | for (i = 0; i < hpet_num_timers; i++) { | |
635 | struct hpet_dev *hdev = &hpet_devs[i]; | |
636 | ||
637 | if (!(hdev->flags & HPET_DEV_VALID)) | |
638 | continue; | |
639 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
640 | (unsigned long *)&hdev->flags)) | |
641 | continue; | |
642 | return hdev; | |
643 | } | |
644 | return NULL; | |
645 | } | |
646 | ||
647 | struct hpet_work_struct { | |
648 | struct delayed_work work; | |
649 | struct completion complete; | |
650 | }; | |
651 | ||
652 | static void hpet_work(struct work_struct *w) | |
653 | { | |
654 | struct hpet_dev *hdev; | |
655 | int cpu = smp_processor_id(); | |
656 | struct hpet_work_struct *hpet_work; | |
657 | ||
658 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
659 | ||
660 | hdev = hpet_get_unused_timer(); | |
661 | if (hdev) | |
662 | init_one_hpet_msi_clockevent(hdev, cpu); | |
663 | ||
664 | complete(&hpet_work->complete); | |
665 | } | |
666 | ||
667 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
668 | unsigned long action, void *hcpu) | |
669 | { | |
670 | unsigned long cpu = (unsigned long)hcpu; | |
671 | struct hpet_work_struct work; | |
672 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
673 | ||
674 | switch (action & 0xf) { | |
675 | case CPU_ONLINE: | |
336f6c32 | 676 | INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work); |
26afe5f2 | 677 | init_completion(&work.complete); |
678 | /* FIXME: add schedule_work_on() */ | |
679 | schedule_delayed_work_on(cpu, &work.work, 0); | |
680 | wait_for_completion(&work.complete); | |
336f6c32 | 681 | destroy_timer_on_stack(&work.work.timer); |
26afe5f2 | 682 | break; |
683 | case CPU_DEAD: | |
684 | if (hdev) { | |
685 | free_irq(hdev->irq, hdev); | |
686 | hdev->flags &= ~HPET_DEV_USED; | |
687 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
688 | } | |
689 | break; | |
690 | } | |
691 | return NOTIFY_OK; | |
692 | } | |
693 | #else | |
694 | ||
ba374c9b SN |
695 | static int hpet_setup_msi_irq(unsigned int irq) |
696 | { | |
697 | return 0; | |
698 | } | |
5f79f2f2 VP |
699 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
700 | { | |
701 | return; | |
702 | } | |
703 | ||
704 | #ifdef CONFIG_HPET | |
705 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 706 | { |
707 | return; | |
708 | } | |
5f79f2f2 | 709 | #endif |
26afe5f2 | 710 | |
711 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
712 | unsigned long action, void *hcpu) | |
713 | { | |
714 | return NOTIFY_OK; | |
715 | } | |
716 | ||
717 | #endif | |
718 | ||
6bb74df4 JS |
719 | /* |
720 | * Clock source related code | |
721 | */ | |
722 | static cycle_t read_hpet(void) | |
723 | { | |
724 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
725 | } | |
726 | ||
28769149 TG |
727 | #ifdef CONFIG_X86_64 |
728 | static cycle_t __vsyscall_fn vread_hpet(void) | |
729 | { | |
730 | return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); | |
731 | } | |
732 | #endif | |
733 | ||
6bb74df4 JS |
734 | static struct clocksource clocksource_hpet = { |
735 | .name = "hpet", | |
736 | .rating = 250, | |
737 | .read = read_hpet, | |
738 | .mask = HPET_MASK, | |
739 | .shift = HPET_SHIFT, | |
740 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
59c69f2a | 741 | .resume = hpet_restart_counter, |
28769149 TG |
742 | #ifdef CONFIG_X86_64 |
743 | .vread = vread_hpet, | |
744 | #endif | |
6bb74df4 JS |
745 | }; |
746 | ||
610bf2f1 | 747 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 748 | { |
6fd592da | 749 | u64 start, now; |
075bcd1f | 750 | cycle_t t1; |
e9e2cdb4 | 751 | |
e9e2cdb4 TG |
752 | /* Start the counter */ |
753 | hpet_start_counter(); | |
754 | ||
075bcd1f TG |
755 | /* Verify whether hpet counter works */ |
756 | t1 = read_hpet(); | |
757 | rdtscll(start); | |
758 | ||
759 | /* | |
760 | * We don't know the TSC frequency yet, but waiting for | |
761 | * 200000 TSC cycles is safe: | |
762 | * 4 GHz == 50us | |
763 | * 1 GHz == 200us | |
764 | */ | |
765 | do { | |
766 | rep_nop(); | |
767 | rdtscll(now); | |
768 | } while ((now - start) < 200000UL); | |
769 | ||
770 | if (t1 == read_hpet()) { | |
771 | printk(KERN_WARNING | |
772 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 773 | return -ENODEV; |
075bcd1f TG |
774 | } |
775 | ||
6fd592da CM |
776 | /* |
777 | * The definition of mult is (include/linux/clocksource.h) | |
778 | * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc | |
779 | * so we first need to convert hpet_period to ns/cyc units: | |
780 | * mult/2^shift = ns/cyc = hpet_period/10^6 | |
781 | * mult = (hpet_period * 2^shift)/10^6 | |
782 | * mult = (hpet_period << shift)/FSEC_PER_NSEC | |
6bb74df4 | 783 | */ |
6fd592da | 784 | clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT); |
6bb74df4 JS |
785 | |
786 | clocksource_register(&clocksource_hpet); | |
787 | ||
610bf2f1 VP |
788 | return 0; |
789 | } | |
790 | ||
b02a7f22 PM |
791 | /** |
792 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
793 | */ |
794 | int __init hpet_enable(void) | |
795 | { | |
796 | unsigned long id; | |
a6825f1c | 797 | int i; |
610bf2f1 VP |
798 | |
799 | if (!is_hpet_capable()) | |
800 | return 0; | |
801 | ||
802 | hpet_set_mapping(); | |
803 | ||
804 | /* | |
805 | * Read the period and check for a sane value: | |
806 | */ | |
807 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
808 | |
809 | /* | |
810 | * AMD SB700 based systems with spread spectrum enabled use a | |
811 | * SMM based HPET emulation to provide proper frequency | |
812 | * setting. The SMM code is initialized with the first HPET | |
813 | * register access and takes some time to complete. During | |
814 | * this time the config register reads 0xffffffff. We check | |
815 | * for max. 1000 loops whether the config register reads a non | |
816 | * 0xffffffff value to make sure that HPET is up and running | |
817 | * before we go further. A counting loop is safe, as the HPET | |
818 | * access takes thousands of CPU cycles. On non SB700 based | |
819 | * machines this check is only done once and has no side | |
820 | * effects. | |
821 | */ | |
822 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
823 | if (i == 1000) { | |
824 | printk(KERN_WARNING | |
825 | "HPET config register value = 0xFFFFFFFF. " | |
826 | "Disabling HPET\n"); | |
827 | goto out_nohpet; | |
828 | } | |
829 | } | |
830 | ||
610bf2f1 VP |
831 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
832 | goto out_nohpet; | |
833 | ||
834 | /* | |
835 | * Read the HPET ID register to retrieve the IRQ routing | |
836 | * information and the number of channels | |
837 | */ | |
838 | id = hpet_readl(HPET_ID); | |
b98103a5 | 839 | hpet_print_config(); |
610bf2f1 VP |
840 | |
841 | #ifdef CONFIG_HPET_EMULATE_RTC | |
842 | /* | |
843 | * The legacy routing mode needs at least two channels, tick timer | |
844 | * and the rtc emulation channel. | |
845 | */ | |
846 | if (!(id & HPET_ID_NUMBER)) | |
847 | goto out_nohpet; | |
848 | #endif | |
849 | ||
850 | if (hpet_clocksource_register()) | |
851 | goto out_nohpet; | |
852 | ||
e9e2cdb4 | 853 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 854 | hpet_legacy_clockevent_register(); |
26afe5f2 | 855 | hpet_msi_capability_lookup(2); |
e9e2cdb4 TG |
856 | return 1; |
857 | } | |
26afe5f2 | 858 | hpet_msi_capability_lookup(0); |
e9e2cdb4 | 859 | return 0; |
5d0cf410 | 860 | |
e9e2cdb4 | 861 | out_nohpet: |
06a24dec | 862 | hpet_clear_mapping(); |
bacbe999 | 863 | hpet_address = 0; |
e9e2cdb4 TG |
864 | return 0; |
865 | } | |
866 | ||
28769149 TG |
867 | /* |
868 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
869 | * | |
870 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
871 | * but on x86_64 it is necessary ! | |
872 | */ | |
873 | static __init int hpet_late_init(void) | |
874 | { | |
26afe5f2 | 875 | int cpu; |
876 | ||
59c69f2a | 877 | if (boot_hpet_disable) |
28769149 TG |
878 | return -ENODEV; |
879 | ||
59c69f2a VP |
880 | if (!hpet_address) { |
881 | if (!force_hpet_address) | |
882 | return -ENODEV; | |
883 | ||
884 | hpet_address = force_hpet_address; | |
885 | hpet_enable(); | |
59c69f2a VP |
886 | } |
887 | ||
39c04b55 JF |
888 | if (!hpet_virt_address) |
889 | return -ENODEV; | |
890 | ||
28769149 | 891 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 892 | hpet_print_config(); |
59c69f2a | 893 | |
26afe5f2 | 894 | for_each_online_cpu(cpu) { |
895 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
896 | } | |
897 | ||
898 | /* This notifier should be called after workqueue is ready */ | |
899 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
900 | ||
28769149 TG |
901 | return 0; |
902 | } | |
903 | fs_initcall(hpet_late_init); | |
904 | ||
c86c7fbc OH |
905 | void hpet_disable(void) |
906 | { | |
907 | if (is_hpet_capable()) { | |
908 | unsigned long cfg = hpet_readl(HPET_CFG); | |
909 | ||
910 | if (hpet_legacy_int_enabled) { | |
911 | cfg &= ~HPET_CFG_LEGACY; | |
912 | hpet_legacy_int_enabled = 0; | |
913 | } | |
914 | cfg &= ~HPET_CFG_ENABLE; | |
915 | hpet_writel(cfg, HPET_CFG); | |
916 | } | |
917 | } | |
918 | ||
e9e2cdb4 TG |
919 | #ifdef CONFIG_HPET_EMULATE_RTC |
920 | ||
921 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
922 | * is enabled, we support RTC interrupt functionality in software. | |
923 | * RTC has 3 kinds of interrupts: | |
924 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
925 | * is updated | |
926 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
927 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
928 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
929 | * (1) and (2) above are implemented using polling at a frequency of | |
930 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
931 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
932 | * For (3), we use interrupts at 64Hz or user specified periodic | |
933 | * frequency, whichever is higher. | |
934 | */ | |
935 | #include <linux/mc146818rtc.h> | |
936 | #include <linux/rtc.h> | |
1bdbdaac | 937 | #include <asm/rtc.h> |
e9e2cdb4 TG |
938 | |
939 | #define DEFAULT_RTC_INT_FREQ 64 | |
940 | #define DEFAULT_RTC_SHIFT 6 | |
941 | #define RTC_NUM_INTS 1 | |
942 | ||
943 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 944 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
945 | static struct rtc_time hpet_alarm_time; |
946 | static unsigned long hpet_pie_count; | |
ff08f76d | 947 | static u32 hpet_t1_cmp; |
e9e2cdb4 TG |
948 | static unsigned long hpet_default_delta; |
949 | static unsigned long hpet_pie_delta; | |
950 | static unsigned long hpet_pie_limit; | |
951 | ||
1bdbdaac BW |
952 | static rtc_irq_handler irq_handler; |
953 | ||
ff08f76d PE |
954 | /* |
955 | * Check that the hpet counter c1 is ahead of the c2 | |
956 | */ | |
957 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
958 | { | |
959 | return (s32)(c2 - c1) < 0; | |
960 | } | |
961 | ||
1bdbdaac BW |
962 | /* |
963 | * Registers a IRQ handler. | |
964 | */ | |
965 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
966 | { | |
967 | if (!is_hpet_enabled()) | |
968 | return -ENODEV; | |
969 | if (irq_handler) | |
970 | return -EBUSY; | |
971 | ||
972 | irq_handler = handler; | |
973 | ||
974 | return 0; | |
975 | } | |
976 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
977 | ||
978 | /* | |
979 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
980 | * and does cleanup. | |
981 | */ | |
982 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
983 | { | |
984 | if (!is_hpet_enabled()) | |
985 | return; | |
986 | ||
987 | irq_handler = NULL; | |
988 | hpet_rtc_flags = 0; | |
989 | } | |
990 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
991 | ||
e9e2cdb4 TG |
992 | /* |
993 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
994 | * is not supported by all HPET implementations for timer 1. | |
995 | * | |
996 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
997 | */ | |
998 | int hpet_rtc_timer_init(void) | |
999 | { | |
1000 | unsigned long cfg, cnt, delta, flags; | |
1001 | ||
1002 | if (!is_hpet_enabled()) | |
1003 | return 0; | |
1004 | ||
1005 | if (!hpet_default_delta) { | |
1006 | uint64_t clc; | |
1007 | ||
1008 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1009 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
1010 | hpet_default_delta = (unsigned long) clc; | |
1011 | } | |
1012 | ||
1013 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1014 | delta = hpet_default_delta; | |
1015 | else | |
1016 | delta = hpet_pie_delta; | |
1017 | ||
1018 | local_irq_save(flags); | |
1019 | ||
1020 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1021 | hpet_writel(cnt, HPET_T1_CMP); | |
1022 | hpet_t1_cmp = cnt; | |
1023 | ||
1024 | cfg = hpet_readl(HPET_T1_CFG); | |
1025 | cfg &= ~HPET_TN_PERIODIC; | |
1026 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1027 | hpet_writel(cfg, HPET_T1_CFG); | |
1028 | ||
1029 | local_irq_restore(flags); | |
1030 | ||
1031 | return 1; | |
1032 | } | |
1bdbdaac | 1033 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
1034 | |
1035 | /* | |
1036 | * The functions below are called from rtc driver. | |
1037 | * Return 0 if HPET is not being used. | |
1038 | * Otherwise do the necessary changes and return 1. | |
1039 | */ | |
1040 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1041 | { | |
1042 | if (!is_hpet_enabled()) | |
1043 | return 0; | |
1044 | ||
1045 | hpet_rtc_flags &= ~bit_mask; | |
1046 | return 1; | |
1047 | } | |
1bdbdaac | 1048 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1049 | |
1050 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1051 | { | |
1052 | unsigned long oldbits = hpet_rtc_flags; | |
1053 | ||
1054 | if (!is_hpet_enabled()) | |
1055 | return 0; | |
1056 | ||
1057 | hpet_rtc_flags |= bit_mask; | |
1058 | ||
7e2a31da DB |
1059 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1060 | hpet_prev_update_sec = -1; | |
1061 | ||
e9e2cdb4 TG |
1062 | if (!oldbits) |
1063 | hpet_rtc_timer_init(); | |
1064 | ||
1065 | return 1; | |
1066 | } | |
1bdbdaac | 1067 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1068 | |
1069 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1070 | unsigned char sec) | |
1071 | { | |
1072 | if (!is_hpet_enabled()) | |
1073 | return 0; | |
1074 | ||
1075 | hpet_alarm_time.tm_hour = hrs; | |
1076 | hpet_alarm_time.tm_min = min; | |
1077 | hpet_alarm_time.tm_sec = sec; | |
1078 | ||
1079 | return 1; | |
1080 | } | |
1bdbdaac | 1081 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1082 | |
1083 | int hpet_set_periodic_freq(unsigned long freq) | |
1084 | { | |
1085 | uint64_t clc; | |
1086 | ||
1087 | if (!is_hpet_enabled()) | |
1088 | return 0; | |
1089 | ||
1090 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1091 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1092 | else { | |
1093 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1094 | do_div(clc, freq); | |
1095 | clc >>= hpet_clockevent.shift; | |
1096 | hpet_pie_delta = (unsigned long) clc; | |
1097 | } | |
1098 | return 1; | |
1099 | } | |
1bdbdaac | 1100 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1101 | |
1102 | int hpet_rtc_dropped_irq(void) | |
1103 | { | |
1104 | return is_hpet_enabled(); | |
1105 | } | |
1bdbdaac | 1106 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1107 | |
1108 | static void hpet_rtc_timer_reinit(void) | |
1109 | { | |
1110 | unsigned long cfg, delta; | |
1111 | int lost_ints = -1; | |
1112 | ||
1113 | if (unlikely(!hpet_rtc_flags)) { | |
1114 | cfg = hpet_readl(HPET_T1_CFG); | |
1115 | cfg &= ~HPET_TN_ENABLE; | |
1116 | hpet_writel(cfg, HPET_T1_CFG); | |
1117 | return; | |
1118 | } | |
1119 | ||
1120 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1121 | delta = hpet_default_delta; | |
1122 | else | |
1123 | delta = hpet_pie_delta; | |
1124 | ||
1125 | /* | |
1126 | * Increment the comparator value until we are ahead of the | |
1127 | * current count. | |
1128 | */ | |
1129 | do { | |
1130 | hpet_t1_cmp += delta; | |
1131 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1132 | lost_ints++; | |
ff08f76d | 1133 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1134 | |
1135 | if (lost_ints) { | |
1136 | if (hpet_rtc_flags & RTC_PIE) | |
1137 | hpet_pie_count += lost_ints; | |
1138 | if (printk_ratelimit()) | |
7e2a31da | 1139 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1140 | lost_ints); |
1141 | } | |
1142 | } | |
1143 | ||
1144 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1145 | { | |
1146 | struct rtc_time curr_time; | |
1147 | unsigned long rtc_int_flag = 0; | |
1148 | ||
1149 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1150 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1151 | |
1152 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1153 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1154 | |
1155 | if (hpet_rtc_flags & RTC_UIE && | |
1156 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1157 | if (hpet_prev_update_sec >= 0) |
1158 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1159 | hpet_prev_update_sec = curr_time.tm_sec; |
1160 | } | |
1161 | ||
1162 | if (hpet_rtc_flags & RTC_PIE && | |
1163 | ++hpet_pie_count >= hpet_pie_limit) { | |
1164 | rtc_int_flag |= RTC_PF; | |
1165 | hpet_pie_count = 0; | |
1166 | } | |
1167 | ||
8ee291f8 | 1168 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1169 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1170 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1171 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1172 | rtc_int_flag |= RTC_AF; | |
1173 | ||
1174 | if (rtc_int_flag) { | |
1175 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1176 | if (irq_handler) |
1177 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1178 | } |
1179 | return IRQ_HANDLED; | |
1180 | } | |
1bdbdaac | 1181 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1182 | #endif |