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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 | 3 | #include <linux/interrupt.h> |
69c60c88 | 4 | #include <linux/export.h> |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 | 6 | #include <linux/errno.h> |
334955ef | 7 | #include <linux/i8253.h> |
5a0e3ad6 | 8 | #include <linux/slab.h> |
5d0cf410 JS |
9 | #include <linux/hpet.h> |
10 | #include <linux/init.h> | |
58ac1e76 | 11 | #include <linux/cpu.h> |
4588c1f0 IM |
12 | #include <linux/pm.h> |
13 | #include <linux/io.h> | |
5d0cf410 | 14 | |
d746d1eb | 15 | #include <asm/irqdomain.h> |
28769149 | 16 | #include <asm/fixmap.h> |
4588c1f0 | 17 | #include <asm/hpet.h> |
16f871bc | 18 | #include <asm/time.h> |
5d0cf410 | 19 | |
4588c1f0 | 20 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 21 | |
b10db7f0 PM |
22 | /* FSEC = 10^-15 |
23 | NSEC = 10^-9 */ | |
4588c1f0 | 24 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 25 | |
26afe5f2 | 26 | #define HPET_DEV_USED_BIT 2 |
27 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
28 | #define HPET_DEV_VALID 0x8 | |
29 | #define HPET_DEV_FSB_CAP 0x1000 | |
30 | #define HPET_DEV_PERI_CAP 0x2000 | |
31 | ||
f1c18071 TG |
32 | #define HPET_MIN_CYCLES 128 |
33 | #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) | |
34 | ||
e9e2cdb4 TG |
35 | /* |
36 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
37 | */ | |
4588c1f0 | 38 | unsigned long hpet_address; |
c8bc6f3c | 39 | u8 hpet_blockid; /* OS timer block num */ |
73472a46 PV |
40 | u8 hpet_msi_disable; |
41 | ||
e951e4af | 42 | #ifdef CONFIG_PCI_MSI |
3b71e9e3 | 43 | static unsigned long hpet_num_timers; |
e951e4af | 44 | #endif |
4588c1f0 | 45 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 46 | |
58ac1e76 | 47 | struct hpet_dev { |
4588c1f0 IM |
48 | struct clock_event_device evt; |
49 | unsigned int num; | |
50 | int cpu; | |
51 | unsigned int irq; | |
52 | unsigned int flags; | |
53 | char name[10]; | |
58ac1e76 | 54 | }; |
55 | ||
3f7787b3 FW |
56 | inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev) |
57 | { | |
58 | return container_of(evtdev, struct hpet_dev, evt); | |
59 | } | |
60 | ||
5946fa3d | 61 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
62 | { |
63 | return readl(hpet_virt_address + a); | |
64 | } | |
65 | ||
5946fa3d | 66 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
67 | { |
68 | writel(d, hpet_virt_address + a); | |
69 | } | |
70 | ||
28769149 | 71 | #ifdef CONFIG_X86_64 |
28769149 | 72 | #include <asm/pgtable.h> |
2387ce57 | 73 | #endif |
28769149 | 74 | |
06a24dec TG |
75 | static inline void hpet_set_mapping(void) |
76 | { | |
77 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
78 | } | |
79 | ||
80 | static inline void hpet_clear_mapping(void) | |
81 | { | |
82 | iounmap(hpet_virt_address); | |
83 | hpet_virt_address = NULL; | |
84 | } | |
85 | ||
e9e2cdb4 TG |
86 | /* |
87 | * HPET command line enable / disable | |
88 | */ | |
f10f383d | 89 | int boot_hpet_disable; |
b17530bd | 90 | int hpet_force_user; |
b98103a5 | 91 | static int hpet_verbose; |
e9e2cdb4 | 92 | |
4588c1f0 | 93 | static int __init hpet_setup(char *str) |
e9e2cdb4 | 94 | { |
b2d6aba9 JB |
95 | while (str) { |
96 | char *next = strchr(str, ','); | |
97 | ||
98 | if (next) | |
99 | *next++ = 0; | |
e9e2cdb4 TG |
100 | if (!strncmp("disable", str, 7)) |
101 | boot_hpet_disable = 1; | |
b17530bd TG |
102 | if (!strncmp("force", str, 5)) |
103 | hpet_force_user = 1; | |
b98103a5 AH |
104 | if (!strncmp("verbose", str, 7)) |
105 | hpet_verbose = 1; | |
b2d6aba9 | 106 | str = next; |
e9e2cdb4 TG |
107 | } |
108 | return 1; | |
109 | } | |
110 | __setup("hpet=", hpet_setup); | |
111 | ||
28769149 TG |
112 | static int __init disable_hpet(char *str) |
113 | { | |
114 | boot_hpet_disable = 1; | |
115 | return 1; | |
116 | } | |
117 | __setup("nohpet", disable_hpet); | |
118 | ||
e9e2cdb4 TG |
119 | static inline int is_hpet_capable(void) |
120 | { | |
4588c1f0 | 121 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
122 | } |
123 | ||
124 | /* | |
125 | * HPET timer interrupt enable / disable | |
126 | */ | |
127 | static int hpet_legacy_int_enabled; | |
128 | ||
129 | /** | |
130 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
131 | */ | |
132 | int is_hpet_enabled(void) | |
133 | { | |
134 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
135 | } | |
1bdbdaac | 136 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 137 | |
b98103a5 AH |
138 | static void _hpet_print_config(const char *function, int line) |
139 | { | |
140 | u32 i, timers, l, h; | |
141 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
142 | l = hpet_readl(HPET_ID); | |
143 | h = hpet_readl(HPET_PERIOD); | |
144 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
145 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
146 | l = hpet_readl(HPET_CFG); | |
147 | h = hpet_readl(HPET_STATUS); | |
148 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
149 | l = hpet_readl(HPET_COUNTER); | |
150 | h = hpet_readl(HPET_COUNTER+4); | |
151 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
152 | ||
153 | for (i = 0; i < timers; i++) { | |
154 | l = hpet_readl(HPET_Tn_CFG(i)); | |
155 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
156 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
157 | i, l, h); | |
158 | l = hpet_readl(HPET_Tn_CMP(i)); | |
159 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
160 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
161 | i, l, h); | |
162 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
163 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
164 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
165 | i, l, h); | |
166 | } | |
167 | } | |
168 | ||
169 | #define hpet_print_config() \ | |
170 | do { \ | |
171 | if (hpet_verbose) \ | |
02f1f217 | 172 | _hpet_print_config(__func__, __LINE__); \ |
b98103a5 AH |
173 | } while (0) |
174 | ||
e9e2cdb4 TG |
175 | /* |
176 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
177 | * timer 0 and timer 1 in case of RTC emulation. | |
178 | */ | |
179 | #ifdef CONFIG_HPET | |
f0ed4e69 | 180 | |
5f79f2f2 | 181 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 182 | |
5946fa3d | 183 | static void hpet_reserve_platform_timers(unsigned int id) |
e9e2cdb4 TG |
184 | { |
185 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
186 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
187 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
188 | struct hpet_data hd; |
189 | ||
190 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
191 | ||
4588c1f0 IM |
192 | memset(&hd, 0, sizeof(hd)); |
193 | hd.hd_phys_address = hpet_address; | |
194 | hd.hd_address = hpet; | |
195 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
196 | hpet_reserve_timer(&hd, 0); |
197 | ||
198 | #ifdef CONFIG_HPET_EMULATE_RTC | |
199 | hpet_reserve_timer(&hd, 1); | |
200 | #endif | |
5761d64b | 201 | |
64a76f66 DB |
202 | /* |
203 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
204 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
205 | * don't bother configuring *any* comparator interrupts. | |
206 | */ | |
e9e2cdb4 TG |
207 | hd.hd_irq[0] = HPET_LEGACY_8254; |
208 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
209 | ||
fc3fbc45 | 210 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
211 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
212 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 213 | } |
5761d64b | 214 | |
f0ed4e69 | 215 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 216 | |
e9e2cdb4 | 217 | hpet_alloc(&hd); |
5761d64b | 218 | |
e9e2cdb4 TG |
219 | } |
220 | #else | |
5946fa3d | 221 | static void hpet_reserve_platform_timers(unsigned int id) { } |
e9e2cdb4 TG |
222 | #endif |
223 | ||
224 | /* | |
225 | * Common hpet info | |
226 | */ | |
ab0e08f1 | 227 | static unsigned long hpet_freq; |
e9e2cdb4 | 228 | |
610bf2f1 | 229 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 230 | struct clock_event_device *evt); |
610bf2f1 | 231 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
232 | struct clock_event_device *evt); |
233 | ||
234 | /* | |
235 | * The hpet clock event device | |
236 | */ | |
237 | static struct clock_event_device hpet_clockevent = { | |
238 | .name = "hpet", | |
239 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
240 | .set_mode = hpet_legacy_set_mode, |
241 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 | 242 | .irq = 0, |
59c69f2a | 243 | .rating = 50, |
e9e2cdb4 TG |
244 | }; |
245 | ||
8d6f0c82 | 246 | static void hpet_stop_counter(void) |
e9e2cdb4 TG |
247 | { |
248 | unsigned long cfg = hpet_readl(HPET_CFG); | |
e9e2cdb4 TG |
249 | cfg &= ~HPET_CFG_ENABLE; |
250 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
251 | } |
252 | ||
253 | static void hpet_reset_counter(void) | |
254 | { | |
e9e2cdb4 TG |
255 | hpet_writel(0, HPET_COUNTER); |
256 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
257 | } |
258 | ||
259 | static void hpet_start_counter(void) | |
260 | { | |
5946fa3d | 261 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
262 | cfg |= HPET_CFG_ENABLE; |
263 | hpet_writel(cfg, HPET_CFG); | |
264 | } | |
265 | ||
8d6f0c82 AH |
266 | static void hpet_restart_counter(void) |
267 | { | |
268 | hpet_stop_counter(); | |
7a6f9cbb | 269 | hpet_reset_counter(); |
8d6f0c82 AH |
270 | hpet_start_counter(); |
271 | } | |
272 | ||
59c69f2a VP |
273 | static void hpet_resume_device(void) |
274 | { | |
bfe0c1cc | 275 | force_hpet_resume(); |
59c69f2a VP |
276 | } |
277 | ||
17622339 | 278 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
279 | { |
280 | hpet_resume_device(); | |
8d6f0c82 | 281 | hpet_restart_counter(); |
59c69f2a VP |
282 | } |
283 | ||
610bf2f1 | 284 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 285 | { |
5946fa3d | 286 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
287 | |
288 | cfg |= HPET_CFG_LEGACY; | |
289 | hpet_writel(cfg, HPET_CFG); | |
290 | hpet_legacy_int_enabled = 1; | |
291 | } | |
292 | ||
610bf2f1 VP |
293 | static void hpet_legacy_clockevent_register(void) |
294 | { | |
610bf2f1 VP |
295 | /* Start HPET legacy interrupts */ |
296 | hpet_enable_legacy_int(); | |
297 | ||
610bf2f1 VP |
298 | /* |
299 | * Start hpet with the boot cpu mask and make it | |
300 | * global after the IO_APIC has been initialized. | |
301 | */ | |
320ab2b0 | 302 | hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); |
ab0e08f1 TG |
303 | clockevents_config_and_register(&hpet_clockevent, hpet_freq, |
304 | HPET_MIN_PROG_DELTA, 0x7FFFFFFF); | |
610bf2f1 VP |
305 | global_clock_event = &hpet_clockevent; |
306 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
307 | } | |
308 | ||
b40d575b | 309 | static void hpet_set_mode(enum clock_event_mode mode, |
310 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 311 | { |
5946fa3d | 312 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
313 | uint64_t delta; |
314 | ||
4588c1f0 | 315 | switch (mode) { |
e9e2cdb4 | 316 | case CLOCK_EVT_MODE_PERIODIC: |
c23e253e | 317 | hpet_stop_counter(); |
b40d575b | 318 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
319 | delta >>= evt->shift; | |
7a6f9cbb | 320 | now = hpet_readl(HPET_COUNTER); |
5946fa3d | 321 | cmp = now + (unsigned int) delta; |
b40d575b | 322 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
323 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
324 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 325 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
7a6f9cbb AH |
326 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
327 | udelay(1); | |
328 | /* | |
329 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
330 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
331 | * bit is automatically cleared after the first write. | |
332 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
333 | * Publication # 24674) | |
334 | */ | |
5946fa3d | 335 | hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer)); |
c23e253e | 336 | hpet_start_counter(); |
b98103a5 | 337 | hpet_print_config(); |
e9e2cdb4 TG |
338 | break; |
339 | ||
340 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 341 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
342 | cfg &= ~HPET_TN_PERIODIC; |
343 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 344 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
345 | break; |
346 | ||
347 | case CLOCK_EVT_MODE_UNUSED: | |
348 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 349 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 350 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 351 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 352 | break; |
18de5bc4 TG |
353 | |
354 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 355 | if (timer == 0) { |
356 | hpet_enable_legacy_int(); | |
357 | } else { | |
358 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
3cb96f0c | 359 | irq_domain_activate_irq(irq_get_irq_data(hdev->irq)); |
26afe5f2 | 360 | disable_irq(hdev->irq); |
0de26520 | 361 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
26afe5f2 | 362 | enable_irq(hdev->irq); |
363 | } | |
b98103a5 | 364 | hpet_print_config(); |
18de5bc4 | 365 | break; |
e9e2cdb4 TG |
366 | } |
367 | } | |
368 | ||
b40d575b | 369 | static int hpet_next_event(unsigned long delta, |
370 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 371 | { |
f7676254 | 372 | u32 cnt; |
995bd3bb | 373 | s32 res; |
e9e2cdb4 TG |
374 | |
375 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 376 | cnt += (u32) delta; |
b40d575b | 377 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 378 | |
72d43d9b | 379 | /* |
995bd3bb TG |
380 | * HPETs are a complete disaster. The compare register is |
381 | * based on a equal comparison and neither provides a less | |
382 | * than or equal functionality (which would require to take | |
383 | * the wraparound into account) nor a simple count down event | |
384 | * mode. Further the write to the comparator register is | |
385 | * delayed internally up to two HPET clock cycles in certain | |
f1c18071 TG |
386 | * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even |
387 | * longer delays. We worked around that by reading back the | |
388 | * compare register, but that required another workaround for | |
389 | * ICH9,10 chips where the first readout after write can | |
390 | * return the old stale value. We already had a minimum | |
391 | * programming delta of 5us enforced, but a NMI or SMI hitting | |
995bd3bb TG |
392 | * between the counter readout and the comparator write can |
393 | * move us behind that point easily. Now instead of reading | |
394 | * the compare register back several times, we make the ETIME | |
395 | * decision based on the following: Return ETIME if the | |
f1c18071 | 396 | * counter value after the write is less than HPET_MIN_CYCLES |
995bd3bb | 397 | * away from the event or if the counter is already ahead of |
f1c18071 TG |
398 | * the event. The minimum programming delta for the generic |
399 | * clockevents code is set to 1.5 * HPET_MIN_CYCLES. | |
72d43d9b | 400 | */ |
995bd3bb | 401 | res = (s32)(cnt - hpet_readl(HPET_COUNTER)); |
72d43d9b | 402 | |
f1c18071 | 403 | return res < HPET_MIN_CYCLES ? -ETIME : 0; |
e9e2cdb4 TG |
404 | } |
405 | ||
b40d575b | 406 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
407 | struct clock_event_device *evt) | |
408 | { | |
409 | hpet_set_mode(mode, evt, 0); | |
410 | } | |
411 | ||
412 | static int hpet_legacy_next_event(unsigned long delta, | |
413 | struct clock_event_device *evt) | |
414 | { | |
415 | return hpet_next_event(delta, evt, 0); | |
416 | } | |
417 | ||
58ac1e76 | 418 | /* |
419 | * HPET MSI Support | |
420 | */ | |
26afe5f2 | 421 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
422 | |
423 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
424 | static struct hpet_dev *hpet_devs; | |
3cb96f0c | 425 | static struct irq_domain *hpet_domain; |
5f79f2f2 | 426 | |
d0fbca8f | 427 | void hpet_msi_unmask(struct irq_data *data) |
58ac1e76 | 428 | { |
d0fbca8f | 429 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 430 | unsigned int cfg; |
58ac1e76 | 431 | |
432 | /* unmask it */ | |
433 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
6acf5a8c | 434 | cfg |= HPET_TN_ENABLE | HPET_TN_FSB; |
58ac1e76 | 435 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); |
436 | } | |
437 | ||
d0fbca8f | 438 | void hpet_msi_mask(struct irq_data *data) |
58ac1e76 | 439 | { |
d0fbca8f | 440 | struct hpet_dev *hdev = data->handler_data; |
5946fa3d | 441 | unsigned int cfg; |
58ac1e76 | 442 | |
443 | /* mask it */ | |
444 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
6acf5a8c | 445 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); |
58ac1e76 | 446 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); |
447 | } | |
448 | ||
d0fbca8f | 449 | void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 450 | { |
58ac1e76 | 451 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); |
452 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
453 | } | |
454 | ||
d0fbca8f | 455 | void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 456 | { |
58ac1e76 | 457 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); |
458 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
459 | msg->address_hi = 0; | |
460 | } | |
461 | ||
26afe5f2 | 462 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
463 | struct clock_event_device *evt) | |
464 | { | |
465 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
466 | hpet_set_mode(mode, evt, hdev->num); | |
467 | } | |
468 | ||
469 | static int hpet_msi_next_event(unsigned long delta, | |
470 | struct clock_event_device *evt) | |
471 | { | |
472 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
473 | return hpet_next_event(delta, evt, hdev->num); | |
474 | } | |
475 | ||
26afe5f2 | 476 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) |
477 | { | |
478 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
479 | struct clock_event_device *hevt = &dev->evt; | |
480 | ||
481 | if (!hevt->event_handler) { | |
482 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
483 | dev->num); | |
484 | return IRQ_HANDLED; | |
485 | } | |
486 | ||
487 | hevt->event_handler(hevt); | |
488 | return IRQ_HANDLED; | |
489 | } | |
490 | ||
491 | static int hpet_setup_irq(struct hpet_dev *dev) | |
492 | { | |
493 | ||
494 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
d20d2efb | 495 | IRQF_TIMER | IRQF_NOBALANCING, |
507fa3a3 | 496 | dev->name, dev)) |
26afe5f2 | 497 | return -1; |
498 | ||
499 | disable_irq(dev->irq); | |
0de26520 | 500 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 501 | enable_irq(dev->irq); |
502 | ||
c81bba49 YL |
503 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
504 | dev->name, dev->irq); | |
505 | ||
26afe5f2 | 506 | return 0; |
507 | } | |
508 | ||
509 | /* This should be called in specific @cpu */ | |
510 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
511 | { | |
512 | struct clock_event_device *evt = &hdev->evt; | |
26afe5f2 | 513 | |
514 | WARN_ON(cpu != smp_processor_id()); | |
515 | if (!(hdev->flags & HPET_DEV_VALID)) | |
516 | return; | |
517 | ||
26afe5f2 | 518 | hdev->cpu = cpu; |
519 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
520 | evt->name = hdev->name; | |
521 | hpet_setup_irq(hdev); | |
522 | evt->irq = hdev->irq; | |
523 | ||
524 | evt->rating = 110; | |
525 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
526 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
527 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
528 | ||
529 | evt->set_mode = hpet_msi_set_mode; | |
530 | evt->set_next_event = hpet_msi_next_event; | |
320ab2b0 | 531 | evt->cpumask = cpumask_of(hdev->cpu); |
ab0e08f1 TG |
532 | |
533 | clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, | |
534 | 0x7FFFFFFF); | |
26afe5f2 | 535 | } |
536 | ||
537 | #ifdef CONFIG_HPET | |
538 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
539 | #define RESERVE_TIMERS 1 | |
540 | #else | |
541 | #define RESERVE_TIMERS 0 | |
542 | #endif | |
5f79f2f2 VP |
543 | |
544 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 545 | { |
546 | unsigned int id; | |
547 | unsigned int num_timers; | |
548 | unsigned int num_timers_used = 0; | |
3cb96f0c | 549 | int i, irq; |
26afe5f2 | 550 | |
73472a46 PV |
551 | if (hpet_msi_disable) |
552 | return; | |
553 | ||
39fe05e5 SL |
554 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
555 | return; | |
26afe5f2 | 556 | id = hpet_readl(HPET_ID); |
557 | ||
558 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
559 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 560 | hpet_print_config(); |
26afe5f2 | 561 | |
3cb96f0c JL |
562 | hpet_domain = hpet_create_irq_domain(hpet_blockid); |
563 | if (!hpet_domain) | |
564 | return; | |
565 | ||
26afe5f2 | 566 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); |
567 | if (!hpet_devs) | |
568 | return; | |
569 | ||
570 | hpet_num_timers = num_timers; | |
571 | ||
572 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
573 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
5946fa3d | 574 | unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); |
26afe5f2 | 575 | |
576 | /* Only consider HPET timer with MSI support */ | |
577 | if (!(cfg & HPET_TN_FSB_CAP)) | |
578 | continue; | |
579 | ||
cb17b2a6 TG |
580 | hdev->flags = 0; |
581 | if (cfg & HPET_TN_PERIODIC_CAP) | |
582 | hdev->flags |= HPET_DEV_PERI_CAP; | |
583 | sprintf(hdev->name, "hpet%d", i); | |
584 | hdev->num = i; | |
585 | ||
3cb96f0c | 586 | irq = hpet_assign_irq(hpet_domain, hdev, hdev->num); |
bafac298 | 587 | if (irq <= 0) |
3cb96f0c JL |
588 | continue; |
589 | ||
3cb96f0c | 590 | hdev->irq = irq; |
26afe5f2 | 591 | hdev->flags |= HPET_DEV_FSB_CAP; |
592 | hdev->flags |= HPET_DEV_VALID; | |
593 | num_timers_used++; | |
594 | if (num_timers_used == num_possible_cpus()) | |
595 | break; | |
596 | } | |
597 | ||
598 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
599 | num_timers, num_timers_used); | |
600 | } | |
601 | ||
5f79f2f2 VP |
602 | #ifdef CONFIG_HPET |
603 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
604 | { | |
605 | int i; | |
606 | ||
607 | if (!hpet_devs) | |
608 | return; | |
609 | ||
610 | for (i = 0; i < hpet_num_timers; i++) { | |
611 | struct hpet_dev *hdev = &hpet_devs[i]; | |
612 | ||
613 | if (!(hdev->flags & HPET_DEV_VALID)) | |
614 | continue; | |
615 | ||
616 | hd->hd_irq[hdev->num] = hdev->irq; | |
617 | hpet_reserve_timer(hd, hdev->num); | |
618 | } | |
619 | } | |
620 | #endif | |
621 | ||
26afe5f2 | 622 | static struct hpet_dev *hpet_get_unused_timer(void) |
623 | { | |
624 | int i; | |
625 | ||
626 | if (!hpet_devs) | |
627 | return NULL; | |
628 | ||
629 | for (i = 0; i < hpet_num_timers; i++) { | |
630 | struct hpet_dev *hdev = &hpet_devs[i]; | |
631 | ||
632 | if (!(hdev->flags & HPET_DEV_VALID)) | |
633 | continue; | |
634 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
635 | (unsigned long *)&hdev->flags)) | |
636 | continue; | |
637 | return hdev; | |
638 | } | |
639 | return NULL; | |
640 | } | |
641 | ||
642 | struct hpet_work_struct { | |
643 | struct delayed_work work; | |
644 | struct completion complete; | |
645 | }; | |
646 | ||
647 | static void hpet_work(struct work_struct *w) | |
648 | { | |
649 | struct hpet_dev *hdev; | |
650 | int cpu = smp_processor_id(); | |
651 | struct hpet_work_struct *hpet_work; | |
652 | ||
653 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
654 | ||
655 | hdev = hpet_get_unused_timer(); | |
656 | if (hdev) | |
657 | init_one_hpet_msi_clockevent(hdev, cpu); | |
658 | ||
659 | complete(&hpet_work->complete); | |
660 | } | |
661 | ||
662 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
663 | unsigned long action, void *hcpu) | |
664 | { | |
665 | unsigned long cpu = (unsigned long)hcpu; | |
666 | struct hpet_work_struct work; | |
667 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
668 | ||
669 | switch (action & 0xf) { | |
670 | case CPU_ONLINE: | |
ca1cab37 | 671 | INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); |
26afe5f2 | 672 | init_completion(&work.complete); |
673 | /* FIXME: add schedule_work_on() */ | |
674 | schedule_delayed_work_on(cpu, &work.work, 0); | |
675 | wait_for_completion(&work.complete); | |
b712c8da | 676 | destroy_delayed_work_on_stack(&work.work); |
26afe5f2 | 677 | break; |
678 | case CPU_DEAD: | |
679 | if (hdev) { | |
680 | free_irq(hdev->irq, hdev); | |
681 | hdev->flags &= ~HPET_DEV_USED; | |
682 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
683 | } | |
684 | break; | |
685 | } | |
686 | return NOTIFY_OK; | |
687 | } | |
688 | #else | |
689 | ||
5f79f2f2 VP |
690 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
691 | { | |
692 | return; | |
693 | } | |
694 | ||
695 | #ifdef CONFIG_HPET | |
696 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 697 | { |
698 | return; | |
699 | } | |
5f79f2f2 | 700 | #endif |
26afe5f2 | 701 | |
702 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
703 | unsigned long action, void *hcpu) | |
704 | { | |
705 | return NOTIFY_OK; | |
706 | } | |
707 | ||
708 | #endif | |
709 | ||
6bb74df4 JS |
710 | /* |
711 | * Clock source related code | |
712 | */ | |
8e19608e | 713 | static cycle_t read_hpet(struct clocksource *cs) |
6bb74df4 JS |
714 | { |
715 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
716 | } | |
717 | ||
718 | static struct clocksource clocksource_hpet = { | |
719 | .name = "hpet", | |
720 | .rating = 250, | |
721 | .read = read_hpet, | |
722 | .mask = HPET_MASK, | |
6bb74df4 | 723 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8d6f0c82 | 724 | .resume = hpet_resume_counter, |
98d0ac38 | 725 | .archdata = { .vclock_mode = VCLOCK_HPET }, |
6bb74df4 JS |
726 | }; |
727 | ||
610bf2f1 | 728 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 729 | { |
6fd592da | 730 | u64 start, now; |
075bcd1f | 731 | cycle_t t1; |
e9e2cdb4 | 732 | |
e9e2cdb4 | 733 | /* Start the counter */ |
8d6f0c82 | 734 | hpet_restart_counter(); |
e9e2cdb4 | 735 | |
075bcd1f | 736 | /* Verify whether hpet counter works */ |
8e19608e | 737 | t1 = hpet_readl(HPET_COUNTER); |
4ea1636b | 738 | start = rdtsc(); |
075bcd1f TG |
739 | |
740 | /* | |
741 | * We don't know the TSC frequency yet, but waiting for | |
742 | * 200000 TSC cycles is safe: | |
743 | * 4 GHz == 50us | |
744 | * 1 GHz == 200us | |
745 | */ | |
746 | do { | |
747 | rep_nop(); | |
4ea1636b | 748 | now = rdtsc(); |
075bcd1f TG |
749 | } while ((now - start) < 200000UL); |
750 | ||
8e19608e | 751 | if (t1 == hpet_readl(HPET_COUNTER)) { |
075bcd1f TG |
752 | printk(KERN_WARNING |
753 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 754 | return -ENODEV; |
075bcd1f TG |
755 | } |
756 | ||
f12a15be | 757 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); |
610bf2f1 VP |
758 | return 0; |
759 | } | |
760 | ||
396e2c6f JB |
761 | static u32 *hpet_boot_cfg; |
762 | ||
b02a7f22 PM |
763 | /** |
764 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
765 | */ |
766 | int __init hpet_enable(void) | |
767 | { | |
396e2c6f | 768 | u32 hpet_period, cfg, id; |
ab0e08f1 | 769 | u64 freq; |
396e2c6f | 770 | unsigned int i, last; |
610bf2f1 VP |
771 | |
772 | if (!is_hpet_capable()) | |
773 | return 0; | |
774 | ||
775 | hpet_set_mapping(); | |
776 | ||
777 | /* | |
778 | * Read the period and check for a sane value: | |
779 | */ | |
780 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
781 | |
782 | /* | |
783 | * AMD SB700 based systems with spread spectrum enabled use a | |
784 | * SMM based HPET emulation to provide proper frequency | |
785 | * setting. The SMM code is initialized with the first HPET | |
786 | * register access and takes some time to complete. During | |
787 | * this time the config register reads 0xffffffff. We check | |
788 | * for max. 1000 loops whether the config register reads a non | |
789 | * 0xffffffff value to make sure that HPET is up and running | |
790 | * before we go further. A counting loop is safe, as the HPET | |
791 | * access takes thousands of CPU cycles. On non SB700 based | |
792 | * machines this check is only done once and has no side | |
793 | * effects. | |
794 | */ | |
795 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
796 | if (i == 1000) { | |
797 | printk(KERN_WARNING | |
798 | "HPET config register value = 0xFFFFFFFF. " | |
799 | "Disabling HPET\n"); | |
800 | goto out_nohpet; | |
801 | } | |
802 | } | |
803 | ||
610bf2f1 VP |
804 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
805 | goto out_nohpet; | |
806 | ||
ab0e08f1 TG |
807 | /* |
808 | * The period is a femto seconds value. Convert it to a | |
809 | * frequency. | |
810 | */ | |
811 | freq = FSEC_PER_SEC; | |
812 | do_div(freq, hpet_period); | |
813 | hpet_freq = freq; | |
814 | ||
610bf2f1 VP |
815 | /* |
816 | * Read the HPET ID register to retrieve the IRQ routing | |
817 | * information and the number of channels | |
818 | */ | |
819 | id = hpet_readl(HPET_ID); | |
b98103a5 | 820 | hpet_print_config(); |
610bf2f1 | 821 | |
396e2c6f JB |
822 | last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; |
823 | ||
610bf2f1 VP |
824 | #ifdef CONFIG_HPET_EMULATE_RTC |
825 | /* | |
826 | * The legacy routing mode needs at least two channels, tick timer | |
827 | * and the rtc emulation channel. | |
828 | */ | |
396e2c6f | 829 | if (!last) |
610bf2f1 VP |
830 | goto out_nohpet; |
831 | #endif | |
832 | ||
396e2c6f JB |
833 | cfg = hpet_readl(HPET_CFG); |
834 | hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg), | |
835 | GFP_KERNEL); | |
836 | if (hpet_boot_cfg) | |
837 | *hpet_boot_cfg = cfg; | |
838 | else | |
839 | pr_warn("HPET initial state will not be saved\n"); | |
840 | cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); | |
1b38a3a1 | 841 | hpet_writel(cfg, HPET_CFG); |
396e2c6f JB |
842 | if (cfg) |
843 | pr_warn("HPET: Unrecognized bits %#x set in global cfg\n", | |
844 | cfg); | |
845 | ||
846 | for (i = 0; i <= last; ++i) { | |
847 | cfg = hpet_readl(HPET_Tn_CFG(i)); | |
848 | if (hpet_boot_cfg) | |
849 | hpet_boot_cfg[i + 1] = cfg; | |
850 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); | |
851 | hpet_writel(cfg, HPET_Tn_CFG(i)); | |
852 | cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP | |
853 | | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE | |
854 | | HPET_TN_FSB | HPET_TN_FSB_CAP); | |
855 | if (cfg) | |
856 | pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n", | |
857 | cfg, i); | |
858 | } | |
859 | hpet_print_config(); | |
860 | ||
610bf2f1 VP |
861 | if (hpet_clocksource_register()) |
862 | goto out_nohpet; | |
863 | ||
e9e2cdb4 | 864 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 865 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
866 | return 1; |
867 | } | |
868 | return 0; | |
5d0cf410 | 869 | |
e9e2cdb4 | 870 | out_nohpet: |
06a24dec | 871 | hpet_clear_mapping(); |
bacbe999 | 872 | hpet_address = 0; |
e9e2cdb4 TG |
873 | return 0; |
874 | } | |
875 | ||
28769149 TG |
876 | /* |
877 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
878 | * | |
879 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
880 | * but on x86_64 it is necessary ! | |
881 | */ | |
882 | static __init int hpet_late_init(void) | |
883 | { | |
26afe5f2 | 884 | int cpu; |
885 | ||
59c69f2a | 886 | if (boot_hpet_disable) |
28769149 TG |
887 | return -ENODEV; |
888 | ||
59c69f2a VP |
889 | if (!hpet_address) { |
890 | if (!force_hpet_address) | |
891 | return -ENODEV; | |
892 | ||
893 | hpet_address = force_hpet_address; | |
894 | hpet_enable(); | |
59c69f2a VP |
895 | } |
896 | ||
39c04b55 JF |
897 | if (!hpet_virt_address) |
898 | return -ENODEV; | |
899 | ||
39fe05e5 SL |
900 | if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) |
901 | hpet_msi_capability_lookup(2); | |
902 | else | |
903 | hpet_msi_capability_lookup(0); | |
904 | ||
28769149 | 905 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 906 | hpet_print_config(); |
59c69f2a | 907 | |
73472a46 PV |
908 | if (hpet_msi_disable) |
909 | return 0; | |
910 | ||
39fe05e5 SL |
911 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
912 | return 0; | |
913 | ||
9014ad2a | 914 | cpu_notifier_register_begin(); |
26afe5f2 | 915 | for_each_online_cpu(cpu) { |
916 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
917 | } | |
918 | ||
919 | /* This notifier should be called after workqueue is ready */ | |
9014ad2a SB |
920 | __hotcpu_notifier(hpet_cpuhp_notify, -20); |
921 | cpu_notifier_register_done(); | |
26afe5f2 | 922 | |
28769149 TG |
923 | return 0; |
924 | } | |
925 | fs_initcall(hpet_late_init); | |
926 | ||
c86c7fbc OH |
927 | void hpet_disable(void) |
928 | { | |
ff487808 | 929 | if (is_hpet_capable() && hpet_virt_address) { |
396e2c6f | 930 | unsigned int cfg = hpet_readl(HPET_CFG), id, last; |
c86c7fbc | 931 | |
396e2c6f JB |
932 | if (hpet_boot_cfg) |
933 | cfg = *hpet_boot_cfg; | |
934 | else if (hpet_legacy_int_enabled) { | |
c86c7fbc OH |
935 | cfg &= ~HPET_CFG_LEGACY; |
936 | hpet_legacy_int_enabled = 0; | |
937 | } | |
938 | cfg &= ~HPET_CFG_ENABLE; | |
939 | hpet_writel(cfg, HPET_CFG); | |
396e2c6f JB |
940 | |
941 | if (!hpet_boot_cfg) | |
942 | return; | |
943 | ||
944 | id = hpet_readl(HPET_ID); | |
945 | last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
946 | ||
947 | for (id = 0; id <= last; ++id) | |
948 | hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id)); | |
949 | ||
950 | if (*hpet_boot_cfg & HPET_CFG_ENABLE) | |
951 | hpet_writel(*hpet_boot_cfg, HPET_CFG); | |
c86c7fbc OH |
952 | } |
953 | } | |
954 | ||
e9e2cdb4 TG |
955 | #ifdef CONFIG_HPET_EMULATE_RTC |
956 | ||
957 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
958 | * is enabled, we support RTC interrupt functionality in software. | |
959 | * RTC has 3 kinds of interrupts: | |
960 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
961 | * is updated | |
962 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
963 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
964 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
965 | * (1) and (2) above are implemented using polling at a frequency of | |
966 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
967 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
968 | * For (3), we use interrupts at 64Hz or user specified periodic | |
969 | * frequency, whichever is higher. | |
970 | */ | |
971 | #include <linux/mc146818rtc.h> | |
972 | #include <linux/rtc.h> | |
1bdbdaac | 973 | #include <asm/rtc.h> |
e9e2cdb4 TG |
974 | |
975 | #define DEFAULT_RTC_INT_FREQ 64 | |
976 | #define DEFAULT_RTC_SHIFT 6 | |
977 | #define RTC_NUM_INTS 1 | |
978 | ||
979 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 980 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
981 | static struct rtc_time hpet_alarm_time; |
982 | static unsigned long hpet_pie_count; | |
ff08f76d | 983 | static u32 hpet_t1_cmp; |
5946fa3d JB |
984 | static u32 hpet_default_delta; |
985 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
986 | static unsigned long hpet_pie_limit; |
987 | ||
1bdbdaac BW |
988 | static rtc_irq_handler irq_handler; |
989 | ||
ff08f76d PE |
990 | /* |
991 | * Check that the hpet counter c1 is ahead of the c2 | |
992 | */ | |
993 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
994 | { | |
995 | return (s32)(c2 - c1) < 0; | |
996 | } | |
997 | ||
1bdbdaac BW |
998 | /* |
999 | * Registers a IRQ handler. | |
1000 | */ | |
1001 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
1002 | { | |
1003 | if (!is_hpet_enabled()) | |
1004 | return -ENODEV; | |
1005 | if (irq_handler) | |
1006 | return -EBUSY; | |
1007 | ||
1008 | irq_handler = handler; | |
1009 | ||
1010 | return 0; | |
1011 | } | |
1012 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
1013 | ||
1014 | /* | |
1015 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
1016 | * and does cleanup. | |
1017 | */ | |
1018 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
1019 | { | |
1020 | if (!is_hpet_enabled()) | |
1021 | return; | |
1022 | ||
1023 | irq_handler = NULL; | |
1024 | hpet_rtc_flags = 0; | |
1025 | } | |
1026 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1027 | ||
e9e2cdb4 TG |
1028 | /* |
1029 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
1030 | * is not supported by all HPET implementations for timer 1. | |
1031 | * | |
1032 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1033 | */ | |
1034 | int hpet_rtc_timer_init(void) | |
1035 | { | |
5946fa3d JB |
1036 | unsigned int cfg, cnt, delta; |
1037 | unsigned long flags; | |
e9e2cdb4 TG |
1038 | |
1039 | if (!is_hpet_enabled()) | |
1040 | return 0; | |
1041 | ||
1042 | if (!hpet_default_delta) { | |
1043 | uint64_t clc; | |
1044 | ||
1045 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1046 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1047 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1048 | } |
1049 | ||
1050 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1051 | delta = hpet_default_delta; | |
1052 | else | |
1053 | delta = hpet_pie_delta; | |
1054 | ||
1055 | local_irq_save(flags); | |
1056 | ||
1057 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1058 | hpet_writel(cnt, HPET_T1_CMP); | |
1059 | hpet_t1_cmp = cnt; | |
1060 | ||
1061 | cfg = hpet_readl(HPET_T1_CFG); | |
1062 | cfg &= ~HPET_TN_PERIODIC; | |
1063 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1064 | hpet_writel(cfg, HPET_T1_CFG); | |
1065 | ||
1066 | local_irq_restore(flags); | |
1067 | ||
1068 | return 1; | |
1069 | } | |
1bdbdaac | 1070 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 | 1071 | |
2ded6e6a ML |
1072 | static void hpet_disable_rtc_channel(void) |
1073 | { | |
1074 | unsigned long cfg; | |
1075 | cfg = hpet_readl(HPET_T1_CFG); | |
1076 | cfg &= ~HPET_TN_ENABLE; | |
1077 | hpet_writel(cfg, HPET_T1_CFG); | |
1078 | } | |
1079 | ||
e9e2cdb4 TG |
1080 | /* |
1081 | * The functions below are called from rtc driver. | |
1082 | * Return 0 if HPET is not being used. | |
1083 | * Otherwise do the necessary changes and return 1. | |
1084 | */ | |
1085 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1086 | { | |
1087 | if (!is_hpet_enabled()) | |
1088 | return 0; | |
1089 | ||
1090 | hpet_rtc_flags &= ~bit_mask; | |
2ded6e6a ML |
1091 | if (unlikely(!hpet_rtc_flags)) |
1092 | hpet_disable_rtc_channel(); | |
1093 | ||
e9e2cdb4 TG |
1094 | return 1; |
1095 | } | |
1bdbdaac | 1096 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1097 | |
1098 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1099 | { | |
1100 | unsigned long oldbits = hpet_rtc_flags; | |
1101 | ||
1102 | if (!is_hpet_enabled()) | |
1103 | return 0; | |
1104 | ||
1105 | hpet_rtc_flags |= bit_mask; | |
1106 | ||
7e2a31da DB |
1107 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1108 | hpet_prev_update_sec = -1; | |
1109 | ||
e9e2cdb4 TG |
1110 | if (!oldbits) |
1111 | hpet_rtc_timer_init(); | |
1112 | ||
1113 | return 1; | |
1114 | } | |
1bdbdaac | 1115 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1116 | |
1117 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1118 | unsigned char sec) | |
1119 | { | |
1120 | if (!is_hpet_enabled()) | |
1121 | return 0; | |
1122 | ||
1123 | hpet_alarm_time.tm_hour = hrs; | |
1124 | hpet_alarm_time.tm_min = min; | |
1125 | hpet_alarm_time.tm_sec = sec; | |
1126 | ||
1127 | return 1; | |
1128 | } | |
1bdbdaac | 1129 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1130 | |
1131 | int hpet_set_periodic_freq(unsigned long freq) | |
1132 | { | |
1133 | uint64_t clc; | |
1134 | ||
1135 | if (!is_hpet_enabled()) | |
1136 | return 0; | |
1137 | ||
1138 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1139 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1140 | else { | |
1141 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1142 | do_div(clc, freq); | |
1143 | clc >>= hpet_clockevent.shift; | |
5946fa3d | 1144 | hpet_pie_delta = clc; |
b4a5e8a1 | 1145 | hpet_pie_limit = 0; |
e9e2cdb4 TG |
1146 | } |
1147 | return 1; | |
1148 | } | |
1bdbdaac | 1149 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1150 | |
1151 | int hpet_rtc_dropped_irq(void) | |
1152 | { | |
1153 | return is_hpet_enabled(); | |
1154 | } | |
1bdbdaac | 1155 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1156 | |
1157 | static void hpet_rtc_timer_reinit(void) | |
1158 | { | |
2ded6e6a | 1159 | unsigned int delta; |
e9e2cdb4 TG |
1160 | int lost_ints = -1; |
1161 | ||
2ded6e6a ML |
1162 | if (unlikely(!hpet_rtc_flags)) |
1163 | hpet_disable_rtc_channel(); | |
e9e2cdb4 TG |
1164 | |
1165 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1166 | delta = hpet_default_delta; | |
1167 | else | |
1168 | delta = hpet_pie_delta; | |
1169 | ||
1170 | /* | |
1171 | * Increment the comparator value until we are ahead of the | |
1172 | * current count. | |
1173 | */ | |
1174 | do { | |
1175 | hpet_t1_cmp += delta; | |
1176 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1177 | lost_ints++; | |
ff08f76d | 1178 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1179 | |
1180 | if (lost_ints) { | |
1181 | if (hpet_rtc_flags & RTC_PIE) | |
1182 | hpet_pie_count += lost_ints; | |
1183 | if (printk_ratelimit()) | |
7e2a31da | 1184 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1185 | lost_ints); |
1186 | } | |
1187 | } | |
1188 | ||
1189 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1190 | { | |
1191 | struct rtc_time curr_time; | |
1192 | unsigned long rtc_int_flag = 0; | |
1193 | ||
1194 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1195 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1196 | |
1197 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1198 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1199 | |
1200 | if (hpet_rtc_flags & RTC_UIE && | |
1201 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1202 | if (hpet_prev_update_sec >= 0) |
1203 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1204 | hpet_prev_update_sec = curr_time.tm_sec; |
1205 | } | |
1206 | ||
1207 | if (hpet_rtc_flags & RTC_PIE && | |
1208 | ++hpet_pie_count >= hpet_pie_limit) { | |
1209 | rtc_int_flag |= RTC_PF; | |
1210 | hpet_pie_count = 0; | |
1211 | } | |
1212 | ||
8ee291f8 | 1213 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1214 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1215 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1216 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1217 | rtc_int_flag |= RTC_AF; | |
1218 | ||
1219 | if (rtc_int_flag) { | |
1220 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1221 | if (irq_handler) |
1222 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1223 | } |
1224 | return IRQ_HANDLED; | |
1225 | } | |
1bdbdaac | 1226 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1227 | #endif |