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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 IM |
3 | #include <linux/interrupt.h> |
4 | #include <linux/sysdev.h> | |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 JS |
6 | #include <linux/errno.h> |
7 | #include <linux/hpet.h> | |
8 | #include <linux/init.h> | |
58ac1e76 | 9 | #include <linux/cpu.h> |
4588c1f0 IM |
10 | #include <linux/pm.h> |
11 | #include <linux/io.h> | |
5d0cf410 | 12 | |
28769149 | 13 | #include <asm/fixmap.h> |
06a24dec | 14 | #include <asm/i8253.h> |
4588c1f0 | 15 | #include <asm/hpet.h> |
5d0cf410 | 16 | |
4588c1f0 IM |
17 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
18 | #define HPET_SHIFT 22 | |
5d0cf410 | 19 | |
b10db7f0 PM |
20 | /* FSEC = 10^-15 |
21 | NSEC = 10^-9 */ | |
4588c1f0 | 22 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 23 | |
26afe5f2 | 24 | #define HPET_DEV_USED_BIT 2 |
25 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
26 | #define HPET_DEV_VALID 0x8 | |
27 | #define HPET_DEV_FSB_CAP 0x1000 | |
28 | #define HPET_DEV_PERI_CAP 0x2000 | |
29 | ||
30 | #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) | |
31 | ||
e9e2cdb4 TG |
32 | /* |
33 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
34 | */ | |
4588c1f0 | 35 | unsigned long hpet_address; |
26afe5f2 | 36 | unsigned long hpet_num_timers; |
4588c1f0 | 37 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 38 | |
58ac1e76 | 39 | struct hpet_dev { |
4588c1f0 IM |
40 | struct clock_event_device evt; |
41 | unsigned int num; | |
42 | int cpu; | |
43 | unsigned int irq; | |
44 | unsigned int flags; | |
45 | char name[10]; | |
58ac1e76 | 46 | }; |
47 | ||
26afe5f2 | 48 | static struct hpet_dev *hpet_devs; |
49 | ||
50 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
51 | ||
31c435d7 | 52 | unsigned long hpet_readl(unsigned long a) |
e9e2cdb4 TG |
53 | { |
54 | return readl(hpet_virt_address + a); | |
55 | } | |
56 | ||
57 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
58 | { | |
59 | writel(d, hpet_virt_address + a); | |
60 | } | |
61 | ||
28769149 | 62 | #ifdef CONFIG_X86_64 |
28769149 | 63 | #include <asm/pgtable.h> |
2387ce57 | 64 | #endif |
28769149 | 65 | |
06a24dec TG |
66 | static inline void hpet_set_mapping(void) |
67 | { | |
68 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 YL |
69 | #ifdef CONFIG_X86_64 |
70 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
71 | #endif | |
06a24dec TG |
72 | } |
73 | ||
74 | static inline void hpet_clear_mapping(void) | |
75 | { | |
76 | iounmap(hpet_virt_address); | |
77 | hpet_virt_address = NULL; | |
78 | } | |
79 | ||
e9e2cdb4 TG |
80 | /* |
81 | * HPET command line enable / disable | |
82 | */ | |
83 | static int boot_hpet_disable; | |
b17530bd | 84 | int hpet_force_user; |
e9e2cdb4 | 85 | |
4588c1f0 | 86 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
87 | { |
88 | if (str) { | |
89 | if (!strncmp("disable", str, 7)) | |
90 | boot_hpet_disable = 1; | |
b17530bd TG |
91 | if (!strncmp("force", str, 5)) |
92 | hpet_force_user = 1; | |
e9e2cdb4 TG |
93 | } |
94 | return 1; | |
95 | } | |
96 | __setup("hpet=", hpet_setup); | |
97 | ||
28769149 TG |
98 | static int __init disable_hpet(char *str) |
99 | { | |
100 | boot_hpet_disable = 1; | |
101 | return 1; | |
102 | } | |
103 | __setup("nohpet", disable_hpet); | |
104 | ||
e9e2cdb4 TG |
105 | static inline int is_hpet_capable(void) |
106 | { | |
4588c1f0 | 107 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
108 | } |
109 | ||
110 | /* | |
111 | * HPET timer interrupt enable / disable | |
112 | */ | |
113 | static int hpet_legacy_int_enabled; | |
114 | ||
115 | /** | |
116 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
117 | */ | |
118 | int is_hpet_enabled(void) | |
119 | { | |
120 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
121 | } | |
1bdbdaac | 122 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 TG |
123 | |
124 | /* | |
125 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
126 | * timer 0 and timer 1 in case of RTC emulation. | |
127 | */ | |
128 | #ifdef CONFIG_HPET | |
f0ed4e69 VP |
129 | static void hpet_reserve_msi_timers(struct hpet_data *hd) |
130 | { | |
131 | int i; | |
132 | ||
133 | if (!hpet_devs) | |
134 | return; | |
135 | ||
136 | for (i = 0; i < hpet_num_timers; i++) { | |
137 | struct hpet_dev *hdev = &hpet_devs[i]; | |
138 | ||
139 | if (!(hdev->flags & HPET_DEV_VALID)) | |
140 | continue; | |
141 | ||
142 | hd->hd_irq[hdev->num] = hdev->irq; | |
143 | hpet_reserve_timer(hd, hdev->num); | |
144 | } | |
145 | } | |
146 | ||
e9e2cdb4 TG |
147 | static void hpet_reserve_platform_timers(unsigned long id) |
148 | { | |
149 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
150 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
151 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
152 | struct hpet_data hd; |
153 | ||
154 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
155 | ||
4588c1f0 IM |
156 | memset(&hd, 0, sizeof(hd)); |
157 | hd.hd_phys_address = hpet_address; | |
158 | hd.hd_address = hpet; | |
159 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
160 | hpet_reserve_timer(&hd, 0); |
161 | ||
162 | #ifdef CONFIG_HPET_EMULATE_RTC | |
163 | hpet_reserve_timer(&hd, 1); | |
164 | #endif | |
5761d64b | 165 | |
64a76f66 DB |
166 | /* |
167 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
168 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
169 | * don't bother configuring *any* comparator interrupts. | |
170 | */ | |
e9e2cdb4 TG |
171 | hd.hd_irq[0] = HPET_LEGACY_8254; |
172 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
173 | ||
fc3fbc45 | 174 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
175 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
176 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 177 | } |
5761d64b | 178 | |
f0ed4e69 | 179 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 180 | |
e9e2cdb4 | 181 | hpet_alloc(&hd); |
5761d64b | 182 | |
e9e2cdb4 TG |
183 | } |
184 | #else | |
185 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
186 | #endif | |
187 | ||
188 | /* | |
189 | * Common hpet info | |
190 | */ | |
191 | static unsigned long hpet_period; | |
192 | ||
610bf2f1 | 193 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 194 | struct clock_event_device *evt); |
610bf2f1 | 195 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
196 | struct clock_event_device *evt); |
197 | ||
198 | /* | |
199 | * The hpet clock event device | |
200 | */ | |
201 | static struct clock_event_device hpet_clockevent = { | |
202 | .name = "hpet", | |
203 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
204 | .set_mode = hpet_legacy_set_mode, |
205 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 TG |
206 | .shift = 32, |
207 | .irq = 0, | |
59c69f2a | 208 | .rating = 50, |
e9e2cdb4 TG |
209 | }; |
210 | ||
211 | static void hpet_start_counter(void) | |
212 | { | |
213 | unsigned long cfg = hpet_readl(HPET_CFG); | |
214 | ||
215 | cfg &= ~HPET_CFG_ENABLE; | |
216 | hpet_writel(cfg, HPET_CFG); | |
217 | hpet_writel(0, HPET_COUNTER); | |
218 | hpet_writel(0, HPET_COUNTER + 4); | |
219 | cfg |= HPET_CFG_ENABLE; | |
220 | hpet_writel(cfg, HPET_CFG); | |
221 | } | |
222 | ||
59c69f2a VP |
223 | static void hpet_resume_device(void) |
224 | { | |
bfe0c1cc | 225 | force_hpet_resume(); |
59c69f2a VP |
226 | } |
227 | ||
228 | static void hpet_restart_counter(void) | |
229 | { | |
230 | hpet_resume_device(); | |
231 | hpet_start_counter(); | |
232 | } | |
233 | ||
610bf2f1 | 234 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 TG |
235 | { |
236 | unsigned long cfg = hpet_readl(HPET_CFG); | |
237 | ||
238 | cfg |= HPET_CFG_LEGACY; | |
239 | hpet_writel(cfg, HPET_CFG); | |
240 | hpet_legacy_int_enabled = 1; | |
241 | } | |
242 | ||
610bf2f1 VP |
243 | static void hpet_legacy_clockevent_register(void) |
244 | { | |
610bf2f1 VP |
245 | /* Start HPET legacy interrupts */ |
246 | hpet_enable_legacy_int(); | |
247 | ||
248 | /* | |
6fd592da CM |
249 | * The mult factor is defined as (include/linux/clockchips.h) |
250 | * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) | |
251 | * hpet_period is in units of femtoseconds (per cycle), so | |
252 | * mult/2^shift = cyc/ns = 10^6/hpet_period | |
253 | * mult = (10^6 * 2^shift)/hpet_period | |
254 | * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period | |
610bf2f1 | 255 | */ |
6fd592da CM |
256 | hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, |
257 | hpet_period, hpet_clockevent.shift); | |
610bf2f1 VP |
258 | /* Calculate the min / max delta */ |
259 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
260 | &hpet_clockevent); | |
7cfb0435 TG |
261 | /* 5 usec minimum reprogramming delta. */ |
262 | hpet_clockevent.min_delta_ns = 5000; | |
610bf2f1 VP |
263 | |
264 | /* | |
265 | * Start hpet with the boot cpu mask and make it | |
266 | * global after the IO_APIC has been initialized. | |
267 | */ | |
268 | hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); | |
269 | clockevents_register_device(&hpet_clockevent); | |
270 | global_clock_event = &hpet_clockevent; | |
271 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
272 | } | |
273 | ||
26afe5f2 | 274 | static int hpet_setup_msi_irq(unsigned int irq); |
275 | ||
b40d575b | 276 | static void hpet_set_mode(enum clock_event_mode mode, |
277 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 TG |
278 | { |
279 | unsigned long cfg, cmp, now; | |
280 | uint64_t delta; | |
281 | ||
4588c1f0 | 282 | switch (mode) { |
e9e2cdb4 | 283 | case CLOCK_EVT_MODE_PERIODIC: |
b40d575b | 284 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
285 | delta >>= evt->shift; | |
e9e2cdb4 TG |
286 | now = hpet_readl(HPET_COUNTER); |
287 | cmp = now + (unsigned long) delta; | |
b40d575b | 288 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
289 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
290 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 291 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
292 | /* |
293 | * The first write after writing TN_SETVAL to the | |
294 | * config register sets the counter value, the second | |
295 | * write sets the period. | |
296 | */ | |
b40d575b | 297 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 298 | udelay(1); |
b40d575b | 299 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); |
e9e2cdb4 TG |
300 | break; |
301 | ||
302 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 303 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
304 | cfg &= ~HPET_TN_PERIODIC; |
305 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 306 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
307 | break; |
308 | ||
309 | case CLOCK_EVT_MODE_UNUSED: | |
310 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 311 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 312 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 313 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 314 | break; |
18de5bc4 TG |
315 | |
316 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 317 | if (timer == 0) { |
318 | hpet_enable_legacy_int(); | |
319 | } else { | |
320 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
321 | hpet_setup_msi_irq(hdev->irq); | |
322 | disable_irq(hdev->irq); | |
323 | irq_set_affinity(hdev->irq, cpumask_of_cpu(hdev->cpu)); | |
324 | enable_irq(hdev->irq); | |
325 | } | |
18de5bc4 | 326 | break; |
e9e2cdb4 TG |
327 | } |
328 | } | |
329 | ||
b40d575b | 330 | static int hpet_next_event(unsigned long delta, |
331 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 332 | { |
f7676254 | 333 | u32 cnt; |
e9e2cdb4 TG |
334 | |
335 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 336 | cnt += (u32) delta; |
b40d575b | 337 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 338 | |
72d43d9b TG |
339 | /* |
340 | * We need to read back the CMP register to make sure that | |
341 | * what we wrote hit the chip before we compare it to the | |
342 | * counter. | |
343 | */ | |
344 | WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt); | |
345 | ||
f7676254 | 346 | return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; |
e9e2cdb4 TG |
347 | } |
348 | ||
b40d575b | 349 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
350 | struct clock_event_device *evt) | |
351 | { | |
352 | hpet_set_mode(mode, evt, 0); | |
353 | } | |
354 | ||
355 | static int hpet_legacy_next_event(unsigned long delta, | |
356 | struct clock_event_device *evt) | |
357 | { | |
358 | return hpet_next_event(delta, evt, 0); | |
359 | } | |
360 | ||
58ac1e76 | 361 | /* |
362 | * HPET MSI Support | |
363 | */ | |
26afe5f2 | 364 | #ifdef CONFIG_PCI_MSI |
58ac1e76 | 365 | void hpet_msi_unmask(unsigned int irq) |
366 | { | |
367 | struct hpet_dev *hdev = get_irq_data(irq); | |
368 | unsigned long cfg; | |
369 | ||
370 | /* unmask it */ | |
371 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
372 | cfg |= HPET_TN_FSB; | |
373 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
374 | } | |
375 | ||
376 | void hpet_msi_mask(unsigned int irq) | |
377 | { | |
378 | unsigned long cfg; | |
379 | struct hpet_dev *hdev = get_irq_data(irq); | |
380 | ||
381 | /* mask it */ | |
382 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
383 | cfg &= ~HPET_TN_FSB; | |
384 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
385 | } | |
386 | ||
387 | void hpet_msi_write(unsigned int irq, struct msi_msg *msg) | |
388 | { | |
389 | struct hpet_dev *hdev = get_irq_data(irq); | |
390 | ||
391 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); | |
392 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
393 | } | |
394 | ||
395 | void hpet_msi_read(unsigned int irq, struct msi_msg *msg) | |
396 | { | |
397 | struct hpet_dev *hdev = get_irq_data(irq); | |
398 | ||
399 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); | |
400 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
401 | msg->address_hi = 0; | |
402 | } | |
403 | ||
26afe5f2 | 404 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
405 | struct clock_event_device *evt) | |
406 | { | |
407 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
408 | hpet_set_mode(mode, evt, hdev->num); | |
409 | } | |
410 | ||
411 | static int hpet_msi_next_event(unsigned long delta, | |
412 | struct clock_event_device *evt) | |
413 | { | |
414 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
415 | return hpet_next_event(delta, evt, hdev->num); | |
416 | } | |
417 | ||
418 | static int hpet_setup_msi_irq(unsigned int irq) | |
419 | { | |
420 | if (arch_setup_hpet_msi(irq)) { | |
421 | destroy_irq(irq); | |
422 | return -EINVAL; | |
423 | } | |
424 | return 0; | |
425 | } | |
426 | ||
427 | static int hpet_assign_irq(struct hpet_dev *dev) | |
428 | { | |
429 | unsigned int irq; | |
430 | ||
431 | irq = create_irq(); | |
432 | if (!irq) | |
433 | return -EINVAL; | |
434 | ||
435 | set_irq_data(irq, dev); | |
436 | ||
437 | if (hpet_setup_msi_irq(irq)) | |
438 | return -EINVAL; | |
439 | ||
440 | dev->irq = irq; | |
441 | return 0; | |
442 | } | |
443 | ||
444 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
445 | { | |
446 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
447 | struct clock_event_device *hevt = &dev->evt; | |
448 | ||
449 | if (!hevt->event_handler) { | |
450 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
451 | dev->num); | |
452 | return IRQ_HANDLED; | |
453 | } | |
454 | ||
455 | hevt->event_handler(hevt); | |
456 | return IRQ_HANDLED; | |
457 | } | |
458 | ||
459 | static int hpet_setup_irq(struct hpet_dev *dev) | |
460 | { | |
461 | ||
462 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
463 | IRQF_SHARED|IRQF_NOBALANCING, dev->name, dev)) | |
464 | return -1; | |
465 | ||
466 | disable_irq(dev->irq); | |
467 | irq_set_affinity(dev->irq, cpumask_of_cpu(dev->cpu)); | |
468 | enable_irq(dev->irq); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | /* This should be called in specific @cpu */ | |
474 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
475 | { | |
476 | struct clock_event_device *evt = &hdev->evt; | |
477 | uint64_t hpet_freq; | |
478 | ||
479 | WARN_ON(cpu != smp_processor_id()); | |
480 | if (!(hdev->flags & HPET_DEV_VALID)) | |
481 | return; | |
482 | ||
483 | if (hpet_setup_msi_irq(hdev->irq)) | |
484 | return; | |
485 | ||
486 | hdev->cpu = cpu; | |
487 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
488 | evt->name = hdev->name; | |
489 | hpet_setup_irq(hdev); | |
490 | evt->irq = hdev->irq; | |
491 | ||
492 | evt->rating = 110; | |
493 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
494 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
495 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
496 | ||
497 | evt->set_mode = hpet_msi_set_mode; | |
498 | evt->set_next_event = hpet_msi_next_event; | |
499 | evt->shift = 32; | |
500 | ||
501 | /* | |
502 | * The period is a femto seconds value. We need to calculate the | |
503 | * scaled math multiplication factor for nanosecond to hpet tick | |
504 | * conversion. | |
505 | */ | |
506 | hpet_freq = 1000000000000000ULL; | |
507 | do_div(hpet_freq, hpet_period); | |
508 | evt->mult = div_sc((unsigned long) hpet_freq, | |
509 | NSEC_PER_SEC, evt->shift); | |
510 | /* Calculate the max delta */ | |
511 | evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); | |
512 | /* 5 usec minimum reprogramming delta. */ | |
513 | evt->min_delta_ns = 5000; | |
514 | ||
515 | evt->cpumask = cpumask_of_cpu(hdev->cpu); | |
516 | clockevents_register_device(evt); | |
517 | } | |
518 | ||
519 | #ifdef CONFIG_HPET | |
520 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
521 | #define RESERVE_TIMERS 1 | |
522 | #else | |
523 | #define RESERVE_TIMERS 0 | |
524 | #endif | |
525 | void hpet_msi_capability_lookup(unsigned int start_timer) | |
526 | { | |
527 | unsigned int id; | |
528 | unsigned int num_timers; | |
529 | unsigned int num_timers_used = 0; | |
530 | int i; | |
531 | ||
532 | id = hpet_readl(HPET_ID); | |
533 | ||
534 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
535 | num_timers++; /* Value read out starts from 0 */ | |
536 | ||
537 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
538 | if (!hpet_devs) | |
539 | return; | |
540 | ||
541 | hpet_num_timers = num_timers; | |
542 | ||
543 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
544 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
545 | unsigned long cfg = hpet_readl(HPET_Tn_CFG(i)); | |
546 | ||
547 | /* Only consider HPET timer with MSI support */ | |
548 | if (!(cfg & HPET_TN_FSB_CAP)) | |
549 | continue; | |
550 | ||
551 | hdev->flags = 0; | |
552 | if (cfg & HPET_TN_PERIODIC_CAP) | |
553 | hdev->flags |= HPET_DEV_PERI_CAP; | |
554 | hdev->num = i; | |
555 | ||
556 | sprintf(hdev->name, "hpet%d", i); | |
557 | if (hpet_assign_irq(hdev)) | |
558 | continue; | |
559 | ||
560 | hdev->flags |= HPET_DEV_FSB_CAP; | |
561 | hdev->flags |= HPET_DEV_VALID; | |
562 | num_timers_used++; | |
563 | if (num_timers_used == num_possible_cpus()) | |
564 | break; | |
565 | } | |
566 | ||
567 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
568 | num_timers, num_timers_used); | |
569 | } | |
570 | ||
571 | static struct hpet_dev *hpet_get_unused_timer(void) | |
572 | { | |
573 | int i; | |
574 | ||
575 | if (!hpet_devs) | |
576 | return NULL; | |
577 | ||
578 | for (i = 0; i < hpet_num_timers; i++) { | |
579 | struct hpet_dev *hdev = &hpet_devs[i]; | |
580 | ||
581 | if (!(hdev->flags & HPET_DEV_VALID)) | |
582 | continue; | |
583 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
584 | (unsigned long *)&hdev->flags)) | |
585 | continue; | |
586 | return hdev; | |
587 | } | |
588 | return NULL; | |
589 | } | |
590 | ||
591 | struct hpet_work_struct { | |
592 | struct delayed_work work; | |
593 | struct completion complete; | |
594 | }; | |
595 | ||
596 | static void hpet_work(struct work_struct *w) | |
597 | { | |
598 | struct hpet_dev *hdev; | |
599 | int cpu = smp_processor_id(); | |
600 | struct hpet_work_struct *hpet_work; | |
601 | ||
602 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
603 | ||
604 | hdev = hpet_get_unused_timer(); | |
605 | if (hdev) | |
606 | init_one_hpet_msi_clockevent(hdev, cpu); | |
607 | ||
608 | complete(&hpet_work->complete); | |
609 | } | |
610 | ||
611 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
612 | unsigned long action, void *hcpu) | |
613 | { | |
614 | unsigned long cpu = (unsigned long)hcpu; | |
615 | struct hpet_work_struct work; | |
616 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
617 | ||
618 | switch (action & 0xf) { | |
619 | case CPU_ONLINE: | |
620 | INIT_DELAYED_WORK(&work.work, hpet_work); | |
621 | init_completion(&work.complete); | |
622 | /* FIXME: add schedule_work_on() */ | |
623 | schedule_delayed_work_on(cpu, &work.work, 0); | |
624 | wait_for_completion(&work.complete); | |
625 | break; | |
626 | case CPU_DEAD: | |
627 | if (hdev) { | |
628 | free_irq(hdev->irq, hdev); | |
629 | hdev->flags &= ~HPET_DEV_USED; | |
630 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
631 | } | |
632 | break; | |
633 | } | |
634 | return NOTIFY_OK; | |
635 | } | |
636 | #else | |
637 | ||
638 | void hpet_msi_capability_lookup(unsigned int start_timer) | |
639 | { | |
640 | return; | |
641 | } | |
642 | ||
643 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
644 | unsigned long action, void *hcpu) | |
645 | { | |
646 | return NOTIFY_OK; | |
647 | } | |
648 | ||
649 | #endif | |
650 | ||
6bb74df4 JS |
651 | /* |
652 | * Clock source related code | |
653 | */ | |
654 | static cycle_t read_hpet(void) | |
655 | { | |
656 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
657 | } | |
658 | ||
28769149 TG |
659 | #ifdef CONFIG_X86_64 |
660 | static cycle_t __vsyscall_fn vread_hpet(void) | |
661 | { | |
662 | return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); | |
663 | } | |
664 | #endif | |
665 | ||
6bb74df4 JS |
666 | static struct clocksource clocksource_hpet = { |
667 | .name = "hpet", | |
668 | .rating = 250, | |
669 | .read = read_hpet, | |
670 | .mask = HPET_MASK, | |
671 | .shift = HPET_SHIFT, | |
672 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
59c69f2a | 673 | .resume = hpet_restart_counter, |
28769149 TG |
674 | #ifdef CONFIG_X86_64 |
675 | .vread = vread_hpet, | |
676 | #endif | |
6bb74df4 JS |
677 | }; |
678 | ||
610bf2f1 | 679 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 680 | { |
6fd592da | 681 | u64 start, now; |
075bcd1f | 682 | cycle_t t1; |
e9e2cdb4 | 683 | |
e9e2cdb4 TG |
684 | /* Start the counter */ |
685 | hpet_start_counter(); | |
686 | ||
075bcd1f TG |
687 | /* Verify whether hpet counter works */ |
688 | t1 = read_hpet(); | |
689 | rdtscll(start); | |
690 | ||
691 | /* | |
692 | * We don't know the TSC frequency yet, but waiting for | |
693 | * 200000 TSC cycles is safe: | |
694 | * 4 GHz == 50us | |
695 | * 1 GHz == 200us | |
696 | */ | |
697 | do { | |
698 | rep_nop(); | |
699 | rdtscll(now); | |
700 | } while ((now - start) < 200000UL); | |
701 | ||
702 | if (t1 == read_hpet()) { | |
703 | printk(KERN_WARNING | |
704 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 705 | return -ENODEV; |
075bcd1f TG |
706 | } |
707 | ||
6fd592da CM |
708 | /* |
709 | * The definition of mult is (include/linux/clocksource.h) | |
710 | * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc | |
711 | * so we first need to convert hpet_period to ns/cyc units: | |
712 | * mult/2^shift = ns/cyc = hpet_period/10^6 | |
713 | * mult = (hpet_period * 2^shift)/10^6 | |
714 | * mult = (hpet_period << shift)/FSEC_PER_NSEC | |
6bb74df4 | 715 | */ |
6fd592da | 716 | clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT); |
6bb74df4 JS |
717 | |
718 | clocksource_register(&clocksource_hpet); | |
719 | ||
610bf2f1 VP |
720 | return 0; |
721 | } | |
722 | ||
b02a7f22 PM |
723 | /** |
724 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
725 | */ |
726 | int __init hpet_enable(void) | |
727 | { | |
728 | unsigned long id; | |
a6825f1c | 729 | int i; |
610bf2f1 VP |
730 | |
731 | if (!is_hpet_capable()) | |
732 | return 0; | |
733 | ||
734 | hpet_set_mapping(); | |
735 | ||
736 | /* | |
737 | * Read the period and check for a sane value: | |
738 | */ | |
739 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
740 | |
741 | /* | |
742 | * AMD SB700 based systems with spread spectrum enabled use a | |
743 | * SMM based HPET emulation to provide proper frequency | |
744 | * setting. The SMM code is initialized with the first HPET | |
745 | * register access and takes some time to complete. During | |
746 | * this time the config register reads 0xffffffff. We check | |
747 | * for max. 1000 loops whether the config register reads a non | |
748 | * 0xffffffff value to make sure that HPET is up and running | |
749 | * before we go further. A counting loop is safe, as the HPET | |
750 | * access takes thousands of CPU cycles. On non SB700 based | |
751 | * machines this check is only done once and has no side | |
752 | * effects. | |
753 | */ | |
754 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
755 | if (i == 1000) { | |
756 | printk(KERN_WARNING | |
757 | "HPET config register value = 0xFFFFFFFF. " | |
758 | "Disabling HPET\n"); | |
759 | goto out_nohpet; | |
760 | } | |
761 | } | |
762 | ||
610bf2f1 VP |
763 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
764 | goto out_nohpet; | |
765 | ||
766 | /* | |
767 | * Read the HPET ID register to retrieve the IRQ routing | |
768 | * information and the number of channels | |
769 | */ | |
770 | id = hpet_readl(HPET_ID); | |
771 | ||
772 | #ifdef CONFIG_HPET_EMULATE_RTC | |
773 | /* | |
774 | * The legacy routing mode needs at least two channels, tick timer | |
775 | * and the rtc emulation channel. | |
776 | */ | |
777 | if (!(id & HPET_ID_NUMBER)) | |
778 | goto out_nohpet; | |
779 | #endif | |
780 | ||
781 | if (hpet_clocksource_register()) | |
782 | goto out_nohpet; | |
783 | ||
e9e2cdb4 | 784 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 785 | hpet_legacy_clockevent_register(); |
26afe5f2 | 786 | hpet_msi_capability_lookup(2); |
e9e2cdb4 TG |
787 | return 1; |
788 | } | |
26afe5f2 | 789 | hpet_msi_capability_lookup(0); |
e9e2cdb4 | 790 | return 0; |
5d0cf410 | 791 | |
e9e2cdb4 | 792 | out_nohpet: |
06a24dec | 793 | hpet_clear_mapping(); |
399afa4f | 794 | boot_hpet_disable = 1; |
e9e2cdb4 TG |
795 | return 0; |
796 | } | |
797 | ||
28769149 TG |
798 | /* |
799 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
800 | * | |
801 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
802 | * but on x86_64 it is necessary ! | |
803 | */ | |
804 | static __init int hpet_late_init(void) | |
805 | { | |
26afe5f2 | 806 | int cpu; |
807 | ||
59c69f2a | 808 | if (boot_hpet_disable) |
28769149 TG |
809 | return -ENODEV; |
810 | ||
59c69f2a VP |
811 | if (!hpet_address) { |
812 | if (!force_hpet_address) | |
813 | return -ENODEV; | |
814 | ||
815 | hpet_address = force_hpet_address; | |
816 | hpet_enable(); | |
817 | if (!hpet_virt_address) | |
818 | return -ENODEV; | |
819 | } | |
820 | ||
28769149 | 821 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
59c69f2a | 822 | |
26afe5f2 | 823 | for_each_online_cpu(cpu) { |
824 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
825 | } | |
826 | ||
827 | /* This notifier should be called after workqueue is ready */ | |
828 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
829 | ||
28769149 TG |
830 | return 0; |
831 | } | |
832 | fs_initcall(hpet_late_init); | |
833 | ||
c86c7fbc OH |
834 | void hpet_disable(void) |
835 | { | |
836 | if (is_hpet_capable()) { | |
837 | unsigned long cfg = hpet_readl(HPET_CFG); | |
838 | ||
839 | if (hpet_legacy_int_enabled) { | |
840 | cfg &= ~HPET_CFG_LEGACY; | |
841 | hpet_legacy_int_enabled = 0; | |
842 | } | |
843 | cfg &= ~HPET_CFG_ENABLE; | |
844 | hpet_writel(cfg, HPET_CFG); | |
845 | } | |
846 | } | |
847 | ||
e9e2cdb4 TG |
848 | #ifdef CONFIG_HPET_EMULATE_RTC |
849 | ||
850 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
851 | * is enabled, we support RTC interrupt functionality in software. | |
852 | * RTC has 3 kinds of interrupts: | |
853 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
854 | * is updated | |
855 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
856 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
857 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
858 | * (1) and (2) above are implemented using polling at a frequency of | |
859 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
860 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
861 | * For (3), we use interrupts at 64Hz or user specified periodic | |
862 | * frequency, whichever is higher. | |
863 | */ | |
864 | #include <linux/mc146818rtc.h> | |
865 | #include <linux/rtc.h> | |
1bdbdaac | 866 | #include <asm/rtc.h> |
e9e2cdb4 TG |
867 | |
868 | #define DEFAULT_RTC_INT_FREQ 64 | |
869 | #define DEFAULT_RTC_SHIFT 6 | |
870 | #define RTC_NUM_INTS 1 | |
871 | ||
872 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 873 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
874 | static struct rtc_time hpet_alarm_time; |
875 | static unsigned long hpet_pie_count; | |
876 | static unsigned long hpet_t1_cmp; | |
877 | static unsigned long hpet_default_delta; | |
878 | static unsigned long hpet_pie_delta; | |
879 | static unsigned long hpet_pie_limit; | |
880 | ||
1bdbdaac BW |
881 | static rtc_irq_handler irq_handler; |
882 | ||
883 | /* | |
884 | * Registers a IRQ handler. | |
885 | */ | |
886 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
887 | { | |
888 | if (!is_hpet_enabled()) | |
889 | return -ENODEV; | |
890 | if (irq_handler) | |
891 | return -EBUSY; | |
892 | ||
893 | irq_handler = handler; | |
894 | ||
895 | return 0; | |
896 | } | |
897 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
898 | ||
899 | /* | |
900 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
901 | * and does cleanup. | |
902 | */ | |
903 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
904 | { | |
905 | if (!is_hpet_enabled()) | |
906 | return; | |
907 | ||
908 | irq_handler = NULL; | |
909 | hpet_rtc_flags = 0; | |
910 | } | |
911 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
912 | ||
e9e2cdb4 TG |
913 | /* |
914 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
915 | * is not supported by all HPET implementations for timer 1. | |
916 | * | |
917 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
918 | */ | |
919 | int hpet_rtc_timer_init(void) | |
920 | { | |
921 | unsigned long cfg, cnt, delta, flags; | |
922 | ||
923 | if (!is_hpet_enabled()) | |
924 | return 0; | |
925 | ||
926 | if (!hpet_default_delta) { | |
927 | uint64_t clc; | |
928 | ||
929 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
930 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
931 | hpet_default_delta = (unsigned long) clc; | |
932 | } | |
933 | ||
934 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
935 | delta = hpet_default_delta; | |
936 | else | |
937 | delta = hpet_pie_delta; | |
938 | ||
939 | local_irq_save(flags); | |
940 | ||
941 | cnt = delta + hpet_readl(HPET_COUNTER); | |
942 | hpet_writel(cnt, HPET_T1_CMP); | |
943 | hpet_t1_cmp = cnt; | |
944 | ||
945 | cfg = hpet_readl(HPET_T1_CFG); | |
946 | cfg &= ~HPET_TN_PERIODIC; | |
947 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
948 | hpet_writel(cfg, HPET_T1_CFG); | |
949 | ||
950 | local_irq_restore(flags); | |
951 | ||
952 | return 1; | |
953 | } | |
1bdbdaac | 954 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
955 | |
956 | /* | |
957 | * The functions below are called from rtc driver. | |
958 | * Return 0 if HPET is not being used. | |
959 | * Otherwise do the necessary changes and return 1. | |
960 | */ | |
961 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
962 | { | |
963 | if (!is_hpet_enabled()) | |
964 | return 0; | |
965 | ||
966 | hpet_rtc_flags &= ~bit_mask; | |
967 | return 1; | |
968 | } | |
1bdbdaac | 969 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
970 | |
971 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
972 | { | |
973 | unsigned long oldbits = hpet_rtc_flags; | |
974 | ||
975 | if (!is_hpet_enabled()) | |
976 | return 0; | |
977 | ||
978 | hpet_rtc_flags |= bit_mask; | |
979 | ||
7e2a31da DB |
980 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
981 | hpet_prev_update_sec = -1; | |
982 | ||
e9e2cdb4 TG |
983 | if (!oldbits) |
984 | hpet_rtc_timer_init(); | |
985 | ||
986 | return 1; | |
987 | } | |
1bdbdaac | 988 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
989 | |
990 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
991 | unsigned char sec) | |
992 | { | |
993 | if (!is_hpet_enabled()) | |
994 | return 0; | |
995 | ||
996 | hpet_alarm_time.tm_hour = hrs; | |
997 | hpet_alarm_time.tm_min = min; | |
998 | hpet_alarm_time.tm_sec = sec; | |
999 | ||
1000 | return 1; | |
1001 | } | |
1bdbdaac | 1002 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1003 | |
1004 | int hpet_set_periodic_freq(unsigned long freq) | |
1005 | { | |
1006 | uint64_t clc; | |
1007 | ||
1008 | if (!is_hpet_enabled()) | |
1009 | return 0; | |
1010 | ||
1011 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1012 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1013 | else { | |
1014 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1015 | do_div(clc, freq); | |
1016 | clc >>= hpet_clockevent.shift; | |
1017 | hpet_pie_delta = (unsigned long) clc; | |
1018 | } | |
1019 | return 1; | |
1020 | } | |
1bdbdaac | 1021 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1022 | |
1023 | int hpet_rtc_dropped_irq(void) | |
1024 | { | |
1025 | return is_hpet_enabled(); | |
1026 | } | |
1bdbdaac | 1027 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1028 | |
1029 | static void hpet_rtc_timer_reinit(void) | |
1030 | { | |
1031 | unsigned long cfg, delta; | |
1032 | int lost_ints = -1; | |
1033 | ||
1034 | if (unlikely(!hpet_rtc_flags)) { | |
1035 | cfg = hpet_readl(HPET_T1_CFG); | |
1036 | cfg &= ~HPET_TN_ENABLE; | |
1037 | hpet_writel(cfg, HPET_T1_CFG); | |
1038 | return; | |
1039 | } | |
1040 | ||
1041 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1042 | delta = hpet_default_delta; | |
1043 | else | |
1044 | delta = hpet_pie_delta; | |
1045 | ||
1046 | /* | |
1047 | * Increment the comparator value until we are ahead of the | |
1048 | * current count. | |
1049 | */ | |
1050 | do { | |
1051 | hpet_t1_cmp += delta; | |
1052 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1053 | lost_ints++; | |
1054 | } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); | |
1055 | ||
1056 | if (lost_ints) { | |
1057 | if (hpet_rtc_flags & RTC_PIE) | |
1058 | hpet_pie_count += lost_ints; | |
1059 | if (printk_ratelimit()) | |
7e2a31da | 1060 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1061 | lost_ints); |
1062 | } | |
1063 | } | |
1064 | ||
1065 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1066 | { | |
1067 | struct rtc_time curr_time; | |
1068 | unsigned long rtc_int_flag = 0; | |
1069 | ||
1070 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1071 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1072 | |
1073 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1074 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1075 | |
1076 | if (hpet_rtc_flags & RTC_UIE && | |
1077 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1078 | if (hpet_prev_update_sec >= 0) |
1079 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1080 | hpet_prev_update_sec = curr_time.tm_sec; |
1081 | } | |
1082 | ||
1083 | if (hpet_rtc_flags & RTC_PIE && | |
1084 | ++hpet_pie_count >= hpet_pie_limit) { | |
1085 | rtc_int_flag |= RTC_PF; | |
1086 | hpet_pie_count = 0; | |
1087 | } | |
1088 | ||
8ee291f8 | 1089 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1090 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1091 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1092 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1093 | rtc_int_flag |= RTC_AF; | |
1094 | ||
1095 | if (rtc_int_flag) { | |
1096 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1097 | if (irq_handler) |
1098 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1099 | } |
1100 | return IRQ_HANDLED; | |
1101 | } | |
1bdbdaac | 1102 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1103 | #endif |