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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 IM |
3 | #include <linux/interrupt.h> |
4 | #include <linux/sysdev.h> | |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 JS |
6 | #include <linux/errno.h> |
7 | #include <linux/hpet.h> | |
8 | #include <linux/init.h> | |
58ac1e76 | 9 | #include <linux/cpu.h> |
4588c1f0 IM |
10 | #include <linux/pm.h> |
11 | #include <linux/io.h> | |
5d0cf410 | 12 | |
28769149 | 13 | #include <asm/fixmap.h> |
06a24dec | 14 | #include <asm/i8253.h> |
4588c1f0 | 15 | #include <asm/hpet.h> |
5d0cf410 | 16 | |
4588c1f0 IM |
17 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
18 | #define HPET_SHIFT 22 | |
5d0cf410 | 19 | |
b10db7f0 PM |
20 | /* FSEC = 10^-15 |
21 | NSEC = 10^-9 */ | |
4588c1f0 | 22 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 23 | |
26afe5f2 | 24 | #define HPET_DEV_USED_BIT 2 |
25 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
26 | #define HPET_DEV_VALID 0x8 | |
27 | #define HPET_DEV_FSB_CAP 0x1000 | |
28 | #define HPET_DEV_PERI_CAP 0x2000 | |
29 | ||
30 | #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) | |
31 | ||
e9e2cdb4 TG |
32 | /* |
33 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
34 | */ | |
4588c1f0 | 35 | unsigned long hpet_address; |
e951e4af | 36 | #ifdef CONFIG_PCI_MSI |
3b71e9e3 | 37 | static unsigned long hpet_num_timers; |
e951e4af | 38 | #endif |
4588c1f0 | 39 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 40 | |
58ac1e76 | 41 | struct hpet_dev { |
4588c1f0 IM |
42 | struct clock_event_device evt; |
43 | unsigned int num; | |
44 | int cpu; | |
45 | unsigned int irq; | |
46 | unsigned int flags; | |
47 | char name[10]; | |
58ac1e76 | 48 | }; |
49 | ||
31c435d7 | 50 | unsigned long hpet_readl(unsigned long a) |
e9e2cdb4 TG |
51 | { |
52 | return readl(hpet_virt_address + a); | |
53 | } | |
54 | ||
55 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
56 | { | |
57 | writel(d, hpet_virt_address + a); | |
58 | } | |
59 | ||
28769149 | 60 | #ifdef CONFIG_X86_64 |
28769149 | 61 | #include <asm/pgtable.h> |
2387ce57 | 62 | #endif |
28769149 | 63 | |
06a24dec TG |
64 | static inline void hpet_set_mapping(void) |
65 | { | |
66 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 YL |
67 | #ifdef CONFIG_X86_64 |
68 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
69 | #endif | |
06a24dec TG |
70 | } |
71 | ||
72 | static inline void hpet_clear_mapping(void) | |
73 | { | |
74 | iounmap(hpet_virt_address); | |
75 | hpet_virt_address = NULL; | |
76 | } | |
77 | ||
e9e2cdb4 TG |
78 | /* |
79 | * HPET command line enable / disable | |
80 | */ | |
81 | static int boot_hpet_disable; | |
b17530bd | 82 | int hpet_force_user; |
e9e2cdb4 | 83 | |
4588c1f0 | 84 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
85 | { |
86 | if (str) { | |
87 | if (!strncmp("disable", str, 7)) | |
88 | boot_hpet_disable = 1; | |
b17530bd TG |
89 | if (!strncmp("force", str, 5)) |
90 | hpet_force_user = 1; | |
e9e2cdb4 TG |
91 | } |
92 | return 1; | |
93 | } | |
94 | __setup("hpet=", hpet_setup); | |
95 | ||
28769149 TG |
96 | static int __init disable_hpet(char *str) |
97 | { | |
98 | boot_hpet_disable = 1; | |
99 | return 1; | |
100 | } | |
101 | __setup("nohpet", disable_hpet); | |
102 | ||
e9e2cdb4 TG |
103 | static inline int is_hpet_capable(void) |
104 | { | |
4588c1f0 | 105 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
106 | } |
107 | ||
108 | /* | |
109 | * HPET timer interrupt enable / disable | |
110 | */ | |
111 | static int hpet_legacy_int_enabled; | |
112 | ||
113 | /** | |
114 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
115 | */ | |
116 | int is_hpet_enabled(void) | |
117 | { | |
118 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
119 | } | |
1bdbdaac | 120 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 TG |
121 | |
122 | /* | |
123 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
124 | * timer 0 and timer 1 in case of RTC emulation. | |
125 | */ | |
126 | #ifdef CONFIG_HPET | |
f0ed4e69 | 127 | |
5f79f2f2 | 128 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 129 | |
e9e2cdb4 TG |
130 | static void hpet_reserve_platform_timers(unsigned long id) |
131 | { | |
132 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
133 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
134 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
135 | struct hpet_data hd; |
136 | ||
137 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
138 | ||
4588c1f0 IM |
139 | memset(&hd, 0, sizeof(hd)); |
140 | hd.hd_phys_address = hpet_address; | |
141 | hd.hd_address = hpet; | |
142 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
143 | hpet_reserve_timer(&hd, 0); |
144 | ||
145 | #ifdef CONFIG_HPET_EMULATE_RTC | |
146 | hpet_reserve_timer(&hd, 1); | |
147 | #endif | |
5761d64b | 148 | |
64a76f66 DB |
149 | /* |
150 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
151 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
152 | * don't bother configuring *any* comparator interrupts. | |
153 | */ | |
e9e2cdb4 TG |
154 | hd.hd_irq[0] = HPET_LEGACY_8254; |
155 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
156 | ||
fc3fbc45 | 157 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
158 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
159 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 160 | } |
5761d64b | 161 | |
f0ed4e69 | 162 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 163 | |
e9e2cdb4 | 164 | hpet_alloc(&hd); |
5761d64b | 165 | |
e9e2cdb4 TG |
166 | } |
167 | #else | |
168 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
169 | #endif | |
170 | ||
171 | /* | |
172 | * Common hpet info | |
173 | */ | |
174 | static unsigned long hpet_period; | |
175 | ||
610bf2f1 | 176 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 177 | struct clock_event_device *evt); |
610bf2f1 | 178 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
179 | struct clock_event_device *evt); |
180 | ||
181 | /* | |
182 | * The hpet clock event device | |
183 | */ | |
184 | static struct clock_event_device hpet_clockevent = { | |
185 | .name = "hpet", | |
186 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
187 | .set_mode = hpet_legacy_set_mode, |
188 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 TG |
189 | .shift = 32, |
190 | .irq = 0, | |
59c69f2a | 191 | .rating = 50, |
e9e2cdb4 TG |
192 | }; |
193 | ||
194 | static void hpet_start_counter(void) | |
195 | { | |
196 | unsigned long cfg = hpet_readl(HPET_CFG); | |
197 | ||
198 | cfg &= ~HPET_CFG_ENABLE; | |
199 | hpet_writel(cfg, HPET_CFG); | |
200 | hpet_writel(0, HPET_COUNTER); | |
201 | hpet_writel(0, HPET_COUNTER + 4); | |
202 | cfg |= HPET_CFG_ENABLE; | |
203 | hpet_writel(cfg, HPET_CFG); | |
204 | } | |
205 | ||
59c69f2a VP |
206 | static void hpet_resume_device(void) |
207 | { | |
bfe0c1cc | 208 | force_hpet_resume(); |
59c69f2a VP |
209 | } |
210 | ||
211 | static void hpet_restart_counter(void) | |
212 | { | |
213 | hpet_resume_device(); | |
214 | hpet_start_counter(); | |
215 | } | |
216 | ||
610bf2f1 | 217 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 TG |
218 | { |
219 | unsigned long cfg = hpet_readl(HPET_CFG); | |
220 | ||
221 | cfg |= HPET_CFG_LEGACY; | |
222 | hpet_writel(cfg, HPET_CFG); | |
223 | hpet_legacy_int_enabled = 1; | |
224 | } | |
225 | ||
610bf2f1 VP |
226 | static void hpet_legacy_clockevent_register(void) |
227 | { | |
610bf2f1 VP |
228 | /* Start HPET legacy interrupts */ |
229 | hpet_enable_legacy_int(); | |
230 | ||
231 | /* | |
6fd592da CM |
232 | * The mult factor is defined as (include/linux/clockchips.h) |
233 | * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) | |
234 | * hpet_period is in units of femtoseconds (per cycle), so | |
235 | * mult/2^shift = cyc/ns = 10^6/hpet_period | |
236 | * mult = (10^6 * 2^shift)/hpet_period | |
237 | * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period | |
610bf2f1 | 238 | */ |
6fd592da CM |
239 | hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, |
240 | hpet_period, hpet_clockevent.shift); | |
610bf2f1 VP |
241 | /* Calculate the min / max delta */ |
242 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
243 | &hpet_clockevent); | |
7cfb0435 TG |
244 | /* 5 usec minimum reprogramming delta. */ |
245 | hpet_clockevent.min_delta_ns = 5000; | |
610bf2f1 VP |
246 | |
247 | /* | |
248 | * Start hpet with the boot cpu mask and make it | |
249 | * global after the IO_APIC has been initialized. | |
250 | */ | |
320ab2b0 | 251 | hpet_clockevent.cpumask = cpumask_of(smp_processor_id()); |
610bf2f1 VP |
252 | clockevents_register_device(&hpet_clockevent); |
253 | global_clock_event = &hpet_clockevent; | |
254 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
255 | } | |
256 | ||
26afe5f2 | 257 | static int hpet_setup_msi_irq(unsigned int irq); |
258 | ||
b40d575b | 259 | static void hpet_set_mode(enum clock_event_mode mode, |
260 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 TG |
261 | { |
262 | unsigned long cfg, cmp, now; | |
263 | uint64_t delta; | |
264 | ||
4588c1f0 | 265 | switch (mode) { |
e9e2cdb4 | 266 | case CLOCK_EVT_MODE_PERIODIC: |
b40d575b | 267 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
268 | delta >>= evt->shift; | |
e9e2cdb4 TG |
269 | now = hpet_readl(HPET_COUNTER); |
270 | cmp = now + (unsigned long) delta; | |
b40d575b | 271 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
272 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
273 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 274 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
275 | /* |
276 | * The first write after writing TN_SETVAL to the | |
277 | * config register sets the counter value, the second | |
278 | * write sets the period. | |
279 | */ | |
b40d575b | 280 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 281 | udelay(1); |
b40d575b | 282 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); |
e9e2cdb4 TG |
283 | break; |
284 | ||
285 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 286 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
287 | cfg &= ~HPET_TN_PERIODIC; |
288 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 289 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
290 | break; |
291 | ||
292 | case CLOCK_EVT_MODE_UNUSED: | |
293 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 294 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 295 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 296 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 297 | break; |
18de5bc4 TG |
298 | |
299 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 300 | if (timer == 0) { |
301 | hpet_enable_legacy_int(); | |
302 | } else { | |
303 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
304 | hpet_setup_msi_irq(hdev->irq); | |
305 | disable_irq(hdev->irq); | |
0de26520 | 306 | irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu)); |
26afe5f2 | 307 | enable_irq(hdev->irq); |
308 | } | |
18de5bc4 | 309 | break; |
e9e2cdb4 TG |
310 | } |
311 | } | |
312 | ||
b40d575b | 313 | static int hpet_next_event(unsigned long delta, |
314 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 315 | { |
f7676254 | 316 | u32 cnt; |
e9e2cdb4 TG |
317 | |
318 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 319 | cnt += (u32) delta; |
b40d575b | 320 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 321 | |
72d43d9b TG |
322 | /* |
323 | * We need to read back the CMP register to make sure that | |
324 | * what we wrote hit the chip before we compare it to the | |
325 | * counter. | |
326 | */ | |
89d77a1e | 327 | WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt); |
72d43d9b | 328 | |
f7676254 | 329 | return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; |
e9e2cdb4 TG |
330 | } |
331 | ||
b40d575b | 332 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
333 | struct clock_event_device *evt) | |
334 | { | |
335 | hpet_set_mode(mode, evt, 0); | |
336 | } | |
337 | ||
338 | static int hpet_legacy_next_event(unsigned long delta, | |
339 | struct clock_event_device *evt) | |
340 | { | |
341 | return hpet_next_event(delta, evt, 0); | |
342 | } | |
343 | ||
58ac1e76 | 344 | /* |
345 | * HPET MSI Support | |
346 | */ | |
26afe5f2 | 347 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
348 | |
349 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
350 | static struct hpet_dev *hpet_devs; | |
351 | ||
58ac1e76 | 352 | void hpet_msi_unmask(unsigned int irq) |
353 | { | |
354 | struct hpet_dev *hdev = get_irq_data(irq); | |
355 | unsigned long cfg; | |
356 | ||
357 | /* unmask it */ | |
358 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
359 | cfg |= HPET_TN_FSB; | |
360 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
361 | } | |
362 | ||
363 | void hpet_msi_mask(unsigned int irq) | |
364 | { | |
365 | unsigned long cfg; | |
366 | struct hpet_dev *hdev = get_irq_data(irq); | |
367 | ||
368 | /* mask it */ | |
369 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
370 | cfg &= ~HPET_TN_FSB; | |
371 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
372 | } | |
373 | ||
374 | void hpet_msi_write(unsigned int irq, struct msi_msg *msg) | |
375 | { | |
376 | struct hpet_dev *hdev = get_irq_data(irq); | |
377 | ||
378 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); | |
379 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
380 | } | |
381 | ||
382 | void hpet_msi_read(unsigned int irq, struct msi_msg *msg) | |
383 | { | |
384 | struct hpet_dev *hdev = get_irq_data(irq); | |
385 | ||
386 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); | |
387 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
388 | msg->address_hi = 0; | |
389 | } | |
390 | ||
26afe5f2 | 391 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
392 | struct clock_event_device *evt) | |
393 | { | |
394 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
395 | hpet_set_mode(mode, evt, hdev->num); | |
396 | } | |
397 | ||
398 | static int hpet_msi_next_event(unsigned long delta, | |
399 | struct clock_event_device *evt) | |
400 | { | |
401 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
402 | return hpet_next_event(delta, evt, hdev->num); | |
403 | } | |
404 | ||
405 | static int hpet_setup_msi_irq(unsigned int irq) | |
406 | { | |
407 | if (arch_setup_hpet_msi(irq)) { | |
408 | destroy_irq(irq); | |
409 | return -EINVAL; | |
410 | } | |
411 | return 0; | |
412 | } | |
413 | ||
414 | static int hpet_assign_irq(struct hpet_dev *dev) | |
415 | { | |
416 | unsigned int irq; | |
417 | ||
418 | irq = create_irq(); | |
419 | if (!irq) | |
420 | return -EINVAL; | |
421 | ||
422 | set_irq_data(irq, dev); | |
423 | ||
424 | if (hpet_setup_msi_irq(irq)) | |
425 | return -EINVAL; | |
426 | ||
427 | dev->irq = irq; | |
428 | return 0; | |
429 | } | |
430 | ||
431 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
432 | { | |
433 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
434 | struct clock_event_device *hevt = &dev->evt; | |
435 | ||
436 | if (!hevt->event_handler) { | |
437 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
438 | dev->num); | |
439 | return IRQ_HANDLED; | |
440 | } | |
441 | ||
442 | hevt->event_handler(hevt); | |
443 | return IRQ_HANDLED; | |
444 | } | |
445 | ||
446 | static int hpet_setup_irq(struct hpet_dev *dev) | |
447 | { | |
448 | ||
449 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
5ceb1a04 | 450 | IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev)) |
26afe5f2 | 451 | return -1; |
452 | ||
453 | disable_irq(dev->irq); | |
0de26520 | 454 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 455 | enable_irq(dev->irq); |
456 | ||
c81bba49 YL |
457 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
458 | dev->name, dev->irq); | |
459 | ||
26afe5f2 | 460 | return 0; |
461 | } | |
462 | ||
463 | /* This should be called in specific @cpu */ | |
464 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
465 | { | |
466 | struct clock_event_device *evt = &hdev->evt; | |
467 | uint64_t hpet_freq; | |
468 | ||
469 | WARN_ON(cpu != smp_processor_id()); | |
470 | if (!(hdev->flags & HPET_DEV_VALID)) | |
471 | return; | |
472 | ||
473 | if (hpet_setup_msi_irq(hdev->irq)) | |
474 | return; | |
475 | ||
476 | hdev->cpu = cpu; | |
477 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
478 | evt->name = hdev->name; | |
479 | hpet_setup_irq(hdev); | |
480 | evt->irq = hdev->irq; | |
481 | ||
482 | evt->rating = 110; | |
483 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
484 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
485 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
486 | ||
487 | evt->set_mode = hpet_msi_set_mode; | |
488 | evt->set_next_event = hpet_msi_next_event; | |
489 | evt->shift = 32; | |
490 | ||
491 | /* | |
492 | * The period is a femto seconds value. We need to calculate the | |
493 | * scaled math multiplication factor for nanosecond to hpet tick | |
494 | * conversion. | |
495 | */ | |
496 | hpet_freq = 1000000000000000ULL; | |
497 | do_div(hpet_freq, hpet_period); | |
498 | evt->mult = div_sc((unsigned long) hpet_freq, | |
499 | NSEC_PER_SEC, evt->shift); | |
500 | /* Calculate the max delta */ | |
501 | evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); | |
502 | /* 5 usec minimum reprogramming delta. */ | |
503 | evt->min_delta_ns = 5000; | |
504 | ||
320ab2b0 | 505 | evt->cpumask = cpumask_of(hdev->cpu); |
26afe5f2 | 506 | clockevents_register_device(evt); |
507 | } | |
508 | ||
509 | #ifdef CONFIG_HPET | |
510 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
511 | #define RESERVE_TIMERS 1 | |
512 | #else | |
513 | #define RESERVE_TIMERS 0 | |
514 | #endif | |
5f79f2f2 VP |
515 | |
516 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 517 | { |
518 | unsigned int id; | |
519 | unsigned int num_timers; | |
520 | unsigned int num_timers_used = 0; | |
521 | int i; | |
522 | ||
523 | id = hpet_readl(HPET_ID); | |
524 | ||
525 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
526 | num_timers++; /* Value read out starts from 0 */ | |
527 | ||
528 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
529 | if (!hpet_devs) | |
530 | return; | |
531 | ||
532 | hpet_num_timers = num_timers; | |
533 | ||
534 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
535 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
536 | unsigned long cfg = hpet_readl(HPET_Tn_CFG(i)); | |
537 | ||
538 | /* Only consider HPET timer with MSI support */ | |
539 | if (!(cfg & HPET_TN_FSB_CAP)) | |
540 | continue; | |
541 | ||
542 | hdev->flags = 0; | |
543 | if (cfg & HPET_TN_PERIODIC_CAP) | |
544 | hdev->flags |= HPET_DEV_PERI_CAP; | |
545 | hdev->num = i; | |
546 | ||
547 | sprintf(hdev->name, "hpet%d", i); | |
548 | if (hpet_assign_irq(hdev)) | |
549 | continue; | |
550 | ||
551 | hdev->flags |= HPET_DEV_FSB_CAP; | |
552 | hdev->flags |= HPET_DEV_VALID; | |
553 | num_timers_used++; | |
554 | if (num_timers_used == num_possible_cpus()) | |
555 | break; | |
556 | } | |
557 | ||
558 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
559 | num_timers, num_timers_used); | |
560 | } | |
561 | ||
5f79f2f2 VP |
562 | #ifdef CONFIG_HPET |
563 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
564 | { | |
565 | int i; | |
566 | ||
567 | if (!hpet_devs) | |
568 | return; | |
569 | ||
570 | for (i = 0; i < hpet_num_timers; i++) { | |
571 | struct hpet_dev *hdev = &hpet_devs[i]; | |
572 | ||
573 | if (!(hdev->flags & HPET_DEV_VALID)) | |
574 | continue; | |
575 | ||
576 | hd->hd_irq[hdev->num] = hdev->irq; | |
577 | hpet_reserve_timer(hd, hdev->num); | |
578 | } | |
579 | } | |
580 | #endif | |
581 | ||
26afe5f2 | 582 | static struct hpet_dev *hpet_get_unused_timer(void) |
583 | { | |
584 | int i; | |
585 | ||
586 | if (!hpet_devs) | |
587 | return NULL; | |
588 | ||
589 | for (i = 0; i < hpet_num_timers; i++) { | |
590 | struct hpet_dev *hdev = &hpet_devs[i]; | |
591 | ||
592 | if (!(hdev->flags & HPET_DEV_VALID)) | |
593 | continue; | |
594 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
595 | (unsigned long *)&hdev->flags)) | |
596 | continue; | |
597 | return hdev; | |
598 | } | |
599 | return NULL; | |
600 | } | |
601 | ||
602 | struct hpet_work_struct { | |
603 | struct delayed_work work; | |
604 | struct completion complete; | |
605 | }; | |
606 | ||
607 | static void hpet_work(struct work_struct *w) | |
608 | { | |
609 | struct hpet_dev *hdev; | |
610 | int cpu = smp_processor_id(); | |
611 | struct hpet_work_struct *hpet_work; | |
612 | ||
613 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
614 | ||
615 | hdev = hpet_get_unused_timer(); | |
616 | if (hdev) | |
617 | init_one_hpet_msi_clockevent(hdev, cpu); | |
618 | ||
619 | complete(&hpet_work->complete); | |
620 | } | |
621 | ||
622 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
623 | unsigned long action, void *hcpu) | |
624 | { | |
625 | unsigned long cpu = (unsigned long)hcpu; | |
626 | struct hpet_work_struct work; | |
627 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
628 | ||
629 | switch (action & 0xf) { | |
630 | case CPU_ONLINE: | |
631 | INIT_DELAYED_WORK(&work.work, hpet_work); | |
632 | init_completion(&work.complete); | |
633 | /* FIXME: add schedule_work_on() */ | |
634 | schedule_delayed_work_on(cpu, &work.work, 0); | |
635 | wait_for_completion(&work.complete); | |
636 | break; | |
637 | case CPU_DEAD: | |
638 | if (hdev) { | |
639 | free_irq(hdev->irq, hdev); | |
640 | hdev->flags &= ~HPET_DEV_USED; | |
641 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
642 | } | |
643 | break; | |
644 | } | |
645 | return NOTIFY_OK; | |
646 | } | |
647 | #else | |
648 | ||
ba374c9b SN |
649 | static int hpet_setup_msi_irq(unsigned int irq) |
650 | { | |
651 | return 0; | |
652 | } | |
5f79f2f2 VP |
653 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
654 | { | |
655 | return; | |
656 | } | |
657 | ||
658 | #ifdef CONFIG_HPET | |
659 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 660 | { |
661 | return; | |
662 | } | |
5f79f2f2 | 663 | #endif |
26afe5f2 | 664 | |
665 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
666 | unsigned long action, void *hcpu) | |
667 | { | |
668 | return NOTIFY_OK; | |
669 | } | |
670 | ||
671 | #endif | |
672 | ||
6bb74df4 JS |
673 | /* |
674 | * Clock source related code | |
675 | */ | |
676 | static cycle_t read_hpet(void) | |
677 | { | |
678 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
679 | } | |
680 | ||
28769149 TG |
681 | #ifdef CONFIG_X86_64 |
682 | static cycle_t __vsyscall_fn vread_hpet(void) | |
683 | { | |
684 | return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); | |
685 | } | |
686 | #endif | |
687 | ||
6bb74df4 JS |
688 | static struct clocksource clocksource_hpet = { |
689 | .name = "hpet", | |
690 | .rating = 250, | |
691 | .read = read_hpet, | |
692 | .mask = HPET_MASK, | |
693 | .shift = HPET_SHIFT, | |
694 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
59c69f2a | 695 | .resume = hpet_restart_counter, |
28769149 TG |
696 | #ifdef CONFIG_X86_64 |
697 | .vread = vread_hpet, | |
698 | #endif | |
6bb74df4 JS |
699 | }; |
700 | ||
610bf2f1 | 701 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 702 | { |
6fd592da | 703 | u64 start, now; |
075bcd1f | 704 | cycle_t t1; |
e9e2cdb4 | 705 | |
e9e2cdb4 TG |
706 | /* Start the counter */ |
707 | hpet_start_counter(); | |
708 | ||
075bcd1f TG |
709 | /* Verify whether hpet counter works */ |
710 | t1 = read_hpet(); | |
711 | rdtscll(start); | |
712 | ||
713 | /* | |
714 | * We don't know the TSC frequency yet, but waiting for | |
715 | * 200000 TSC cycles is safe: | |
716 | * 4 GHz == 50us | |
717 | * 1 GHz == 200us | |
718 | */ | |
719 | do { | |
720 | rep_nop(); | |
721 | rdtscll(now); | |
722 | } while ((now - start) < 200000UL); | |
723 | ||
724 | if (t1 == read_hpet()) { | |
725 | printk(KERN_WARNING | |
726 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 727 | return -ENODEV; |
075bcd1f TG |
728 | } |
729 | ||
6fd592da CM |
730 | /* |
731 | * The definition of mult is (include/linux/clocksource.h) | |
732 | * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc | |
733 | * so we first need to convert hpet_period to ns/cyc units: | |
734 | * mult/2^shift = ns/cyc = hpet_period/10^6 | |
735 | * mult = (hpet_period * 2^shift)/10^6 | |
736 | * mult = (hpet_period << shift)/FSEC_PER_NSEC | |
6bb74df4 | 737 | */ |
6fd592da | 738 | clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT); |
6bb74df4 JS |
739 | |
740 | clocksource_register(&clocksource_hpet); | |
741 | ||
610bf2f1 VP |
742 | return 0; |
743 | } | |
744 | ||
b02a7f22 PM |
745 | /** |
746 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
747 | */ |
748 | int __init hpet_enable(void) | |
749 | { | |
750 | unsigned long id; | |
a6825f1c | 751 | int i; |
610bf2f1 VP |
752 | |
753 | if (!is_hpet_capable()) | |
754 | return 0; | |
755 | ||
756 | hpet_set_mapping(); | |
757 | ||
758 | /* | |
759 | * Read the period and check for a sane value: | |
760 | */ | |
761 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
762 | |
763 | /* | |
764 | * AMD SB700 based systems with spread spectrum enabled use a | |
765 | * SMM based HPET emulation to provide proper frequency | |
766 | * setting. The SMM code is initialized with the first HPET | |
767 | * register access and takes some time to complete. During | |
768 | * this time the config register reads 0xffffffff. We check | |
769 | * for max. 1000 loops whether the config register reads a non | |
770 | * 0xffffffff value to make sure that HPET is up and running | |
771 | * before we go further. A counting loop is safe, as the HPET | |
772 | * access takes thousands of CPU cycles. On non SB700 based | |
773 | * machines this check is only done once and has no side | |
774 | * effects. | |
775 | */ | |
776 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
777 | if (i == 1000) { | |
778 | printk(KERN_WARNING | |
779 | "HPET config register value = 0xFFFFFFFF. " | |
780 | "Disabling HPET\n"); | |
781 | goto out_nohpet; | |
782 | } | |
783 | } | |
784 | ||
610bf2f1 VP |
785 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
786 | goto out_nohpet; | |
787 | ||
788 | /* | |
789 | * Read the HPET ID register to retrieve the IRQ routing | |
790 | * information and the number of channels | |
791 | */ | |
792 | id = hpet_readl(HPET_ID); | |
793 | ||
794 | #ifdef CONFIG_HPET_EMULATE_RTC | |
795 | /* | |
796 | * The legacy routing mode needs at least two channels, tick timer | |
797 | * and the rtc emulation channel. | |
798 | */ | |
799 | if (!(id & HPET_ID_NUMBER)) | |
800 | goto out_nohpet; | |
801 | #endif | |
802 | ||
803 | if (hpet_clocksource_register()) | |
804 | goto out_nohpet; | |
805 | ||
e9e2cdb4 | 806 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 807 | hpet_legacy_clockevent_register(); |
26afe5f2 | 808 | hpet_msi_capability_lookup(2); |
e9e2cdb4 TG |
809 | return 1; |
810 | } | |
26afe5f2 | 811 | hpet_msi_capability_lookup(0); |
e9e2cdb4 | 812 | return 0; |
5d0cf410 | 813 | |
e9e2cdb4 | 814 | out_nohpet: |
06a24dec | 815 | hpet_clear_mapping(); |
bacbe999 | 816 | hpet_address = 0; |
e9e2cdb4 TG |
817 | return 0; |
818 | } | |
819 | ||
28769149 TG |
820 | /* |
821 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
822 | * | |
823 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
824 | * but on x86_64 it is necessary ! | |
825 | */ | |
826 | static __init int hpet_late_init(void) | |
827 | { | |
26afe5f2 | 828 | int cpu; |
829 | ||
59c69f2a | 830 | if (boot_hpet_disable) |
28769149 TG |
831 | return -ENODEV; |
832 | ||
59c69f2a VP |
833 | if (!hpet_address) { |
834 | if (!force_hpet_address) | |
835 | return -ENODEV; | |
836 | ||
837 | hpet_address = force_hpet_address; | |
838 | hpet_enable(); | |
59c69f2a VP |
839 | } |
840 | ||
39c04b55 JF |
841 | if (!hpet_virt_address) |
842 | return -ENODEV; | |
843 | ||
28769149 | 844 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
59c69f2a | 845 | |
26afe5f2 | 846 | for_each_online_cpu(cpu) { |
847 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
848 | } | |
849 | ||
850 | /* This notifier should be called after workqueue is ready */ | |
851 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
852 | ||
28769149 TG |
853 | return 0; |
854 | } | |
855 | fs_initcall(hpet_late_init); | |
856 | ||
c86c7fbc OH |
857 | void hpet_disable(void) |
858 | { | |
859 | if (is_hpet_capable()) { | |
860 | unsigned long cfg = hpet_readl(HPET_CFG); | |
861 | ||
862 | if (hpet_legacy_int_enabled) { | |
863 | cfg &= ~HPET_CFG_LEGACY; | |
864 | hpet_legacy_int_enabled = 0; | |
865 | } | |
866 | cfg &= ~HPET_CFG_ENABLE; | |
867 | hpet_writel(cfg, HPET_CFG); | |
868 | } | |
869 | } | |
870 | ||
e9e2cdb4 TG |
871 | #ifdef CONFIG_HPET_EMULATE_RTC |
872 | ||
873 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
874 | * is enabled, we support RTC interrupt functionality in software. | |
875 | * RTC has 3 kinds of interrupts: | |
876 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
877 | * is updated | |
878 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
879 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
880 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
881 | * (1) and (2) above are implemented using polling at a frequency of | |
882 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
883 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
884 | * For (3), we use interrupts at 64Hz or user specified periodic | |
885 | * frequency, whichever is higher. | |
886 | */ | |
887 | #include <linux/mc146818rtc.h> | |
888 | #include <linux/rtc.h> | |
1bdbdaac | 889 | #include <asm/rtc.h> |
e9e2cdb4 TG |
890 | |
891 | #define DEFAULT_RTC_INT_FREQ 64 | |
892 | #define DEFAULT_RTC_SHIFT 6 | |
893 | #define RTC_NUM_INTS 1 | |
894 | ||
895 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 896 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
897 | static struct rtc_time hpet_alarm_time; |
898 | static unsigned long hpet_pie_count; | |
899 | static unsigned long hpet_t1_cmp; | |
900 | static unsigned long hpet_default_delta; | |
901 | static unsigned long hpet_pie_delta; | |
902 | static unsigned long hpet_pie_limit; | |
903 | ||
1bdbdaac BW |
904 | static rtc_irq_handler irq_handler; |
905 | ||
906 | /* | |
907 | * Registers a IRQ handler. | |
908 | */ | |
909 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
910 | { | |
911 | if (!is_hpet_enabled()) | |
912 | return -ENODEV; | |
913 | if (irq_handler) | |
914 | return -EBUSY; | |
915 | ||
916 | irq_handler = handler; | |
917 | ||
918 | return 0; | |
919 | } | |
920 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
921 | ||
922 | /* | |
923 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
924 | * and does cleanup. | |
925 | */ | |
926 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
927 | { | |
928 | if (!is_hpet_enabled()) | |
929 | return; | |
930 | ||
931 | irq_handler = NULL; | |
932 | hpet_rtc_flags = 0; | |
933 | } | |
934 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
935 | ||
e9e2cdb4 TG |
936 | /* |
937 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
938 | * is not supported by all HPET implementations for timer 1. | |
939 | * | |
940 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
941 | */ | |
942 | int hpet_rtc_timer_init(void) | |
943 | { | |
944 | unsigned long cfg, cnt, delta, flags; | |
945 | ||
946 | if (!is_hpet_enabled()) | |
947 | return 0; | |
948 | ||
949 | if (!hpet_default_delta) { | |
950 | uint64_t clc; | |
951 | ||
952 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
953 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
954 | hpet_default_delta = (unsigned long) clc; | |
955 | } | |
956 | ||
957 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
958 | delta = hpet_default_delta; | |
959 | else | |
960 | delta = hpet_pie_delta; | |
961 | ||
962 | local_irq_save(flags); | |
963 | ||
964 | cnt = delta + hpet_readl(HPET_COUNTER); | |
965 | hpet_writel(cnt, HPET_T1_CMP); | |
966 | hpet_t1_cmp = cnt; | |
967 | ||
968 | cfg = hpet_readl(HPET_T1_CFG); | |
969 | cfg &= ~HPET_TN_PERIODIC; | |
970 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
971 | hpet_writel(cfg, HPET_T1_CFG); | |
972 | ||
973 | local_irq_restore(flags); | |
974 | ||
975 | return 1; | |
976 | } | |
1bdbdaac | 977 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
978 | |
979 | /* | |
980 | * The functions below are called from rtc driver. | |
981 | * Return 0 if HPET is not being used. | |
982 | * Otherwise do the necessary changes and return 1. | |
983 | */ | |
984 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
985 | { | |
986 | if (!is_hpet_enabled()) | |
987 | return 0; | |
988 | ||
989 | hpet_rtc_flags &= ~bit_mask; | |
990 | return 1; | |
991 | } | |
1bdbdaac | 992 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
993 | |
994 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
995 | { | |
996 | unsigned long oldbits = hpet_rtc_flags; | |
997 | ||
998 | if (!is_hpet_enabled()) | |
999 | return 0; | |
1000 | ||
1001 | hpet_rtc_flags |= bit_mask; | |
1002 | ||
7e2a31da DB |
1003 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1004 | hpet_prev_update_sec = -1; | |
1005 | ||
e9e2cdb4 TG |
1006 | if (!oldbits) |
1007 | hpet_rtc_timer_init(); | |
1008 | ||
1009 | return 1; | |
1010 | } | |
1bdbdaac | 1011 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1012 | |
1013 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1014 | unsigned char sec) | |
1015 | { | |
1016 | if (!is_hpet_enabled()) | |
1017 | return 0; | |
1018 | ||
1019 | hpet_alarm_time.tm_hour = hrs; | |
1020 | hpet_alarm_time.tm_min = min; | |
1021 | hpet_alarm_time.tm_sec = sec; | |
1022 | ||
1023 | return 1; | |
1024 | } | |
1bdbdaac | 1025 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1026 | |
1027 | int hpet_set_periodic_freq(unsigned long freq) | |
1028 | { | |
1029 | uint64_t clc; | |
1030 | ||
1031 | if (!is_hpet_enabled()) | |
1032 | return 0; | |
1033 | ||
1034 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1035 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1036 | else { | |
1037 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1038 | do_div(clc, freq); | |
1039 | clc >>= hpet_clockevent.shift; | |
1040 | hpet_pie_delta = (unsigned long) clc; | |
1041 | } | |
1042 | return 1; | |
1043 | } | |
1bdbdaac | 1044 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1045 | |
1046 | int hpet_rtc_dropped_irq(void) | |
1047 | { | |
1048 | return is_hpet_enabled(); | |
1049 | } | |
1bdbdaac | 1050 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1051 | |
1052 | static void hpet_rtc_timer_reinit(void) | |
1053 | { | |
1054 | unsigned long cfg, delta; | |
1055 | int lost_ints = -1; | |
1056 | ||
1057 | if (unlikely(!hpet_rtc_flags)) { | |
1058 | cfg = hpet_readl(HPET_T1_CFG); | |
1059 | cfg &= ~HPET_TN_ENABLE; | |
1060 | hpet_writel(cfg, HPET_T1_CFG); | |
1061 | return; | |
1062 | } | |
1063 | ||
1064 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1065 | delta = hpet_default_delta; | |
1066 | else | |
1067 | delta = hpet_pie_delta; | |
1068 | ||
1069 | /* | |
1070 | * Increment the comparator value until we are ahead of the | |
1071 | * current count. | |
1072 | */ | |
1073 | do { | |
1074 | hpet_t1_cmp += delta; | |
1075 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1076 | lost_ints++; | |
1077 | } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); | |
1078 | ||
1079 | if (lost_ints) { | |
1080 | if (hpet_rtc_flags & RTC_PIE) | |
1081 | hpet_pie_count += lost_ints; | |
1082 | if (printk_ratelimit()) | |
7e2a31da | 1083 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1084 | lost_ints); |
1085 | } | |
1086 | } | |
1087 | ||
1088 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1089 | { | |
1090 | struct rtc_time curr_time; | |
1091 | unsigned long rtc_int_flag = 0; | |
1092 | ||
1093 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1094 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1095 | |
1096 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1097 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1098 | |
1099 | if (hpet_rtc_flags & RTC_UIE && | |
1100 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1101 | if (hpet_prev_update_sec >= 0) |
1102 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1103 | hpet_prev_update_sec = curr_time.tm_sec; |
1104 | } | |
1105 | ||
1106 | if (hpet_rtc_flags & RTC_PIE && | |
1107 | ++hpet_pie_count >= hpet_pie_limit) { | |
1108 | rtc_int_flag |= RTC_PF; | |
1109 | hpet_pie_count = 0; | |
1110 | } | |
1111 | ||
8ee291f8 | 1112 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1113 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1114 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1115 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1116 | rtc_int_flag |= RTC_AF; | |
1117 | ||
1118 | if (rtc_int_flag) { | |
1119 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1120 | if (irq_handler) |
1121 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1122 | } |
1123 | return IRQ_HANDLED; | |
1124 | } | |
1bdbdaac | 1125 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1126 | #endif |