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Commit | Line | Data |
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5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 | 3 | #include <linux/interrupt.h> |
f901f138 | 4 | #include <linux/irq.h> |
69c60c88 | 5 | #include <linux/export.h> |
28769149 | 6 | #include <linux/delay.h> |
5d0cf410 | 7 | #include <linux/errno.h> |
334955ef | 8 | #include <linux/i8253.h> |
5a0e3ad6 | 9 | #include <linux/slab.h> |
5d0cf410 JS |
10 | #include <linux/hpet.h> |
11 | #include <linux/init.h> | |
58ac1e76 | 12 | #include <linux/cpu.h> |
4588c1f0 IM |
13 | #include <linux/pm.h> |
14 | #include <linux/io.h> | |
5d0cf410 | 15 | |
cd4d09ec | 16 | #include <asm/cpufeature.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
28769149 | 18 | #include <asm/fixmap.h> |
4588c1f0 | 19 | #include <asm/hpet.h> |
16f871bc | 20 | #include <asm/time.h> |
5d0cf410 | 21 | |
4588c1f0 | 22 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 23 | |
b10db7f0 PM |
24 | /* FSEC = 10^-15 |
25 | NSEC = 10^-9 */ | |
4588c1f0 | 26 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 27 | |
26afe5f2 | 28 | #define HPET_DEV_USED_BIT 2 |
29 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
30 | #define HPET_DEV_VALID 0x8 | |
31 | #define HPET_DEV_FSB_CAP 0x1000 | |
32 | #define HPET_DEV_PERI_CAP 0x2000 | |
33 | ||
f1c18071 TG |
34 | #define HPET_MIN_CYCLES 128 |
35 | #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) | |
36 | ||
e9e2cdb4 TG |
37 | /* |
38 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
39 | */ | |
4588c1f0 | 40 | unsigned long hpet_address; |
c8bc6f3c | 41 | u8 hpet_blockid; /* OS timer block num */ |
3d45ac4b | 42 | bool hpet_msi_disable; |
73472a46 | 43 | |
e951e4af | 44 | #ifdef CONFIG_PCI_MSI |
3d45ac4b | 45 | static unsigned int hpet_num_timers; |
e951e4af | 46 | #endif |
4588c1f0 | 47 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 48 | |
58ac1e76 | 49 | struct hpet_dev { |
4588c1f0 IM |
50 | struct clock_event_device evt; |
51 | unsigned int num; | |
52 | int cpu; | |
53 | unsigned int irq; | |
54 | unsigned int flags; | |
55 | char name[10]; | |
58ac1e76 | 56 | }; |
57 | ||
a3819e3e | 58 | static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev) |
3f7787b3 FW |
59 | { |
60 | return container_of(evtdev, struct hpet_dev, evt); | |
61 | } | |
62 | ||
5946fa3d | 63 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
64 | { |
65 | return readl(hpet_virt_address + a); | |
66 | } | |
67 | ||
5946fa3d | 68 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
69 | { |
70 | writel(d, hpet_virt_address + a); | |
71 | } | |
72 | ||
28769149 | 73 | #ifdef CONFIG_X86_64 |
28769149 | 74 | #include <asm/pgtable.h> |
2387ce57 | 75 | #endif |
28769149 | 76 | |
06a24dec TG |
77 | static inline void hpet_set_mapping(void) |
78 | { | |
79 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
80 | } | |
81 | ||
82 | static inline void hpet_clear_mapping(void) | |
83 | { | |
84 | iounmap(hpet_virt_address); | |
85 | hpet_virt_address = NULL; | |
86 | } | |
87 | ||
e9e2cdb4 TG |
88 | /* |
89 | * HPET command line enable / disable | |
90 | */ | |
3d45ac4b JB |
91 | bool boot_hpet_disable; |
92 | bool hpet_force_user; | |
93 | static bool hpet_verbose; | |
e9e2cdb4 | 94 | |
4588c1f0 | 95 | static int __init hpet_setup(char *str) |
e9e2cdb4 | 96 | { |
b2d6aba9 JB |
97 | while (str) { |
98 | char *next = strchr(str, ','); | |
99 | ||
100 | if (next) | |
101 | *next++ = 0; | |
e9e2cdb4 | 102 | if (!strncmp("disable", str, 7)) |
3d45ac4b | 103 | boot_hpet_disable = true; |
b17530bd | 104 | if (!strncmp("force", str, 5)) |
3d45ac4b | 105 | hpet_force_user = true; |
b98103a5 | 106 | if (!strncmp("verbose", str, 7)) |
3d45ac4b | 107 | hpet_verbose = true; |
b2d6aba9 | 108 | str = next; |
e9e2cdb4 TG |
109 | } |
110 | return 1; | |
111 | } | |
112 | __setup("hpet=", hpet_setup); | |
113 | ||
28769149 TG |
114 | static int __init disable_hpet(char *str) |
115 | { | |
3d45ac4b | 116 | boot_hpet_disable = true; |
28769149 TG |
117 | return 1; |
118 | } | |
119 | __setup("nohpet", disable_hpet); | |
120 | ||
e9e2cdb4 TG |
121 | static inline int is_hpet_capable(void) |
122 | { | |
4588c1f0 | 123 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
124 | } |
125 | ||
126 | /* | |
127 | * HPET timer interrupt enable / disable | |
128 | */ | |
3d45ac4b | 129 | static bool hpet_legacy_int_enabled; |
e9e2cdb4 TG |
130 | |
131 | /** | |
132 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
133 | */ | |
134 | int is_hpet_enabled(void) | |
135 | { | |
136 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
137 | } | |
1bdbdaac | 138 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 139 | |
b98103a5 AH |
140 | static void _hpet_print_config(const char *function, int line) |
141 | { | |
142 | u32 i, timers, l, h; | |
143 | printk(KERN_INFO "hpet: %s(%d):\n", function, line); | |
144 | l = hpet_readl(HPET_ID); | |
145 | h = hpet_readl(HPET_PERIOD); | |
146 | timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
147 | printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h); | |
148 | l = hpet_readl(HPET_CFG); | |
149 | h = hpet_readl(HPET_STATUS); | |
150 | printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h); | |
151 | l = hpet_readl(HPET_COUNTER); | |
152 | h = hpet_readl(HPET_COUNTER+4); | |
153 | printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); | |
154 | ||
155 | for (i = 0; i < timers; i++) { | |
156 | l = hpet_readl(HPET_Tn_CFG(i)); | |
157 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
158 | printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", | |
159 | i, l, h); | |
160 | l = hpet_readl(HPET_Tn_CMP(i)); | |
161 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
162 | printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", | |
163 | i, l, h); | |
164 | l = hpet_readl(HPET_Tn_ROUTE(i)); | |
165 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
166 | printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", | |
167 | i, l, h); | |
168 | } | |
169 | } | |
170 | ||
171 | #define hpet_print_config() \ | |
172 | do { \ | |
173 | if (hpet_verbose) \ | |
02f1f217 | 174 | _hpet_print_config(__func__, __LINE__); \ |
b98103a5 AH |
175 | } while (0) |
176 | ||
e9e2cdb4 TG |
177 | /* |
178 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
179 | * timer 0 and timer 1 in case of RTC emulation. | |
180 | */ | |
181 | #ifdef CONFIG_HPET | |
f0ed4e69 | 182 | |
5f79f2f2 | 183 | static void hpet_reserve_msi_timers(struct hpet_data *hd); |
f0ed4e69 | 184 | |
5946fa3d | 185 | static void hpet_reserve_platform_timers(unsigned int id) |
e9e2cdb4 TG |
186 | { |
187 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
188 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
189 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
190 | struct hpet_data hd; |
191 | ||
192 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
193 | ||
4588c1f0 IM |
194 | memset(&hd, 0, sizeof(hd)); |
195 | hd.hd_phys_address = hpet_address; | |
196 | hd.hd_address = hpet; | |
197 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
198 | hpet_reserve_timer(&hd, 0); |
199 | ||
200 | #ifdef CONFIG_HPET_EMULATE_RTC | |
201 | hpet_reserve_timer(&hd, 1); | |
202 | #endif | |
5761d64b | 203 | |
64a76f66 DB |
204 | /* |
205 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
206 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
207 | * don't bother configuring *any* comparator interrupts. | |
208 | */ | |
e9e2cdb4 TG |
209 | hd.hd_irq[0] = HPET_LEGACY_8254; |
210 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
211 | ||
fc3fbc45 | 212 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
213 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
214 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 215 | } |
5761d64b | 216 | |
f0ed4e69 | 217 | hpet_reserve_msi_timers(&hd); |
26afe5f2 | 218 | |
e9e2cdb4 | 219 | hpet_alloc(&hd); |
5761d64b | 220 | |
e9e2cdb4 TG |
221 | } |
222 | #else | |
5946fa3d | 223 | static void hpet_reserve_platform_timers(unsigned int id) { } |
e9e2cdb4 TG |
224 | #endif |
225 | ||
226 | /* | |
227 | * Common hpet info | |
228 | */ | |
ab0e08f1 | 229 | static unsigned long hpet_freq; |
e9e2cdb4 | 230 | |
c8b5db7d | 231 | static struct clock_event_device hpet_clockevent; |
e9e2cdb4 | 232 | |
8d6f0c82 | 233 | static void hpet_stop_counter(void) |
e9e2cdb4 | 234 | { |
3d45ac4b | 235 | u32 cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
236 | cfg &= ~HPET_CFG_ENABLE; |
237 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
238 | } |
239 | ||
240 | static void hpet_reset_counter(void) | |
241 | { | |
e9e2cdb4 TG |
242 | hpet_writel(0, HPET_COUNTER); |
243 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
244 | } |
245 | ||
246 | static void hpet_start_counter(void) | |
247 | { | |
5946fa3d | 248 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
249 | cfg |= HPET_CFG_ENABLE; |
250 | hpet_writel(cfg, HPET_CFG); | |
251 | } | |
252 | ||
8d6f0c82 AH |
253 | static void hpet_restart_counter(void) |
254 | { | |
255 | hpet_stop_counter(); | |
7a6f9cbb | 256 | hpet_reset_counter(); |
8d6f0c82 AH |
257 | hpet_start_counter(); |
258 | } | |
259 | ||
59c69f2a VP |
260 | static void hpet_resume_device(void) |
261 | { | |
bfe0c1cc | 262 | force_hpet_resume(); |
59c69f2a VP |
263 | } |
264 | ||
17622339 | 265 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
266 | { |
267 | hpet_resume_device(); | |
8d6f0c82 | 268 | hpet_restart_counter(); |
59c69f2a VP |
269 | } |
270 | ||
610bf2f1 | 271 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 272 | { |
5946fa3d | 273 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
274 | |
275 | cfg |= HPET_CFG_LEGACY; | |
276 | hpet_writel(cfg, HPET_CFG); | |
3d45ac4b | 277 | hpet_legacy_int_enabled = true; |
e9e2cdb4 TG |
278 | } |
279 | ||
610bf2f1 VP |
280 | static void hpet_legacy_clockevent_register(void) |
281 | { | |
610bf2f1 VP |
282 | /* Start HPET legacy interrupts */ |
283 | hpet_enable_legacy_int(); | |
284 | ||
610bf2f1 VP |
285 | /* |
286 | * Start hpet with the boot cpu mask and make it | |
287 | * global after the IO_APIC has been initialized. | |
288 | */ | |
803ff8a7 | 289 | hpet_clockevent.cpumask = cpumask_of(boot_cpu_data.cpu_index); |
ab0e08f1 TG |
290 | clockevents_config_and_register(&hpet_clockevent, hpet_freq, |
291 | HPET_MIN_PROG_DELTA, 0x7FFFFFFF); | |
610bf2f1 VP |
292 | global_clock_event = &hpet_clockevent; |
293 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
294 | } | |
295 | ||
c8b5db7d | 296 | static int hpet_set_periodic(struct clock_event_device *evt, int timer) |
e9e2cdb4 | 297 | { |
5946fa3d | 298 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
299 | uint64_t delta; |
300 | ||
c8b5db7d VK |
301 | hpet_stop_counter(); |
302 | delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; | |
303 | delta >>= evt->shift; | |
304 | now = hpet_readl(HPET_COUNTER); | |
305 | cmp = now + (unsigned int)delta; | |
306 | cfg = hpet_readl(HPET_Tn_CFG(timer)); | |
307 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | | |
308 | HPET_TN_32BIT; | |
309 | hpet_writel(cfg, HPET_Tn_CFG(timer)); | |
310 | hpet_writel(cmp, HPET_Tn_CMP(timer)); | |
311 | udelay(1); | |
312 | /* | |
313 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
314 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
315 | * bit is automatically cleared after the first write. | |
316 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
317 | * Publication # 24674) | |
318 | */ | |
319 | hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer)); | |
320 | hpet_start_counter(); | |
321 | hpet_print_config(); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | static int hpet_set_oneshot(struct clock_event_device *evt, int timer) | |
327 | { | |
328 | unsigned int cfg; | |
329 | ||
330 | cfg = hpet_readl(HPET_Tn_CFG(timer)); | |
331 | cfg &= ~HPET_TN_PERIODIC; | |
332 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
333 | hpet_writel(cfg, HPET_Tn_CFG(timer)); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | static int hpet_shutdown(struct clock_event_device *evt, int timer) | |
339 | { | |
340 | unsigned int cfg; | |
341 | ||
342 | cfg = hpet_readl(HPET_Tn_CFG(timer)); | |
343 | cfg &= ~HPET_TN_ENABLE; | |
344 | hpet_writel(cfg, HPET_Tn_CFG(timer)); | |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
bb68cfe2 TG |
349 | static int hpet_resume(struct clock_event_device *evt) |
350 | { | |
351 | hpet_enable_legacy_int(); | |
c8b5db7d | 352 | hpet_print_config(); |
c8b5db7d | 353 | return 0; |
e9e2cdb4 TG |
354 | } |
355 | ||
b40d575b | 356 | static int hpet_next_event(unsigned long delta, |
357 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 358 | { |
f7676254 | 359 | u32 cnt; |
995bd3bb | 360 | s32 res; |
e9e2cdb4 TG |
361 | |
362 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 363 | cnt += (u32) delta; |
b40d575b | 364 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 365 | |
72d43d9b | 366 | /* |
995bd3bb TG |
367 | * HPETs are a complete disaster. The compare register is |
368 | * based on a equal comparison and neither provides a less | |
369 | * than or equal functionality (which would require to take | |
370 | * the wraparound into account) nor a simple count down event | |
371 | * mode. Further the write to the comparator register is | |
372 | * delayed internally up to two HPET clock cycles in certain | |
f1c18071 TG |
373 | * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even |
374 | * longer delays. We worked around that by reading back the | |
375 | * compare register, but that required another workaround for | |
376 | * ICH9,10 chips where the first readout after write can | |
377 | * return the old stale value. We already had a minimum | |
378 | * programming delta of 5us enforced, but a NMI or SMI hitting | |
995bd3bb TG |
379 | * between the counter readout and the comparator write can |
380 | * move us behind that point easily. Now instead of reading | |
381 | * the compare register back several times, we make the ETIME | |
382 | * decision based on the following: Return ETIME if the | |
f1c18071 | 383 | * counter value after the write is less than HPET_MIN_CYCLES |
995bd3bb | 384 | * away from the event or if the counter is already ahead of |
f1c18071 TG |
385 | * the event. The minimum programming delta for the generic |
386 | * clockevents code is set to 1.5 * HPET_MIN_CYCLES. | |
72d43d9b | 387 | */ |
995bd3bb | 388 | res = (s32)(cnt - hpet_readl(HPET_COUNTER)); |
72d43d9b | 389 | |
f1c18071 | 390 | return res < HPET_MIN_CYCLES ? -ETIME : 0; |
e9e2cdb4 TG |
391 | } |
392 | ||
c8b5db7d | 393 | static int hpet_legacy_shutdown(struct clock_event_device *evt) |
b40d575b | 394 | { |
c8b5db7d VK |
395 | return hpet_shutdown(evt, 0); |
396 | } | |
397 | ||
398 | static int hpet_legacy_set_oneshot(struct clock_event_device *evt) | |
399 | { | |
400 | return hpet_set_oneshot(evt, 0); | |
401 | } | |
402 | ||
403 | static int hpet_legacy_set_periodic(struct clock_event_device *evt) | |
404 | { | |
405 | return hpet_set_periodic(evt, 0); | |
406 | } | |
407 | ||
408 | static int hpet_legacy_resume(struct clock_event_device *evt) | |
409 | { | |
bb68cfe2 | 410 | return hpet_resume(evt); |
b40d575b | 411 | } |
412 | ||
413 | static int hpet_legacy_next_event(unsigned long delta, | |
414 | struct clock_event_device *evt) | |
415 | { | |
416 | return hpet_next_event(delta, evt, 0); | |
417 | } | |
418 | ||
c8b5db7d VK |
419 | /* |
420 | * The hpet clock event device | |
421 | */ | |
422 | static struct clock_event_device hpet_clockevent = { | |
423 | .name = "hpet", | |
424 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
425 | CLOCK_EVT_FEAT_ONESHOT, | |
426 | .set_state_periodic = hpet_legacy_set_periodic, | |
427 | .set_state_oneshot = hpet_legacy_set_oneshot, | |
428 | .set_state_shutdown = hpet_legacy_shutdown, | |
429 | .tick_resume = hpet_legacy_resume, | |
430 | .set_next_event = hpet_legacy_next_event, | |
431 | .irq = 0, | |
432 | .rating = 50, | |
433 | }; | |
434 | ||
58ac1e76 | 435 | /* |
436 | * HPET MSI Support | |
437 | */ | |
26afe5f2 | 438 | #ifdef CONFIG_PCI_MSI |
5f79f2f2 VP |
439 | |
440 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
441 | static struct hpet_dev *hpet_devs; | |
3cb96f0c | 442 | static struct irq_domain *hpet_domain; |
5f79f2f2 | 443 | |
d0fbca8f | 444 | void hpet_msi_unmask(struct irq_data *data) |
58ac1e76 | 445 | { |
ff96b4d0 | 446 | struct hpet_dev *hdev = irq_data_get_irq_handler_data(data); |
5946fa3d | 447 | unsigned int cfg; |
58ac1e76 | 448 | |
449 | /* unmask it */ | |
450 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
6acf5a8c | 451 | cfg |= HPET_TN_ENABLE | HPET_TN_FSB; |
58ac1e76 | 452 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); |
453 | } | |
454 | ||
d0fbca8f | 455 | void hpet_msi_mask(struct irq_data *data) |
58ac1e76 | 456 | { |
ff96b4d0 | 457 | struct hpet_dev *hdev = irq_data_get_irq_handler_data(data); |
5946fa3d | 458 | unsigned int cfg; |
58ac1e76 | 459 | |
460 | /* mask it */ | |
461 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
6acf5a8c | 462 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); |
58ac1e76 | 463 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); |
464 | } | |
465 | ||
d0fbca8f | 466 | void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 467 | { |
58ac1e76 | 468 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); |
469 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
470 | } | |
471 | ||
d0fbca8f | 472 | void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg) |
58ac1e76 | 473 | { |
58ac1e76 | 474 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); |
475 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
476 | msg->address_hi = 0; | |
477 | } | |
478 | ||
c8b5db7d | 479 | static int hpet_msi_shutdown(struct clock_event_device *evt) |
26afe5f2 | 480 | { |
481 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
c8b5db7d VK |
482 | |
483 | return hpet_shutdown(evt, hdev->num); | |
484 | } | |
485 | ||
486 | static int hpet_msi_set_oneshot(struct clock_event_device *evt) | |
487 | { | |
488 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
489 | ||
490 | return hpet_set_oneshot(evt, hdev->num); | |
491 | } | |
492 | ||
493 | static int hpet_msi_set_periodic(struct clock_event_device *evt) | |
494 | { | |
495 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
496 | ||
497 | return hpet_set_periodic(evt, hdev->num); | |
498 | } | |
499 | ||
500 | static int hpet_msi_resume(struct clock_event_device *evt) | |
501 | { | |
502 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
bb68cfe2 TG |
503 | struct irq_data *data = irq_get_irq_data(hdev->irq); |
504 | struct msi_msg msg; | |
c8b5db7d | 505 | |
bb68cfe2 TG |
506 | /* Restore the MSI msg and unmask the interrupt */ |
507 | irq_chip_compose_msi_msg(data, &msg); | |
508 | hpet_msi_write(hdev, &msg); | |
509 | hpet_msi_unmask(data); | |
510 | return 0; | |
26afe5f2 | 511 | } |
512 | ||
513 | static int hpet_msi_next_event(unsigned long delta, | |
514 | struct clock_event_device *evt) | |
515 | { | |
516 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
517 | return hpet_next_event(delta, evt, hdev->num); | |
518 | } | |
519 | ||
26afe5f2 | 520 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) |
521 | { | |
522 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
523 | struct clock_event_device *hevt = &dev->evt; | |
524 | ||
525 | if (!hevt->event_handler) { | |
526 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
527 | dev->num); | |
528 | return IRQ_HANDLED; | |
529 | } | |
530 | ||
531 | hevt->event_handler(hevt); | |
532 | return IRQ_HANDLED; | |
533 | } | |
534 | ||
535 | static int hpet_setup_irq(struct hpet_dev *dev) | |
536 | { | |
537 | ||
538 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
d20d2efb | 539 | IRQF_TIMER | IRQF_NOBALANCING, |
507fa3a3 | 540 | dev->name, dev)) |
26afe5f2 | 541 | return -1; |
542 | ||
543 | disable_irq(dev->irq); | |
0de26520 | 544 | irq_set_affinity(dev->irq, cpumask_of(dev->cpu)); |
26afe5f2 | 545 | enable_irq(dev->irq); |
546 | ||
c81bba49 YL |
547 | printk(KERN_DEBUG "hpet: %s irq %d for MSI\n", |
548 | dev->name, dev->irq); | |
549 | ||
26afe5f2 | 550 | return 0; |
551 | } | |
552 | ||
553 | /* This should be called in specific @cpu */ | |
554 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
555 | { | |
556 | struct clock_event_device *evt = &hdev->evt; | |
26afe5f2 | 557 | |
558 | WARN_ON(cpu != smp_processor_id()); | |
559 | if (!(hdev->flags & HPET_DEV_VALID)) | |
560 | return; | |
561 | ||
26afe5f2 | 562 | hdev->cpu = cpu; |
563 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
564 | evt->name = hdev->name; | |
565 | hpet_setup_irq(hdev); | |
566 | evt->irq = hdev->irq; | |
567 | ||
568 | evt->rating = 110; | |
569 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
c8b5db7d | 570 | if (hdev->flags & HPET_DEV_PERI_CAP) { |
26afe5f2 | 571 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; |
c8b5db7d VK |
572 | evt->set_state_periodic = hpet_msi_set_periodic; |
573 | } | |
26afe5f2 | 574 | |
c8b5db7d VK |
575 | evt->set_state_shutdown = hpet_msi_shutdown; |
576 | evt->set_state_oneshot = hpet_msi_set_oneshot; | |
577 | evt->tick_resume = hpet_msi_resume; | |
26afe5f2 | 578 | evt->set_next_event = hpet_msi_next_event; |
320ab2b0 | 579 | evt->cpumask = cpumask_of(hdev->cpu); |
ab0e08f1 TG |
580 | |
581 | clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, | |
582 | 0x7FFFFFFF); | |
26afe5f2 | 583 | } |
584 | ||
585 | #ifdef CONFIG_HPET | |
586 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
587 | #define RESERVE_TIMERS 1 | |
588 | #else | |
589 | #define RESERVE_TIMERS 0 | |
590 | #endif | |
5f79f2f2 VP |
591 | |
592 | static void hpet_msi_capability_lookup(unsigned int start_timer) | |
26afe5f2 | 593 | { |
594 | unsigned int id; | |
595 | unsigned int num_timers; | |
596 | unsigned int num_timers_used = 0; | |
3cb96f0c | 597 | int i, irq; |
26afe5f2 | 598 | |
73472a46 PV |
599 | if (hpet_msi_disable) |
600 | return; | |
601 | ||
39fe05e5 SL |
602 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
603 | return; | |
26afe5f2 | 604 | id = hpet_readl(HPET_ID); |
605 | ||
606 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
607 | num_timers++; /* Value read out starts from 0 */ | |
b98103a5 | 608 | hpet_print_config(); |
26afe5f2 | 609 | |
3cb96f0c JL |
610 | hpet_domain = hpet_create_irq_domain(hpet_blockid); |
611 | if (!hpet_domain) | |
612 | return; | |
613 | ||
26afe5f2 | 614 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); |
615 | if (!hpet_devs) | |
616 | return; | |
617 | ||
618 | hpet_num_timers = num_timers; | |
619 | ||
620 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
621 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
5946fa3d | 622 | unsigned int cfg = hpet_readl(HPET_Tn_CFG(i)); |
26afe5f2 | 623 | |
624 | /* Only consider HPET timer with MSI support */ | |
625 | if (!(cfg & HPET_TN_FSB_CAP)) | |
626 | continue; | |
627 | ||
cb17b2a6 TG |
628 | hdev->flags = 0; |
629 | if (cfg & HPET_TN_PERIODIC_CAP) | |
630 | hdev->flags |= HPET_DEV_PERI_CAP; | |
631 | sprintf(hdev->name, "hpet%d", i); | |
632 | hdev->num = i; | |
633 | ||
3cb96f0c | 634 | irq = hpet_assign_irq(hpet_domain, hdev, hdev->num); |
bafac298 | 635 | if (irq <= 0) |
3cb96f0c JL |
636 | continue; |
637 | ||
3cb96f0c | 638 | hdev->irq = irq; |
26afe5f2 | 639 | hdev->flags |= HPET_DEV_FSB_CAP; |
640 | hdev->flags |= HPET_DEV_VALID; | |
641 | num_timers_used++; | |
642 | if (num_timers_used == num_possible_cpus()) | |
643 | break; | |
644 | } | |
645 | ||
646 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
647 | num_timers, num_timers_used); | |
648 | } | |
649 | ||
5f79f2f2 VP |
650 | #ifdef CONFIG_HPET |
651 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
652 | { | |
653 | int i; | |
654 | ||
655 | if (!hpet_devs) | |
656 | return; | |
657 | ||
658 | for (i = 0; i < hpet_num_timers; i++) { | |
659 | struct hpet_dev *hdev = &hpet_devs[i]; | |
660 | ||
661 | if (!(hdev->flags & HPET_DEV_VALID)) | |
662 | continue; | |
663 | ||
664 | hd->hd_irq[hdev->num] = hdev->irq; | |
665 | hpet_reserve_timer(hd, hdev->num); | |
666 | } | |
667 | } | |
668 | #endif | |
669 | ||
26afe5f2 | 670 | static struct hpet_dev *hpet_get_unused_timer(void) |
671 | { | |
672 | int i; | |
673 | ||
674 | if (!hpet_devs) | |
675 | return NULL; | |
676 | ||
677 | for (i = 0; i < hpet_num_timers; i++) { | |
678 | struct hpet_dev *hdev = &hpet_devs[i]; | |
679 | ||
680 | if (!(hdev->flags & HPET_DEV_VALID)) | |
681 | continue; | |
682 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
683 | (unsigned long *)&hdev->flags)) | |
684 | continue; | |
685 | return hdev; | |
686 | } | |
687 | return NULL; | |
688 | } | |
689 | ||
690 | struct hpet_work_struct { | |
691 | struct delayed_work work; | |
692 | struct completion complete; | |
693 | }; | |
694 | ||
695 | static void hpet_work(struct work_struct *w) | |
696 | { | |
697 | struct hpet_dev *hdev; | |
698 | int cpu = smp_processor_id(); | |
699 | struct hpet_work_struct *hpet_work; | |
700 | ||
701 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
702 | ||
703 | hdev = hpet_get_unused_timer(); | |
704 | if (hdev) | |
705 | init_one_hpet_msi_clockevent(hdev, cpu); | |
706 | ||
707 | complete(&hpet_work->complete); | |
708 | } | |
709 | ||
48d7f6c7 | 710 | static int hpet_cpuhp_online(unsigned int cpu) |
26afe5f2 | 711 | { |
26afe5f2 | 712 | struct hpet_work_struct work; |
48d7f6c7 SAS |
713 | |
714 | INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work); | |
715 | init_completion(&work.complete); | |
716 | /* FIXME: add schedule_work_on() */ | |
717 | schedule_delayed_work_on(cpu, &work.work, 0); | |
718 | wait_for_completion(&work.complete); | |
719 | destroy_delayed_work_on_stack(&work.work); | |
720 | return 0; | |
721 | } | |
722 | ||
723 | static int hpet_cpuhp_dead(unsigned int cpu) | |
724 | { | |
26afe5f2 | 725 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); |
726 | ||
48d7f6c7 SAS |
727 | if (!hdev) |
728 | return 0; | |
729 | free_irq(hdev->irq, hdev); | |
730 | hdev->flags &= ~HPET_DEV_USED; | |
731 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
732 | return 0; | |
26afe5f2 | 733 | } |
734 | #else | |
735 | ||
5f79f2f2 VP |
736 | static void hpet_msi_capability_lookup(unsigned int start_timer) |
737 | { | |
738 | return; | |
739 | } | |
740 | ||
741 | #ifdef CONFIG_HPET | |
742 | static void hpet_reserve_msi_timers(struct hpet_data *hd) | |
26afe5f2 | 743 | { |
744 | return; | |
745 | } | |
5f79f2f2 | 746 | #endif |
26afe5f2 | 747 | |
48d7f6c7 SAS |
748 | #define hpet_cpuhp_online NULL |
749 | #define hpet_cpuhp_dead NULL | |
26afe5f2 | 750 | |
751 | #endif | |
752 | ||
6bb74df4 JS |
753 | /* |
754 | * Clock source related code | |
755 | */ | |
f99fd22e WL |
756 | #if defined(CONFIG_SMP) && defined(CONFIG_64BIT) |
757 | /* | |
758 | * Reading the HPET counter is a very slow operation. If a large number of | |
759 | * CPUs are trying to access the HPET counter simultaneously, it can cause | |
760 | * massive delay and slow down system performance dramatically. This may | |
761 | * happen when HPET is the default clock source instead of TSC. For a | |
762 | * really large system with hundreds of CPUs, the slowdown may be so | |
763 | * severe that it may actually crash the system because of a NMI watchdog | |
764 | * soft lockup, for example. | |
765 | * | |
766 | * If multiple CPUs are trying to access the HPET counter at the same time, | |
767 | * we don't actually need to read the counter multiple times. Instead, the | |
768 | * other CPUs can use the counter value read by the first CPU in the group. | |
769 | * | |
770 | * This special feature is only enabled on x86-64 systems. It is unlikely | |
771 | * that 32-bit x86 systems will have enough CPUs to require this feature | |
772 | * with its associated locking overhead. And we also need 64-bit atomic | |
773 | * read. | |
774 | * | |
775 | * The lock and the hpet value are stored together and can be read in a | |
776 | * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t | |
777 | * is 32 bits in size. | |
778 | */ | |
779 | union hpet_lock { | |
780 | struct { | |
781 | arch_spinlock_t lock; | |
782 | u32 value; | |
783 | }; | |
784 | u64 lockval; | |
785 | }; | |
786 | ||
787 | static union hpet_lock hpet __cacheline_aligned = { | |
788 | { .lock = __ARCH_SPIN_LOCK_UNLOCKED, }, | |
789 | }; | |
790 | ||
a5a1d1c2 | 791 | static u64 read_hpet(struct clocksource *cs) |
f99fd22e WL |
792 | { |
793 | unsigned long flags; | |
794 | union hpet_lock old, new; | |
795 | ||
796 | BUILD_BUG_ON(sizeof(union hpet_lock) != 8); | |
797 | ||
798 | /* | |
799 | * Read HPET directly if in NMI. | |
800 | */ | |
801 | if (in_nmi()) | |
a5a1d1c2 | 802 | return (u64)hpet_readl(HPET_COUNTER); |
f99fd22e WL |
803 | |
804 | /* | |
805 | * Read the current state of the lock and HPET value atomically. | |
806 | */ | |
807 | old.lockval = READ_ONCE(hpet.lockval); | |
808 | ||
809 | if (arch_spin_is_locked(&old.lock)) | |
810 | goto contended; | |
811 | ||
812 | local_irq_save(flags); | |
813 | if (arch_spin_trylock(&hpet.lock)) { | |
814 | new.value = hpet_readl(HPET_COUNTER); | |
815 | /* | |
816 | * Use WRITE_ONCE() to prevent store tearing. | |
817 | */ | |
818 | WRITE_ONCE(hpet.value, new.value); | |
819 | arch_spin_unlock(&hpet.lock); | |
820 | local_irq_restore(flags); | |
a5a1d1c2 | 821 | return (u64)new.value; |
f99fd22e WL |
822 | } |
823 | local_irq_restore(flags); | |
824 | ||
825 | contended: | |
826 | /* | |
827 | * Contended case | |
828 | * -------------- | |
829 | * Wait until the HPET value change or the lock is free to indicate | |
830 | * its value is up-to-date. | |
831 | * | |
832 | * It is possible that old.value has already contained the latest | |
833 | * HPET value while the lock holder was in the process of releasing | |
834 | * the lock. Checking for lock state change will enable us to return | |
835 | * the value immediately instead of waiting for the next HPET reader | |
836 | * to come along. | |
837 | */ | |
838 | do { | |
839 | cpu_relax(); | |
840 | new.lockval = READ_ONCE(hpet.lockval); | |
841 | } while ((new.value == old.value) && arch_spin_is_locked(&new.lock)); | |
842 | ||
a5a1d1c2 | 843 | return (u64)new.value; |
f99fd22e WL |
844 | } |
845 | #else | |
846 | /* | |
847 | * For UP or 32-bit. | |
848 | */ | |
a5a1d1c2 | 849 | static u64 read_hpet(struct clocksource *cs) |
6bb74df4 | 850 | { |
a5a1d1c2 | 851 | return (u64)hpet_readl(HPET_COUNTER); |
6bb74df4 | 852 | } |
f99fd22e | 853 | #endif |
6bb74df4 JS |
854 | |
855 | static struct clocksource clocksource_hpet = { | |
856 | .name = "hpet", | |
857 | .rating = 250, | |
858 | .read = read_hpet, | |
859 | .mask = HPET_MASK, | |
6bb74df4 | 860 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8d6f0c82 | 861 | .resume = hpet_resume_counter, |
6bb74df4 JS |
862 | }; |
863 | ||
610bf2f1 | 864 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 865 | { |
6fd592da | 866 | u64 start, now; |
a5a1d1c2 | 867 | u64 t1; |
e9e2cdb4 | 868 | |
e9e2cdb4 | 869 | /* Start the counter */ |
8d6f0c82 | 870 | hpet_restart_counter(); |
e9e2cdb4 | 871 | |
075bcd1f | 872 | /* Verify whether hpet counter works */ |
8e19608e | 873 | t1 = hpet_readl(HPET_COUNTER); |
4ea1636b | 874 | start = rdtsc(); |
075bcd1f TG |
875 | |
876 | /* | |
877 | * We don't know the TSC frequency yet, but waiting for | |
878 | * 200000 TSC cycles is safe: | |
879 | * 4 GHz == 50us | |
880 | * 1 GHz == 200us | |
881 | */ | |
882 | do { | |
883 | rep_nop(); | |
4ea1636b | 884 | now = rdtsc(); |
075bcd1f TG |
885 | } while ((now - start) < 200000UL); |
886 | ||
8e19608e | 887 | if (t1 == hpet_readl(HPET_COUNTER)) { |
075bcd1f TG |
888 | printk(KERN_WARNING |
889 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 890 | return -ENODEV; |
075bcd1f TG |
891 | } |
892 | ||
f12a15be | 893 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); |
610bf2f1 VP |
894 | return 0; |
895 | } | |
896 | ||
396e2c6f JB |
897 | static u32 *hpet_boot_cfg; |
898 | ||
b02a7f22 PM |
899 | /** |
900 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
901 | */ |
902 | int __init hpet_enable(void) | |
903 | { | |
396e2c6f | 904 | u32 hpet_period, cfg, id; |
ab0e08f1 | 905 | u64 freq; |
396e2c6f | 906 | unsigned int i, last; |
610bf2f1 VP |
907 | |
908 | if (!is_hpet_capable()) | |
909 | return 0; | |
910 | ||
911 | hpet_set_mapping(); | |
912 | ||
913 | /* | |
914 | * Read the period and check for a sane value: | |
915 | */ | |
916 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
917 | |
918 | /* | |
919 | * AMD SB700 based systems with spread spectrum enabled use a | |
920 | * SMM based HPET emulation to provide proper frequency | |
921 | * setting. The SMM code is initialized with the first HPET | |
922 | * register access and takes some time to complete. During | |
923 | * this time the config register reads 0xffffffff. We check | |
924 | * for max. 1000 loops whether the config register reads a non | |
925 | * 0xffffffff value to make sure that HPET is up and running | |
926 | * before we go further. A counting loop is safe, as the HPET | |
927 | * access takes thousands of CPU cycles. On non SB700 based | |
928 | * machines this check is only done once and has no side | |
929 | * effects. | |
930 | */ | |
931 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
932 | if (i == 1000) { | |
933 | printk(KERN_WARNING | |
934 | "HPET config register value = 0xFFFFFFFF. " | |
935 | "Disabling HPET\n"); | |
936 | goto out_nohpet; | |
937 | } | |
938 | } | |
939 | ||
610bf2f1 VP |
940 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
941 | goto out_nohpet; | |
942 | ||
ab0e08f1 TG |
943 | /* |
944 | * The period is a femto seconds value. Convert it to a | |
945 | * frequency. | |
946 | */ | |
947 | freq = FSEC_PER_SEC; | |
948 | do_div(freq, hpet_period); | |
949 | hpet_freq = freq; | |
950 | ||
610bf2f1 VP |
951 | /* |
952 | * Read the HPET ID register to retrieve the IRQ routing | |
953 | * information and the number of channels | |
954 | */ | |
955 | id = hpet_readl(HPET_ID); | |
b98103a5 | 956 | hpet_print_config(); |
610bf2f1 | 957 | |
396e2c6f JB |
958 | last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT; |
959 | ||
610bf2f1 VP |
960 | #ifdef CONFIG_HPET_EMULATE_RTC |
961 | /* | |
962 | * The legacy routing mode needs at least two channels, tick timer | |
963 | * and the rtc emulation channel. | |
964 | */ | |
396e2c6f | 965 | if (!last) |
610bf2f1 VP |
966 | goto out_nohpet; |
967 | #endif | |
968 | ||
396e2c6f JB |
969 | cfg = hpet_readl(HPET_CFG); |
970 | hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg), | |
971 | GFP_KERNEL); | |
972 | if (hpet_boot_cfg) | |
973 | *hpet_boot_cfg = cfg; | |
974 | else | |
975 | pr_warn("HPET initial state will not be saved\n"); | |
976 | cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); | |
1b38a3a1 | 977 | hpet_writel(cfg, HPET_CFG); |
396e2c6f JB |
978 | if (cfg) |
979 | pr_warn("HPET: Unrecognized bits %#x set in global cfg\n", | |
980 | cfg); | |
981 | ||
982 | for (i = 0; i <= last; ++i) { | |
983 | cfg = hpet_readl(HPET_Tn_CFG(i)); | |
984 | if (hpet_boot_cfg) | |
985 | hpet_boot_cfg[i + 1] = cfg; | |
986 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); | |
987 | hpet_writel(cfg, HPET_Tn_CFG(i)); | |
988 | cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP | |
989 | | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE | |
990 | | HPET_TN_FSB | HPET_TN_FSB_CAP); | |
991 | if (cfg) | |
992 | pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n", | |
993 | cfg, i); | |
994 | } | |
995 | hpet_print_config(); | |
996 | ||
610bf2f1 VP |
997 | if (hpet_clocksource_register()) |
998 | goto out_nohpet; | |
999 | ||
e9e2cdb4 | 1000 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 1001 | hpet_legacy_clockevent_register(); |
e9e2cdb4 TG |
1002 | return 1; |
1003 | } | |
1004 | return 0; | |
5d0cf410 | 1005 | |
e9e2cdb4 | 1006 | out_nohpet: |
06a24dec | 1007 | hpet_clear_mapping(); |
bacbe999 | 1008 | hpet_address = 0; |
e9e2cdb4 TG |
1009 | return 0; |
1010 | } | |
1011 | ||
28769149 TG |
1012 | /* |
1013 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
1014 | * | |
1015 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
1016 | * but on x86_64 it is necessary ! | |
1017 | */ | |
1018 | static __init int hpet_late_init(void) | |
1019 | { | |
48d7f6c7 | 1020 | int ret; |
26afe5f2 | 1021 | |
59c69f2a | 1022 | if (boot_hpet_disable) |
28769149 TG |
1023 | return -ENODEV; |
1024 | ||
59c69f2a VP |
1025 | if (!hpet_address) { |
1026 | if (!force_hpet_address) | |
1027 | return -ENODEV; | |
1028 | ||
1029 | hpet_address = force_hpet_address; | |
1030 | hpet_enable(); | |
59c69f2a VP |
1031 | } |
1032 | ||
39c04b55 JF |
1033 | if (!hpet_virt_address) |
1034 | return -ENODEV; | |
1035 | ||
39fe05e5 SL |
1036 | if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP) |
1037 | hpet_msi_capability_lookup(2); | |
1038 | else | |
1039 | hpet_msi_capability_lookup(0); | |
1040 | ||
28769149 | 1041 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
b98103a5 | 1042 | hpet_print_config(); |
59c69f2a | 1043 | |
73472a46 PV |
1044 | if (hpet_msi_disable) |
1045 | return 0; | |
1046 | ||
39fe05e5 SL |
1047 | if (boot_cpu_has(X86_FEATURE_ARAT)) |
1048 | return 0; | |
1049 | ||
26afe5f2 | 1050 | /* This notifier should be called after workqueue is ready */ |
73c1b41e | 1051 | ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online", |
48d7f6c7 SAS |
1052 | hpet_cpuhp_online, NULL); |
1053 | if (ret) | |
1054 | return ret; | |
73c1b41e | 1055 | ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL, |
48d7f6c7 SAS |
1056 | hpet_cpuhp_dead); |
1057 | if (ret) | |
1058 | goto err_cpuhp; | |
28769149 | 1059 | return 0; |
48d7f6c7 SAS |
1060 | |
1061 | err_cpuhp: | |
1062 | cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE); | |
1063 | return ret; | |
28769149 TG |
1064 | } |
1065 | fs_initcall(hpet_late_init); | |
1066 | ||
c86c7fbc OH |
1067 | void hpet_disable(void) |
1068 | { | |
ff487808 | 1069 | if (is_hpet_capable() && hpet_virt_address) { |
396e2c6f | 1070 | unsigned int cfg = hpet_readl(HPET_CFG), id, last; |
c86c7fbc | 1071 | |
396e2c6f JB |
1072 | if (hpet_boot_cfg) |
1073 | cfg = *hpet_boot_cfg; | |
1074 | else if (hpet_legacy_int_enabled) { | |
c86c7fbc | 1075 | cfg &= ~HPET_CFG_LEGACY; |
3d45ac4b | 1076 | hpet_legacy_int_enabled = false; |
c86c7fbc OH |
1077 | } |
1078 | cfg &= ~HPET_CFG_ENABLE; | |
1079 | hpet_writel(cfg, HPET_CFG); | |
396e2c6f JB |
1080 | |
1081 | if (!hpet_boot_cfg) | |
1082 | return; | |
1083 | ||
1084 | id = hpet_readl(HPET_ID); | |
1085 | last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
1086 | ||
1087 | for (id = 0; id <= last; ++id) | |
1088 | hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id)); | |
1089 | ||
1090 | if (*hpet_boot_cfg & HPET_CFG_ENABLE) | |
1091 | hpet_writel(*hpet_boot_cfg, HPET_CFG); | |
c86c7fbc OH |
1092 | } |
1093 | } | |
1094 | ||
e9e2cdb4 TG |
1095 | #ifdef CONFIG_HPET_EMULATE_RTC |
1096 | ||
1097 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
1098 | * is enabled, we support RTC interrupt functionality in software. | |
1099 | * RTC has 3 kinds of interrupts: | |
1100 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
1101 | * is updated | |
1102 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
1103 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
1104 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
1105 | * (1) and (2) above are implemented using polling at a frequency of | |
1106 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
1107 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
1108 | * For (3), we use interrupts at 64Hz or user specified periodic | |
1109 | * frequency, whichever is higher. | |
1110 | */ | |
1111 | #include <linux/mc146818rtc.h> | |
1112 | #include <linux/rtc.h> | |
1113 | ||
1114 | #define DEFAULT_RTC_INT_FREQ 64 | |
1115 | #define DEFAULT_RTC_SHIFT 6 | |
1116 | #define RTC_NUM_INTS 1 | |
1117 | ||
1118 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 1119 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
1120 | static struct rtc_time hpet_alarm_time; |
1121 | static unsigned long hpet_pie_count; | |
ff08f76d | 1122 | static u32 hpet_t1_cmp; |
5946fa3d JB |
1123 | static u32 hpet_default_delta; |
1124 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
1125 | static unsigned long hpet_pie_limit; |
1126 | ||
1bdbdaac BW |
1127 | static rtc_irq_handler irq_handler; |
1128 | ||
ff08f76d PE |
1129 | /* |
1130 | * Check that the hpet counter c1 is ahead of the c2 | |
1131 | */ | |
1132 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
1133 | { | |
1134 | return (s32)(c2 - c1) < 0; | |
1135 | } | |
1136 | ||
1bdbdaac BW |
1137 | /* |
1138 | * Registers a IRQ handler. | |
1139 | */ | |
1140 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
1141 | { | |
1142 | if (!is_hpet_enabled()) | |
1143 | return -ENODEV; | |
1144 | if (irq_handler) | |
1145 | return -EBUSY; | |
1146 | ||
1147 | irq_handler = handler; | |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
1152 | ||
1153 | /* | |
1154 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
1155 | * and does cleanup. | |
1156 | */ | |
1157 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
1158 | { | |
1159 | if (!is_hpet_enabled()) | |
1160 | return; | |
1161 | ||
1162 | irq_handler = NULL; | |
1163 | hpet_rtc_flags = 0; | |
1164 | } | |
1165 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1166 | ||
e9e2cdb4 TG |
1167 | /* |
1168 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
1169 | * is not supported by all HPET implementations for timer 1. | |
1170 | * | |
1171 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1172 | */ | |
1173 | int hpet_rtc_timer_init(void) | |
1174 | { | |
5946fa3d JB |
1175 | unsigned int cfg, cnt, delta; |
1176 | unsigned long flags; | |
e9e2cdb4 TG |
1177 | |
1178 | if (!is_hpet_enabled()) | |
1179 | return 0; | |
1180 | ||
1181 | if (!hpet_default_delta) { | |
1182 | uint64_t clc; | |
1183 | ||
1184 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1185 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1186 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1187 | } |
1188 | ||
1189 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1190 | delta = hpet_default_delta; | |
1191 | else | |
1192 | delta = hpet_pie_delta; | |
1193 | ||
1194 | local_irq_save(flags); | |
1195 | ||
1196 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1197 | hpet_writel(cnt, HPET_T1_CMP); | |
1198 | hpet_t1_cmp = cnt; | |
1199 | ||
1200 | cfg = hpet_readl(HPET_T1_CFG); | |
1201 | cfg &= ~HPET_TN_PERIODIC; | |
1202 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1203 | hpet_writel(cfg, HPET_T1_CFG); | |
1204 | ||
1205 | local_irq_restore(flags); | |
1206 | ||
1207 | return 1; | |
1208 | } | |
1bdbdaac | 1209 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 | 1210 | |
2ded6e6a ML |
1211 | static void hpet_disable_rtc_channel(void) |
1212 | { | |
3d45ac4b | 1213 | u32 cfg = hpet_readl(HPET_T1_CFG); |
2ded6e6a ML |
1214 | cfg &= ~HPET_TN_ENABLE; |
1215 | hpet_writel(cfg, HPET_T1_CFG); | |
1216 | } | |
1217 | ||
e9e2cdb4 TG |
1218 | /* |
1219 | * The functions below are called from rtc driver. | |
1220 | * Return 0 if HPET is not being used. | |
1221 | * Otherwise do the necessary changes and return 1. | |
1222 | */ | |
1223 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1224 | { | |
1225 | if (!is_hpet_enabled()) | |
1226 | return 0; | |
1227 | ||
1228 | hpet_rtc_flags &= ~bit_mask; | |
2ded6e6a ML |
1229 | if (unlikely(!hpet_rtc_flags)) |
1230 | hpet_disable_rtc_channel(); | |
1231 | ||
e9e2cdb4 TG |
1232 | return 1; |
1233 | } | |
1bdbdaac | 1234 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1235 | |
1236 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1237 | { | |
1238 | unsigned long oldbits = hpet_rtc_flags; | |
1239 | ||
1240 | if (!is_hpet_enabled()) | |
1241 | return 0; | |
1242 | ||
1243 | hpet_rtc_flags |= bit_mask; | |
1244 | ||
7e2a31da DB |
1245 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1246 | hpet_prev_update_sec = -1; | |
1247 | ||
e9e2cdb4 TG |
1248 | if (!oldbits) |
1249 | hpet_rtc_timer_init(); | |
1250 | ||
1251 | return 1; | |
1252 | } | |
1bdbdaac | 1253 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
1254 | |
1255 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
1256 | unsigned char sec) | |
1257 | { | |
1258 | if (!is_hpet_enabled()) | |
1259 | return 0; | |
1260 | ||
1261 | hpet_alarm_time.tm_hour = hrs; | |
1262 | hpet_alarm_time.tm_min = min; | |
1263 | hpet_alarm_time.tm_sec = sec; | |
1264 | ||
1265 | return 1; | |
1266 | } | |
1bdbdaac | 1267 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1268 | |
1269 | int hpet_set_periodic_freq(unsigned long freq) | |
1270 | { | |
1271 | uint64_t clc; | |
1272 | ||
1273 | if (!is_hpet_enabled()) | |
1274 | return 0; | |
1275 | ||
1276 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1277 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1278 | else { | |
1279 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1280 | do_div(clc, freq); | |
1281 | clc >>= hpet_clockevent.shift; | |
5946fa3d | 1282 | hpet_pie_delta = clc; |
b4a5e8a1 | 1283 | hpet_pie_limit = 0; |
e9e2cdb4 TG |
1284 | } |
1285 | return 1; | |
1286 | } | |
1bdbdaac | 1287 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1288 | |
1289 | int hpet_rtc_dropped_irq(void) | |
1290 | { | |
1291 | return is_hpet_enabled(); | |
1292 | } | |
1bdbdaac | 1293 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1294 | |
1295 | static void hpet_rtc_timer_reinit(void) | |
1296 | { | |
2ded6e6a | 1297 | unsigned int delta; |
e9e2cdb4 TG |
1298 | int lost_ints = -1; |
1299 | ||
2ded6e6a ML |
1300 | if (unlikely(!hpet_rtc_flags)) |
1301 | hpet_disable_rtc_channel(); | |
e9e2cdb4 TG |
1302 | |
1303 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1304 | delta = hpet_default_delta; | |
1305 | else | |
1306 | delta = hpet_pie_delta; | |
1307 | ||
1308 | /* | |
1309 | * Increment the comparator value until we are ahead of the | |
1310 | * current count. | |
1311 | */ | |
1312 | do { | |
1313 | hpet_t1_cmp += delta; | |
1314 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1315 | lost_ints++; | |
ff08f76d | 1316 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1317 | |
1318 | if (lost_ints) { | |
1319 | if (hpet_rtc_flags & RTC_PIE) | |
1320 | hpet_pie_count += lost_ints; | |
1321 | if (printk_ratelimit()) | |
7e2a31da | 1322 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1323 | lost_ints); |
1324 | } | |
1325 | } | |
1326 | ||
1327 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1328 | { | |
1329 | struct rtc_time curr_time; | |
1330 | unsigned long rtc_int_flag = 0; | |
1331 | ||
1332 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1333 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1334 | |
1335 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
22cc1ca3 | 1336 | mc146818_get_time(&curr_time); |
e9e2cdb4 TG |
1337 | |
1338 | if (hpet_rtc_flags & RTC_UIE && | |
1339 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1340 | if (hpet_prev_update_sec >= 0) |
1341 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1342 | hpet_prev_update_sec = curr_time.tm_sec; |
1343 | } | |
1344 | ||
1345 | if (hpet_rtc_flags & RTC_PIE && | |
1346 | ++hpet_pie_count >= hpet_pie_limit) { | |
1347 | rtc_int_flag |= RTC_PF; | |
1348 | hpet_pie_count = 0; | |
1349 | } | |
1350 | ||
8ee291f8 | 1351 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1352 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1353 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1354 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1355 | rtc_int_flag |= RTC_AF; | |
1356 | ||
1357 | if (rtc_int_flag) { | |
1358 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1359 | if (irq_handler) |
1360 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1361 | } |
1362 | return IRQ_HANDLED; | |
1363 | } | |
1bdbdaac | 1364 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1365 | #endif |