]>
Commit | Line | Data |
---|---|---|
5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
5d0cf410 JS |
3 | #include <linux/errno.h> |
4 | #include <linux/hpet.h> | |
5 | #include <linux/init.h> | |
399afa4f ML |
6 | #include <linux/sysdev.h> |
7 | #include <linux/pm.h> | |
0655d7c3 | 8 | #include <linux/delay.h> |
5d0cf410 JS |
9 | |
10 | #include <asm/hpet.h> | |
11 | #include <asm/io.h> | |
12 | ||
e9e2cdb4 TG |
13 | extern struct clock_event_device *global_clock_event; |
14 | ||
7f9f303a | 15 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 JS |
16 | #define HPET_SHIFT 22 |
17 | ||
18 | /* FSEC = 10^-15 NSEC = 10^-9 */ | |
19 | #define FSEC_PER_NSEC 1000000 | |
20 | ||
e9e2cdb4 TG |
21 | /* |
22 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
23 | */ | |
24 | unsigned long hpet_address; | |
25 | static void __iomem * hpet_virt_address; | |
26 | ||
27 | static inline unsigned long hpet_readl(unsigned long a) | |
28 | { | |
29 | return readl(hpet_virt_address + a); | |
30 | } | |
31 | ||
32 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
33 | { | |
34 | writel(d, hpet_virt_address + a); | |
35 | } | |
36 | ||
37 | /* | |
38 | * HPET command line enable / disable | |
39 | */ | |
40 | static int boot_hpet_disable; | |
41 | ||
42 | static int __init hpet_setup(char* str) | |
43 | { | |
44 | if (str) { | |
45 | if (!strncmp("disable", str, 7)) | |
46 | boot_hpet_disable = 1; | |
47 | } | |
48 | return 1; | |
49 | } | |
50 | __setup("hpet=", hpet_setup); | |
51 | ||
52 | static inline int is_hpet_capable(void) | |
53 | { | |
54 | return (!boot_hpet_disable && hpet_address); | |
55 | } | |
56 | ||
57 | /* | |
58 | * HPET timer interrupt enable / disable | |
59 | */ | |
60 | static int hpet_legacy_int_enabled; | |
61 | ||
62 | /** | |
63 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
64 | */ | |
65 | int is_hpet_enabled(void) | |
66 | { | |
67 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
68 | } | |
69 | ||
70 | /* | |
71 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
72 | * timer 0 and timer 1 in case of RTC emulation. | |
73 | */ | |
74 | #ifdef CONFIG_HPET | |
75 | static void hpet_reserve_platform_timers(unsigned long id) | |
76 | { | |
77 | struct hpet __iomem *hpet = hpet_virt_address; | |
78 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; | |
79 | unsigned int nrtimers, i; | |
80 | struct hpet_data hd; | |
81 | ||
82 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
83 | ||
84 | memset(&hd, 0, sizeof (hd)); | |
85 | hd.hd_phys_address = hpet_address; | |
86 | hd.hd_address = hpet_virt_address; | |
87 | hd.hd_nirqs = nrtimers; | |
88 | hd.hd_flags = HPET_DATA_PLATFORM; | |
89 | hpet_reserve_timer(&hd, 0); | |
90 | ||
91 | #ifdef CONFIG_HPET_EMULATE_RTC | |
92 | hpet_reserve_timer(&hd, 1); | |
93 | #endif | |
94 | ||
95 | hd.hd_irq[0] = HPET_LEGACY_8254; | |
96 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
97 | ||
98 | for (i = 2; i < nrtimers; timer++, i++) | |
99 | hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >> | |
100 | Tn_INT_ROUTE_CNF_SHIFT; | |
101 | ||
102 | hpet_alloc(&hd); | |
103 | ||
104 | } | |
105 | #else | |
106 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
107 | #endif | |
108 | ||
109 | /* | |
110 | * Common hpet info | |
111 | */ | |
112 | static unsigned long hpet_period; | |
113 | ||
114 | static void hpet_set_mode(enum clock_event_mode mode, | |
115 | struct clock_event_device *evt); | |
116 | static int hpet_next_event(unsigned long delta, | |
117 | struct clock_event_device *evt); | |
118 | ||
119 | /* | |
120 | * The hpet clock event device | |
121 | */ | |
122 | static struct clock_event_device hpet_clockevent = { | |
123 | .name = "hpet", | |
124 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
125 | .set_mode = hpet_set_mode, | |
126 | .set_next_event = hpet_next_event, | |
127 | .shift = 32, | |
128 | .irq = 0, | |
129 | }; | |
130 | ||
131 | static void hpet_start_counter(void) | |
132 | { | |
133 | unsigned long cfg = hpet_readl(HPET_CFG); | |
134 | ||
135 | cfg &= ~HPET_CFG_ENABLE; | |
136 | hpet_writel(cfg, HPET_CFG); | |
137 | hpet_writel(0, HPET_COUNTER); | |
138 | hpet_writel(0, HPET_COUNTER + 4); | |
139 | cfg |= HPET_CFG_ENABLE; | |
140 | hpet_writel(cfg, HPET_CFG); | |
141 | } | |
142 | ||
143 | static void hpet_enable_int(void) | |
144 | { | |
145 | unsigned long cfg = hpet_readl(HPET_CFG); | |
146 | ||
147 | cfg |= HPET_CFG_LEGACY; | |
148 | hpet_writel(cfg, HPET_CFG); | |
149 | hpet_legacy_int_enabled = 1; | |
150 | } | |
151 | ||
152 | static void hpet_set_mode(enum clock_event_mode mode, | |
153 | struct clock_event_device *evt) | |
154 | { | |
155 | unsigned long cfg, cmp, now; | |
156 | uint64_t delta; | |
157 | ||
158 | switch(mode) { | |
159 | case CLOCK_EVT_MODE_PERIODIC: | |
160 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult; | |
161 | delta >>= hpet_clockevent.shift; | |
162 | now = hpet_readl(HPET_COUNTER); | |
163 | cmp = now + (unsigned long) delta; | |
164 | cfg = hpet_readl(HPET_T0_CFG); | |
165 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | | |
166 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
167 | hpet_writel(cfg, HPET_T0_CFG); | |
168 | /* | |
169 | * The first write after writing TN_SETVAL to the | |
170 | * config register sets the counter value, the second | |
171 | * write sets the period. | |
172 | */ | |
173 | hpet_writel(cmp, HPET_T0_CMP); | |
174 | udelay(1); | |
175 | hpet_writel((unsigned long) delta, HPET_T0_CMP); | |
176 | break; | |
177 | ||
178 | case CLOCK_EVT_MODE_ONESHOT: | |
179 | cfg = hpet_readl(HPET_T0_CFG); | |
180 | cfg &= ~HPET_TN_PERIODIC; | |
181 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
182 | hpet_writel(cfg, HPET_T0_CFG); | |
183 | break; | |
184 | ||
185 | case CLOCK_EVT_MODE_UNUSED: | |
186 | case CLOCK_EVT_MODE_SHUTDOWN: | |
187 | cfg = hpet_readl(HPET_T0_CFG); | |
188 | cfg &= ~HPET_TN_ENABLE; | |
189 | hpet_writel(cfg, HPET_T0_CFG); | |
190 | break; | |
18de5bc4 TG |
191 | |
192 | case CLOCK_EVT_MODE_RESUME: | |
193 | hpet_enable_int(); | |
194 | break; | |
e9e2cdb4 TG |
195 | } |
196 | } | |
197 | ||
198 | static int hpet_next_event(unsigned long delta, | |
199 | struct clock_event_device *evt) | |
200 | { | |
201 | unsigned long cnt; | |
202 | ||
203 | cnt = hpet_readl(HPET_COUNTER); | |
204 | cnt += delta; | |
205 | hpet_writel(cnt, HPET_T0_CMP); | |
206 | ||
c7f6d15f | 207 | return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0; |
e9e2cdb4 TG |
208 | } |
209 | ||
6bb74df4 JS |
210 | /* |
211 | * Clock source related code | |
212 | */ | |
213 | static cycle_t read_hpet(void) | |
214 | { | |
215 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
216 | } | |
217 | ||
218 | static struct clocksource clocksource_hpet = { | |
219 | .name = "hpet", | |
220 | .rating = 250, | |
221 | .read = read_hpet, | |
222 | .mask = HPET_MASK, | |
223 | .shift = HPET_SHIFT, | |
224 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
18de5bc4 | 225 | .resume = hpet_start_counter, |
6bb74df4 JS |
226 | }; |
227 | ||
e9e2cdb4 TG |
228 | /* |
229 | * Try to setup the HPET timer | |
230 | */ | |
231 | int __init hpet_enable(void) | |
232 | { | |
233 | unsigned long id; | |
234 | uint64_t hpet_freq; | |
075bcd1f TG |
235 | u64 tmp, start, now; |
236 | cycle_t t1; | |
e9e2cdb4 TG |
237 | |
238 | if (!is_hpet_capable()) | |
239 | return 0; | |
240 | ||
241 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
242 | ||
243 | /* | |
244 | * Read the period and check for a sane value: | |
245 | */ | |
246 | hpet_period = hpet_readl(HPET_PERIOD); | |
247 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) | |
248 | goto out_nohpet; | |
249 | ||
250 | /* | |
251 | * The period is a femto seconds value. We need to calculate the | |
252 | * scaled math multiplication factor for nanosecond to hpet tick | |
253 | * conversion. | |
254 | */ | |
255 | hpet_freq = 1000000000000000ULL; | |
256 | do_div(hpet_freq, hpet_period); | |
257 | hpet_clockevent.mult = div_sc((unsigned long) hpet_freq, | |
258 | NSEC_PER_SEC, 32); | |
259 | /* Calculate the min / max delta */ | |
260 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
261 | &hpet_clockevent); | |
262 | hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30, | |
263 | &hpet_clockevent); | |
264 | ||
265 | /* | |
266 | * Read the HPET ID register to retrieve the IRQ routing | |
267 | * information and the number of channels | |
268 | */ | |
269 | id = hpet_readl(HPET_ID); | |
270 | ||
271 | #ifdef CONFIG_HPET_EMULATE_RTC | |
272 | /* | |
273 | * The legacy routing mode needs at least two channels, tick timer | |
274 | * and the rtc emulation channel. | |
275 | */ | |
276 | if (!(id & HPET_ID_NUMBER)) | |
277 | goto out_nohpet; | |
278 | #endif | |
279 | ||
280 | /* Start the counter */ | |
281 | hpet_start_counter(); | |
282 | ||
075bcd1f TG |
283 | /* Verify whether hpet counter works */ |
284 | t1 = read_hpet(); | |
285 | rdtscll(start); | |
286 | ||
287 | /* | |
288 | * We don't know the TSC frequency yet, but waiting for | |
289 | * 200000 TSC cycles is safe: | |
290 | * 4 GHz == 50us | |
291 | * 1 GHz == 200us | |
292 | */ | |
293 | do { | |
294 | rep_nop(); | |
295 | rdtscll(now); | |
296 | } while ((now - start) < 200000UL); | |
297 | ||
298 | if (t1 == read_hpet()) { | |
299 | printk(KERN_WARNING | |
300 | "HPET counter not counting. HPET disabled\n"); | |
301 | goto out_nohpet; | |
302 | } | |
303 | ||
6bb74df4 JS |
304 | /* Initialize and register HPET clocksource |
305 | * | |
306 | * hpet period is in femto seconds per cycle | |
307 | * so we need to convert this to ns/cyc units | |
308 | * aproximated by mult/2^shift | |
309 | * | |
310 | * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift | |
311 | * fsec/cyc * 1ns/1000000fsec * 2^shift = mult | |
312 | * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult | |
313 | * (fsec/cyc << shift)/1000000 = mult | |
314 | * (hpet_period << shift)/FSEC_PER_NSEC = mult | |
315 | */ | |
316 | tmp = (u64)hpet_period << HPET_SHIFT; | |
317 | do_div(tmp, FSEC_PER_NSEC); | |
318 | clocksource_hpet.mult = (u32)tmp; | |
319 | ||
320 | clocksource_register(&clocksource_hpet); | |
321 | ||
e9e2cdb4 TG |
322 | if (id & HPET_ID_LEGSUP) { |
323 | hpet_enable_int(); | |
324 | hpet_reserve_platform_timers(id); | |
325 | /* | |
326 | * Start hpet with the boot cpu mask and make it | |
327 | * global after the IO_APIC has been initialized. | |
328 | */ | |
43d6ca01 | 329 | hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); |
e9e2cdb4 TG |
330 | clockevents_register_device(&hpet_clockevent); |
331 | global_clock_event = &hpet_clockevent; | |
332 | return 1; | |
333 | } | |
334 | return 0; | |
5d0cf410 | 335 | |
e9e2cdb4 TG |
336 | out_nohpet: |
337 | iounmap(hpet_virt_address); | |
338 | hpet_virt_address = NULL; | |
399afa4f | 339 | boot_hpet_disable = 1; |
e9e2cdb4 TG |
340 | return 0; |
341 | } | |
342 | ||
e9e2cdb4 TG |
343 | |
344 | #ifdef CONFIG_HPET_EMULATE_RTC | |
345 | ||
346 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
347 | * is enabled, we support RTC interrupt functionality in software. | |
348 | * RTC has 3 kinds of interrupts: | |
349 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
350 | * is updated | |
351 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
352 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
353 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
354 | * (1) and (2) above are implemented using polling at a frequency of | |
355 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
356 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
357 | * For (3), we use interrupts at 64Hz or user specified periodic | |
358 | * frequency, whichever is higher. | |
359 | */ | |
360 | #include <linux/mc146818rtc.h> | |
361 | #include <linux/rtc.h> | |
362 | ||
363 | #define DEFAULT_RTC_INT_FREQ 64 | |
364 | #define DEFAULT_RTC_SHIFT 6 | |
365 | #define RTC_NUM_INTS 1 | |
366 | ||
367 | static unsigned long hpet_rtc_flags; | |
368 | static unsigned long hpet_prev_update_sec; | |
369 | static struct rtc_time hpet_alarm_time; | |
370 | static unsigned long hpet_pie_count; | |
371 | static unsigned long hpet_t1_cmp; | |
372 | static unsigned long hpet_default_delta; | |
373 | static unsigned long hpet_pie_delta; | |
374 | static unsigned long hpet_pie_limit; | |
375 | ||
376 | /* | |
377 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
378 | * is not supported by all HPET implementations for timer 1. | |
379 | * | |
380 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
381 | */ | |
382 | int hpet_rtc_timer_init(void) | |
383 | { | |
384 | unsigned long cfg, cnt, delta, flags; | |
385 | ||
386 | if (!is_hpet_enabled()) | |
387 | return 0; | |
388 | ||
389 | if (!hpet_default_delta) { | |
390 | uint64_t clc; | |
391 | ||
392 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
393 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
394 | hpet_default_delta = (unsigned long) clc; | |
395 | } | |
396 | ||
397 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
398 | delta = hpet_default_delta; | |
399 | else | |
400 | delta = hpet_pie_delta; | |
401 | ||
402 | local_irq_save(flags); | |
403 | ||
404 | cnt = delta + hpet_readl(HPET_COUNTER); | |
405 | hpet_writel(cnt, HPET_T1_CMP); | |
406 | hpet_t1_cmp = cnt; | |
407 | ||
408 | cfg = hpet_readl(HPET_T1_CFG); | |
409 | cfg &= ~HPET_TN_PERIODIC; | |
410 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
411 | hpet_writel(cfg, HPET_T1_CFG); | |
412 | ||
413 | local_irq_restore(flags); | |
414 | ||
415 | return 1; | |
416 | } | |
417 | ||
418 | /* | |
419 | * The functions below are called from rtc driver. | |
420 | * Return 0 if HPET is not being used. | |
421 | * Otherwise do the necessary changes and return 1. | |
422 | */ | |
423 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
424 | { | |
425 | if (!is_hpet_enabled()) | |
426 | return 0; | |
427 | ||
428 | hpet_rtc_flags &= ~bit_mask; | |
429 | return 1; | |
430 | } | |
431 | ||
432 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
433 | { | |
434 | unsigned long oldbits = hpet_rtc_flags; | |
435 | ||
436 | if (!is_hpet_enabled()) | |
437 | return 0; | |
438 | ||
439 | hpet_rtc_flags |= bit_mask; | |
440 | ||
441 | if (!oldbits) | |
442 | hpet_rtc_timer_init(); | |
443 | ||
444 | return 1; | |
445 | } | |
446 | ||
447 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
448 | unsigned char sec) | |
449 | { | |
450 | if (!is_hpet_enabled()) | |
451 | return 0; | |
452 | ||
453 | hpet_alarm_time.tm_hour = hrs; | |
454 | hpet_alarm_time.tm_min = min; | |
455 | hpet_alarm_time.tm_sec = sec; | |
456 | ||
457 | return 1; | |
458 | } | |
459 | ||
460 | int hpet_set_periodic_freq(unsigned long freq) | |
461 | { | |
462 | uint64_t clc; | |
463 | ||
464 | if (!is_hpet_enabled()) | |
465 | return 0; | |
466 | ||
467 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
468 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
469 | else { | |
470 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
471 | do_div(clc, freq); | |
472 | clc >>= hpet_clockevent.shift; | |
473 | hpet_pie_delta = (unsigned long) clc; | |
474 | } | |
475 | return 1; | |
476 | } | |
477 | ||
478 | int hpet_rtc_dropped_irq(void) | |
479 | { | |
480 | return is_hpet_enabled(); | |
481 | } | |
482 | ||
483 | static void hpet_rtc_timer_reinit(void) | |
484 | { | |
485 | unsigned long cfg, delta; | |
486 | int lost_ints = -1; | |
487 | ||
488 | if (unlikely(!hpet_rtc_flags)) { | |
489 | cfg = hpet_readl(HPET_T1_CFG); | |
490 | cfg &= ~HPET_TN_ENABLE; | |
491 | hpet_writel(cfg, HPET_T1_CFG); | |
492 | return; | |
493 | } | |
494 | ||
495 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
496 | delta = hpet_default_delta; | |
497 | else | |
498 | delta = hpet_pie_delta; | |
499 | ||
500 | /* | |
501 | * Increment the comparator value until we are ahead of the | |
502 | * current count. | |
503 | */ | |
504 | do { | |
505 | hpet_t1_cmp += delta; | |
506 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
507 | lost_ints++; | |
508 | } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); | |
509 | ||
510 | if (lost_ints) { | |
511 | if (hpet_rtc_flags & RTC_PIE) | |
512 | hpet_pie_count += lost_ints; | |
513 | if (printk_ratelimit()) | |
514 | printk(KERN_WARNING "rtc: lost %d interrupts\n", | |
515 | lost_ints); | |
516 | } | |
517 | } | |
518 | ||
519 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
520 | { | |
521 | struct rtc_time curr_time; | |
522 | unsigned long rtc_int_flag = 0; | |
523 | ||
524 | hpet_rtc_timer_reinit(); | |
525 | ||
526 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
527 | rtc_get_rtc_time(&curr_time); | |
528 | ||
529 | if (hpet_rtc_flags & RTC_UIE && | |
530 | curr_time.tm_sec != hpet_prev_update_sec) { | |
531 | rtc_int_flag = RTC_UF; | |
532 | hpet_prev_update_sec = curr_time.tm_sec; | |
533 | } | |
534 | ||
535 | if (hpet_rtc_flags & RTC_PIE && | |
536 | ++hpet_pie_count >= hpet_pie_limit) { | |
537 | rtc_int_flag |= RTC_PF; | |
538 | hpet_pie_count = 0; | |
539 | } | |
540 | ||
541 | if (hpet_rtc_flags & RTC_PIE && | |
542 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && | |
543 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
544 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
545 | rtc_int_flag |= RTC_AF; | |
546 | ||
547 | if (rtc_int_flag) { | |
548 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
549 | rtc_interrupt(rtc_int_flag, dev_id); | |
550 | } | |
551 | return IRQ_HANDLED; | |
552 | } | |
553 | #endif |