]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e | 10 | #include <linux/sched.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
f668964e IM |
12 | |
13 | #include <asm/sigcontext.h> | |
1da177e4 | 14 | #include <asm/processor.h> |
1da177e4 | 15 | #include <asm/math_emu.h> |
375074cc | 16 | #include <asm/tlbflush.h> |
1da177e4 | 17 | #include <asm/uaccess.h> |
f668964e IM |
18 | #include <asm/ptrace.h> |
19 | #include <asm/i387.h> | |
1361b83a | 20 | #include <asm/fpu-internal.h> |
f668964e | 21 | #include <asm/user.h> |
1da177e4 | 22 | |
14e153ef ON |
23 | static DEFINE_PER_CPU(bool, in_kernel_fpu); |
24 | ||
7575637a ON |
25 | void kernel_fpu_disable(void) |
26 | { | |
27 | WARN_ON(this_cpu_read(in_kernel_fpu)); | |
28 | this_cpu_write(in_kernel_fpu, true); | |
29 | } | |
30 | ||
31 | void kernel_fpu_enable(void) | |
32 | { | |
33 | this_cpu_write(in_kernel_fpu, false); | |
34 | } | |
35 | ||
8546c008 LT |
36 | /* |
37 | * Were we in an interrupt that interrupted kernel mode? | |
38 | * | |
304bceda | 39 | * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that |
8546c008 LT |
40 | * pair does nothing at all: the thread must not have fpu (so |
41 | * that we don't try to save the FPU state), and TS must | |
42 | * be set (so that the clts/stts pair does nothing that is | |
43 | * visible in the interrupted kernel thread). | |
5187b28f | 44 | * |
4b2e762e ON |
45 | * Except for the eagerfpu case when we return true; in the likely case |
46 | * the thread has FPU but we are not going to set/clear TS. | |
8546c008 LT |
47 | */ |
48 | static inline bool interrupted_kernel_fpu_idle(void) | |
49 | { | |
14e153ef ON |
50 | if (this_cpu_read(in_kernel_fpu)) |
51 | return false; | |
52 | ||
5d2bd700 | 53 | if (use_eager_fpu()) |
4b2e762e | 54 | return true; |
304bceda | 55 | |
8546c008 LT |
56 | return !__thread_has_fpu(current) && |
57 | (read_cr0() & X86_CR0_TS); | |
58 | } | |
59 | ||
60 | /* | |
61 | * Were we in user mode (or vm86 mode) when we were | |
62 | * interrupted? | |
63 | * | |
64 | * Doing kernel_fpu_begin/end() is ok if we are running | |
65 | * in an interrupt context from user mode - we'll just | |
66 | * save the FPU state as required. | |
67 | */ | |
68 | static inline bool interrupted_user_mode(void) | |
69 | { | |
70 | struct pt_regs *regs = get_irq_regs(); | |
f39b6f0e | 71 | return regs && user_mode(regs); |
8546c008 LT |
72 | } |
73 | ||
74 | /* | |
75 | * Can we use the FPU in kernel mode with the | |
76 | * whole "kernel_fpu_begin/end()" sequence? | |
77 | * | |
78 | * It's always ok in process context (ie "not interrupt") | |
79 | * but it is sometimes ok even from an irq. | |
80 | */ | |
81 | bool irq_fpu_usable(void) | |
82 | { | |
83 | return !in_interrupt() || | |
84 | interrupted_user_mode() || | |
85 | interrupted_kernel_fpu_idle(); | |
86 | } | |
87 | EXPORT_SYMBOL(irq_fpu_usable); | |
88 | ||
b1a74bf8 | 89 | void __kernel_fpu_begin(void) |
8546c008 LT |
90 | { |
91 | struct task_struct *me = current; | |
92 | ||
14e153ef ON |
93 | this_cpu_write(in_kernel_fpu, true); |
94 | ||
8546c008 | 95 | if (__thread_has_fpu(me)) { |
5187b28f | 96 | __save_init_fpu(me); |
7aeccb83 | 97 | } else { |
c6ae41e7 | 98 | this_cpu_write(fpu_owner_task, NULL); |
7aeccb83 ON |
99 | if (!use_eager_fpu()) |
100 | clts(); | |
8546c008 LT |
101 | } |
102 | } | |
b1a74bf8 | 103 | EXPORT_SYMBOL(__kernel_fpu_begin); |
8546c008 | 104 | |
b1a74bf8 | 105 | void __kernel_fpu_end(void) |
8546c008 | 106 | { |
33a3ebdc ON |
107 | struct task_struct *me = current; |
108 | ||
109 | if (__thread_has_fpu(me)) { | |
110 | if (WARN_ON(restore_fpu_checking(me))) | |
b85e67d1 | 111 | fpu_reset_state(me); |
33a3ebdc | 112 | } else if (!use_eager_fpu()) { |
304bceda | 113 | stts(); |
731bd6a9 | 114 | } |
14e153ef ON |
115 | |
116 | this_cpu_write(in_kernel_fpu, false); | |
8546c008 | 117 | } |
b1a74bf8 | 118 | EXPORT_SYMBOL(__kernel_fpu_end); |
8546c008 LT |
119 | |
120 | void unlazy_fpu(struct task_struct *tsk) | |
121 | { | |
122 | preempt_disable(); | |
123 | if (__thread_has_fpu(tsk)) { | |
1a2a7f4e ON |
124 | if (use_eager_fpu()) { |
125 | __save_fpu(tsk); | |
126 | } else { | |
127 | __save_init_fpu(tsk); | |
128 | __thread_fpu_end(tsk); | |
129 | } | |
a9241ea5 | 130 | } |
8546c008 LT |
131 | preempt_enable(); |
132 | } | |
133 | EXPORT_SYMBOL(unlazy_fpu); | |
134 | ||
72a671ce | 135 | unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b | 136 | unsigned int xstate_size; |
f45755b8 | 137 | EXPORT_SYMBOL_GPL(xstate_size); |
148f9bb8 | 138 | static struct i387_fxsave_struct fx_scratch; |
1da177e4 | 139 | |
148f9bb8 | 140 | static void mxcsr_feature_mask_init(void) |
1da177e4 LT |
141 | { |
142 | unsigned long mask = 0; | |
f668964e | 143 | |
1da177e4 | 144 | if (cpu_has_fxsr) { |
61c4628b | 145 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
eaa5a990 | 146 | asm volatile("fxsave %0" : "+m" (fx_scratch)); |
61c4628b | 147 | mask = fx_scratch.mxcsr_mask; |
3b095a04 CG |
148 | if (mask == 0) |
149 | mask = 0x0000ffbf; | |
150 | } | |
1da177e4 | 151 | mxcsr_feature_mask &= mask; |
1da177e4 LT |
152 | } |
153 | ||
148f9bb8 | 154 | static void init_thread_xstate(void) |
61c4628b | 155 | { |
0e49bf66 RR |
156 | /* |
157 | * Note that xstate_size might be overwriten later during | |
158 | * xsave_init(). | |
159 | */ | |
160 | ||
60e019eb | 161 | if (!cpu_has_fpu) { |
1f999ab5 RR |
162 | /* |
163 | * Disable xsave as we do not support it if i387 | |
164 | * emulation is enabled. | |
165 | */ | |
166 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
167 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
e8a496ac SS |
168 | xstate_size = sizeof(struct i387_soft_struct); |
169 | return; | |
170 | } | |
171 | ||
61c4628b SS |
172 | if (cpu_has_fxsr) |
173 | xstate_size = sizeof(struct i387_fxsave_struct); | |
61c4628b SS |
174 | else |
175 | xstate_size = sizeof(struct i387_fsave_struct); | |
61c4628b SS |
176 | } |
177 | ||
44210111 RM |
178 | /* |
179 | * Called at bootup to set up the initial FPU state that is later cloned | |
180 | * into all processes. | |
181 | */ | |
0e49bf66 | 182 | |
148f9bb8 | 183 | void fpu_init(void) |
44210111 | 184 | { |
6ac8bac2 BG |
185 | unsigned long cr0; |
186 | unsigned long cr4_mask = 0; | |
44210111 | 187 | |
60e019eb PA |
188 | #ifndef CONFIG_MATH_EMULATION |
189 | if (!cpu_has_fpu) { | |
190 | pr_emerg("No FPU found and no math emulation present\n"); | |
191 | pr_emerg("Giving up\n"); | |
192 | for (;;) | |
193 | asm volatile("hlt"); | |
194 | } | |
195 | #endif | |
6ac8bac2 BG |
196 | if (cpu_has_fxsr) |
197 | cr4_mask |= X86_CR4_OSFXSR; | |
198 | if (cpu_has_xmm) | |
199 | cr4_mask |= X86_CR4_OSXMMEXCPT; | |
200 | if (cr4_mask) | |
375074cc | 201 | cr4_set_bits(cr4_mask); |
6ac8bac2 BG |
202 | |
203 | cr0 = read_cr0(); | |
204 | cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */ | |
60e019eb | 205 | if (!cpu_has_fpu) |
6ac8bac2 BG |
206 | cr0 |= X86_CR0_EM; |
207 | write_cr0(cr0); | |
44210111 | 208 | |
6f5298c2 FY |
209 | /* |
210 | * init_thread_xstate is only called once to avoid overriding | |
211 | * xstate_size during boot time or during CPU hotplug. | |
212 | */ | |
213 | if (xstate_size == 0) | |
dc1e35c6 | 214 | init_thread_xstate(); |
dc1e35c6 | 215 | |
44210111 | 216 | mxcsr_feature_mask_init(); |
5d2bd700 SS |
217 | xsave_init(); |
218 | eager_fpu_init(); | |
44210111 | 219 | } |
0e49bf66 | 220 | |
5ee481da | 221 | void fpu_finit(struct fpu *fpu) |
1da177e4 | 222 | { |
60e019eb | 223 | if (!cpu_has_fpu) { |
86603283 AK |
224 | finit_soft_fpu(&fpu->state->soft); |
225 | return; | |
e8a496ac | 226 | } |
e8a496ac | 227 | |
1d23c451 ON |
228 | memset(fpu->state, 0, xstate_size); |
229 | ||
1da177e4 | 230 | if (cpu_has_fxsr) { |
5d2bd700 | 231 | fx_finit(&fpu->state->fxsave); |
1da177e4 | 232 | } else { |
86603283 | 233 | struct i387_fsave_struct *fp = &fpu->state->fsave; |
61c4628b SS |
234 | fp->cwd = 0xffff037fu; |
235 | fp->swd = 0xffff0000u; | |
236 | fp->twd = 0xffffffffu; | |
237 | fp->fos = 0xffff0000u; | |
1da177e4 | 238 | } |
86603283 | 239 | } |
5ee481da | 240 | EXPORT_SYMBOL_GPL(fpu_finit); |
86603283 AK |
241 | |
242 | /* | |
243 | * The _current_ task is using the FPU for the first time | |
244 | * so initialize it and set the mxcsr to its default | |
245 | * value at reset if we support XMM instructions and then | |
0d2eb44f | 246 | * remember the current task has used the FPU. |
86603283 AK |
247 | */ |
248 | int init_fpu(struct task_struct *tsk) | |
249 | { | |
250 | int ret; | |
251 | ||
252 | if (tsk_used_math(tsk)) { | |
60e019eb | 253 | if (cpu_has_fpu && tsk == current) |
86603283 | 254 | unlazy_fpu(tsk); |
6a5fe895 | 255 | task_disable_lazy_fpu_restore(tsk); |
86603283 AK |
256 | return 0; |
257 | } | |
258 | ||
44210111 | 259 | /* |
86603283 | 260 | * Memory allocation at the first usage of the FPU and other state. |
44210111 | 261 | */ |
86603283 AK |
262 | ret = fpu_alloc(&tsk->thread.fpu); |
263 | if (ret) | |
264 | return ret; | |
265 | ||
266 | fpu_finit(&tsk->thread.fpu); | |
267 | ||
1da177e4 | 268 | set_stopped_child_used_math(tsk); |
aa283f49 | 269 | return 0; |
1da177e4 | 270 | } |
e5c30142 | 271 | EXPORT_SYMBOL_GPL(init_fpu); |
1da177e4 | 272 | |
5b3efd50 SS |
273 | /* |
274 | * The xstateregs_active() routine is the same as the fpregs_active() routine, | |
275 | * as the "regset->n" for the xstate regset will be updated based on the feature | |
276 | * capabilites supported by the xsave. | |
277 | */ | |
44210111 RM |
278 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
279 | { | |
280 | return tsk_used_math(target) ? regset->n : 0; | |
281 | } | |
1da177e4 | 282 | |
44210111 | 283 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 284 | { |
44210111 RM |
285 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
286 | } | |
1da177e4 | 287 | |
44210111 RM |
288 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
289 | unsigned int pos, unsigned int count, | |
290 | void *kbuf, void __user *ubuf) | |
291 | { | |
aa283f49 SS |
292 | int ret; |
293 | ||
44210111 RM |
294 | if (!cpu_has_fxsr) |
295 | return -ENODEV; | |
296 | ||
aa283f49 SS |
297 | ret = init_fpu(target); |
298 | if (ret) | |
299 | return ret; | |
44210111 | 300 | |
29104e10 SS |
301 | sanitize_i387_state(target); |
302 | ||
44210111 | 303 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 304 | &target->thread.fpu.state->fxsave, 0, -1); |
1da177e4 | 305 | } |
44210111 RM |
306 | |
307 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
308 | unsigned int pos, unsigned int count, | |
309 | const void *kbuf, const void __user *ubuf) | |
310 | { | |
311 | int ret; | |
312 | ||
313 | if (!cpu_has_fxsr) | |
314 | return -ENODEV; | |
315 | ||
aa283f49 SS |
316 | ret = init_fpu(target); |
317 | if (ret) | |
318 | return ret; | |
319 | ||
29104e10 SS |
320 | sanitize_i387_state(target); |
321 | ||
44210111 | 322 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
86603283 | 323 | &target->thread.fpu.state->fxsave, 0, -1); |
44210111 RM |
324 | |
325 | /* | |
326 | * mxcsr reserved bits must be masked to zero for security reasons. | |
327 | */ | |
86603283 | 328 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 329 | |
42deec6f SS |
330 | /* |
331 | * update the header bits in the xsave header, indicating the | |
332 | * presence of FP and SSE state. | |
333 | */ | |
334 | if (cpu_has_xsave) | |
86603283 | 335 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; |
42deec6f | 336 | |
44210111 RM |
337 | return ret; |
338 | } | |
339 | ||
5b3efd50 SS |
340 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
341 | unsigned int pos, unsigned int count, | |
342 | void *kbuf, void __user *ubuf) | |
343 | { | |
18ecb3bf | 344 | struct xsave_struct *xsave; |
5b3efd50 SS |
345 | int ret; |
346 | ||
347 | if (!cpu_has_xsave) | |
348 | return -ENODEV; | |
349 | ||
350 | ret = init_fpu(target); | |
351 | if (ret) | |
352 | return ret; | |
353 | ||
18ecb3bf BP |
354 | xsave = &target->thread.fpu.state->xsave; |
355 | ||
5b3efd50 | 356 | /* |
ff7fbc72 SS |
357 | * Copy the 48bytes defined by the software first into the xstate |
358 | * memory layout in the thread struct, so that we can copy the entire | |
359 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 360 | */ |
e7f180dc ON |
361 | memcpy(&xsave->i387.sw_reserved, |
362 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); | |
5b3efd50 | 363 | /* |
ff7fbc72 | 364 | * Copy the xstate memory layout. |
5b3efd50 | 365 | */ |
e7f180dc | 366 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
367 | return ret; |
368 | } | |
369 | ||
370 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
371 | unsigned int pos, unsigned int count, | |
372 | const void *kbuf, const void __user *ubuf) | |
373 | { | |
18ecb3bf | 374 | struct xsave_struct *xsave; |
5b3efd50 | 375 | int ret; |
5b3efd50 SS |
376 | |
377 | if (!cpu_has_xsave) | |
378 | return -ENODEV; | |
379 | ||
380 | ret = init_fpu(target); | |
381 | if (ret) | |
382 | return ret; | |
383 | ||
18ecb3bf BP |
384 | xsave = &target->thread.fpu.state->xsave; |
385 | ||
e7f180dc | 386 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
387 | /* |
388 | * mxcsr reserved bits must be masked to zero for security reasons. | |
389 | */ | |
e7f180dc ON |
390 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
391 | xsave->xsave_hdr.xstate_bv &= pcntxt_mask; | |
5b3efd50 SS |
392 | /* |
393 | * These bits must be zero. | |
394 | */ | |
e7f180dc | 395 | memset(&xsave->xsave_hdr.reserved, 0, 48); |
5b3efd50 SS |
396 | return ret; |
397 | } | |
398 | ||
44210111 | 399 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 400 | |
1da177e4 LT |
401 | /* |
402 | * FPU tag word conversions. | |
403 | */ | |
404 | ||
3b095a04 | 405 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
406 | { |
407 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 408 | |
1da177e4 | 409 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 410 | tmp = ~twd; |
44210111 | 411 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
412 | /* and move the valid bits to the lower byte. */ |
413 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
414 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
415 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 416 | |
3b095a04 | 417 | return tmp; |
1da177e4 LT |
418 | } |
419 | ||
497888cf | 420 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16) |
44210111 RM |
421 | #define FP_EXP_TAG_VALID 0 |
422 | #define FP_EXP_TAG_ZERO 1 | |
423 | #define FP_EXP_TAG_SPECIAL 2 | |
424 | #define FP_EXP_TAG_EMPTY 3 | |
425 | ||
426 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
427 | { | |
428 | struct _fpxreg *st; | |
429 | u32 tos = (fxsave->swd >> 11) & 7; | |
430 | u32 twd = (unsigned long) fxsave->twd; | |
431 | u32 tag; | |
432 | u32 ret = 0xffff0000u; | |
433 | int i; | |
1da177e4 | 434 | |
44210111 | 435 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
436 | if (twd & 0x1) { |
437 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 438 | |
3b095a04 | 439 | switch (st->exponent & 0x7fff) { |
1da177e4 | 440 | case 0x7fff: |
44210111 | 441 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
442 | break; |
443 | case 0x0000: | |
3b095a04 CG |
444 | if (!st->significand[0] && |
445 | !st->significand[1] && | |
446 | !st->significand[2] && | |
44210111 RM |
447 | !st->significand[3]) |
448 | tag = FP_EXP_TAG_ZERO; | |
449 | else | |
450 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
451 | break; |
452 | default: | |
44210111 RM |
453 | if (st->significand[3] & 0x8000) |
454 | tag = FP_EXP_TAG_VALID; | |
455 | else | |
456 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
457 | break; |
458 | } | |
459 | } else { | |
44210111 | 460 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 461 | } |
44210111 | 462 | ret |= tag << (2 * i); |
1da177e4 LT |
463 | } |
464 | return ret; | |
465 | } | |
466 | ||
467 | /* | |
44210111 | 468 | * FXSR floating point environment conversions. |
1da177e4 LT |
469 | */ |
470 | ||
72a671ce | 471 | void |
f668964e | 472 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) |
1da177e4 | 473 | { |
86603283 | 474 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
475 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
476 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
477 | int i; | |
1da177e4 | 478 | |
44210111 RM |
479 | env->cwd = fxsave->cwd | 0xffff0000u; |
480 | env->swd = fxsave->swd | 0xffff0000u; | |
481 | env->twd = twd_fxsr_to_i387(fxsave); | |
482 | ||
483 | #ifdef CONFIG_X86_64 | |
484 | env->fip = fxsave->rip; | |
485 | env->foo = fxsave->rdp; | |
10c11f30 BG |
486 | /* |
487 | * should be actually ds/cs at fpu exception time, but | |
488 | * that information is not available in 64bit mode. | |
489 | */ | |
490 | env->fcs = task_pt_regs(tsk)->cs; | |
44210111 | 491 | if (tsk == current) { |
10c11f30 | 492 | savesegment(ds, env->fos); |
1da177e4 | 493 | } else { |
10c11f30 | 494 | env->fos = tsk->thread.ds; |
1da177e4 | 495 | } |
10c11f30 | 496 | env->fos |= 0xffff0000; |
44210111 RM |
497 | #else |
498 | env->fip = fxsave->fip; | |
609b5297 | 499 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
500 | env->foo = fxsave->foo; |
501 | env->fos = fxsave->fos; | |
502 | #endif | |
1da177e4 | 503 | |
44210111 RM |
504 | for (i = 0; i < 8; ++i) |
505 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
506 | } |
507 | ||
72a671ce SS |
508 | void convert_to_fxsr(struct task_struct *tsk, |
509 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 510 | |
1da177e4 | 511 | { |
86603283 | 512 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
513 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
514 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
515 | int i; | |
1da177e4 | 516 | |
44210111 RM |
517 | fxsave->cwd = env->cwd; |
518 | fxsave->swd = env->swd; | |
519 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
520 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
521 | #ifdef CONFIG_X86_64 | |
522 | fxsave->rip = env->fip; | |
523 | fxsave->rdp = env->foo; | |
524 | /* cs and ds ignored */ | |
525 | #else | |
526 | fxsave->fip = env->fip; | |
527 | fxsave->fcs = (env->fcs & 0xffff); | |
528 | fxsave->foo = env->foo; | |
529 | fxsave->fos = env->fos; | |
530 | #endif | |
1da177e4 | 531 | |
44210111 RM |
532 | for (i = 0; i < 8; ++i) |
533 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
534 | } |
535 | ||
44210111 RM |
536 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
537 | unsigned int pos, unsigned int count, | |
538 | void *kbuf, void __user *ubuf) | |
1da177e4 | 539 | { |
44210111 | 540 | struct user_i387_ia32_struct env; |
aa283f49 | 541 | int ret; |
1da177e4 | 542 | |
aa283f49 SS |
543 | ret = init_fpu(target); |
544 | if (ret) | |
545 | return ret; | |
1da177e4 | 546 | |
60e019eb | 547 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
548 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); |
549 | ||
60e019eb | 550 | if (!cpu_has_fxsr) |
44210111 | 551 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 552 | &target->thread.fpu.state->fsave, 0, |
61c4628b | 553 | -1); |
1da177e4 | 554 | |
29104e10 SS |
555 | sanitize_i387_state(target); |
556 | ||
44210111 RM |
557 | if (kbuf && pos == 0 && count == sizeof(env)) { |
558 | convert_from_fxsr(kbuf, target); | |
559 | return 0; | |
1da177e4 | 560 | } |
44210111 RM |
561 | |
562 | convert_from_fxsr(&env, target); | |
f668964e | 563 | |
44210111 | 564 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
565 | } |
566 | ||
44210111 RM |
567 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
568 | unsigned int pos, unsigned int count, | |
569 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 570 | { |
44210111 RM |
571 | struct user_i387_ia32_struct env; |
572 | int ret; | |
1da177e4 | 573 | |
aa283f49 SS |
574 | ret = init_fpu(target); |
575 | if (ret) | |
576 | return ret; | |
577 | ||
29104e10 SS |
578 | sanitize_i387_state(target); |
579 | ||
60e019eb | 580 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
581 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); |
582 | ||
60e019eb | 583 | if (!cpu_has_fxsr) |
44210111 | 584 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
60e019eb PA |
585 | &target->thread.fpu.state->fsave, 0, |
586 | -1); | |
44210111 RM |
587 | |
588 | if (pos > 0 || count < sizeof(env)) | |
589 | convert_from_fxsr(&env, target); | |
590 | ||
591 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
592 | if (!ret) | |
593 | convert_to_fxsr(target, &env); | |
594 | ||
42deec6f SS |
595 | /* |
596 | * update the header bit in the xsave header, indicating the | |
597 | * presence of FP. | |
598 | */ | |
599 | if (cpu_has_xsave) | |
86603283 | 600 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP; |
44210111 | 601 | return ret; |
1da177e4 LT |
602 | } |
603 | ||
1da177e4 LT |
604 | /* |
605 | * FPU state for core dumps. | |
60b3b9af RM |
606 | * This is only used for a.out dumps now. |
607 | * It is declared generically using elf_fpregset_t (which is | |
608 | * struct user_i387_struct) but is in fact only used for 32-bit | |
609 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 610 | */ |
3b095a04 | 611 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 612 | { |
1da177e4 | 613 | struct task_struct *tsk = current; |
f668964e | 614 | int fpvalid; |
1da177e4 LT |
615 | |
616 | fpvalid = !!used_math(); | |
60b3b9af RM |
617 | if (fpvalid) |
618 | fpvalid = !fpregs_get(tsk, NULL, | |
619 | 0, sizeof(struct user_i387_ia32_struct), | |
620 | fpu, NULL); | |
1da177e4 LT |
621 | |
622 | return fpvalid; | |
623 | } | |
129f6946 | 624 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 625 | |
60b3b9af | 626 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |
60e019eb PA |
627 | |
628 | static int __init no_387(char *s) | |
629 | { | |
630 | setup_clear_cpu_cap(X86_FEATURE_FPU); | |
631 | return 1; | |
632 | } | |
633 | ||
634 | __setup("no387", no_387); | |
635 | ||
148f9bb8 | 636 | void fpu_detect(struct cpuinfo_x86 *c) |
60e019eb PA |
637 | { |
638 | unsigned long cr0; | |
639 | u16 fsw, fcw; | |
640 | ||
641 | fsw = fcw = 0xffff; | |
642 | ||
643 | cr0 = read_cr0(); | |
644 | cr0 &= ~(X86_CR0_TS | X86_CR0_EM); | |
645 | write_cr0(cr0); | |
646 | ||
647 | asm volatile("fninit ; fnstsw %0 ; fnstcw %1" | |
648 | : "+m" (fsw), "+m" (fcw)); | |
649 | ||
650 | if (fsw == 0 && (fcw & 0x103f) == 0x003f) | |
651 | set_cpu_cap(c, X86_FEATURE_FPU); | |
652 | else | |
653 | clear_cpu_cap(c, X86_FEATURE_FPU); | |
654 | ||
655 | /* The final cr0 value is set in fpu_init() */ | |
656 | } |