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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e | 10 | #include <linux/sched.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
f668964e IM |
12 | |
13 | #include <asm/sigcontext.h> | |
1da177e4 | 14 | #include <asm/processor.h> |
1da177e4 | 15 | #include <asm/math_emu.h> |
1da177e4 | 16 | #include <asm/uaccess.h> |
f668964e IM |
17 | #include <asm/ptrace.h> |
18 | #include <asm/i387.h> | |
1361b83a | 19 | #include <asm/fpu-internal.h> |
f668964e | 20 | #include <asm/user.h> |
1da177e4 | 21 | |
8546c008 LT |
22 | /* |
23 | * Were we in an interrupt that interrupted kernel mode? | |
24 | * | |
304bceda | 25 | * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that |
8546c008 LT |
26 | * pair does nothing at all: the thread must not have fpu (so |
27 | * that we don't try to save the FPU state), and TS must | |
28 | * be set (so that the clts/stts pair does nothing that is | |
29 | * visible in the interrupted kernel thread). | |
5187b28f PR |
30 | * |
31 | * Except for the eagerfpu case when we return 1 unless we've already | |
32 | * been eager and saved the state in kernel_fpu_begin(). | |
8546c008 LT |
33 | */ |
34 | static inline bool interrupted_kernel_fpu_idle(void) | |
35 | { | |
5d2bd700 | 36 | if (use_eager_fpu()) |
5187b28f | 37 | return __thread_has_fpu(current); |
304bceda | 38 | |
8546c008 LT |
39 | return !__thread_has_fpu(current) && |
40 | (read_cr0() & X86_CR0_TS); | |
41 | } | |
42 | ||
43 | /* | |
44 | * Were we in user mode (or vm86 mode) when we were | |
45 | * interrupted? | |
46 | * | |
47 | * Doing kernel_fpu_begin/end() is ok if we are running | |
48 | * in an interrupt context from user mode - we'll just | |
49 | * save the FPU state as required. | |
50 | */ | |
51 | static inline bool interrupted_user_mode(void) | |
52 | { | |
53 | struct pt_regs *regs = get_irq_regs(); | |
54 | return regs && user_mode_vm(regs); | |
55 | } | |
56 | ||
57 | /* | |
58 | * Can we use the FPU in kernel mode with the | |
59 | * whole "kernel_fpu_begin/end()" sequence? | |
60 | * | |
61 | * It's always ok in process context (ie "not interrupt") | |
62 | * but it is sometimes ok even from an irq. | |
63 | */ | |
64 | bool irq_fpu_usable(void) | |
65 | { | |
66 | return !in_interrupt() || | |
67 | interrupted_user_mode() || | |
68 | interrupted_kernel_fpu_idle(); | |
69 | } | |
70 | EXPORT_SYMBOL(irq_fpu_usable); | |
71 | ||
b1a74bf8 | 72 | void __kernel_fpu_begin(void) |
8546c008 LT |
73 | { |
74 | struct task_struct *me = current; | |
75 | ||
8546c008 | 76 | if (__thread_has_fpu(me)) { |
8546c008 | 77 | __thread_clear_has_fpu(me); |
5187b28f | 78 | __save_init_fpu(me); |
b1a74bf8 | 79 | /* We do 'stts()' in __kernel_fpu_end() */ |
5d2bd700 | 80 | } else if (!use_eager_fpu()) { |
c6ae41e7 | 81 | this_cpu_write(fpu_owner_task, NULL); |
8546c008 LT |
82 | clts(); |
83 | } | |
84 | } | |
b1a74bf8 | 85 | EXPORT_SYMBOL(__kernel_fpu_begin); |
8546c008 | 86 | |
b1a74bf8 | 87 | void __kernel_fpu_end(void) |
8546c008 | 88 | { |
5d2bd700 | 89 | if (use_eager_fpu()) |
304bceda SS |
90 | math_state_restore(); |
91 | else | |
92 | stts(); | |
8546c008 | 93 | } |
b1a74bf8 | 94 | EXPORT_SYMBOL(__kernel_fpu_end); |
8546c008 LT |
95 | |
96 | void unlazy_fpu(struct task_struct *tsk) | |
97 | { | |
98 | preempt_disable(); | |
99 | if (__thread_has_fpu(tsk)) { | |
100 | __save_init_fpu(tsk); | |
101 | __thread_fpu_end(tsk); | |
102 | } else | |
103 | tsk->fpu_counter = 0; | |
104 | preempt_enable(); | |
105 | } | |
106 | EXPORT_SYMBOL(unlazy_fpu); | |
107 | ||
72a671ce | 108 | unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b | 109 | unsigned int xstate_size; |
f45755b8 | 110 | EXPORT_SYMBOL_GPL(xstate_size); |
148f9bb8 | 111 | static struct i387_fxsave_struct fx_scratch; |
1da177e4 | 112 | |
148f9bb8 | 113 | static void mxcsr_feature_mask_init(void) |
1da177e4 LT |
114 | { |
115 | unsigned long mask = 0; | |
f668964e | 116 | |
1da177e4 | 117 | if (cpu_has_fxsr) { |
61c4628b | 118 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
eaa5a990 | 119 | asm volatile("fxsave %0" : "+m" (fx_scratch)); |
61c4628b | 120 | mask = fx_scratch.mxcsr_mask; |
3b095a04 CG |
121 | if (mask == 0) |
122 | mask = 0x0000ffbf; | |
123 | } | |
1da177e4 | 124 | mxcsr_feature_mask &= mask; |
1da177e4 LT |
125 | } |
126 | ||
148f9bb8 | 127 | static void init_thread_xstate(void) |
61c4628b | 128 | { |
0e49bf66 RR |
129 | /* |
130 | * Note that xstate_size might be overwriten later during | |
131 | * xsave_init(). | |
132 | */ | |
133 | ||
60e019eb | 134 | if (!cpu_has_fpu) { |
1f999ab5 RR |
135 | /* |
136 | * Disable xsave as we do not support it if i387 | |
137 | * emulation is enabled. | |
138 | */ | |
139 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
140 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
e8a496ac SS |
141 | xstate_size = sizeof(struct i387_soft_struct); |
142 | return; | |
143 | } | |
144 | ||
61c4628b SS |
145 | if (cpu_has_fxsr) |
146 | xstate_size = sizeof(struct i387_fxsave_struct); | |
61c4628b SS |
147 | else |
148 | xstate_size = sizeof(struct i387_fsave_struct); | |
61c4628b SS |
149 | } |
150 | ||
44210111 RM |
151 | /* |
152 | * Called at bootup to set up the initial FPU state that is later cloned | |
153 | * into all processes. | |
154 | */ | |
0e49bf66 | 155 | |
148f9bb8 | 156 | void fpu_init(void) |
44210111 | 157 | { |
6ac8bac2 BG |
158 | unsigned long cr0; |
159 | unsigned long cr4_mask = 0; | |
44210111 | 160 | |
60e019eb PA |
161 | #ifndef CONFIG_MATH_EMULATION |
162 | if (!cpu_has_fpu) { | |
163 | pr_emerg("No FPU found and no math emulation present\n"); | |
164 | pr_emerg("Giving up\n"); | |
165 | for (;;) | |
166 | asm volatile("hlt"); | |
167 | } | |
168 | #endif | |
6ac8bac2 BG |
169 | if (cpu_has_fxsr) |
170 | cr4_mask |= X86_CR4_OSFXSR; | |
171 | if (cpu_has_xmm) | |
172 | cr4_mask |= X86_CR4_OSXMMEXCPT; | |
173 | if (cr4_mask) | |
174 | set_in_cr4(cr4_mask); | |
175 | ||
176 | cr0 = read_cr0(); | |
177 | cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */ | |
60e019eb | 178 | if (!cpu_has_fpu) |
6ac8bac2 BG |
179 | cr0 |= X86_CR0_EM; |
180 | write_cr0(cr0); | |
44210111 | 181 | |
6f5298c2 FY |
182 | /* |
183 | * init_thread_xstate is only called once to avoid overriding | |
184 | * xstate_size during boot time or during CPU hotplug. | |
185 | */ | |
186 | if (xstate_size == 0) | |
dc1e35c6 | 187 | init_thread_xstate(); |
dc1e35c6 | 188 | |
44210111 | 189 | mxcsr_feature_mask_init(); |
5d2bd700 SS |
190 | xsave_init(); |
191 | eager_fpu_init(); | |
44210111 | 192 | } |
0e49bf66 | 193 | |
5ee481da | 194 | void fpu_finit(struct fpu *fpu) |
1da177e4 | 195 | { |
60e019eb | 196 | if (!cpu_has_fpu) { |
86603283 AK |
197 | finit_soft_fpu(&fpu->state->soft); |
198 | return; | |
e8a496ac | 199 | } |
e8a496ac | 200 | |
1da177e4 | 201 | if (cpu_has_fxsr) { |
5d2bd700 | 202 | fx_finit(&fpu->state->fxsave); |
1da177e4 | 203 | } else { |
86603283 | 204 | struct i387_fsave_struct *fp = &fpu->state->fsave; |
61c4628b SS |
205 | memset(fp, 0, xstate_size); |
206 | fp->cwd = 0xffff037fu; | |
207 | fp->swd = 0xffff0000u; | |
208 | fp->twd = 0xffffffffu; | |
209 | fp->fos = 0xffff0000u; | |
1da177e4 | 210 | } |
86603283 | 211 | } |
5ee481da | 212 | EXPORT_SYMBOL_GPL(fpu_finit); |
86603283 AK |
213 | |
214 | /* | |
215 | * The _current_ task is using the FPU for the first time | |
216 | * so initialize it and set the mxcsr to its default | |
217 | * value at reset if we support XMM instructions and then | |
0d2eb44f | 218 | * remember the current task has used the FPU. |
86603283 AK |
219 | */ |
220 | int init_fpu(struct task_struct *tsk) | |
221 | { | |
222 | int ret; | |
223 | ||
224 | if (tsk_used_math(tsk)) { | |
60e019eb | 225 | if (cpu_has_fpu && tsk == current) |
86603283 | 226 | unlazy_fpu(tsk); |
089f9fba | 227 | tsk->thread.fpu.last_cpu = ~0; |
86603283 AK |
228 | return 0; |
229 | } | |
230 | ||
44210111 | 231 | /* |
86603283 | 232 | * Memory allocation at the first usage of the FPU and other state. |
44210111 | 233 | */ |
86603283 AK |
234 | ret = fpu_alloc(&tsk->thread.fpu); |
235 | if (ret) | |
236 | return ret; | |
237 | ||
238 | fpu_finit(&tsk->thread.fpu); | |
239 | ||
1da177e4 | 240 | set_stopped_child_used_math(tsk); |
aa283f49 | 241 | return 0; |
1da177e4 | 242 | } |
e5c30142 | 243 | EXPORT_SYMBOL_GPL(init_fpu); |
1da177e4 | 244 | |
5b3efd50 SS |
245 | /* |
246 | * The xstateregs_active() routine is the same as the fpregs_active() routine, | |
247 | * as the "regset->n" for the xstate regset will be updated based on the feature | |
248 | * capabilites supported by the xsave. | |
249 | */ | |
44210111 RM |
250 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
251 | { | |
252 | return tsk_used_math(target) ? regset->n : 0; | |
253 | } | |
1da177e4 | 254 | |
44210111 | 255 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 256 | { |
44210111 RM |
257 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
258 | } | |
1da177e4 | 259 | |
44210111 RM |
260 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
261 | unsigned int pos, unsigned int count, | |
262 | void *kbuf, void __user *ubuf) | |
263 | { | |
aa283f49 SS |
264 | int ret; |
265 | ||
44210111 RM |
266 | if (!cpu_has_fxsr) |
267 | return -ENODEV; | |
268 | ||
aa283f49 SS |
269 | ret = init_fpu(target); |
270 | if (ret) | |
271 | return ret; | |
44210111 | 272 | |
29104e10 SS |
273 | sanitize_i387_state(target); |
274 | ||
44210111 | 275 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 276 | &target->thread.fpu.state->fxsave, 0, -1); |
1da177e4 | 277 | } |
44210111 RM |
278 | |
279 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
280 | unsigned int pos, unsigned int count, | |
281 | const void *kbuf, const void __user *ubuf) | |
282 | { | |
283 | int ret; | |
284 | ||
285 | if (!cpu_has_fxsr) | |
286 | return -ENODEV; | |
287 | ||
aa283f49 SS |
288 | ret = init_fpu(target); |
289 | if (ret) | |
290 | return ret; | |
291 | ||
29104e10 SS |
292 | sanitize_i387_state(target); |
293 | ||
44210111 | 294 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
86603283 | 295 | &target->thread.fpu.state->fxsave, 0, -1); |
44210111 RM |
296 | |
297 | /* | |
298 | * mxcsr reserved bits must be masked to zero for security reasons. | |
299 | */ | |
86603283 | 300 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 301 | |
42deec6f SS |
302 | /* |
303 | * update the header bits in the xsave header, indicating the | |
304 | * presence of FP and SSE state. | |
305 | */ | |
306 | if (cpu_has_xsave) | |
86603283 | 307 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; |
42deec6f | 308 | |
44210111 RM |
309 | return ret; |
310 | } | |
311 | ||
5b3efd50 SS |
312 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
313 | unsigned int pos, unsigned int count, | |
314 | void *kbuf, void __user *ubuf) | |
315 | { | |
316 | int ret; | |
317 | ||
318 | if (!cpu_has_xsave) | |
319 | return -ENODEV; | |
320 | ||
321 | ret = init_fpu(target); | |
322 | if (ret) | |
323 | return ret; | |
324 | ||
325 | /* | |
ff7fbc72 SS |
326 | * Copy the 48bytes defined by the software first into the xstate |
327 | * memory layout in the thread struct, so that we can copy the entire | |
328 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 329 | */ |
86603283 | 330 | memcpy(&target->thread.fpu.state->fxsave.sw_reserved, |
ff7fbc72 | 331 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); |
5b3efd50 SS |
332 | |
333 | /* | |
ff7fbc72 | 334 | * Copy the xstate memory layout. |
5b3efd50 SS |
335 | */ |
336 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
86603283 | 337 | &target->thread.fpu.state->xsave, 0, -1); |
5b3efd50 SS |
338 | return ret; |
339 | } | |
340 | ||
341 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
342 | unsigned int pos, unsigned int count, | |
343 | const void *kbuf, const void __user *ubuf) | |
344 | { | |
345 | int ret; | |
346 | struct xsave_hdr_struct *xsave_hdr; | |
347 | ||
348 | if (!cpu_has_xsave) | |
349 | return -ENODEV; | |
350 | ||
351 | ret = init_fpu(target); | |
352 | if (ret) | |
353 | return ret; | |
354 | ||
355 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
86603283 | 356 | &target->thread.fpu.state->xsave, 0, -1); |
5b3efd50 SS |
357 | |
358 | /* | |
359 | * mxcsr reserved bits must be masked to zero for security reasons. | |
360 | */ | |
86603283 | 361 | target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask; |
5b3efd50 | 362 | |
86603283 | 363 | xsave_hdr = &target->thread.fpu.state->xsave.xsave_hdr; |
5b3efd50 SS |
364 | |
365 | xsave_hdr->xstate_bv &= pcntxt_mask; | |
366 | /* | |
367 | * These bits must be zero. | |
368 | */ | |
369 | xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0; | |
370 | ||
371 | return ret; | |
372 | } | |
373 | ||
44210111 | 374 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 375 | |
1da177e4 LT |
376 | /* |
377 | * FPU tag word conversions. | |
378 | */ | |
379 | ||
3b095a04 | 380 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
381 | { |
382 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 383 | |
1da177e4 | 384 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 385 | tmp = ~twd; |
44210111 | 386 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
387 | /* and move the valid bits to the lower byte. */ |
388 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
389 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
390 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 391 | |
3b095a04 | 392 | return tmp; |
1da177e4 LT |
393 | } |
394 | ||
497888cf | 395 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16) |
44210111 RM |
396 | #define FP_EXP_TAG_VALID 0 |
397 | #define FP_EXP_TAG_ZERO 1 | |
398 | #define FP_EXP_TAG_SPECIAL 2 | |
399 | #define FP_EXP_TAG_EMPTY 3 | |
400 | ||
401 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
402 | { | |
403 | struct _fpxreg *st; | |
404 | u32 tos = (fxsave->swd >> 11) & 7; | |
405 | u32 twd = (unsigned long) fxsave->twd; | |
406 | u32 tag; | |
407 | u32 ret = 0xffff0000u; | |
408 | int i; | |
1da177e4 | 409 | |
44210111 | 410 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
411 | if (twd & 0x1) { |
412 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 413 | |
3b095a04 | 414 | switch (st->exponent & 0x7fff) { |
1da177e4 | 415 | case 0x7fff: |
44210111 | 416 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
417 | break; |
418 | case 0x0000: | |
3b095a04 CG |
419 | if (!st->significand[0] && |
420 | !st->significand[1] && | |
421 | !st->significand[2] && | |
44210111 RM |
422 | !st->significand[3]) |
423 | tag = FP_EXP_TAG_ZERO; | |
424 | else | |
425 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
426 | break; |
427 | default: | |
44210111 RM |
428 | if (st->significand[3] & 0x8000) |
429 | tag = FP_EXP_TAG_VALID; | |
430 | else | |
431 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
432 | break; |
433 | } | |
434 | } else { | |
44210111 | 435 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 436 | } |
44210111 | 437 | ret |= tag << (2 * i); |
1da177e4 LT |
438 | } |
439 | return ret; | |
440 | } | |
441 | ||
442 | /* | |
44210111 | 443 | * FXSR floating point environment conversions. |
1da177e4 LT |
444 | */ |
445 | ||
72a671ce | 446 | void |
f668964e | 447 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) |
1da177e4 | 448 | { |
86603283 | 449 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
450 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
451 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
452 | int i; | |
1da177e4 | 453 | |
44210111 RM |
454 | env->cwd = fxsave->cwd | 0xffff0000u; |
455 | env->swd = fxsave->swd | 0xffff0000u; | |
456 | env->twd = twd_fxsr_to_i387(fxsave); | |
457 | ||
458 | #ifdef CONFIG_X86_64 | |
459 | env->fip = fxsave->rip; | |
460 | env->foo = fxsave->rdp; | |
10c11f30 BG |
461 | /* |
462 | * should be actually ds/cs at fpu exception time, but | |
463 | * that information is not available in 64bit mode. | |
464 | */ | |
465 | env->fcs = task_pt_regs(tsk)->cs; | |
44210111 | 466 | if (tsk == current) { |
10c11f30 | 467 | savesegment(ds, env->fos); |
1da177e4 | 468 | } else { |
10c11f30 | 469 | env->fos = tsk->thread.ds; |
1da177e4 | 470 | } |
10c11f30 | 471 | env->fos |= 0xffff0000; |
44210111 RM |
472 | #else |
473 | env->fip = fxsave->fip; | |
609b5297 | 474 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
475 | env->foo = fxsave->foo; |
476 | env->fos = fxsave->fos; | |
477 | #endif | |
1da177e4 | 478 | |
44210111 RM |
479 | for (i = 0; i < 8; ++i) |
480 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
481 | } |
482 | ||
72a671ce SS |
483 | void convert_to_fxsr(struct task_struct *tsk, |
484 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 485 | |
1da177e4 | 486 | { |
86603283 | 487 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
488 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
489 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
490 | int i; | |
1da177e4 | 491 | |
44210111 RM |
492 | fxsave->cwd = env->cwd; |
493 | fxsave->swd = env->swd; | |
494 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
495 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
496 | #ifdef CONFIG_X86_64 | |
497 | fxsave->rip = env->fip; | |
498 | fxsave->rdp = env->foo; | |
499 | /* cs and ds ignored */ | |
500 | #else | |
501 | fxsave->fip = env->fip; | |
502 | fxsave->fcs = (env->fcs & 0xffff); | |
503 | fxsave->foo = env->foo; | |
504 | fxsave->fos = env->fos; | |
505 | #endif | |
1da177e4 | 506 | |
44210111 RM |
507 | for (i = 0; i < 8; ++i) |
508 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
509 | } |
510 | ||
44210111 RM |
511 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
512 | unsigned int pos, unsigned int count, | |
513 | void *kbuf, void __user *ubuf) | |
1da177e4 | 514 | { |
44210111 | 515 | struct user_i387_ia32_struct env; |
aa283f49 | 516 | int ret; |
1da177e4 | 517 | |
aa283f49 SS |
518 | ret = init_fpu(target); |
519 | if (ret) | |
520 | return ret; | |
1da177e4 | 521 | |
60e019eb | 522 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
523 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); |
524 | ||
60e019eb | 525 | if (!cpu_has_fxsr) |
44210111 | 526 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
86603283 | 527 | &target->thread.fpu.state->fsave, 0, |
61c4628b | 528 | -1); |
1da177e4 | 529 | |
29104e10 SS |
530 | sanitize_i387_state(target); |
531 | ||
44210111 RM |
532 | if (kbuf && pos == 0 && count == sizeof(env)) { |
533 | convert_from_fxsr(kbuf, target); | |
534 | return 0; | |
1da177e4 | 535 | } |
44210111 RM |
536 | |
537 | convert_from_fxsr(&env, target); | |
f668964e | 538 | |
44210111 | 539 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
540 | } |
541 | ||
44210111 RM |
542 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
543 | unsigned int pos, unsigned int count, | |
544 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 545 | { |
44210111 RM |
546 | struct user_i387_ia32_struct env; |
547 | int ret; | |
1da177e4 | 548 | |
aa283f49 SS |
549 | ret = init_fpu(target); |
550 | if (ret) | |
551 | return ret; | |
552 | ||
29104e10 SS |
553 | sanitize_i387_state(target); |
554 | ||
60e019eb | 555 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
556 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); |
557 | ||
60e019eb | 558 | if (!cpu_has_fxsr) |
44210111 | 559 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
60e019eb PA |
560 | &target->thread.fpu.state->fsave, 0, |
561 | -1); | |
44210111 RM |
562 | |
563 | if (pos > 0 || count < sizeof(env)) | |
564 | convert_from_fxsr(&env, target); | |
565 | ||
566 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
567 | if (!ret) | |
568 | convert_to_fxsr(target, &env); | |
569 | ||
42deec6f SS |
570 | /* |
571 | * update the header bit in the xsave header, indicating the | |
572 | * presence of FP. | |
573 | */ | |
574 | if (cpu_has_xsave) | |
86603283 | 575 | target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP; |
44210111 | 576 | return ret; |
1da177e4 LT |
577 | } |
578 | ||
1da177e4 LT |
579 | /* |
580 | * FPU state for core dumps. | |
60b3b9af RM |
581 | * This is only used for a.out dumps now. |
582 | * It is declared generically using elf_fpregset_t (which is | |
583 | * struct user_i387_struct) but is in fact only used for 32-bit | |
584 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 585 | */ |
3b095a04 | 586 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 587 | { |
1da177e4 | 588 | struct task_struct *tsk = current; |
f668964e | 589 | int fpvalid; |
1da177e4 LT |
590 | |
591 | fpvalid = !!used_math(); | |
60b3b9af RM |
592 | if (fpvalid) |
593 | fpvalid = !fpregs_get(tsk, NULL, | |
594 | 0, sizeof(struct user_i387_ia32_struct), | |
595 | fpu, NULL); | |
1da177e4 LT |
596 | |
597 | return fpvalid; | |
598 | } | |
129f6946 | 599 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 600 | |
60b3b9af | 601 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |
60e019eb PA |
602 | |
603 | static int __init no_387(char *s) | |
604 | { | |
605 | setup_clear_cpu_cap(X86_FEATURE_FPU); | |
606 | return 1; | |
607 | } | |
608 | ||
609 | __setup("no387", no_387); | |
610 | ||
148f9bb8 | 611 | void fpu_detect(struct cpuinfo_x86 *c) |
60e019eb PA |
612 | { |
613 | unsigned long cr0; | |
614 | u16 fsw, fcw; | |
615 | ||
616 | fsw = fcw = 0xffff; | |
617 | ||
618 | cr0 = read_cr0(); | |
619 | cr0 &= ~(X86_CR0_TS | X86_CR0_EM); | |
620 | write_cr0(cr0); | |
621 | ||
622 | asm volatile("fninit ; fnstsw %0 ; fnstcw %1" | |
623 | : "+m" (fsw), "+m" (fcw)); | |
624 | ||
625 | if (fsw == 0 && (fcw & 0x103f) == 0x003f) | |
626 | set_cpu_cap(c, X86_FEATURE_FPU); | |
627 | else | |
628 | clear_cpu_cap(c, X86_FEATURE_FPU); | |
629 | ||
630 | /* The final cr0 value is set in fpu_init() */ | |
631 | } |