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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e | 10 | #include <linux/sched.h> |
5a0e3ad6 | 11 | #include <linux/slab.h> |
f668964e IM |
12 | |
13 | #include <asm/sigcontext.h> | |
1da177e4 | 14 | #include <asm/processor.h> |
1da177e4 | 15 | #include <asm/math_emu.h> |
1da177e4 | 16 | #include <asm/uaccess.h> |
f668964e IM |
17 | #include <asm/ptrace.h> |
18 | #include <asm/i387.h> | |
19 | #include <asm/user.h> | |
1da177e4 | 20 | |
44210111 | 21 | #ifdef CONFIG_X86_64 |
f668964e IM |
22 | # include <asm/sigcontext32.h> |
23 | # include <asm/user32.h> | |
44210111 | 24 | #else |
ab513701 SS |
25 | # define save_i387_xstate_ia32 save_i387_xstate |
26 | # define restore_i387_xstate_ia32 restore_i387_xstate | |
f668964e | 27 | # define _fpstate_ia32 _fpstate |
ab513701 | 28 | # define _xstate_ia32 _xstate |
3c1c7f10 | 29 | # define sig_xstate_ia32_size sig_xstate_size |
c37b5efe | 30 | # define fx_sw_reserved_ia32 fx_sw_reserved |
f668964e IM |
31 | # define user_i387_ia32_struct user_i387_struct |
32 | # define user32_fxsr_struct user_fxsr_struct | |
44210111 RM |
33 | #endif |
34 | ||
1da177e4 | 35 | #ifdef CONFIG_MATH_EMULATION |
f668964e | 36 | # define HAVE_HWFP (boot_cpu_data.hard_math) |
1da177e4 | 37 | #else |
f668964e | 38 | # define HAVE_HWFP 1 |
1da177e4 LT |
39 | #endif |
40 | ||
f668964e | 41 | static unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b | 42 | unsigned int xstate_size; |
3c1c7f10 | 43 | unsigned int sig_xstate_ia32_size = sizeof(struct _fpstate_ia32); |
61c4628b | 44 | static struct i387_fxsave_struct fx_scratch __cpuinitdata; |
1da177e4 | 45 | |
61c4628b | 46 | void __cpuinit mxcsr_feature_mask_init(void) |
1da177e4 LT |
47 | { |
48 | unsigned long mask = 0; | |
f668964e | 49 | |
1da177e4 LT |
50 | clts(); |
51 | if (cpu_has_fxsr) { | |
61c4628b SS |
52 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
53 | asm volatile("fxsave %0" : : "m" (fx_scratch)); | |
54 | mask = fx_scratch.mxcsr_mask; | |
3b095a04 CG |
55 | if (mask == 0) |
56 | mask = 0x0000ffbf; | |
57 | } | |
1da177e4 LT |
58 | mxcsr_feature_mask &= mask; |
59 | stts(); | |
60 | } | |
61 | ||
9bc646f1 | 62 | void __cpuinit init_thread_xstate(void) |
61c4628b | 63 | { |
e8a496ac SS |
64 | if (!HAVE_HWFP) { |
65 | xstate_size = sizeof(struct i387_soft_struct); | |
66 | return; | |
67 | } | |
68 | ||
dc1e35c6 SS |
69 | if (cpu_has_xsave) { |
70 | xsave_cntxt_init(); | |
71 | return; | |
72 | } | |
73 | ||
61c4628b SS |
74 | if (cpu_has_fxsr) |
75 | xstate_size = sizeof(struct i387_fxsave_struct); | |
76 | #ifdef CONFIG_X86_32 | |
77 | else | |
78 | xstate_size = sizeof(struct i387_fsave_struct); | |
79 | #endif | |
61c4628b SS |
80 | } |
81 | ||
44210111 RM |
82 | #ifdef CONFIG_X86_64 |
83 | /* | |
84 | * Called at bootup to set up the initial FPU state that is later cloned | |
85 | * into all processes. | |
86 | */ | |
87 | void __cpuinit fpu_init(void) | |
88 | { | |
89 | unsigned long oldcr0 = read_cr0(); | |
f668964e | 90 | |
44210111 RM |
91 | set_in_cr4(X86_CR4_OSFXSR); |
92 | set_in_cr4(X86_CR4_OSXMMEXCPT); | |
93 | ||
f668964e | 94 | write_cr0(oldcr0 & ~(X86_CR0_TS|X86_CR0_EM)); /* clear TS and EM */ |
44210111 | 95 | |
dc1e35c6 SS |
96 | /* |
97 | * Boot processor to setup the FP and extended state context info. | |
98 | */ | |
99 | if (!smp_processor_id()) | |
100 | init_thread_xstate(); | |
101 | xsave_init(); | |
102 | ||
44210111 RM |
103 | mxcsr_feature_mask_init(); |
104 | /* clean state in init */ | |
b359e8a4 SS |
105 | if (cpu_has_xsave) |
106 | current_thread_info()->status = TS_XSAVE; | |
107 | else | |
108 | current_thread_info()->status = 0; | |
44210111 RM |
109 | clear_used_math(); |
110 | } | |
111 | #endif /* CONFIG_X86_64 */ | |
112 | ||
1da177e4 LT |
113 | /* |
114 | * The _current_ task is using the FPU for the first time | |
115 | * so initialize it and set the mxcsr to its default | |
116 | * value at reset if we support XMM instructions and then | |
117 | * remeber the current task has used the FPU. | |
118 | */ | |
aa283f49 | 119 | int init_fpu(struct task_struct *tsk) |
1da177e4 | 120 | { |
44210111 | 121 | if (tsk_used_math(tsk)) { |
e8a496ac | 122 | if (HAVE_HWFP && tsk == current) |
44210111 | 123 | unlazy_fpu(tsk); |
aa283f49 SS |
124 | return 0; |
125 | } | |
126 | ||
127 | /* | |
128 | * Memory allocation at the first usage of the FPU and other state. | |
129 | */ | |
130 | if (!tsk->thread.xstate) { | |
131 | tsk->thread.xstate = kmem_cache_alloc(task_xstate_cachep, | |
132 | GFP_KERNEL); | |
133 | if (!tsk->thread.xstate) | |
134 | return -ENOMEM; | |
44210111 RM |
135 | } |
136 | ||
e8a496ac SS |
137 | #ifdef CONFIG_X86_32 |
138 | if (!HAVE_HWFP) { | |
139 | memset(tsk->thread.xstate, 0, xstate_size); | |
ab9e1858 | 140 | finit_task(tsk); |
e8a496ac SS |
141 | set_stopped_child_used_math(tsk); |
142 | return 0; | |
143 | } | |
144 | #endif | |
145 | ||
1da177e4 | 146 | if (cpu_has_fxsr) { |
61c4628b SS |
147 | struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave; |
148 | ||
149 | memset(fx, 0, xstate_size); | |
150 | fx->cwd = 0x37f; | |
1da177e4 | 151 | if (cpu_has_xmm) |
61c4628b | 152 | fx->mxcsr = MXCSR_DEFAULT; |
1da177e4 | 153 | } else { |
61c4628b SS |
154 | struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave; |
155 | memset(fp, 0, xstate_size); | |
156 | fp->cwd = 0xffff037fu; | |
157 | fp->swd = 0xffff0000u; | |
158 | fp->twd = 0xffffffffu; | |
159 | fp->fos = 0xffff0000u; | |
1da177e4 | 160 | } |
44210111 RM |
161 | /* |
162 | * Only the device not available exception or ptrace can call init_fpu. | |
163 | */ | |
1da177e4 | 164 | set_stopped_child_used_math(tsk); |
aa283f49 | 165 | return 0; |
1da177e4 LT |
166 | } |
167 | ||
5b3efd50 SS |
168 | /* |
169 | * The xstateregs_active() routine is the same as the fpregs_active() routine, | |
170 | * as the "regset->n" for the xstate regset will be updated based on the feature | |
171 | * capabilites supported by the xsave. | |
172 | */ | |
44210111 RM |
173 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
174 | { | |
175 | return tsk_used_math(target) ? regset->n : 0; | |
176 | } | |
1da177e4 | 177 | |
44210111 | 178 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 179 | { |
44210111 RM |
180 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
181 | } | |
1da177e4 | 182 | |
44210111 RM |
183 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
184 | unsigned int pos, unsigned int count, | |
185 | void *kbuf, void __user *ubuf) | |
186 | { | |
aa283f49 SS |
187 | int ret; |
188 | ||
44210111 RM |
189 | if (!cpu_has_fxsr) |
190 | return -ENODEV; | |
191 | ||
aa283f49 SS |
192 | ret = init_fpu(target); |
193 | if (ret) | |
194 | return ret; | |
44210111 RM |
195 | |
196 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
61c4628b | 197 | &target->thread.xstate->fxsave, 0, -1); |
1da177e4 | 198 | } |
44210111 RM |
199 | |
200 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
201 | unsigned int pos, unsigned int count, | |
202 | const void *kbuf, const void __user *ubuf) | |
203 | { | |
204 | int ret; | |
205 | ||
206 | if (!cpu_has_fxsr) | |
207 | return -ENODEV; | |
208 | ||
aa283f49 SS |
209 | ret = init_fpu(target); |
210 | if (ret) | |
211 | return ret; | |
212 | ||
44210111 | 213 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
61c4628b | 214 | &target->thread.xstate->fxsave, 0, -1); |
44210111 RM |
215 | |
216 | /* | |
217 | * mxcsr reserved bits must be masked to zero for security reasons. | |
218 | */ | |
61c4628b | 219 | target->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 220 | |
42deec6f SS |
221 | /* |
222 | * update the header bits in the xsave header, indicating the | |
223 | * presence of FP and SSE state. | |
224 | */ | |
225 | if (cpu_has_xsave) | |
226 | target->thread.xstate->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; | |
227 | ||
44210111 RM |
228 | return ret; |
229 | } | |
230 | ||
5b3efd50 SS |
231 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
232 | unsigned int pos, unsigned int count, | |
233 | void *kbuf, void __user *ubuf) | |
234 | { | |
235 | int ret; | |
236 | ||
237 | if (!cpu_has_xsave) | |
238 | return -ENODEV; | |
239 | ||
240 | ret = init_fpu(target); | |
241 | if (ret) | |
242 | return ret; | |
243 | ||
244 | /* | |
ff7fbc72 SS |
245 | * Copy the 48bytes defined by the software first into the xstate |
246 | * memory layout in the thread struct, so that we can copy the entire | |
247 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 248 | */ |
ff7fbc72 SS |
249 | memcpy(&target->thread.xstate->fxsave.sw_reserved, |
250 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); | |
5b3efd50 SS |
251 | |
252 | /* | |
ff7fbc72 | 253 | * Copy the xstate memory layout. |
5b3efd50 SS |
254 | */ |
255 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
ff7fbc72 | 256 | &target->thread.xstate->xsave, 0, -1); |
5b3efd50 SS |
257 | return ret; |
258 | } | |
259 | ||
260 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
261 | unsigned int pos, unsigned int count, | |
262 | const void *kbuf, const void __user *ubuf) | |
263 | { | |
264 | int ret; | |
265 | struct xsave_hdr_struct *xsave_hdr; | |
266 | ||
267 | if (!cpu_has_xsave) | |
268 | return -ENODEV; | |
269 | ||
270 | ret = init_fpu(target); | |
271 | if (ret) | |
272 | return ret; | |
273 | ||
274 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
275 | &target->thread.xstate->xsave, 0, -1); | |
276 | ||
277 | /* | |
278 | * mxcsr reserved bits must be masked to zero for security reasons. | |
279 | */ | |
280 | target->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask; | |
281 | ||
282 | xsave_hdr = &target->thread.xstate->xsave.xsave_hdr; | |
283 | ||
284 | xsave_hdr->xstate_bv &= pcntxt_mask; | |
285 | /* | |
286 | * These bits must be zero. | |
287 | */ | |
288 | xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0; | |
289 | ||
290 | return ret; | |
291 | } | |
292 | ||
44210111 | 293 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 294 | |
1da177e4 LT |
295 | /* |
296 | * FPU tag word conversions. | |
297 | */ | |
298 | ||
3b095a04 | 299 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
300 | { |
301 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 302 | |
1da177e4 | 303 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 304 | tmp = ~twd; |
44210111 | 305 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
306 | /* and move the valid bits to the lower byte. */ |
307 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
308 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
309 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 310 | |
3b095a04 | 311 | return tmp; |
1da177e4 LT |
312 | } |
313 | ||
1da177e4 | 314 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16); |
44210111 RM |
315 | #define FP_EXP_TAG_VALID 0 |
316 | #define FP_EXP_TAG_ZERO 1 | |
317 | #define FP_EXP_TAG_SPECIAL 2 | |
318 | #define FP_EXP_TAG_EMPTY 3 | |
319 | ||
320 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
321 | { | |
322 | struct _fpxreg *st; | |
323 | u32 tos = (fxsave->swd >> 11) & 7; | |
324 | u32 twd = (unsigned long) fxsave->twd; | |
325 | u32 tag; | |
326 | u32 ret = 0xffff0000u; | |
327 | int i; | |
1da177e4 | 328 | |
44210111 | 329 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
330 | if (twd & 0x1) { |
331 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 332 | |
3b095a04 | 333 | switch (st->exponent & 0x7fff) { |
1da177e4 | 334 | case 0x7fff: |
44210111 | 335 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
336 | break; |
337 | case 0x0000: | |
3b095a04 CG |
338 | if (!st->significand[0] && |
339 | !st->significand[1] && | |
340 | !st->significand[2] && | |
44210111 RM |
341 | !st->significand[3]) |
342 | tag = FP_EXP_TAG_ZERO; | |
343 | else | |
344 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
345 | break; |
346 | default: | |
44210111 RM |
347 | if (st->significand[3] & 0x8000) |
348 | tag = FP_EXP_TAG_VALID; | |
349 | else | |
350 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
351 | break; |
352 | } | |
353 | } else { | |
44210111 | 354 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 355 | } |
44210111 | 356 | ret |= tag << (2 * i); |
1da177e4 LT |
357 | } |
358 | return ret; | |
359 | } | |
360 | ||
361 | /* | |
44210111 | 362 | * FXSR floating point environment conversions. |
1da177e4 LT |
363 | */ |
364 | ||
f668964e IM |
365 | static void |
366 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) | |
1da177e4 | 367 | { |
61c4628b | 368 | struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave; |
44210111 RM |
369 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
370 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
371 | int i; | |
1da177e4 | 372 | |
44210111 RM |
373 | env->cwd = fxsave->cwd | 0xffff0000u; |
374 | env->swd = fxsave->swd | 0xffff0000u; | |
375 | env->twd = twd_fxsr_to_i387(fxsave); | |
376 | ||
377 | #ifdef CONFIG_X86_64 | |
378 | env->fip = fxsave->rip; | |
379 | env->foo = fxsave->rdp; | |
380 | if (tsk == current) { | |
381 | /* | |
382 | * should be actually ds/cs at fpu exception time, but | |
383 | * that information is not available in 64bit mode. | |
384 | */ | |
f668964e IM |
385 | asm("mov %%ds, %[fos]" : [fos] "=r" (env->fos)); |
386 | asm("mov %%cs, %[fcs]" : [fcs] "=r" (env->fcs)); | |
1da177e4 | 387 | } else { |
44210111 | 388 | struct pt_regs *regs = task_pt_regs(tsk); |
f668964e | 389 | |
44210111 RM |
390 | env->fos = 0xffff0000 | tsk->thread.ds; |
391 | env->fcs = regs->cs; | |
1da177e4 | 392 | } |
44210111 RM |
393 | #else |
394 | env->fip = fxsave->fip; | |
609b5297 | 395 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
396 | env->foo = fxsave->foo; |
397 | env->fos = fxsave->fos; | |
398 | #endif | |
1da177e4 | 399 | |
44210111 RM |
400 | for (i = 0; i < 8; ++i) |
401 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
402 | } |
403 | ||
44210111 RM |
404 | static void convert_to_fxsr(struct task_struct *tsk, |
405 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 406 | |
1da177e4 | 407 | { |
61c4628b | 408 | struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave; |
44210111 RM |
409 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
410 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
411 | int i; | |
1da177e4 | 412 | |
44210111 RM |
413 | fxsave->cwd = env->cwd; |
414 | fxsave->swd = env->swd; | |
415 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
416 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
417 | #ifdef CONFIG_X86_64 | |
418 | fxsave->rip = env->fip; | |
419 | fxsave->rdp = env->foo; | |
420 | /* cs and ds ignored */ | |
421 | #else | |
422 | fxsave->fip = env->fip; | |
423 | fxsave->fcs = (env->fcs & 0xffff); | |
424 | fxsave->foo = env->foo; | |
425 | fxsave->fos = env->fos; | |
426 | #endif | |
1da177e4 | 427 | |
44210111 RM |
428 | for (i = 0; i < 8; ++i) |
429 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
430 | } |
431 | ||
44210111 RM |
432 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
433 | unsigned int pos, unsigned int count, | |
434 | void *kbuf, void __user *ubuf) | |
1da177e4 | 435 | { |
44210111 | 436 | struct user_i387_ia32_struct env; |
aa283f49 | 437 | int ret; |
1da177e4 | 438 | |
aa283f49 SS |
439 | ret = init_fpu(target); |
440 | if (ret) | |
441 | return ret; | |
1da177e4 | 442 | |
e8a496ac SS |
443 | if (!HAVE_HWFP) |
444 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); | |
445 | ||
f668964e | 446 | if (!cpu_has_fxsr) { |
44210111 | 447 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
61c4628b SS |
448 | &target->thread.xstate->fsave, 0, |
449 | -1); | |
f668964e | 450 | } |
1da177e4 | 451 | |
44210111 RM |
452 | if (kbuf && pos == 0 && count == sizeof(env)) { |
453 | convert_from_fxsr(kbuf, target); | |
454 | return 0; | |
1da177e4 | 455 | } |
44210111 RM |
456 | |
457 | convert_from_fxsr(&env, target); | |
f668964e | 458 | |
44210111 | 459 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
460 | } |
461 | ||
44210111 RM |
462 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
463 | unsigned int pos, unsigned int count, | |
464 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 465 | { |
44210111 RM |
466 | struct user_i387_ia32_struct env; |
467 | int ret; | |
1da177e4 | 468 | |
aa283f49 SS |
469 | ret = init_fpu(target); |
470 | if (ret) | |
471 | return ret; | |
472 | ||
e8a496ac SS |
473 | if (!HAVE_HWFP) |
474 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); | |
475 | ||
f668964e | 476 | if (!cpu_has_fxsr) { |
44210111 | 477 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
61c4628b | 478 | &target->thread.xstate->fsave, 0, -1); |
f668964e | 479 | } |
44210111 RM |
480 | |
481 | if (pos > 0 || count < sizeof(env)) | |
482 | convert_from_fxsr(&env, target); | |
483 | ||
484 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
485 | if (!ret) | |
486 | convert_to_fxsr(target, &env); | |
487 | ||
42deec6f SS |
488 | /* |
489 | * update the header bit in the xsave header, indicating the | |
490 | * presence of FP. | |
491 | */ | |
492 | if (cpu_has_xsave) | |
493 | target->thread.xstate->xsave.xsave_hdr.xstate_bv |= XSTATE_FP; | |
44210111 | 494 | return ret; |
1da177e4 LT |
495 | } |
496 | ||
497 | /* | |
498 | * Signal frame handlers. | |
499 | */ | |
500 | ||
44210111 | 501 | static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
502 | { |
503 | struct task_struct *tsk = current; | |
61c4628b | 504 | struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave; |
1da177e4 | 505 | |
61c4628b SS |
506 | fp->status = fp->swd; |
507 | if (__copy_to_user(buf, fp, sizeof(struct i387_fsave_struct))) | |
1da177e4 LT |
508 | return -1; |
509 | return 1; | |
510 | } | |
511 | ||
44210111 | 512 | static int save_i387_fxsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
513 | { |
514 | struct task_struct *tsk = current; | |
61c4628b | 515 | struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave; |
44210111 | 516 | struct user_i387_ia32_struct env; |
1da177e4 LT |
517 | int err = 0; |
518 | ||
44210111 RM |
519 | convert_from_fxsr(&env, tsk); |
520 | if (__copy_to_user(buf, &env, sizeof(env))) | |
1da177e4 LT |
521 | return -1; |
522 | ||
61c4628b | 523 | err |= __put_user(fx->swd, &buf->status); |
3b095a04 CG |
524 | err |= __put_user(X86_FXSR_MAGIC, &buf->magic); |
525 | if (err) | |
1da177e4 LT |
526 | return -1; |
527 | ||
c37b5efe | 528 | if (__copy_to_user(&buf->_fxsr_env[0], fx, xstate_size)) |
1da177e4 LT |
529 | return -1; |
530 | return 1; | |
531 | } | |
532 | ||
c37b5efe SS |
533 | static int save_i387_xsave(void __user *buf) |
534 | { | |
04944b79 | 535 | struct task_struct *tsk = current; |
c37b5efe SS |
536 | struct _fpstate_ia32 __user *fx = buf; |
537 | int err = 0; | |
538 | ||
04944b79 SS |
539 | /* |
540 | * For legacy compatible, we always set FP/SSE bits in the bit | |
541 | * vector while saving the state to the user context. | |
542 | * This will enable us capturing any changes(during sigreturn) to | |
543 | * the FP/SSE bits by the legacy applications which don't touch | |
544 | * xstate_bv in the xsave header. | |
545 | * | |
546 | * xsave aware applications can change the xstate_bv in the xsave | |
547 | * header as well as change any contents in the memory layout. | |
548 | * xrestore as part of sigreturn will capture all the changes. | |
549 | */ | |
550 | tsk->thread.xstate->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE; | |
551 | ||
c37b5efe SS |
552 | if (save_i387_fxsave(fx) < 0) |
553 | return -1; | |
554 | ||
555 | err = __copy_to_user(&fx->sw_reserved, &fx_sw_reserved_ia32, | |
556 | sizeof(struct _fpx_sw_bytes)); | |
557 | err |= __put_user(FP_XSTATE_MAGIC2, | |
558 | (__u32 __user *) (buf + sig_xstate_ia32_size | |
559 | - FP_XSTATE_MAGIC2_SIZE)); | |
560 | if (err) | |
561 | return -1; | |
562 | ||
563 | return 1; | |
564 | } | |
565 | ||
ab513701 | 566 | int save_i387_xstate_ia32(void __user *buf) |
1da177e4 | 567 | { |
ab513701 SS |
568 | struct _fpstate_ia32 __user *fp = (struct _fpstate_ia32 __user *) buf; |
569 | struct task_struct *tsk = current; | |
570 | ||
3b095a04 | 571 | if (!used_math()) |
1da177e4 | 572 | return 0; |
ab513701 SS |
573 | |
574 | if (!access_ok(VERIFY_WRITE, buf, sig_xstate_ia32_size)) | |
575 | return -EACCES; | |
f668964e IM |
576 | /* |
577 | * This will cause a "finit" to be triggered by the next | |
1da177e4 LT |
578 | * attempted FPU operation by the 'current' process. |
579 | */ | |
580 | clear_used_math(); | |
581 | ||
f668964e | 582 | if (!HAVE_HWFP) { |
44210111 RM |
583 | return fpregs_soft_get(current, NULL, |
584 | 0, sizeof(struct user_i387_ia32_struct), | |
ab513701 | 585 | NULL, fp) ? -1 : 1; |
1da177e4 | 586 | } |
f668964e | 587 | |
ab513701 SS |
588 | unlazy_fpu(tsk); |
589 | ||
c37b5efe SS |
590 | if (cpu_has_xsave) |
591 | return save_i387_xsave(fp); | |
f668964e | 592 | if (cpu_has_fxsr) |
ab513701 | 593 | return save_i387_fxsave(fp); |
f668964e | 594 | else |
ab513701 | 595 | return save_i387_fsave(fp); |
1da177e4 LT |
596 | } |
597 | ||
44210111 | 598 | static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
599 | { |
600 | struct task_struct *tsk = current; | |
f668964e | 601 | |
61c4628b | 602 | return __copy_from_user(&tsk->thread.xstate->fsave, buf, |
3b095a04 | 603 | sizeof(struct i387_fsave_struct)); |
1da177e4 LT |
604 | } |
605 | ||
c37b5efe SS |
606 | static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf, |
607 | unsigned int size) | |
1da177e4 | 608 | { |
1da177e4 | 609 | struct task_struct *tsk = current; |
44210111 | 610 | struct user_i387_ia32_struct env; |
f668964e IM |
611 | int err; |
612 | ||
61c4628b | 613 | err = __copy_from_user(&tsk->thread.xstate->fxsave, &buf->_fxsr_env[0], |
c37b5efe | 614 | size); |
1da177e4 | 615 | /* mxcsr reserved bits must be masked to zero for security reasons */ |
61c4628b | 616 | tsk->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 RM |
617 | if (err || __copy_from_user(&env, buf, sizeof(env))) |
618 | return 1; | |
619 | convert_to_fxsr(tsk, &env); | |
f668964e | 620 | |
44210111 | 621 | return 0; |
1da177e4 LT |
622 | } |
623 | ||
c37b5efe SS |
624 | static int restore_i387_xsave(void __user *buf) |
625 | { | |
626 | struct _fpx_sw_bytes fx_sw_user; | |
627 | struct _fpstate_ia32 __user *fx_user = | |
628 | ((struct _fpstate_ia32 __user *) buf); | |
629 | struct i387_fxsave_struct __user *fx = | |
630 | (struct i387_fxsave_struct __user *) &fx_user->_fxsr_env[0]; | |
631 | struct xsave_hdr_struct *xsave_hdr = | |
632 | ¤t->thread.xstate->xsave.xsave_hdr; | |
6152e4b1 | 633 | u64 mask; |
c37b5efe SS |
634 | int err; |
635 | ||
636 | if (check_for_xstate(fx, buf, &fx_sw_user)) | |
637 | goto fx_only; | |
638 | ||
6152e4b1 | 639 | mask = fx_sw_user.xstate_bv; |
c37b5efe SS |
640 | |
641 | err = restore_i387_fxsave(buf, fx_sw_user.xstate_size); | |
642 | ||
6152e4b1 | 643 | xsave_hdr->xstate_bv &= pcntxt_mask; |
c37b5efe SS |
644 | /* |
645 | * These bits must be zero. | |
646 | */ | |
647 | xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0; | |
648 | ||
649 | /* | |
650 | * Init the state that is not present in the memory layout | |
651 | * and enabled by the OS. | |
652 | */ | |
6152e4b1 PA |
653 | mask = ~(pcntxt_mask & ~mask); |
654 | xsave_hdr->xstate_bv &= mask; | |
c37b5efe SS |
655 | |
656 | return err; | |
657 | fx_only: | |
658 | /* | |
659 | * Couldn't find the extended state information in the memory | |
660 | * layout. Restore the FP/SSE and init the other extended state | |
661 | * enabled by the OS. | |
662 | */ | |
663 | xsave_hdr->xstate_bv = XSTATE_FPSSE; | |
664 | return restore_i387_fxsave(buf, sizeof(struct i387_fxsave_struct)); | |
665 | } | |
666 | ||
ab513701 | 667 | int restore_i387_xstate_ia32(void __user *buf) |
1da177e4 LT |
668 | { |
669 | int err; | |
e8a496ac | 670 | struct task_struct *tsk = current; |
ab513701 | 671 | struct _fpstate_ia32 __user *fp = (struct _fpstate_ia32 __user *) buf; |
1da177e4 | 672 | |
e8a496ac | 673 | if (HAVE_HWFP) |
fd3c3ed5 SS |
674 | clear_fpu(tsk); |
675 | ||
ab513701 SS |
676 | if (!buf) { |
677 | if (used_math()) { | |
678 | clear_fpu(tsk); | |
679 | clear_used_math(); | |
680 | } | |
681 | ||
682 | return 0; | |
683 | } else | |
684 | if (!access_ok(VERIFY_READ, buf, sig_xstate_ia32_size)) | |
685 | return -EACCES; | |
686 | ||
e8a496ac SS |
687 | if (!used_math()) { |
688 | err = init_fpu(tsk); | |
689 | if (err) | |
690 | return err; | |
691 | } | |
fd3c3ed5 | 692 | |
e8a496ac | 693 | if (HAVE_HWFP) { |
c37b5efe SS |
694 | if (cpu_has_xsave) |
695 | err = restore_i387_xsave(buf); | |
696 | else if (cpu_has_fxsr) | |
697 | err = restore_i387_fxsave(fp, sizeof(struct | |
698 | i387_fxsave_struct)); | |
f668964e | 699 | else |
ab513701 | 700 | err = restore_i387_fsave(fp); |
1da177e4 | 701 | } else { |
44210111 RM |
702 | err = fpregs_soft_set(current, NULL, |
703 | 0, sizeof(struct user_i387_ia32_struct), | |
ab513701 | 704 | NULL, fp) != 0; |
1da177e4 LT |
705 | } |
706 | set_used_math(); | |
f668964e | 707 | |
1da177e4 LT |
708 | return err; |
709 | } | |
710 | ||
1da177e4 LT |
711 | /* |
712 | * FPU state for core dumps. | |
60b3b9af RM |
713 | * This is only used for a.out dumps now. |
714 | * It is declared generically using elf_fpregset_t (which is | |
715 | * struct user_i387_struct) but is in fact only used for 32-bit | |
716 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 717 | */ |
3b095a04 | 718 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 719 | { |
1da177e4 | 720 | struct task_struct *tsk = current; |
f668964e | 721 | int fpvalid; |
1da177e4 LT |
722 | |
723 | fpvalid = !!used_math(); | |
60b3b9af RM |
724 | if (fpvalid) |
725 | fpvalid = !fpregs_get(tsk, NULL, | |
726 | 0, sizeof(struct user_i387_ia32_struct), | |
727 | fpu, NULL); | |
1da177e4 LT |
728 | |
729 | return fpvalid; | |
730 | } | |
129f6946 | 731 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 732 | |
60b3b9af | 733 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |