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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
795312e7 | 2 | /* |
835c34a1 | 3 | * 8237A DMA controller suspend functions. |
795312e7 PO |
4 | * |
5 | * Written by Pierre Ossman, 2005. | |
6 | */ | |
7 | ||
f79b1c57 | 8 | #include <linux/dmi.h> |
795312e7 | 9 | #include <linux/init.h> |
f3c6ea1b | 10 | #include <linux/syscore_ops.h> |
795312e7 PO |
11 | |
12 | #include <asm/dma.h> | |
f79b1c57 | 13 | #include <asm/x86_init.h> |
795312e7 PO |
14 | |
15 | /* | |
16 | * This module just handles suspend/resume issues with the | |
17 | * 8237A DMA controller (used for ISA and LPC). | |
18 | * Allocation is handled in kernel/dma.c and normal usage is | |
19 | * in asm/dma.h. | |
20 | */ | |
21 | ||
f3c6ea1b | 22 | static void i8237A_resume(void) |
795312e7 PO |
23 | { |
24 | unsigned long flags; | |
25 | int i; | |
26 | ||
27 | flags = claim_dma_lock(); | |
28 | ||
b52af409 CL |
29 | dma_outb(0, DMA1_RESET_REG); |
30 | dma_outb(0, DMA2_RESET_REG); | |
795312e7 | 31 | |
b52af409 | 32 | for (i = 0; i < 8; i++) { |
795312e7 PO |
33 | set_dma_addr(i, 0x000000); |
34 | /* DMA count is a bit weird so this is not 0 */ | |
35 | set_dma_count(i, 1); | |
36 | } | |
37 | ||
38 | /* Enable cascade DMA or channel 0-3 won't work */ | |
39 | enable_dma(4); | |
40 | ||
41 | release_dma_lock(flags); | |
795312e7 PO |
42 | } |
43 | ||
f3c6ea1b | 44 | static struct syscore_ops i8237_syscore_ops = { |
b52af409 | 45 | .resume = i8237A_resume, |
795312e7 PO |
46 | }; |
47 | ||
f3c6ea1b | 48 | static int __init i8237A_init_ops(void) |
795312e7 | 49 | { |
f79b1c57 RB |
50 | /* |
51 | * From SKL PCH onwards, the legacy DMA device is removed in which the | |
52 | * I/O ports (81h-83h, 87h, 89h-8Bh, 8Fh) related to it are removed | |
53 | * as well. All removed ports must return 0xff for a inb() request. | |
54 | * | |
55 | * Note: DMA_PAGE_2 (port 0x81) should not be checked for detecting | |
56 | * the presence of DMA device since it may be used by BIOS to decode | |
57 | * LPC traffic for POST codes. Original LPC only decodes one byte of | |
58 | * port 0x80 but some BIOS may choose to enhance PCH LPC port 0x8x | |
59 | * decoding. | |
60 | */ | |
61 | if (dma_inb(DMA_PAGE_0) == 0xFF) | |
62 | return -ENODEV; | |
63 | ||
64 | /* | |
65 | * It is not required to load this driver as newer SoC may not | |
66 | * support 8237 DMA or bus mastering from LPC. Platform firmware | |
67 | * must announce the support for such legacy devices via | |
68 | * ACPI_FADT_LEGACY_DEVICES field in FADT table. | |
69 | */ | |
70 | if (x86_pnpbios_disabled() && dmi_get_bios_year() >= 2017) | |
71 | return -ENODEV; | |
72 | ||
f3c6ea1b RW |
73 | register_syscore_ops(&i8237_syscore_ops); |
74 | return 0; | |
795312e7 | 75 | } |
f3c6ea1b | 76 | device_initcall(i8237A_init_ops); |