[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / i8259.c

#include <linux/linkage.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/syscore_ops.h>
#include <linux/bitops.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/delay.h>

#include <linux/atomic.h>
#include <asm/timer.h>
#include <asm/hw_irq.h>
#include <asm/pgtable.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/i8259.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 */
static void init_8259A(int auto_eoi);

static int i8259A_auto_eoi;
DEFINE_RAW_SPINLOCK(i8259A_lock);

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
unsigned int cached_irq_mask = 0xffff;

/*
 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 * boards the timer interrupt is not really connected to any IO-APIC pin,
 * it's fed to the master 8259A's IR0 line only.
 *
 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 * this 'mixed mode' IRQ handling costs nothing because it's only used
 * at IRQ setup time.
 */
unsigned long io_apic_irqs;

static void mask_8259A_irq(unsigned int irq)
{
	unsigned int mask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void disable_8259A_irq(struct irq_data *data)
{
	mask_8259A_irq(data->irq);
}

static void unmask_8259A_irq(unsigned int irq)
{
	unsigned int mask = ~(1 << irq);
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void enable_8259A_irq(struct irq_data *data)
{
	unmask_8259A_irq(data->irq);
}

static int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask = 1<<irq;
	unsigned long flags;
	int ret;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

static void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	io_apic_irqs &= ~(1<<irq);
	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1<<irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(struct irq_data *data)
{
	unsigned int irq = data->irq;
	unsigned int irqmask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		/* 'Specific EOI' to slave */
		outb(0x60+(irq&7), PIC_SLAVE_CMD);
		 /* 'Specific EOI' to master-IRQ2 */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG
			       "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

struct irq_chip i8259A_chip = {
	.name		= "XT-PIC",
	.irq_mask	= disable_8259A_irq,
	.irq_disable	= disable_8259A_irq,
	.irq_unmask	= enable_8259A_irq,
	.irq_mask_ack	= mask_and_ack_8259A,
};

static char irq_trigger[2];
/**
 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 */
static void restore_ELCR(char *trigger)
{
	outb(trigger[0], 0x4d0);
	outb(trigger[1], 0x4d1);
}

static void save_ELCR(char *trigger)
{
	/* IRQ 0,1,2,8,13 are marked as reserved */
	trigger[0] = inb(0x4d0) & 0xF8;
	trigger[1] = inb(0x4d1) & 0xDE;
}

static void i8259A_resume(void)
{
	init_8259A(i8259A_auto_eoi);
	restore_ELCR(irq_trigger);
}

static int i8259A_suspend(void)
{
	save_ELCR(irq_trigger);
	return 0;
}

static void i8259A_shutdown(void)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */
}

static struct syscore_ops i8259_syscore_ops = {
	.suspend = i8259A_suspend,
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static void mask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void unmask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static int probe_8259A(void)
{
	unsigned long flags;
	unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
	unsigned char new_val;
	/*
	 * Check to see if we have a PIC.
	 * Mask all except the cascade and read
	 * back the value we just wrote. If we don't
	 * have a PIC, we will read 0xff as opposed to the
	 * value we wrote.
	 */
	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */
	outb(probe_val, PIC_MASTER_IMR);
	new_val = inb(PIC_MASTER_IMR);
	if (new_val != probe_val) {
		printk(KERN_INFO "Using NULL legacy PIC\n");
		legacy_pic = &null_legacy_pic;
	}

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return nr_legacy_irqs();
}

static void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */

	/*
	 * outb_pic - this has to work on a wide range of PC hardware.
	 */
	outb_pic(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	/* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */
	outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR);

	/* 8259A-1 (the master) has a slave on IR2 */
	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);

	if (auto_eoi)	/* master does Auto EOI */
		outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_pic(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	/* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */
	outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR);
	/* 8259A-2 is a slave on master's IR2 */
	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	/* (slave's support for AEOI in flat mode is to be investigated) */
	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);

	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.irq_mask_ack = disable_8259A_irq;
	else
		i8259A_chip.irq_mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * make i8259 a driver so that we can select pic functions at run time. the goal
 * is to make x86 binary compatible among pc compatible and non-pc compatible
 * platforms, such as x86 MID.
 */

static void legacy_pic_noop(void) { };
static void legacy_pic_uint_noop(unsigned int unused) { };
static void legacy_pic_int_noop(int unused) { };
static int legacy_pic_irq_pending_noop(unsigned int irq)
{
	return 0;
}
static int legacy_pic_probe(void)
{
	return 0;
}

struct legacy_pic null_legacy_pic = {
	.nr_legacy_irqs = 0,
	.chip = &dummy_irq_chip,
	.mask = legacy_pic_uint_noop,
	.unmask = legacy_pic_uint_noop,
	.mask_all = legacy_pic_noop,
	.restore_mask = legacy_pic_noop,
	.init = legacy_pic_int_noop,
	.probe = legacy_pic_probe,
	.irq_pending = legacy_pic_irq_pending_noop,
	.make_irq = legacy_pic_uint_noop,
};

struct legacy_pic default_legacy_pic = {
	.nr_legacy_irqs = NR_IRQS_LEGACY,
	.chip  = &i8259A_chip,
	.mask = mask_8259A_irq,
	.unmask = unmask_8259A_irq,
	.mask_all = mask_8259A,
	.restore_mask = unmask_8259A,
	.init = init_8259A,
	.probe = probe_8259A,
	.irq_pending = i8259A_irq_pending,
	.make_irq = make_8259A_irq,
};

struct legacy_pic *legacy_pic = &default_legacy_pic;
EXPORT_SYMBOL(legacy_pic);

static int __init i8259A_init_ops(void)
{
	if (legacy_pic == &default_legacy_pic)
		register_syscore_ops(&i8259_syscore_ops);

	return 0;
}

device_initcall(i8259A_init_ops);
Commit	Line	Data
21fd5132	1	#include <linux/linkage.h>
21fd5132 PM	2	#include <linux/errno.h>
	3	#include <linux/signal.h>
	4	#include <linux/sched.h>
	5	#include <linux/ioport.h>
	6	#include <linux/interrupt.h>
21fd5132	7	#include <linux/timex.h>
21fd5132 PM	8	#include <linux/random.h>
	9	#include <linux/init.h>
	10	#include <linux/kernel_stat.h>
f3c6ea1b	11	#include <linux/syscore_ops.h>
21fd5132	12	#include <linux/bitops.h>
7bafaf30 JSR	13	#include <linux/acpi.h>
	14	#include <linux/io.h>
	15	#include <linux/delay.h>
21fd5132	16
60063497	17	#include <linux/atomic.h>
21fd5132	18	#include <asm/timer.h>
21fd5132	19	#include <asm/hw_irq.h>
21fd5132	20	#include <asm/pgtable.h>
21fd5132 PM	21	#include <asm/desc.h>
21fd5132 PM	22	#include <asm/apic.h>
21fd5132 PM	23	#include <asm/i8259.h>
	24
	25	/*
	26	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	27	* present in the majority of PC/AT boxes.
	28	* plus some generic x86 specific things if generic specifics makes
	29	* any sense at all.
	30	*/
4305df94	31	static void init_8259A(int auto_eoi);
21fd5132 PM	32
21fd5132 PM	33	static int i8259A_auto_eoi;
5619c280	34	DEFINE_RAW_SPINLOCK(i8259A_lock);
21fd5132 PM	35
	36	/*
	37	* 8259A PIC functions to handle ISA devices:
	38	*/
	39
	40	/*
	41	* This contains the irq mask for both 8259A irq controllers,
	42	*/
	43	unsigned int cached_irq_mask = 0xffff;
	44
	45	/*
	46	* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
	47	* boards the timer interrupt is not really connected to any IO-APIC pin,
	48	* it's fed to the master 8259A's IR0 line only.
	49	*
	50	* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
	51	* this 'mixed mode' IRQ handling costs nothing because it's only used
	52	* at IRQ setup time.
	53	*/
	54	unsigned long io_apic_irqs;
	55
4305df94	56	static void mask_8259A_irq(unsigned int irq)
21fd5132 PM	57	{
	58	unsigned int mask = 1 << irq;
	59	unsigned long flags;
	60
5619c280	61	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	62	cached_irq_mask \|= mask;
	63	if (irq & 8)
	64	outb(cached_slave_mask, PIC_SLAVE_IMR);
	65	else
	66	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	67	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	68	}
21fd5132 PM	69
4305df94 TG	70	static void disable_8259A_irq(struct irq_data *data)
	71	{
	72	mask_8259A_irq(data->irq);
	73	}
	74
	75	static void unmask_8259A_irq(unsigned int irq)
21fd5132 PM	76	{
	77	unsigned int mask = ~(1 << irq);
	78	unsigned long flags;
	79
5619c280	80	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	81	cached_irq_mask &= mask;
	82	if (irq & 8)
	83	outb(cached_slave_mask, PIC_SLAVE_IMR);
	84	else
	85	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	86	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	87	}
21fd5132 PM	88
4305df94 TG	89	static void enable_8259A_irq(struct irq_data *data)
	90	{
	91	unmask_8259A_irq(data->irq);
	92	}
	93
b81bb373	94	static int i8259A_irq_pending(unsigned int irq)
21fd5132 PM	95	{
	96	unsigned int mask = 1<<irq;
	97	unsigned long flags;
	98	int ret;
	99
5619c280	100	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	101	if (irq < 8)
	102	ret = inb(PIC_MASTER_CMD) & mask;
	103	else
	104	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
5619c280	105	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	106
	107	return ret;
	108	}
	109
b81bb373	110	static void make_8259A_irq(unsigned int irq)
21fd5132 PM	111	{
	112	disable_irq_nosync(irq);
	113	io_apic_irqs &= ~(1<<irq);
60e684f0	114	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
21fd5132 PM	115	enable_irq(irq);
	116	}
	117
	118	/*
	119	* This function assumes to be called rarely. Switching between
	120	* 8259A registers is slow.
	121	* This has to be protected by the irq controller spinlock
	122	* before being called.
	123	*/
	124	static inline int i8259A_irq_real(unsigned int irq)
	125	{
	126	int value;
	127	int irqmask = 1<<irq;
	128
	129	if (irq < 8) {
680afbf9	130	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
21fd5132	131	value = inb(PIC_MASTER_CMD) & irqmask;
680afbf9	132	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
21fd5132 PM	133	return value;
21fd5132 PM	134	}
680afbf9	135	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
21fd5132	136	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
680afbf9	137	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
21fd5132 PM	138	return value;
	139	}
	140
	141	/*
	142	* Careful! The 8259A is a fragile beast, it pretty
	143	* much _has_ to be done exactly like this (mask it
	144	* first, _then_ send the EOI, and the order of EOI
	145	* to the two 8259s is important!
	146	*/
4305df94	147	static void mask_and_ack_8259A(struct irq_data *data)
21fd5132	148	{
4305df94	149	unsigned int irq = data->irq;
21fd5132 PM	150	unsigned int irqmask = 1 << irq;
	151	unsigned long flags;
	152
5619c280	153	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	154	/*
	155	* Lightweight spurious IRQ detection. We do not want
	156	* to overdo spurious IRQ handling - it's usually a sign
	157	* of hardware problems, so we only do the checks we can
	158	* do without slowing down good hardware unnecessarily.
	159	*
	160	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	161	* usually resulting from the 8259A-1\|2 PICs) occur
	162	* even if the IRQ is masked in the 8259A. Thus we
	163	* can check spurious 8259A IRQs without doing the
	164	* quite slow i8259A_irq_real() call for every IRQ.
	165	* This does not cover 100% of spurious interrupts,
	166	* but should be enough to warn the user that there
	167	* is something bad going on ...
	168	*/
	169	if (cached_irq_mask & irqmask)
	170	goto spurious_8259A_irq;
	171	cached_irq_mask \|= irqmask;
	172
	173	handle_real_irq:
	174	if (irq & 8) {
	175	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
	176	outb(cached_slave_mask, PIC_SLAVE_IMR);
21fd5132	177	/* 'Specific EOI' to slave */
3e8631d2	178	outb(0x60+(irq&7), PIC_SLAVE_CMD);
21fd5132	179	/* 'Specific EOI' to master-IRQ2 */
3e8631d2	180	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
21fd5132 PM	181	} else {
	182	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
	183	outb(cached_master_mask, PIC_MASTER_IMR);
3e8631d2	184	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
21fd5132	185	}
5619c280	186	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	187	return;
	188
	189	spurious_8259A_irq:
	190	/*
	191	* this is the slow path - should happen rarely.
	192	*/
	193	if (i8259A_irq_real(irq))
	194	/*
	195	* oops, the IRQ _is_ in service according to the
	196	* 8259A - not spurious, go handle it.
	197	*/
	198	goto handle_real_irq;
	199
	200	{
	201	static int spurious_irq_mask;
	202	/*
	203	* At this point we can be sure the IRQ is spurious,
	204	* lets ACK and report it. [once per IRQ]
	205	*/
	206	if (!(spurious_irq_mask & irqmask)) {
21fd5132 PM	207	printk(KERN_DEBUG
21fd5132 PM	208	"spurious 8259A interrupt: IRQ%d.\n", irq);
21fd5132 PM	209	spurious_irq_mask \|= irqmask;
	210	}
	211	atomic_inc(&irq_err_count);
	212	/*
	213	* Theoretically we do not have to handle this IRQ,
	214	* but in Linux this does not cause problems and is
	215	* simpler for us.
	216	*/
	217	goto handle_real_irq;
	218	}
	219	}
	220
4305df94 TG	221	struct irq_chip i8259A_chip = {
	222	.name = "XT-PIC",
	223	.irq_mask = disable_8259A_irq,
	224	.irq_disable = disable_8259A_irq,
	225	.irq_unmask = enable_8259A_irq,
	226	.irq_mask_ack = mask_and_ack_8259A,
	227	};
	228
21fd5132 PM	229	static char irq_trigger[2];
	230	/**
	231	* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
	232	*/
	233	static void restore_ELCR(char *trigger)
	234	{
	235	outb(trigger[0], 0x4d0);
	236	outb(trigger[1], 0x4d1);
	237	}
	238
	239	static void save_ELCR(char *trigger)
	240	{
	241	/* IRQ 0,1,2,8,13 are marked as reserved */
	242	trigger[0] = inb(0x4d0) & 0xF8;
	243	trigger[1] = inb(0x4d1) & 0xDE;
	244	}
	245
f3c6ea1b	246	static void i8259A_resume(void)
21fd5132 PM	247	{
	248	init_8259A(i8259A_auto_eoi);
	249	restore_ELCR(irq_trigger);
21fd5132 PM	250	}
21fd5132 PM	251
f3c6ea1b	252	static int i8259A_suspend(void)
21fd5132 PM	253	{
	254	save_ELCR(irq_trigger);
	255	return 0;
	256	}
	257
f3c6ea1b	258	static void i8259A_shutdown(void)
21fd5132 PM	259	{
	260	/* Put the i8259A into a quiescent state that
	261	* the kernel initialization code can get it
	262	* out of.
	263	*/
	264	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
d3a8009b	265	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
21fd5132 PM	266	}
21fd5132 PM	267
f3c6ea1b	268	static struct syscore_ops i8259_syscore_ops = {
21fd5132 PM	269	.suspend = i8259A_suspend,
	270	.resume = i8259A_resume,
	271	.shutdown = i8259A_shutdown,
	272	};
	273
b81bb373	274	static void mask_8259A(void)
d94d93ca SS	275	{
	276	unsigned long flags;
	277
5619c280	278	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	279
	280	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	281	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	282
5619c280	283	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	284	}
d94d93ca SS	285
b81bb373	286	static void unmask_8259A(void)
d94d93ca SS	287	{
	288	unsigned long flags;
	289
5619c280	290	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	291
	292	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	293	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	294
5619c280	295	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	296	}
d94d93ca SS	297
8c058b0b	298	static int probe_8259A(void)
21fd5132 PM	299	{
21fd5132 PM	300	unsigned long flags;
e179f691 S	301	unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
e179f691 S	302	unsigned char new_val;
e179f691 S	303	/*
	304	* Check to see if we have a PIC.
	305	* Mask all except the cascade and read
	306	* back the value we just wrote. If we don't
	307	* have a PIC, we will read 0xff as opposed to the
	308	* value we wrote.
	309	*/
8c058b0b VK	310	raw_spin_lock_irqsave(&i8259A_lock, flags);
8c058b0b VK	311
21fd5132	312	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
e179f691 S	313	outb(probe_val, PIC_MASTER_IMR);
	314	new_val = inb(PIC_MASTER_IMR);
	315	if (new_val != probe_val) {
	316	printk(KERN_INFO "Using NULL legacy PIC\n");
	317	legacy_pic = &null_legacy_pic;
e179f691 S	318	}
e179f691 S	319
8c058b0b VK	320	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	321	return nr_legacy_irqs();
	322	}
	323
	324	static void init_8259A(int auto_eoi)
	325	{
	326	unsigned long flags;
	327
	328	i8259A_auto_eoi = auto_eoi;
	329
	330	raw_spin_lock_irqsave(&i8259A_lock, flags);
	331
e179f691	332	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
21fd5132 PM	333
	334	/*
	335	* outb_pic - this has to work on a wide range of PC hardware.
	336	*/
	337	outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
c46e62f7	338
8b455e65 BG	339	/* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */
8b455e65 BG	340	outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR);
c46e62f7	341
21fd5132	342	/* 8259A-1 (the master) has a slave on IR2 */
c46e62f7 PM	343	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
c46e62f7 PM	344
21fd5132 PM	345	if (auto_eoi) /* master does Auto EOI */
	346	outb_pic(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	347	else /* master expects normal EOI */
	348	outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	349
	350	outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
c46e62f7	351
8b455e65 BG	352	/* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */
8b455e65 BG	353	outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR);
21fd5132 PM	354	/* 8259A-2 is a slave on master's IR2 */
	355	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	356	/* (slave's support for AEOI in flat mode is to be investigated) */
	357	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
	358
21fd5132 PM	359	if (auto_eoi)
	360	/*
	361	* In AEOI mode we just have to mask the interrupt
	362	* when acking.
	363	*/
4305df94	364	i8259A_chip.irq_mask_ack = disable_8259A_irq;
21fd5132	365	else
4305df94	366	i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
21fd5132 PM	367
	368	udelay(100); /* wait for 8259A to initialize */
	369
	370	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	371	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	372
5619c280	373	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132	374	}
b81bb373	375
ef354866 JP	376	/*
	377	* make i8259 a driver so that we can select pic functions at run time. the goal
	378	* is to make x86 binary compatible among pc compatible and non-pc compatible
	379	* platforms, such as x86 MID.
	380	*/
	381
28a3c93d JP	382	static void legacy_pic_noop(void) { };
	383	static void legacy_pic_uint_noop(unsigned int unused) { };
	384	static void legacy_pic_int_noop(int unused) { };
ef354866 JP	385	static int legacy_pic_irq_pending_noop(unsigned int irq)
	386	{
	387	return 0;
	388	}
8c058b0b VK	389	static int legacy_pic_probe(void)
	390	{
	391	return 0;
	392	}
ef354866 JP	393
	394	struct legacy_pic null_legacy_pic = {
	395	.nr_legacy_irqs = 0,
4305df94 TG	396	.chip = &dummy_irq_chip,
	397	.mask = legacy_pic_uint_noop,
	398	.unmask = legacy_pic_uint_noop,
ef354866 JP	399	.mask_all = legacy_pic_noop,
	400	.restore_mask = legacy_pic_noop,
	401	.init = legacy_pic_int_noop,
8c058b0b	402	.probe = legacy_pic_probe,
ef354866 JP	403	.irq_pending = legacy_pic_irq_pending_noop,
	404	.make_irq = legacy_pic_uint_noop,
	405	};
	406
	407	struct legacy_pic default_legacy_pic = {
	408	.nr_legacy_irqs = NR_IRQS_LEGACY,
	409	.chip = &i8259A_chip,
4305df94 TG	410	.mask = mask_8259A_irq,
	411	.unmask = unmask_8259A_irq,
	412	.mask_all = mask_8259A,
ef354866 JP	413	.restore_mask = unmask_8259A,
ef354866 JP	414	.init = init_8259A,
8c058b0b	415	.probe = probe_8259A,
ef354866 JP	416	.irq_pending = i8259A_irq_pending,
	417	.make_irq = make_8259A_irq,
	418	};
	419
	420	struct legacy_pic *legacy_pic = &default_legacy_pic;
7ee06cb2	421	EXPORT_SYMBOL(legacy_pic);
087b255a	422
f3c6ea1b	423	static int __init i8259A_init_ops(void)
087b255a	424	{
f3c6ea1b RW	425	if (legacy_pic == &default_legacy_pic)
f3c6ea1b RW	426	register_syscore_ops(&i8259_syscore_ops);
087b255a	427
f3c6ea1b	428	return 0;
087b255a AL	429	}
087b255a AL	430
f3c6ea1b	431	device_initcall(i8259A_init_ops);