[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / i8259.c

// SPDX-License-Identifier: GPL-2.0
#include <linux/linkage.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/timex.h>
#include <linux/random.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/syscore_ops.h>
#include <linux/bitops.h>
#include <linux/acpi.h>
#include <linux/io.h>
#include <linux/delay.h>

#include <linux/atomic.h>
#include <asm/timer.h>
#include <asm/hw_irq.h>
#include <asm/pgtable.h>
#include <asm/desc.h>
#include <asm/apic.h>
#include <asm/i8259.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 */
static void init_8259A(int auto_eoi);

static int i8259A_auto_eoi;
DEFINE_RAW_SPINLOCK(i8259A_lock);

/*
 * 8259A PIC functions to handle ISA devices:
 */

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
unsigned int cached_irq_mask = 0xffff;

/*
 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
 * boards the timer interrupt is not really connected to any IO-APIC pin,
 * it's fed to the master 8259A's IR0 line only.
 *
 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
 * this 'mixed mode' IRQ handling costs nothing because it's only used
 * at IRQ setup time.
 */
unsigned long io_apic_irqs;

static void mask_8259A_irq(unsigned int irq)
{
	unsigned int mask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void disable_8259A_irq(struct irq_data *data)
{
	mask_8259A_irq(data->irq);
}

static void unmask_8259A_irq(unsigned int irq)
{
	unsigned int mask = ~(1 << irq);
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void enable_8259A_irq(struct irq_data *data)
{
	unmask_8259A_irq(data->irq);
}

static int i8259A_irq_pending(unsigned int irq)
{
	unsigned int mask = 1<<irq;
	unsigned long flags;
	int ret;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	if (irq < 8)
		ret = inb(PIC_MASTER_CMD) & mask;
	else
		ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);

	return ret;
}

static void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	io_apic_irqs &= ~(1<<irq);
	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
	enable_irq(irq);
	lapic_assign_legacy_vector(irq, true);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1<<irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(struct irq_data *data)
{
	unsigned int irq = data->irq;
	unsigned int irqmask = 1 << irq;
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		/* 'Specific EOI' to slave */
		outb(0x60+(irq&7), PIC_SLAVE_CMD);
		 /* 'Specific EOI' to master-IRQ2 */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD);	/* 'Specific EOI to master */
	}
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG
			       "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

struct irq_chip i8259A_chip = {
	.name		= "XT-PIC",
	.irq_mask	= disable_8259A_irq,
	.irq_disable	= disable_8259A_irq,
	.irq_unmask	= enable_8259A_irq,
	.irq_mask_ack	= mask_and_ack_8259A,
};

static char irq_trigger[2];
/**
 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
 */
static void restore_ELCR(char *trigger)
{
	outb(trigger[0], 0x4d0);
	outb(trigger[1], 0x4d1);
}

static void save_ELCR(char *trigger)
{
	/* IRQ 0,1,2,8,13 are marked as reserved */
	trigger[0] = inb(0x4d0) & 0xF8;
	trigger[1] = inb(0x4d1) & 0xDE;
}

static void i8259A_resume(void)
{
	init_8259A(i8259A_auto_eoi);
	restore_ELCR(irq_trigger);
}

static int i8259A_suspend(void)
{
	save_ELCR(irq_trigger);
	return 0;
}

static void i8259A_shutdown(void)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */
}

static struct syscore_ops i8259_syscore_ops = {
	.suspend = i8259A_suspend,
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static void mask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void unmask_8259A(void)
{
	unsigned long flags;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static int probe_8259A(void)
{
	unsigned long flags;
	unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
	unsigned char new_val;
	/*
	 * Check to see if we have a PIC.
	 * Mask all except the cascade and read
	 * back the value we just wrote. If we don't
	 * have a PIC, we will read 0xff as opposed to the
	 * value we wrote.
	 */
	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */
	outb(probe_val, PIC_MASTER_IMR);
	new_val = inb(PIC_MASTER_IMR);
	if (new_val != probe_val) {
		printk(KERN_INFO "Using NULL legacy PIC\n");
		legacy_pic = &null_legacy_pic;
	}

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return nr_legacy_irqs();
}

static void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */

	/*
	 * outb_pic - this has to work on a wide range of PC hardware.
	 */
	outb_pic(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */

	/* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */
	outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR);

	/* 8259A-1 (the master) has a slave on IR2 */
	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);

	if (auto_eoi)	/* master does Auto EOI */
		outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_pic(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */

	/* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */
	outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR);
	/* 8259A-2 is a slave on master's IR2 */
	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	/* (slave's support for AEOI in flat mode is to be investigated) */
	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);

	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.irq_mask_ack = disable_8259A_irq;
	else
		i8259A_chip.irq_mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * make i8259 a driver so that we can select pic functions at run time. the goal
 * is to make x86 binary compatible among pc compatible and non-pc compatible
 * platforms, such as x86 MID.
 */

static void legacy_pic_noop(void) { };
static void legacy_pic_uint_noop(unsigned int unused) { };
static void legacy_pic_int_noop(int unused) { };
static int legacy_pic_irq_pending_noop(unsigned int irq)
{
	return 0;
}
static int legacy_pic_probe(void)
{
	return 0;
}

struct legacy_pic null_legacy_pic = {
	.nr_legacy_irqs = 0,
	.chip = &dummy_irq_chip,
	.mask = legacy_pic_uint_noop,
	.unmask = legacy_pic_uint_noop,
	.mask_all = legacy_pic_noop,
	.restore_mask = legacy_pic_noop,
	.init = legacy_pic_int_noop,
	.probe = legacy_pic_probe,
	.irq_pending = legacy_pic_irq_pending_noop,
	.make_irq = legacy_pic_uint_noop,
};

struct legacy_pic default_legacy_pic = {
	.nr_legacy_irqs = NR_IRQS_LEGACY,
	.chip  = &i8259A_chip,
	.mask = mask_8259A_irq,
	.unmask = unmask_8259A_irq,
	.mask_all = mask_8259A,
	.restore_mask = unmask_8259A,
	.init = init_8259A,
	.probe = probe_8259A,
	.irq_pending = i8259A_irq_pending,
	.make_irq = make_8259A_irq,
};

struct legacy_pic *legacy_pic = &default_legacy_pic;
EXPORT_SYMBOL(legacy_pic);

static int __init i8259A_init_ops(void)
{
	if (legacy_pic == &default_legacy_pic)
		register_syscore_ops(&i8259_syscore_ops);

	return 0;
}

device_initcall(i8259A_init_ops);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
21fd5132	2	#include <linux/linkage.h>
21fd5132 PM	3	#include <linux/errno.h>
	4	#include <linux/signal.h>
	5	#include <linux/sched.h>
	6	#include <linux/ioport.h>
	7	#include <linux/interrupt.h>
f901f138	8	#include <linux/irq.h>
21fd5132	9	#include <linux/timex.h>
21fd5132 PM	10	#include <linux/random.h>
	11	#include <linux/init.h>
	12	#include <linux/kernel_stat.h>
f3c6ea1b	13	#include <linux/syscore_ops.h>
21fd5132	14	#include <linux/bitops.h>
7bafaf30 JSR	15	#include <linux/acpi.h>
	16	#include <linux/io.h>
	17	#include <linux/delay.h>
21fd5132	18
60063497	19	#include <linux/atomic.h>
21fd5132	20	#include <asm/timer.h>
21fd5132	21	#include <asm/hw_irq.h>
21fd5132	22	#include <asm/pgtable.h>
21fd5132 PM	23	#include <asm/desc.h>
21fd5132 PM	24	#include <asm/apic.h>
21fd5132 PM	25	#include <asm/i8259.h>
	26
	27	/*
	28	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	29	* present in the majority of PC/AT boxes.
	30	* plus some generic x86 specific things if generic specifics makes
	31	* any sense at all.
	32	*/
4305df94	33	static void init_8259A(int auto_eoi);
21fd5132 PM	34
21fd5132 PM	35	static int i8259A_auto_eoi;
5619c280	36	DEFINE_RAW_SPINLOCK(i8259A_lock);
21fd5132 PM	37
	38	/*
	39	* 8259A PIC functions to handle ISA devices:
	40	*/
	41
	42	/*
	43	* This contains the irq mask for both 8259A irq controllers,
	44	*/
	45	unsigned int cached_irq_mask = 0xffff;
	46
	47	/*
	48	* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
	49	* boards the timer interrupt is not really connected to any IO-APIC pin,
	50	* it's fed to the master 8259A's IR0 line only.
	51	*
	52	* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
	53	* this 'mixed mode' IRQ handling costs nothing because it's only used
	54	* at IRQ setup time.
	55	*/
	56	unsigned long io_apic_irqs;
	57
4305df94	58	static void mask_8259A_irq(unsigned int irq)
21fd5132 PM	59	{
	60	unsigned int mask = 1 << irq;
	61	unsigned long flags;
	62
5619c280	63	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	64	cached_irq_mask \|= mask;
	65	if (irq & 8)
	66	outb(cached_slave_mask, PIC_SLAVE_IMR);
	67	else
	68	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	69	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	70	}
21fd5132 PM	71
4305df94 TG	72	static void disable_8259A_irq(struct irq_data *data)
	73	{
	74	mask_8259A_irq(data->irq);
	75	}
	76
	77	static void unmask_8259A_irq(unsigned int irq)
21fd5132 PM	78	{
	79	unsigned int mask = ~(1 << irq);
	80	unsigned long flags;
	81
5619c280	82	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	83	cached_irq_mask &= mask;
	84	if (irq & 8)
	85	outb(cached_slave_mask, PIC_SLAVE_IMR);
	86	else
	87	outb(cached_master_mask, PIC_MASTER_IMR);
5619c280	88	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	89	}
21fd5132 PM	90
4305df94 TG	91	static void enable_8259A_irq(struct irq_data *data)
	92	{
	93	unmask_8259A_irq(data->irq);
	94	}
	95
b81bb373	96	static int i8259A_irq_pending(unsigned int irq)
21fd5132 PM	97	{
	98	unsigned int mask = 1<<irq;
	99	unsigned long flags;
	100	int ret;
	101
5619c280	102	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	103	if (irq < 8)
	104	ret = inb(PIC_MASTER_CMD) & mask;
	105	else
	106	ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
5619c280	107	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	108
	109	return ret;
	110	}
	111
b81bb373	112	static void make_8259A_irq(unsigned int irq)
21fd5132 PM	113	{
	114	disable_irq_nosync(irq);
	115	io_apic_irqs &= ~(1<<irq);
60e684f0	116	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
21fd5132	117	enable_irq(irq);
0fa115da	118	lapic_assign_legacy_vector(irq, true);
21fd5132 PM	119	}
	120
	121	/*
	122	* This function assumes to be called rarely. Switching between
	123	* 8259A registers is slow.
	124	* This has to be protected by the irq controller spinlock
	125	* before being called.
	126	*/
	127	static inline int i8259A_irq_real(unsigned int irq)
	128	{
	129	int value;
	130	int irqmask = 1<<irq;
	131
	132	if (irq < 8) {
680afbf9	133	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
21fd5132	134	value = inb(PIC_MASTER_CMD) & irqmask;
680afbf9	135	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
21fd5132 PM	136	return value;
21fd5132 PM	137	}
680afbf9	138	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
21fd5132	139	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
680afbf9	140	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
21fd5132 PM	141	return value;
	142	}
	143
	144	/*
	145	* Careful! The 8259A is a fragile beast, it pretty
	146	* much _has_ to be done exactly like this (mask it
	147	* first, _then_ send the EOI, and the order of EOI
	148	* to the two 8259s is important!
	149	*/
4305df94	150	static void mask_and_ack_8259A(struct irq_data *data)
21fd5132	151	{
4305df94	152	unsigned int irq = data->irq;
21fd5132 PM	153	unsigned int irqmask = 1 << irq;
	154	unsigned long flags;
	155
5619c280	156	raw_spin_lock_irqsave(&i8259A_lock, flags);
21fd5132 PM	157	/*
	158	* Lightweight spurious IRQ detection. We do not want
	159	* to overdo spurious IRQ handling - it's usually a sign
	160	* of hardware problems, so we only do the checks we can
	161	* do without slowing down good hardware unnecessarily.
	162	*
	163	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	164	* usually resulting from the 8259A-1\|2 PICs) occur
	165	* even if the IRQ is masked in the 8259A. Thus we
	166	* can check spurious 8259A IRQs without doing the
	167	* quite slow i8259A_irq_real() call for every IRQ.
	168	* This does not cover 100% of spurious interrupts,
	169	* but should be enough to warn the user that there
	170	* is something bad going on ...
	171	*/
	172	if (cached_irq_mask & irqmask)
	173	goto spurious_8259A_irq;
	174	cached_irq_mask \|= irqmask;
	175
	176	handle_real_irq:
	177	if (irq & 8) {
	178	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
	179	outb(cached_slave_mask, PIC_SLAVE_IMR);
21fd5132	180	/* 'Specific EOI' to slave */
3e8631d2	181	outb(0x60+(irq&7), PIC_SLAVE_CMD);
21fd5132	182	/* 'Specific EOI' to master-IRQ2 */
3e8631d2	183	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
21fd5132 PM	184	} else {
	185	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
	186	outb(cached_master_mask, PIC_MASTER_IMR);
3e8631d2	187	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
21fd5132	188	}
5619c280	189	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132 PM	190	return;
	191
	192	spurious_8259A_irq:
	193	/*
	194	* this is the slow path - should happen rarely.
	195	*/
	196	if (i8259A_irq_real(irq))
	197	/*
	198	* oops, the IRQ _is_ in service according to the
	199	* 8259A - not spurious, go handle it.
	200	*/
	201	goto handle_real_irq;
	202
	203	{
	204	static int spurious_irq_mask;
	205	/*
	206	* At this point we can be sure the IRQ is spurious,
	207	* lets ACK and report it. [once per IRQ]
	208	*/
	209	if (!(spurious_irq_mask & irqmask)) {
21fd5132 PM	210	printk(KERN_DEBUG
21fd5132 PM	211	"spurious 8259A interrupt: IRQ%d.\n", irq);
21fd5132 PM	212	spurious_irq_mask \|= irqmask;
	213	}
	214	atomic_inc(&irq_err_count);
	215	/*
	216	* Theoretically we do not have to handle this IRQ,
	217	* but in Linux this does not cause problems and is
	218	* simpler for us.
	219	*/
	220	goto handle_real_irq;
	221	}
	222	}
	223
4305df94 TG	224	struct irq_chip i8259A_chip = {
	225	.name = "XT-PIC",
	226	.irq_mask = disable_8259A_irq,
	227	.irq_disable = disable_8259A_irq,
	228	.irq_unmask = enable_8259A_irq,
	229	.irq_mask_ack = mask_and_ack_8259A,
	230	};
	231
21fd5132 PM	232	static char irq_trigger[2];
	233	/**
	234	* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
	235	*/
	236	static void restore_ELCR(char *trigger)
	237	{
	238	outb(trigger[0], 0x4d0);
	239	outb(trigger[1], 0x4d1);
	240	}
	241
	242	static void save_ELCR(char *trigger)
	243	{
	244	/* IRQ 0,1,2,8,13 are marked as reserved */
	245	trigger[0] = inb(0x4d0) & 0xF8;
	246	trigger[1] = inb(0x4d1) & 0xDE;
	247	}
	248
f3c6ea1b	249	static void i8259A_resume(void)
21fd5132 PM	250	{
	251	init_8259A(i8259A_auto_eoi);
	252	restore_ELCR(irq_trigger);
21fd5132 PM	253	}
21fd5132 PM	254
f3c6ea1b	255	static int i8259A_suspend(void)
21fd5132 PM	256	{
	257	save_ELCR(irq_trigger);
	258	return 0;
	259	}
	260
f3c6ea1b	261	static void i8259A_shutdown(void)
21fd5132 PM	262	{
	263	/* Put the i8259A into a quiescent state that
	264	* the kernel initialization code can get it
	265	* out of.
	266	*/
	267	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
d3a8009b	268	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
21fd5132 PM	269	}
21fd5132 PM	270
f3c6ea1b	271	static struct syscore_ops i8259_syscore_ops = {
21fd5132 PM	272	.suspend = i8259A_suspend,
	273	.resume = i8259A_resume,
	274	.shutdown = i8259A_shutdown,
	275	};
	276
b81bb373	277	static void mask_8259A(void)
d94d93ca SS	278	{
	279	unsigned long flags;
	280
5619c280	281	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	282
	283	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
	284	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
	285
5619c280	286	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	287	}
d94d93ca SS	288
b81bb373	289	static void unmask_8259A(void)
d94d93ca SS	290	{
	291	unsigned long flags;
	292
5619c280	293	raw_spin_lock_irqsave(&i8259A_lock, flags);
d94d93ca SS	294
	295	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	296	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	297
5619c280	298	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
d94d93ca SS	299	}
d94d93ca SS	300
8c058b0b	301	static int probe_8259A(void)
21fd5132 PM	302	{
21fd5132 PM	303	unsigned long flags;
e179f691 S	304	unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
e179f691 S	305	unsigned char new_val;
e179f691 S	306	/*
	307	* Check to see if we have a PIC.
	308	* Mask all except the cascade and read
	309	* back the value we just wrote. If we don't
	310	* have a PIC, we will read 0xff as opposed to the
	311	* value we wrote.
	312	*/
8c058b0b VK	313	raw_spin_lock_irqsave(&i8259A_lock, flags);
8c058b0b VK	314
21fd5132	315	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
e179f691 S	316	outb(probe_val, PIC_MASTER_IMR);
	317	new_val = inb(PIC_MASTER_IMR);
	318	if (new_val != probe_val) {
	319	printk(KERN_INFO "Using NULL legacy PIC\n");
	320	legacy_pic = &null_legacy_pic;
e179f691 S	321	}
e179f691 S	322
8c058b0b VK	323	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	324	return nr_legacy_irqs();
	325	}
	326
	327	static void init_8259A(int auto_eoi)
	328	{
	329	unsigned long flags;
	330
	331	i8259A_auto_eoi = auto_eoi;
	332
	333	raw_spin_lock_irqsave(&i8259A_lock, flags);
	334
e179f691	335	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
21fd5132 PM	336
	337	/*
	338	* outb_pic - this has to work on a wide range of PC hardware.
	339	*/
	340	outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
c46e62f7	341
8b455e65 BG	342	/* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */
8b455e65 BG	343	outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR);
c46e62f7	344
21fd5132	345	/* 8259A-1 (the master) has a slave on IR2 */
c46e62f7 PM	346	outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
c46e62f7 PM	347
21fd5132 PM	348	if (auto_eoi) /* master does Auto EOI */
	349	outb_pic(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	350	else /* master expects normal EOI */
	351	outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	352
	353	outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
c46e62f7	354
8b455e65 BG	355	/* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */
8b455e65 BG	356	outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR);
21fd5132 PM	357	/* 8259A-2 is a slave on master's IR2 */
	358	outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
	359	/* (slave's support for AEOI in flat mode is to be investigated) */
	360	outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
	361
21fd5132 PM	362	if (auto_eoi)
	363	/*
	364	* In AEOI mode we just have to mask the interrupt
	365	* when acking.
	366	*/
4305df94	367	i8259A_chip.irq_mask_ack = disable_8259A_irq;
21fd5132	368	else
4305df94	369	i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
21fd5132 PM	370
	371	udelay(100); /* wait for 8259A to initialize */
	372
	373	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	374	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
	375
5619c280	376	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
21fd5132	377	}
b81bb373	378
ef354866 JP	379	/*
	380	* make i8259 a driver so that we can select pic functions at run time. the goal
	381	* is to make x86 binary compatible among pc compatible and non-pc compatible
	382	* platforms, such as x86 MID.
	383	*/
	384
28a3c93d JP	385	static void legacy_pic_noop(void) { };
	386	static void legacy_pic_uint_noop(unsigned int unused) { };
	387	static void legacy_pic_int_noop(int unused) { };
ef354866 JP	388	static int legacy_pic_irq_pending_noop(unsigned int irq)
	389	{
	390	return 0;
	391	}
8c058b0b VK	392	static int legacy_pic_probe(void)
	393	{
	394	return 0;
	395	}
ef354866 JP	396
	397	struct legacy_pic null_legacy_pic = {
	398	.nr_legacy_irqs = 0,
4305df94 TG	399	.chip = &dummy_irq_chip,
	400	.mask = legacy_pic_uint_noop,
	401	.unmask = legacy_pic_uint_noop,
ef354866 JP	402	.mask_all = legacy_pic_noop,
	403	.restore_mask = legacy_pic_noop,
	404	.init = legacy_pic_int_noop,
8c058b0b	405	.probe = legacy_pic_probe,
ef354866 JP	406	.irq_pending = legacy_pic_irq_pending_noop,
	407	.make_irq = legacy_pic_uint_noop,
	408	};
	409
	410	struct legacy_pic default_legacy_pic = {
	411	.nr_legacy_irqs = NR_IRQS_LEGACY,
	412	.chip = &i8259A_chip,
4305df94 TG	413	.mask = mask_8259A_irq,
	414	.unmask = unmask_8259A_irq,
	415	.mask_all = mask_8259A,
ef354866 JP	416	.restore_mask = unmask_8259A,
ef354866 JP	417	.init = init_8259A,
8c058b0b	418	.probe = probe_8259A,
ef354866 JP	419	.irq_pending = i8259A_irq_pending,
	420	.make_irq = make_8259A_irq,
	421	};
	422
	423	struct legacy_pic *legacy_pic = &default_legacy_pic;
7ee06cb2	424	EXPORT_SYMBOL(legacy_pic);
087b255a	425
f3c6ea1b	426	static int __init i8259A_init_ops(void)
087b255a	427	{
f3c6ea1b RW	428	if (legacy_pic == &default_legacy_pic)
f3c6ea1b RW	429	register_syscore_ops(&i8259_syscore_ops);
087b255a	430
f3c6ea1b	431	return 0;
087b255a AL	432	}
087b255a AL	433
f3c6ea1b	434	device_initcall(i8259A_init_ops);