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82c73e0a | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d8ed9d48 TG |
2 | /* |
3 | * Interrupt descriptor table related code | |
d8ed9d48 TG |
4 | */ |
5 | #include <linux/interrupt.h> | |
6 | ||
00229a54 | 7 | #include <asm/cpu_entry_area.h> |
3e77abda | 8 | #include <asm/set_memory.h> |
3318e974 TG |
9 | #include <asm/traps.h> |
10 | #include <asm/proto.h> | |
d8ed9d48 | 11 | #include <asm/desc.h> |
447ae316 | 12 | #include <asm/hw_irq.h> |
d8ed9d48 | 13 | |
3318e974 TG |
14 | #define DPL0 0x0 |
15 | #define DPL3 0x3 | |
16 | ||
17 | #define DEFAULT_STACK 0 | |
18 | ||
19 | #define G(_vector, _addr, _ist, _type, _dpl, _segment) \ | |
20 | { \ | |
21 | .vector = _vector, \ | |
22 | .bits.ist = _ist, \ | |
23 | .bits.type = _type, \ | |
24 | .bits.dpl = _dpl, \ | |
25 | .bits.p = 1, \ | |
26 | .addr = _addr, \ | |
27 | .segment = _segment, \ | |
28 | } | |
29 | ||
30 | /* Interrupt gate */ | |
31 | #define INTG(_vector, _addr) \ | |
32 | G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS) | |
33 | ||
34 | /* System interrupt gate */ | |
35 | #define SYSG(_vector, _addr) \ | |
36 | G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS) | |
37 | ||
1dcc917a | 38 | #ifdef CONFIG_X86_64 |
8f34c5b5 TG |
39 | /* |
40 | * Interrupt gate with interrupt stack. The _ist index is the index in | |
41 | * the tss.ist[] array, but for the descriptor it needs to start at 1. | |
42 | */ | |
3318e974 | 43 | #define ISTG(_vector, _addr, _ist) \ |
8f34c5b5 | 44 | G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS) |
1dcc917a TG |
45 | #else |
46 | #define ISTG(_vector, _addr, _ist) INTG(_vector, _addr) | |
47 | #endif | |
3318e974 TG |
48 | |
49 | /* Task gate */ | |
50 | #define TSKG(_vector, _gdt) \ | |
51 | G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3) | |
52 | ||
5a2bafca | 53 | #define IDT_TABLE_SIZE (IDT_ENTRIES * sizeof(gate_desc)) |
06184325 VK |
54 | |
55 | static bool idt_setup_done __initdata; | |
56 | ||
433f8924 TG |
57 | /* |
58 | * Early traps running on the DEFAULT_STACK because the other interrupt | |
59 | * stacks work only after cpu_init(). | |
60 | */ | |
327867fa | 61 | static const __initconst struct idt_data early_idts[] = { |
2bbc68f8 | 62 | INTG(X86_TRAP_DB, asm_exc_debug), |
8edd7e37 | 63 | SYSG(X86_TRAP_BP, asm_exc_int3), |
94438af4 | 64 | |
433f8924 | 65 | #ifdef CONFIG_X86_32 |
94438af4 TG |
66 | /* |
67 | * Not possible on 64-bit. See idt_setup_early_pf() for details. | |
68 | */ | |
91eeafea | 69 | INTG(X86_TRAP_PF, asm_exc_page_fault), |
433f8924 TG |
70 | #endif |
71 | }; | |
72 | ||
b70543a0 TG |
73 | /* |
74 | * The default IDT entries which are set up in trap_init() before | |
75 | * cpu_init() is invoked. Interrupt stacks cannot be used at that point and | |
76 | * the traps which use them are reinitialized with IST after cpu_init() has | |
77 | * set up TSS. | |
78 | */ | |
327867fa | 79 | static const __initconst struct idt_data def_idts[] = { |
9d06c402 | 80 | INTG(X86_TRAP_DE, asm_exc_divide_error), |
1dcc917a | 81 | ISTG(X86_TRAP_NMI, asm_exc_nmi, IST_INDEX_NMI), |
58d9c81f | 82 | INTG(X86_TRAP_BR, asm_exc_bounds), |
49893c5c | 83 | INTG(X86_TRAP_UD, asm_exc_invalid_op), |
866ae2cc | 84 | INTG(X86_TRAP_NM, asm_exc_device_not_available), |
f95658fd | 85 | INTG(X86_TRAP_OLD_MF, asm_exc_coproc_segment_overrun), |
97b3d290 | 86 | INTG(X86_TRAP_TS, asm_exc_invalid_tss), |
99a3fb8d | 87 | INTG(X86_TRAP_NP, asm_exc_segment_not_present), |
fd9689bf | 88 | INTG(X86_TRAP_SS, asm_exc_stack_segment), |
be4c11af | 89 | INTG(X86_TRAP_GP, asm_exc_general_protection), |
dad7106f | 90 | INTG(X86_TRAP_SPURIOUS, asm_exc_spurious_interrupt_bug), |
14a8bd2a | 91 | INTG(X86_TRAP_MF, asm_exc_coprocessor_error), |
436608bb | 92 | INTG(X86_TRAP_AC, asm_exc_alignment_check), |
48227e21 | 93 | INTG(X86_TRAP_XF, asm_exc_simd_coprocessor_error), |
b70543a0 TG |
94 | |
95 | #ifdef CONFIG_X86_32 | |
96 | TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS), | |
97 | #else | |
1dcc917a | 98 | ISTG(X86_TRAP_DF, asm_exc_double_fault, IST_INDEX_DF), |
b70543a0 | 99 | #endif |
1dcc917a | 100 | ISTG(X86_TRAP_DB, asm_exc_debug, IST_INDEX_DB), |
b70543a0 TG |
101 | |
102 | #ifdef CONFIG_X86_MCE | |
1dcc917a TG |
103 | ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE), |
104 | #endif | |
105 | ||
106 | #ifdef CONFIG_AMD_MEM_ENCRYPT | |
107 | ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC), | |
b70543a0 TG |
108 | #endif |
109 | ||
4b6b9111 | 110 | SYSG(X86_TRAP_OF, asm_exc_overflow), |
b70543a0 TG |
111 | #if defined(CONFIG_IA32_EMULATION) |
112 | SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat), | |
113 | #elif defined(CONFIG_X86_32) | |
114 | SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32), | |
115 | #endif | |
116 | }; | |
117 | ||
636a7598 TG |
118 | /* |
119 | * The APIC and SMP idt entries | |
120 | */ | |
327867fa | 121 | static const __initconst struct idt_data apic_idts[] = { |
636a7598 | 122 | #ifdef CONFIG_SMP |
13cad985 | 123 | INTG(RESCHEDULE_VECTOR, asm_sysvec_reschedule_ipi), |
582f9191 TG |
124 | INTG(CALL_FUNCTION_VECTOR, asm_sysvec_call_function), |
125 | INTG(CALL_FUNCTION_SINGLE_VECTOR, asm_sysvec_call_function_single), | |
126 | INTG(IRQ_MOVE_CLEANUP_VECTOR, asm_sysvec_irq_move_cleanup), | |
127 | INTG(REBOOT_VECTOR, asm_sysvec_reboot), | |
636a7598 TG |
128 | #endif |
129 | ||
130 | #ifdef CONFIG_X86_THERMAL_VECTOR | |
720909a7 | 131 | INTG(THERMAL_APIC_VECTOR, asm_sysvec_thermal), |
636a7598 TG |
132 | #endif |
133 | ||
134 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
720909a7 | 135 | INTG(THRESHOLD_APIC_VECTOR, asm_sysvec_threshold), |
636a7598 TG |
136 | #endif |
137 | ||
138 | #ifdef CONFIG_X86_MCE_AMD | |
720909a7 | 139 | INTG(DEFERRED_ERROR_VECTOR, asm_sysvec_deferred_error), |
636a7598 TG |
140 | #endif |
141 | ||
142 | #ifdef CONFIG_X86_LOCAL_APIC | |
720909a7 TG |
143 | INTG(LOCAL_TIMER_VECTOR, asm_sysvec_apic_timer_interrupt), |
144 | INTG(X86_PLATFORM_IPI_VECTOR, asm_sysvec_x86_platform_ipi), | |
636a7598 | 145 | # ifdef CONFIG_HAVE_KVM |
9c3b1f49 TG |
146 | INTG(POSTED_INTR_VECTOR, asm_sysvec_kvm_posted_intr_ipi), |
147 | INTG(POSTED_INTR_WAKEUP_VECTOR, asm_sysvec_kvm_posted_intr_wakeup_ipi), | |
148 | INTG(POSTED_INTR_NESTED_VECTOR, asm_sysvec_kvm_posted_intr_nested_ipi), | |
636a7598 TG |
149 | # endif |
150 | # ifdef CONFIG_IRQ_WORK | |
720909a7 | 151 | INTG(IRQ_WORK_VECTOR, asm_sysvec_irq_work), |
720909a7 TG |
152 | # endif |
153 | INTG(SPURIOUS_APIC_VECTOR, asm_sysvec_spurious_apic_interrupt), | |
154 | INTG(ERROR_APIC_VECTOR, asm_sysvec_error_interrupt), | |
636a7598 TG |
155 | #endif |
156 | }; | |
157 | ||
3e77abda TG |
158 | /* Must be page-aligned because the real IDT is used in the cpu entry area */ |
159 | static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; | |
d8ed9d48 | 160 | |
286d966b | 161 | static struct desc_ptr idt_descr __ro_after_init = { |
5a2bafca | 162 | .size = IDT_TABLE_SIZE - 1, |
d8ed9d48 TG |
163 | .address = (unsigned long) idt_table, |
164 | }; | |
165 | ||
3e77abda TG |
166 | void load_current_idt(void) |
167 | { | |
168 | lockdep_assert_irqs_disabled(); | |
169 | load_idt(&idt_descr); | |
170 | } | |
171 | ||
172 | #ifdef CONFIG_X86_F00F_BUG | |
173 | bool idt_is_f00f_address(unsigned long address) | |
174 | { | |
175 | return ((address - idt_descr.address) >> 3) == 6; | |
176 | } | |
d8ed9d48 | 177 | #endif |
e802a51e | 178 | |
bdf5bde8 | 179 | static __init void |
db18da78 | 180 | idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys) |
3318e974 TG |
181 | { |
182 | gate_desc desc; | |
183 | ||
184 | for (; size > 0; t++, size--) { | |
185 | idt_init_desc(&desc, t); | |
3318e974 | 186 | write_idt_entry(idt, t->vector, &desc); |
db18da78 | 187 | if (sys) |
7854f822 | 188 | set_bit(t->vector, system_vectors); |
3318e974 TG |
189 | } |
190 | } | |
191 | ||
bdf5bde8 | 192 | static __init void set_intr_gate(unsigned int n, const void *addr) |
facaa3e3 TG |
193 | { |
194 | struct idt_data data; | |
195 | ||
4bed2266 | 196 | init_idt_data(&data, n, addr); |
facaa3e3 TG |
197 | |
198 | idt_setup_from_table(idt_table, &data, 1, false); | |
199 | } | |
200 | ||
433f8924 TG |
201 | /** |
202 | * idt_setup_early_traps - Initialize the idt table with early traps | |
203 | * | |
204 | * On X8664 these traps do not use interrupt stacks as they can't work | |
205 | * before cpu_init() is invoked and sets up TSS. The IST variants are | |
206 | * installed after that. | |
207 | */ | |
208 | void __init idt_setup_early_traps(void) | |
209 | { | |
db18da78 TG |
210 | idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts), |
211 | true); | |
433f8924 TG |
212 | load_idt(&idt_descr); |
213 | } | |
214 | ||
b70543a0 TG |
215 | /** |
216 | * idt_setup_traps - Initialize the idt table with default traps | |
217 | */ | |
218 | void __init idt_setup_traps(void) | |
219 | { | |
db18da78 | 220 | idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true); |
b70543a0 TG |
221 | } |
222 | ||
433f8924 | 223 | #ifdef CONFIG_X86_64 |
3e77abda TG |
224 | /* |
225 | * Early traps running on the DEFAULT_STACK because the other interrupt | |
226 | * stacks work only after cpu_init(). | |
227 | */ | |
228 | static const __initconst struct idt_data early_pf_idts[] = { | |
229 | INTG(X86_TRAP_PF, asm_exc_page_fault), | |
230 | }; | |
231 | ||
433f8924 TG |
232 | /** |
233 | * idt_setup_early_pf - Initialize the idt table with early pagefault handler | |
234 | * | |
235 | * On X8664 this does not use interrupt stacks as they can't work before | |
236 | * cpu_init() is invoked and sets up TSS. The IST variant is installed | |
237 | * after that. | |
238 | * | |
94438af4 | 239 | * Note, that X86_64 cannot install the real #PF handler in |
d9f6e12f | 240 | * idt_setup_early_traps() because the memory initialization needs the #PF |
94438af4 TG |
241 | * handler from the early_idt_handler_array to initialize the early page |
242 | * tables. | |
433f8924 TG |
243 | */ |
244 | void __init idt_setup_early_pf(void) | |
245 | { | |
246 | idt_setup_from_table(idt_table, early_pf_idts, | |
db18da78 | 247 | ARRAY_SIZE(early_pf_idts), true); |
433f8924 TG |
248 | } |
249 | #endif | |
250 | ||
00229a54 TG |
251 | static void __init idt_map_in_cea(void) |
252 | { | |
253 | /* | |
254 | * Set the IDT descriptor to a fixed read-only location in the cpu | |
255 | * entry area, so that the "sidt" instruction will not leak the | |
256 | * location of the kernel, and to defend the IDT against arbitrary | |
257 | * memory write vulnerabilities. | |
258 | */ | |
259 | cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table), | |
260 | PAGE_KERNEL_RO); | |
261 | idt_descr.address = CPU_ENTRY_AREA_RO_IDT; | |
262 | } | |
263 | ||
636a7598 TG |
264 | /** |
265 | * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates | |
266 | */ | |
267 | void __init idt_setup_apic_and_irq_gates(void) | |
268 | { | |
dc20b2d5 TG |
269 | int i = FIRST_EXTERNAL_VECTOR; |
270 | void *entry; | |
271 | ||
db18da78 | 272 | idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true); |
dc20b2d5 | 273 | |
7854f822 | 274 | for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) { |
dc20b2d5 TG |
275 | entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR); |
276 | set_intr_gate(i, entry); | |
277 | } | |
278 | ||
dc20b2d5 | 279 | #ifdef CONFIG_X86_LOCAL_APIC |
33662812 | 280 | for_each_clear_bit_from(i, system_vectors, NR_VECTORS) { |
1f1fbc70 VK |
281 | /* |
282 | * Don't set the non assigned system vectors in the | |
283 | * system_vectors bitmap. Otherwise they show up in | |
284 | * /proc/interrupts. | |
285 | */ | |
f8a8fe61 TG |
286 | entry = spurious_entries_start + 8 * (i - FIRST_SYSTEM_VECTOR); |
287 | set_intr_gate(i, entry); | |
dc20b2d5 | 288 | } |
33662812 | 289 | #endif |
00229a54 TG |
290 | /* Map IDT into CPU entry area and reload it. */ |
291 | idt_map_in_cea(); | |
292 | load_idt(&idt_descr); | |
293 | ||
3e77abda TG |
294 | /* Make the IDT table read only */ |
295 | set_memory_ro((unsigned long)&idt_table, 1); | |
296 | ||
06184325 | 297 | idt_setup_done = true; |
636a7598 TG |
298 | } |
299 | ||
588787fd TG |
300 | /** |
301 | * idt_setup_early_handler - Initializes the idt table with early handlers | |
302 | */ | |
303 | void __init idt_setup_early_handler(void) | |
304 | { | |
305 | int i; | |
306 | ||
307 | for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) | |
308 | set_intr_gate(i, early_idt_handler_array[i]); | |
87e81786 TG |
309 | #ifdef CONFIG_X86_32 |
310 | for ( ; i < NR_VECTORS; i++) | |
311 | set_intr_gate(i, early_ignore_irq); | |
312 | #endif | |
588787fd TG |
313 | load_idt(&idt_descr); |
314 | } | |
315 | ||
e802a51e TG |
316 | /** |
317 | * idt_invalidate - Invalidate interrupt descriptor table | |
e802a51e | 318 | */ |
8ec9069a | 319 | void idt_invalidate(void) |
e802a51e | 320 | { |
8ec9069a | 321 | static const struct desc_ptr idt = { .address = 0, .size = 0 }; |
e802a51e TG |
322 | |
323 | load_idt(&idt); | |
324 | } | |
db18da78 | 325 | |
06184325 | 326 | void __init alloc_intr_gate(unsigned int n, const void *addr) |
db18da78 | 327 | { |
06184325 VK |
328 | if (WARN_ON(n < FIRST_SYSTEM_VECTOR)) |
329 | return; | |
330 | ||
331 | if (WARN_ON(idt_setup_done)) | |
332 | return; | |
333 | ||
334 | if (!WARN_ON(test_and_set_bit(n, system_vectors))) | |
4447ac11 | 335 | set_intr_gate(n, addr); |
db18da78 | 336 | } |