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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
49 | #include <asm/desc.h> | |
d4057bdb YL |
50 | #include <asm/proto.h> |
51 | #include <asm/acpi.h> | |
52 | #include <asm/dma.h> | |
1da177e4 | 53 | #include <asm/timer.h> |
306e440d | 54 | #include <asm/i8259.h> |
3e4ff115 | 55 | #include <asm/nmi.h> |
2d3fcc1c | 56 | #include <asm/msidef.h> |
8b955b0d | 57 | #include <asm/hypertransport.h> |
a4dbc34d | 58 | #include <asm/setup.h> |
d4057bdb | 59 | #include <asm/irq_remapping.h> |
58ac1e76 | 60 | #include <asm/hpet.h> |
4173a0e7 DN |
61 | #include <asm/uv/uv_hub.h> |
62 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 63 | |
497c9a19 | 64 | #include <mach_ipi.h> |
1da177e4 | 65 | #include <mach_apic.h> |
874c4fe3 | 66 | #include <mach_apicdef.h> |
1da177e4 | 67 | |
32f71aff MR |
68 | #define __apicdebuginit(type) static type __init |
69 | ||
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
ec2cd0a2 | 85 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
584f734d | 88 | /* MP IRQ source entries */ |
2fddb6e2 | 89 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
90 | |
91 | /* # of MP IRQ source entries */ | |
92 | int mp_irq_entries; | |
93 | ||
8732fc4b AS |
94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
96 | #endif | |
97 | ||
98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
99 | ||
efa2559f YL |
100 | int skip_ioapic_setup; |
101 | ||
54168ed7 | 102 | static int __init parse_noapic(char *str) |
efa2559f YL |
103 | { |
104 | /* disable IO-APIC */ | |
105 | disable_ioapic_setup(); | |
106 | return 0; | |
107 | } | |
108 | early_param("noapic", parse_noapic); | |
66759a01 | 109 | |
0f978f45 | 110 | struct irq_pin_list; |
0b8f1efa YL |
111 | |
112 | /* | |
113 | * This is performance-critical, we want to do it O(1) | |
114 | * | |
115 | * the indexing order of this array favors 1:1 mappings | |
116 | * between pins and IRQs. | |
117 | */ | |
118 | ||
119 | struct irq_pin_list { | |
120 | int apic, pin; | |
121 | struct irq_pin_list *next; | |
122 | }; | |
123 | ||
124 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
125 | { | |
126 | struct irq_pin_list *pin; | |
127 | int node; | |
128 | ||
129 | node = cpu_to_node(cpu); | |
130 | ||
131 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
132 | printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node); | |
133 | ||
134 | return pin; | |
135 | } | |
136 | ||
a1420f39 | 137 | struct irq_cfg { |
0f978f45 | 138 | struct irq_pin_list *irq_2_pin; |
497c9a19 YL |
139 | cpumask_t domain; |
140 | cpumask_t old_domain; | |
141 | unsigned move_cleanup_count; | |
a1420f39 | 142 | u8 vector; |
497c9a19 | 143 | u8 move_in_progress : 1; |
48a1b10a YL |
144 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
145 | u8 move_desc_pending : 1; | |
146 | #endif | |
a1420f39 YL |
147 | }; |
148 | ||
a1420f39 | 149 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
150 | #ifdef CONFIG_SPARSE_IRQ |
151 | static struct irq_cfg irq_cfgx[] = { | |
152 | #else | |
d6c88a50 | 153 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa YL |
154 | #endif |
155 | [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, | |
156 | [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
157 | [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
158 | [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
159 | [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
160 | [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
161 | [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
162 | [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
163 | [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
164 | [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
165 | [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
166 | [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
167 | [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
168 | [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
169 | [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
170 | [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
171 | }; |
172 | ||
0b8f1efa | 173 | void __init arch_early_irq_init(void) |
8f09cd20 | 174 | { |
0b8f1efa YL |
175 | struct irq_cfg *cfg; |
176 | struct irq_desc *desc; | |
177 | int count; | |
178 | int i; | |
d6c88a50 | 179 | |
0b8f1efa YL |
180 | cfg = irq_cfgx; |
181 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 182 | |
0b8f1efa YL |
183 | for (i = 0; i < count; i++) { |
184 | desc = irq_to_desc(i); | |
185 | desc->chip_data = &cfg[i]; | |
186 | } | |
187 | } | |
d6c88a50 | 188 | |
0b8f1efa YL |
189 | #ifdef CONFIG_SPARSE_IRQ |
190 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
191 | { | |
192 | struct irq_cfg *cfg = NULL; | |
193 | struct irq_desc *desc; | |
1da177e4 | 194 | |
0b8f1efa YL |
195 | desc = irq_to_desc(irq); |
196 | if (desc) | |
197 | cfg = desc->chip_data; | |
0f978f45 | 198 | |
0b8f1efa YL |
199 | return cfg; |
200 | } | |
d6c88a50 | 201 | |
0b8f1efa | 202 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
0f978f45 | 203 | { |
0b8f1efa YL |
204 | struct irq_cfg *cfg; |
205 | int node; | |
206 | ||
207 | node = cpu_to_node(cpu); | |
0f978f45 | 208 | |
0b8f1efa YL |
209 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
210 | printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node); | |
0f978f45 | 211 | |
0b8f1efa | 212 | return cfg; |
0f978f45 | 213 | } |
0f978f45 | 214 | |
0b8f1efa | 215 | void arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 216 | { |
0b8f1efa | 217 | struct irq_cfg *cfg; |
0f978f45 | 218 | |
0b8f1efa YL |
219 | cfg = desc->chip_data; |
220 | if (!cfg) { | |
221 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
222 | if (!desc->chip_data) { | |
223 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
224 | BUG_ON(1); | |
225 | } | |
226 | } | |
227 | } | |
301e6190 | 228 | |
48a1b10a YL |
229 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
230 | ||
231 | static void | |
232 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu) | |
233 | { | |
234 | struct irq_pin_list *old_entry, *head, *tail, *entry; | |
235 | ||
236 | cfg->irq_2_pin = NULL; | |
237 | old_entry = old_cfg->irq_2_pin; | |
238 | if (!old_entry) | |
239 | return; | |
240 | ||
241 | entry = get_one_free_irq_2_pin(cpu); | |
242 | if (!entry) | |
243 | return; | |
244 | ||
245 | entry->apic = old_entry->apic; | |
246 | entry->pin = old_entry->pin; | |
247 | head = entry; | |
248 | tail = entry; | |
249 | old_entry = old_entry->next; | |
250 | while (old_entry) { | |
251 | entry = get_one_free_irq_2_pin(cpu); | |
252 | if (!entry) { | |
253 | entry = head; | |
254 | while (entry) { | |
255 | head = entry->next; | |
256 | kfree(entry); | |
257 | entry = head; | |
258 | } | |
259 | /* still use the old one */ | |
260 | return; | |
261 | } | |
262 | entry->apic = old_entry->apic; | |
263 | entry->pin = old_entry->pin; | |
264 | tail->next = entry; | |
265 | tail = entry; | |
266 | old_entry = old_entry->next; | |
267 | } | |
268 | ||
269 | tail->next = NULL; | |
270 | cfg->irq_2_pin = head; | |
271 | } | |
272 | ||
273 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) | |
274 | { | |
275 | struct irq_pin_list *entry, *next; | |
276 | ||
277 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) | |
278 | return; | |
279 | ||
280 | entry = old_cfg->irq_2_pin; | |
281 | ||
282 | while (entry) { | |
283 | next = entry->next; | |
284 | kfree(entry); | |
285 | entry = next; | |
286 | } | |
287 | old_cfg->irq_2_pin = NULL; | |
288 | } | |
289 | ||
290 | void arch_init_copy_chip_data(struct irq_desc *old_desc, | |
291 | struct irq_desc *desc, int cpu) | |
292 | { | |
293 | struct irq_cfg *cfg; | |
294 | struct irq_cfg *old_cfg; | |
295 | ||
296 | cfg = get_one_free_irq_cfg(cpu); | |
297 | ||
298 | if (!cfg) | |
299 | return; | |
300 | ||
301 | desc->chip_data = cfg; | |
302 | ||
303 | old_cfg = old_desc->chip_data; | |
304 | ||
305 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
306 | ||
307 | init_copy_irq_2_pin(old_cfg, cfg, cpu); | |
308 | } | |
309 | ||
310 | static void free_irq_cfg(struct irq_cfg *old_cfg) | |
311 | { | |
312 | kfree(old_cfg); | |
313 | } | |
314 | ||
315 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
316 | { | |
317 | struct irq_cfg *old_cfg, *cfg; | |
318 | ||
319 | old_cfg = old_desc->chip_data; | |
320 | cfg = desc->chip_data; | |
321 | ||
322 | if (old_cfg == cfg) | |
323 | return; | |
324 | ||
325 | if (old_cfg) { | |
326 | free_irq_2_pin(old_cfg, cfg); | |
327 | free_irq_cfg(old_cfg); | |
328 | old_desc->chip_data = NULL; | |
329 | } | |
330 | } | |
331 | ||
332 | static void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask) | |
333 | { | |
334 | struct irq_cfg *cfg = desc->chip_data; | |
335 | ||
336 | if (!cfg->move_in_progress) { | |
337 | /* it means that domain is not changed */ | |
338 | if (!cpus_intersects(desc->affinity, mask)) | |
339 | cfg->move_desc_pending = 1; | |
340 | } | |
341 | } | |
342 | #endif | |
343 | ||
0b8f1efa YL |
344 | #else |
345 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
346 | { | |
347 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 348 | } |
1da177e4 | 349 | |
0b8f1efa YL |
350 | #endif |
351 | ||
48a1b10a | 352 | #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC |
3145e941 YL |
353 | static inline void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask) |
354 | { | |
355 | } | |
48a1b10a | 356 | #endif |
3145e941 | 357 | |
130fe05d LT |
358 | struct io_apic { |
359 | unsigned int index; | |
360 | unsigned int unused[3]; | |
361 | unsigned int data; | |
362 | }; | |
363 | ||
364 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
365 | { | |
366 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 367 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
368 | } |
369 | ||
370 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
371 | { | |
372 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
373 | writel(reg, &io_apic->index); | |
374 | return readl(&io_apic->data); | |
375 | } | |
376 | ||
377 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
378 | { | |
379 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
380 | writel(reg, &io_apic->index); | |
381 | writel(value, &io_apic->data); | |
382 | } | |
383 | ||
384 | /* | |
385 | * Re-write a value: to be used for read-modify-write | |
386 | * cycles where the read already set up the index register. | |
387 | * | |
388 | * Older SiS APIC requires we rewrite the index register | |
389 | */ | |
390 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
391 | { | |
54168ed7 | 392 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
393 | |
394 | if (sis_apic_bug) | |
395 | writel(reg, &io_apic->index); | |
130fe05d LT |
396 | writel(value, &io_apic->data); |
397 | } | |
398 | ||
3145e941 | 399 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
400 | { |
401 | struct irq_pin_list *entry; | |
402 | unsigned long flags; | |
047c8fdb YL |
403 | |
404 | spin_lock_irqsave(&ioapic_lock, flags); | |
405 | entry = cfg->irq_2_pin; | |
406 | for (;;) { | |
407 | unsigned int reg; | |
408 | int pin; | |
409 | ||
410 | if (!entry) | |
411 | break; | |
412 | pin = entry->pin; | |
413 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
414 | /* Is the remote IRR bit set? */ | |
415 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
416 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
417 | return true; | |
418 | } | |
419 | if (!entry->next) | |
420 | break; | |
421 | entry = entry->next; | |
422 | } | |
423 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
424 | ||
425 | return false; | |
426 | } | |
047c8fdb | 427 | |
cf4c6a2f AK |
428 | union entry_union { |
429 | struct { u32 w1, w2; }; | |
430 | struct IO_APIC_route_entry entry; | |
431 | }; | |
432 | ||
433 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
434 | { | |
435 | union entry_union eu; | |
436 | unsigned long flags; | |
437 | spin_lock_irqsave(&ioapic_lock, flags); | |
438 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
439 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
440 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
441 | return eu.entry; | |
442 | } | |
443 | ||
f9dadfa7 LT |
444 | /* |
445 | * When we write a new IO APIC routing entry, we need to write the high | |
446 | * word first! If the mask bit in the low word is clear, we will enable | |
447 | * the interrupt, and we need to make sure the entry is fully populated | |
448 | * before that happens. | |
449 | */ | |
d15512f4 AK |
450 | static void |
451 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 452 | { |
cf4c6a2f AK |
453 | union entry_union eu; |
454 | eu.entry = e; | |
f9dadfa7 LT |
455 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
456 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
457 | } |
458 | ||
459 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
460 | { | |
461 | unsigned long flags; | |
462 | spin_lock_irqsave(&ioapic_lock, flags); | |
463 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
464 | spin_unlock_irqrestore(&ioapic_lock, flags); |
465 | } | |
466 | ||
467 | /* | |
468 | * When we mask an IO APIC routing entry, we need to write the low | |
469 | * word first, in order to set the mask bit before we change the | |
470 | * high bits! | |
471 | */ | |
472 | static void ioapic_mask_entry(int apic, int pin) | |
473 | { | |
474 | unsigned long flags; | |
475 | union entry_union eu = { .entry.mask = 1 }; | |
476 | ||
cf4c6a2f AK |
477 | spin_lock_irqsave(&ioapic_lock, flags); |
478 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
479 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
480 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
481 | } | |
482 | ||
497c9a19 | 483 | #ifdef CONFIG_SMP |
3145e941 | 484 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
485 | { |
486 | int apic, pin; | |
497c9a19 | 487 | struct irq_pin_list *entry; |
3145e941 | 488 | u8 vector = cfg->vector; |
497c9a19 | 489 | |
497c9a19 YL |
490 | entry = cfg->irq_2_pin; |
491 | for (;;) { | |
492 | unsigned int reg; | |
493 | ||
494 | if (!entry) | |
495 | break; | |
496 | ||
497 | apic = entry->apic; | |
498 | pin = entry->pin; | |
54168ed7 IM |
499 | #ifdef CONFIG_INTR_REMAP |
500 | /* | |
501 | * With interrupt-remapping, destination information comes | |
502 | * from interrupt-remapping table entry. | |
503 | */ | |
504 | if (!irq_remapped(irq)) | |
505 | io_apic_write(apic, 0x11 + pin*2, dest); | |
506 | #else | |
497c9a19 | 507 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 508 | #endif |
497c9a19 YL |
509 | reg = io_apic_read(apic, 0x10 + pin*2); |
510 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
511 | reg |= vector; | |
54168ed7 | 512 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
513 | if (!entry->next) |
514 | break; | |
515 | entry = entry->next; | |
516 | } | |
517 | } | |
efa2559f | 518 | |
3145e941 | 519 | static int assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask); |
efa2559f | 520 | |
3145e941 | 521 | static void set_ioapic_affinity_irq_desc(struct irq_desc *desc, cpumask_t mask) |
497c9a19 YL |
522 | { |
523 | struct irq_cfg *cfg; | |
524 | unsigned long flags; | |
525 | unsigned int dest; | |
526 | cpumask_t tmp; | |
3145e941 | 527 | unsigned int irq; |
497c9a19 | 528 | |
497c9a19 YL |
529 | cpus_and(tmp, mask, cpu_online_map); |
530 | if (cpus_empty(tmp)) | |
531 | return; | |
532 | ||
3145e941 YL |
533 | irq = desc->irq; |
534 | cfg = desc->chip_data; | |
535 | if (assign_irq_vector(irq, cfg, mask)) | |
497c9a19 YL |
536 | return; |
537 | ||
3145e941 YL |
538 | set_extra_move_desc(desc, mask); |
539 | ||
497c9a19 | 540 | cpus_and(tmp, cfg->domain, mask); |
497c9a19 YL |
541 | dest = cpu_mask_to_apicid(tmp); |
542 | /* | |
543 | * Only the high 8 bits are valid. | |
544 | */ | |
545 | dest = SET_APIC_LOGICAL_ID(dest); | |
546 | ||
547 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 548 | __target_IO_APIC_irq(irq, dest, cfg); |
54168ed7 | 549 | desc->affinity = mask; |
497c9a19 YL |
550 | spin_unlock_irqrestore(&ioapic_lock, flags); |
551 | } | |
3145e941 YL |
552 | |
553 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
554 | { | |
555 | struct irq_desc *desc; | |
556 | ||
557 | desc = irq_to_desc(irq); | |
558 | ||
559 | set_ioapic_affinity_irq_desc(desc, mask); | |
560 | } | |
497c9a19 YL |
561 | #endif /* CONFIG_SMP */ |
562 | ||
1da177e4 LT |
563 | /* |
564 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
565 | * shared ISA-space IRQs, so we have to support them. We are super | |
566 | * fast in the common case, and fast for shared ISA-space IRQs. | |
567 | */ | |
3145e941 | 568 | static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin) |
1da177e4 | 569 | { |
0f978f45 YL |
570 | struct irq_pin_list *entry; |
571 | ||
0f978f45 YL |
572 | entry = cfg->irq_2_pin; |
573 | if (!entry) { | |
0b8f1efa YL |
574 | entry = get_one_free_irq_2_pin(cpu); |
575 | if (!entry) { | |
576 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
577 | apic, pin); | |
578 | return; | |
579 | } | |
0f978f45 YL |
580 | cfg->irq_2_pin = entry; |
581 | entry->apic = apic; | |
582 | entry->pin = pin; | |
0f978f45 YL |
583 | return; |
584 | } | |
1da177e4 | 585 | |
0f978f45 YL |
586 | while (entry->next) { |
587 | /* not again, please */ | |
588 | if (entry->apic == apic && entry->pin == pin) | |
589 | return; | |
1da177e4 | 590 | |
0f978f45 | 591 | entry = entry->next; |
1da177e4 | 592 | } |
0f978f45 | 593 | |
0b8f1efa | 594 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 595 | entry = entry->next; |
1da177e4 LT |
596 | entry->apic = apic; |
597 | entry->pin = pin; | |
598 | } | |
599 | ||
600 | /* | |
601 | * Reroute an IRQ to a different pin. | |
602 | */ | |
3145e941 | 603 | static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu, |
1da177e4 LT |
604 | int oldapic, int oldpin, |
605 | int newapic, int newpin) | |
606 | { | |
0f978f45 YL |
607 | struct irq_pin_list *entry = cfg->irq_2_pin; |
608 | int replaced = 0; | |
1da177e4 | 609 | |
0f978f45 | 610 | while (entry) { |
1da177e4 LT |
611 | if (entry->apic == oldapic && entry->pin == oldpin) { |
612 | entry->apic = newapic; | |
613 | entry->pin = newpin; | |
0f978f45 YL |
614 | replaced = 1; |
615 | /* every one is different, right? */ | |
1da177e4 | 616 | break; |
0f978f45 YL |
617 | } |
618 | entry = entry->next; | |
1da177e4 | 619 | } |
0f978f45 YL |
620 | |
621 | /* why? call replace before add? */ | |
622 | if (!replaced) | |
3145e941 | 623 | add_pin_to_irq_cpu(cfg, cpu, newapic, newpin); |
1da177e4 LT |
624 | } |
625 | ||
3145e941 | 626 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
627 | int mask_and, int mask_or, |
628 | void (*final)(struct irq_pin_list *entry)) | |
629 | { | |
630 | int pin; | |
87783be4 | 631 | struct irq_pin_list *entry; |
047c8fdb | 632 | |
87783be4 CG |
633 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
634 | unsigned int reg; | |
635 | pin = entry->pin; | |
636 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
637 | reg &= mask_and; | |
638 | reg |= mask_or; | |
639 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
640 | if (final) | |
641 | final(entry); | |
642 | } | |
643 | } | |
047c8fdb | 644 | |
3145e941 | 645 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 646 | { |
3145e941 | 647 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 648 | } |
047c8fdb | 649 | |
4e738e2f | 650 | #ifdef CONFIG_X86_64 |
87783be4 | 651 | void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 652 | { |
87783be4 CG |
653 | /* |
654 | * Synchronize the IO-APIC and the CPU by doing | |
655 | * a dummy read from the IO-APIC | |
656 | */ | |
657 | struct io_apic __iomem *io_apic; | |
658 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 659 | readl(&io_apic->data); |
1da177e4 LT |
660 | } |
661 | ||
3145e941 | 662 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 663 | { |
3145e941 | 664 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
665 | } |
666 | #else /* CONFIG_X86_32 */ | |
3145e941 | 667 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 668 | { |
3145e941 | 669 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 670 | } |
1da177e4 | 671 | |
3145e941 | 672 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 673 | { |
3145e941 | 674 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
675 | IO_APIC_REDIR_MASKED, NULL); |
676 | } | |
1da177e4 | 677 | |
3145e941 | 678 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 679 | { |
3145e941 | 680 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
681 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
682 | } | |
683 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 684 | |
3145e941 | 685 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 686 | { |
3145e941 | 687 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
688 | unsigned long flags; |
689 | ||
3145e941 YL |
690 | BUG_ON(!cfg); |
691 | ||
1da177e4 | 692 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 693 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
694 | spin_unlock_irqrestore(&ioapic_lock, flags); |
695 | } | |
696 | ||
3145e941 | 697 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 698 | { |
3145e941 | 699 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
700 | unsigned long flags; |
701 | ||
702 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 703 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
704 | spin_unlock_irqrestore(&ioapic_lock, flags); |
705 | } | |
706 | ||
3145e941 YL |
707 | static void mask_IO_APIC_irq(unsigned int irq) |
708 | { | |
709 | struct irq_desc *desc = irq_to_desc(irq); | |
710 | ||
711 | mask_IO_APIC_irq_desc(desc); | |
712 | } | |
713 | static void unmask_IO_APIC_irq(unsigned int irq) | |
714 | { | |
715 | struct irq_desc *desc = irq_to_desc(irq); | |
716 | ||
717 | unmask_IO_APIC_irq_desc(desc); | |
718 | } | |
719 | ||
1da177e4 LT |
720 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
721 | { | |
722 | struct IO_APIC_route_entry entry; | |
36062448 | 723 | |
1da177e4 | 724 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 725 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
726 | if (entry.delivery_mode == dest_SMI) |
727 | return; | |
1da177e4 LT |
728 | /* |
729 | * Disable it in the IO-APIC irq-routing table: | |
730 | */ | |
f9dadfa7 | 731 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
732 | } |
733 | ||
54168ed7 | 734 | static void clear_IO_APIC (void) |
1da177e4 LT |
735 | { |
736 | int apic, pin; | |
737 | ||
738 | for (apic = 0; apic < nr_ioapics; apic++) | |
739 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
740 | clear_IO_APIC_pin(apic, pin); | |
741 | } | |
742 | ||
54168ed7 | 743 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 744 | void send_IPI_self(int vector) |
1da177e4 LT |
745 | { |
746 | unsigned int cfg; | |
747 | ||
748 | /* | |
749 | * Wait for idle. | |
750 | */ | |
751 | apic_wait_icr_idle(); | |
752 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
753 | /* | |
754 | * Send the IPI. The write to APIC_ICR fires this off. | |
755 | */ | |
593f4a78 | 756 | apic_write(APIC_ICR, cfg); |
1da177e4 | 757 | } |
54168ed7 | 758 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 759 | |
54168ed7 | 760 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
761 | /* |
762 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
763 | * specific CPU-side IRQs. | |
764 | */ | |
765 | ||
766 | #define MAX_PIRQS 8 | |
767 | static int pirq_entries [MAX_PIRQS]; | |
768 | static int pirqs_enabled; | |
1da177e4 | 769 | |
1da177e4 LT |
770 | static int __init ioapic_pirq_setup(char *str) |
771 | { | |
772 | int i, max; | |
773 | int ints[MAX_PIRQS+1]; | |
774 | ||
775 | get_options(str, ARRAY_SIZE(ints), ints); | |
776 | ||
777 | for (i = 0; i < MAX_PIRQS; i++) | |
778 | pirq_entries[i] = -1; | |
779 | ||
780 | pirqs_enabled = 1; | |
781 | apic_printk(APIC_VERBOSE, KERN_INFO | |
782 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
783 | max = MAX_PIRQS; | |
784 | if (ints[0] < MAX_PIRQS) | |
785 | max = ints[0]; | |
786 | ||
787 | for (i = 0; i < max; i++) { | |
788 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
789 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
790 | /* | |
791 | * PIRQs are mapped upside down, usually. | |
792 | */ | |
793 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
794 | } | |
795 | return 1; | |
796 | } | |
797 | ||
798 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
799 | #endif /* CONFIG_X86_32 */ |
800 | ||
801 | #ifdef CONFIG_INTR_REMAP | |
802 | /* I/O APIC RTE contents at the OS boot up */ | |
803 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
804 | ||
805 | /* | |
806 | * Saves and masks all the unmasked IO-APIC RTE's | |
807 | */ | |
808 | int save_mask_IO_APIC_setup(void) | |
809 | { | |
810 | union IO_APIC_reg_01 reg_01; | |
811 | unsigned long flags; | |
812 | int apic, pin; | |
813 | ||
814 | /* | |
815 | * The number of IO-APIC IRQ registers (== #pins): | |
816 | */ | |
817 | for (apic = 0; apic < nr_ioapics; apic++) { | |
818 | spin_lock_irqsave(&ioapic_lock, flags); | |
819 | reg_01.raw = io_apic_read(apic, 1); | |
820 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
821 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
822 | } | |
823 | ||
824 | for (apic = 0; apic < nr_ioapics; apic++) { | |
825 | early_ioapic_entries[apic] = | |
826 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
827 | nr_ioapic_registers[apic], GFP_KERNEL); | |
828 | if (!early_ioapic_entries[apic]) | |
5ffa4eb2 | 829 | goto nomem; |
54168ed7 IM |
830 | } |
831 | ||
832 | for (apic = 0; apic < nr_ioapics; apic++) | |
833 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
834 | struct IO_APIC_route_entry entry; | |
835 | ||
836 | entry = early_ioapic_entries[apic][pin] = | |
837 | ioapic_read_entry(apic, pin); | |
838 | if (!entry.mask) { | |
839 | entry.mask = 1; | |
840 | ioapic_write_entry(apic, pin, entry); | |
841 | } | |
842 | } | |
5ffa4eb2 | 843 | |
54168ed7 | 844 | return 0; |
5ffa4eb2 CG |
845 | |
846 | nomem: | |
c1370b49 CG |
847 | while (apic >= 0) |
848 | kfree(early_ioapic_entries[apic--]); | |
5ffa4eb2 CG |
849 | memset(early_ioapic_entries, 0, |
850 | ARRAY_SIZE(early_ioapic_entries)); | |
851 | ||
852 | return -ENOMEM; | |
54168ed7 IM |
853 | } |
854 | ||
855 | void restore_IO_APIC_setup(void) | |
856 | { | |
857 | int apic, pin; | |
858 | ||
5ffa4eb2 CG |
859 | for (apic = 0; apic < nr_ioapics; apic++) { |
860 | if (!early_ioapic_entries[apic]) | |
861 | break; | |
54168ed7 IM |
862 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
863 | ioapic_write_entry(apic, pin, | |
864 | early_ioapic_entries[apic][pin]); | |
5ffa4eb2 CG |
865 | kfree(early_ioapic_entries[apic]); |
866 | early_ioapic_entries[apic] = NULL; | |
867 | } | |
54168ed7 IM |
868 | } |
869 | ||
870 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
871 | { | |
872 | /* | |
873 | * for now plain restore of previous settings. | |
874 | * TBD: In the case of OS enabling interrupt-remapping, | |
875 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
876 | * table entries. for now, do a plain restore, and wait for | |
877 | * the setup_IO_APIC_irqs() to do proper initialization. | |
878 | */ | |
879 | restore_IO_APIC_setup(); | |
880 | } | |
881 | #endif | |
1da177e4 LT |
882 | |
883 | /* | |
884 | * Find the IRQ entry number of a certain pin. | |
885 | */ | |
886 | static int find_irq_entry(int apic, int pin, int type) | |
887 | { | |
888 | int i; | |
889 | ||
890 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
891 | if (mp_irqs[i].mp_irqtype == type && |
892 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
893 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
894 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
895 | return i; |
896 | ||
897 | return -1; | |
898 | } | |
899 | ||
900 | /* | |
901 | * Find the pin to which IRQ[irq] (ISA) is connected | |
902 | */ | |
fcfd636a | 903 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
904 | { |
905 | int i; | |
906 | ||
907 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 908 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 909 | |
d27e2b8e | 910 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
911 | (mp_irqs[i].mp_irqtype == type) && |
912 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 913 | |
2fddb6e2 | 914 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
915 | } |
916 | return -1; | |
917 | } | |
918 | ||
fcfd636a EB |
919 | static int __init find_isa_irq_apic(int irq, int type) |
920 | { | |
921 | int i; | |
922 | ||
923 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 924 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 925 | |
73b2961b | 926 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
927 | (mp_irqs[i].mp_irqtype == type) && |
928 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
929 | break; |
930 | } | |
931 | if (i < mp_irq_entries) { | |
932 | int apic; | |
54168ed7 | 933 | for(apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 934 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
935 | return apic; |
936 | } | |
937 | } | |
938 | ||
939 | return -1; | |
940 | } | |
941 | ||
1da177e4 LT |
942 | /* |
943 | * Find a specific PCI IRQ entry. | |
944 | * Not an __init, possibly needed by modules | |
945 | */ | |
946 | static int pin_2_irq(int idx, int apic, int pin); | |
947 | ||
948 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
949 | { | |
950 | int apic, i, best_guess = -1; | |
951 | ||
54168ed7 IM |
952 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
953 | bus, slot, pin); | |
ce6444d3 | 954 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 955 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
956 | return -1; |
957 | } | |
958 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 959 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
960 | |
961 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
962 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
963 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
964 | break; |
965 | ||
47cab822 | 966 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 967 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 968 | (bus == lbus) && |
2fddb6e2 | 969 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
54168ed7 | 970 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
1da177e4 LT |
971 | |
972 | if (!(apic || IO_APIC_IRQ(irq))) | |
973 | continue; | |
974 | ||
2fddb6e2 | 975 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
976 | return irq; |
977 | /* | |
978 | * Use the first all-but-pin matching entry as a | |
979 | * best-guess fuzzy result for broken mptables. | |
980 | */ | |
981 | if (best_guess < 0) | |
982 | best_guess = irq; | |
983 | } | |
984 | } | |
985 | return best_guess; | |
986 | } | |
54168ed7 | 987 | |
129f6946 | 988 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 989 | |
c0a282c2 | 990 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
991 | /* |
992 | * EISA Edge/Level control register, ELCR | |
993 | */ | |
994 | static int EISA_ELCR(unsigned int irq) | |
995 | { | |
99d093d1 | 996 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
997 | unsigned int port = 0x4d0 + (irq >> 3); |
998 | return (inb(port) >> (irq & 7)) & 1; | |
999 | } | |
1000 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1001 | "Broken MPtable reports ISA irq %d\n", irq); | |
1002 | return 0; | |
1003 | } | |
54168ed7 | 1004 | |
c0a282c2 | 1005 | #endif |
1da177e4 | 1006 | |
6728801d AS |
1007 | /* ISA interrupts are always polarity zero edge triggered, |
1008 | * when listed as conforming in the MP table. */ | |
1009 | ||
1010 | #define default_ISA_trigger(idx) (0) | |
1011 | #define default_ISA_polarity(idx) (0) | |
1012 | ||
1da177e4 LT |
1013 | /* EISA interrupts are always polarity zero and can be edge or level |
1014 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1015 | * EISA conforming in the MP table, that means its trigger type must | |
1016 | * be read in from the ELCR */ | |
1017 | ||
2fddb6e2 | 1018 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 1019 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1020 | |
1021 | /* PCI interrupts are always polarity one level triggered, | |
1022 | * when listed as conforming in the MP table. */ | |
1023 | ||
1024 | #define default_PCI_trigger(idx) (1) | |
1025 | #define default_PCI_polarity(idx) (1) | |
1026 | ||
1027 | /* MCA interrupts are always polarity zero level triggered, | |
1028 | * when listed as conforming in the MP table. */ | |
1029 | ||
1030 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1031 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1032 | |
61fd47e0 | 1033 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1034 | { |
2fddb6e2 | 1035 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1036 | int polarity; |
1037 | ||
1038 | /* | |
1039 | * Determine IRQ line polarity (high active or low active): | |
1040 | */ | |
54168ed7 | 1041 | switch (mp_irqs[idx].mp_irqflag & 3) |
36062448 | 1042 | { |
54168ed7 IM |
1043 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1044 | if (test_bit(bus, mp_bus_not_pci)) | |
1045 | polarity = default_ISA_polarity(idx); | |
1046 | else | |
1047 | polarity = default_PCI_polarity(idx); | |
1048 | break; | |
1049 | case 1: /* high active */ | |
1050 | { | |
1051 | polarity = 0; | |
1052 | break; | |
1053 | } | |
1054 | case 2: /* reserved */ | |
1055 | { | |
1056 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1057 | polarity = 1; | |
1058 | break; | |
1059 | } | |
1060 | case 3: /* low active */ | |
1061 | { | |
1062 | polarity = 1; | |
1063 | break; | |
1064 | } | |
1065 | default: /* invalid */ | |
1066 | { | |
1067 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1068 | polarity = 1; | |
1069 | break; | |
1070 | } | |
1da177e4 LT |
1071 | } |
1072 | return polarity; | |
1073 | } | |
1074 | ||
1075 | static int MPBIOS_trigger(int idx) | |
1076 | { | |
2fddb6e2 | 1077 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1078 | int trigger; |
1079 | ||
1080 | /* | |
1081 | * Determine IRQ trigger mode (edge or level sensitive): | |
1082 | */ | |
54168ed7 | 1083 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 | 1084 | { |
54168ed7 IM |
1085 | case 0: /* conforms, ie. bus-type dependent */ |
1086 | if (test_bit(bus, mp_bus_not_pci)) | |
1087 | trigger = default_ISA_trigger(idx); | |
1088 | else | |
1089 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1090 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1091 | switch (mp_bus_id_to_type[bus]) { |
1092 | case MP_BUS_ISA: /* ISA pin */ | |
1093 | { | |
1094 | /* set before the switch */ | |
1095 | break; | |
1096 | } | |
1097 | case MP_BUS_EISA: /* EISA pin */ | |
1098 | { | |
1099 | trigger = default_EISA_trigger(idx); | |
1100 | break; | |
1101 | } | |
1102 | case MP_BUS_PCI: /* PCI pin */ | |
1103 | { | |
1104 | /* set before the switch */ | |
1105 | break; | |
1106 | } | |
1107 | case MP_BUS_MCA: /* MCA pin */ | |
1108 | { | |
1109 | trigger = default_MCA_trigger(idx); | |
1110 | break; | |
1111 | } | |
1112 | default: | |
1113 | { | |
1114 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1115 | trigger = 1; | |
1116 | break; | |
1117 | } | |
1118 | } | |
1119 | #endif | |
1da177e4 | 1120 | break; |
54168ed7 | 1121 | case 1: /* edge */ |
1da177e4 | 1122 | { |
54168ed7 | 1123 | trigger = 0; |
1da177e4 LT |
1124 | break; |
1125 | } | |
54168ed7 | 1126 | case 2: /* reserved */ |
1da177e4 | 1127 | { |
54168ed7 IM |
1128 | printk(KERN_WARNING "broken BIOS!!\n"); |
1129 | trigger = 1; | |
1da177e4 LT |
1130 | break; |
1131 | } | |
54168ed7 | 1132 | case 3: /* level */ |
1da177e4 | 1133 | { |
54168ed7 | 1134 | trigger = 1; |
1da177e4 LT |
1135 | break; |
1136 | } | |
54168ed7 | 1137 | default: /* invalid */ |
1da177e4 LT |
1138 | { |
1139 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1140 | trigger = 0; |
1da177e4 LT |
1141 | break; |
1142 | } | |
1143 | } | |
1144 | return trigger; | |
1145 | } | |
1146 | ||
1147 | static inline int irq_polarity(int idx) | |
1148 | { | |
1149 | return MPBIOS_polarity(idx); | |
1150 | } | |
1151 | ||
1152 | static inline int irq_trigger(int idx) | |
1153 | { | |
1154 | return MPBIOS_trigger(idx); | |
1155 | } | |
1156 | ||
efa2559f | 1157 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1158 | static int pin_2_irq(int idx, int apic, int pin) |
1159 | { | |
1160 | int irq, i; | |
2fddb6e2 | 1161 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1162 | |
1163 | /* | |
1164 | * Debugging check, we are in big trouble if this message pops up! | |
1165 | */ | |
2fddb6e2 | 1166 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1167 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1168 | ||
54168ed7 | 1169 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 1170 | irq = mp_irqs[idx].mp_srcbusirq; |
54168ed7 | 1171 | } else { |
643befed AS |
1172 | /* |
1173 | * PCI IRQs are mapped in order | |
1174 | */ | |
1175 | i = irq = 0; | |
1176 | while (i < apic) | |
1177 | irq += nr_ioapic_registers[i++]; | |
1178 | irq += pin; | |
d6c88a50 | 1179 | /* |
54168ed7 IM |
1180 | * For MPS mode, so far only needed by ES7000 platform |
1181 | */ | |
d6c88a50 TG |
1182 | if (ioapic_renumber_irq) |
1183 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1184 | } |
1185 | ||
54168ed7 | 1186 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1187 | /* |
1188 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1189 | */ | |
1190 | if ((pin >= 16) && (pin <= 23)) { | |
1191 | if (pirq_entries[pin-16] != -1) { | |
1192 | if (!pirq_entries[pin-16]) { | |
1193 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1194 | "disabling PIRQ%d\n", pin-16); | |
1195 | } else { | |
1196 | irq = pirq_entries[pin-16]; | |
1197 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1198 | "using PIRQ%d -> IRQ %d\n", | |
1199 | pin-16, irq); | |
1200 | } | |
1201 | } | |
1202 | } | |
54168ed7 IM |
1203 | #endif |
1204 | ||
1da177e4 LT |
1205 | return irq; |
1206 | } | |
1207 | ||
497c9a19 YL |
1208 | void lock_vector_lock(void) |
1209 | { | |
1210 | /* Used to the online set of cpus does not change | |
1211 | * during assign_irq_vector. | |
1212 | */ | |
1213 | spin_lock(&vector_lock); | |
1214 | } | |
1da177e4 | 1215 | |
497c9a19 | 1216 | void unlock_vector_lock(void) |
1da177e4 | 1217 | { |
497c9a19 YL |
1218 | spin_unlock(&vector_lock); |
1219 | } | |
1da177e4 | 1220 | |
3145e941 | 1221 | static int __assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask) |
497c9a19 | 1222 | { |
047c8fdb YL |
1223 | /* |
1224 | * NOTE! The local APIC isn't very good at handling | |
1225 | * multiple interrupts at the same interrupt level. | |
1226 | * As the interrupt level is determined by taking the | |
1227 | * vector number and shifting that right by 4, we | |
1228 | * want to spread these out a bit so that they don't | |
1229 | * all fall in the same interrupt level. | |
1230 | * | |
1231 | * Also, we've got to be careful not to trash gate | |
1232 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1233 | */ | |
54168ed7 IM |
1234 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1235 | unsigned int old_vector; | |
1236 | int cpu; | |
ace80ab7 | 1237 | |
3145e941 YL |
1238 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1239 | return -EBUSY; | |
8339f000 | 1240 | |
54168ed7 IM |
1241 | /* Only try and allocate irqs on cpus that are present */ |
1242 | cpus_and(mask, mask, cpu_online_map); | |
ace80ab7 | 1243 | |
54168ed7 IM |
1244 | old_vector = cfg->vector; |
1245 | if (old_vector) { | |
1246 | cpumask_t tmp; | |
1247 | cpus_and(tmp, cfg->domain, mask); | |
1248 | if (!cpus_empty(tmp)) | |
1249 | return 0; | |
1250 | } | |
497c9a19 | 1251 | |
54168ed7 IM |
1252 | for_each_cpu_mask_nr(cpu, mask) { |
1253 | cpumask_t domain, new_mask; | |
1254 | int new_cpu; | |
1255 | int vector, offset; | |
497c9a19 | 1256 | |
54168ed7 IM |
1257 | domain = vector_allocation_domain(cpu); |
1258 | cpus_and(new_mask, domain, cpu_online_map); | |
497c9a19 | 1259 | |
54168ed7 IM |
1260 | vector = current_vector; |
1261 | offset = current_offset; | |
497c9a19 | 1262 | next: |
54168ed7 IM |
1263 | vector += 8; |
1264 | if (vector >= first_system_vector) { | |
1265 | /* If we run out of vectors on large boxen, must share them. */ | |
1266 | offset = (offset + 1) % 8; | |
1267 | vector = FIRST_DEVICE_VECTOR + offset; | |
1268 | } | |
1269 | if (unlikely(current_vector == vector)) | |
1270 | continue; | |
047c8fdb | 1271 | #ifdef CONFIG_X86_64 |
54168ed7 IM |
1272 | if (vector == IA32_SYSCALL_VECTOR) |
1273 | goto next; | |
047c8fdb | 1274 | #else |
54168ed7 IM |
1275 | if (vector == SYSCALL_VECTOR) |
1276 | goto next; | |
047c8fdb | 1277 | #endif |
54168ed7 IM |
1278 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1279 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) | |
1280 | goto next; | |
1281 | /* Found one! */ | |
1282 | current_vector = vector; | |
1283 | current_offset = offset; | |
1284 | if (old_vector) { | |
1285 | cfg->move_in_progress = 1; | |
1286 | cfg->old_domain = cfg->domain; | |
7a959cff | 1287 | } |
54168ed7 IM |
1288 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1289 | per_cpu(vector_irq, new_cpu)[vector] = irq; | |
1290 | cfg->vector = vector; | |
1291 | cfg->domain = domain; | |
1292 | return 0; | |
1293 | } | |
1294 | return -ENOSPC; | |
497c9a19 YL |
1295 | } |
1296 | ||
3145e941 | 1297 | static int assign_irq_vector(int irq, struct irq_cfg *cfg, cpumask_t mask) |
497c9a19 YL |
1298 | { |
1299 | int err; | |
ace80ab7 | 1300 | unsigned long flags; |
ace80ab7 EB |
1301 | |
1302 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1303 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1304 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1305 | return err; |
1306 | } | |
1307 | ||
3145e941 | 1308 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1309 | { |
497c9a19 YL |
1310 | cpumask_t mask; |
1311 | int cpu, vector; | |
1312 | ||
497c9a19 YL |
1313 | BUG_ON(!cfg->vector); |
1314 | ||
1315 | vector = cfg->vector; | |
1316 | cpus_and(mask, cfg->domain, cpu_online_map); | |
1317 | for_each_cpu_mask_nr(cpu, mask) | |
1318 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1319 | ||
1320 | cfg->vector = 0; | |
1321 | cpus_clear(cfg->domain); | |
0ca4b6b0 MW |
1322 | |
1323 | if (likely(!cfg->move_in_progress)) | |
1324 | return; | |
1325 | cpus_and(mask, cfg->old_domain, cpu_online_map); | |
1326 | for_each_cpu_mask_nr(cpu, mask) { | |
1327 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; | |
1328 | vector++) { | |
1329 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1330 | continue; | |
1331 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1332 | break; | |
1333 | } | |
1334 | } | |
1335 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1336 | } |
1337 | ||
1338 | void __setup_vector_irq(int cpu) | |
1339 | { | |
1340 | /* Initialize vector_irq on a new cpu */ | |
1341 | /* This function must be called with vector_lock held */ | |
1342 | int irq, vector; | |
1343 | struct irq_cfg *cfg; | |
0b8f1efa | 1344 | struct irq_desc *desc; |
497c9a19 YL |
1345 | |
1346 | /* Mark the inuse vectors */ | |
0b8f1efa YL |
1347 | for_each_irq_desc(irq, desc) { |
1348 | if (!desc) | |
1349 | continue; | |
1350 | cfg = desc->chip_data; | |
497c9a19 YL |
1351 | if (!cpu_isset(cpu, cfg->domain)) |
1352 | continue; | |
1353 | vector = cfg->vector; | |
497c9a19 YL |
1354 | per_cpu(vector_irq, cpu)[vector] = irq; |
1355 | } | |
1356 | /* Mark the free vectors */ | |
1357 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1358 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1359 | if (irq < 0) | |
1360 | continue; | |
1361 | ||
1362 | cfg = irq_cfg(irq); | |
1363 | if (!cpu_isset(cpu, cfg->domain)) | |
1364 | per_cpu(vector_irq, cpu)[vector] = -1; | |
54168ed7 | 1365 | } |
1da177e4 | 1366 | } |
3fde6900 | 1367 | |
f5b9ed7a | 1368 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1369 | #ifdef CONFIG_INTR_REMAP |
1370 | static struct irq_chip ir_ioapic_chip; | |
1371 | #endif | |
1da177e4 | 1372 | |
54168ed7 IM |
1373 | #define IOAPIC_AUTO -1 |
1374 | #define IOAPIC_EDGE 0 | |
1375 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1376 | |
047c8fdb | 1377 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1378 | static inline int IO_APIC_irq_trigger(int irq) |
1379 | { | |
d6c88a50 | 1380 | int apic, idx, pin; |
1d025192 | 1381 | |
d6c88a50 TG |
1382 | for (apic = 0; apic < nr_ioapics; apic++) { |
1383 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1384 | idx = find_irq_entry(apic, pin, mp_INT); | |
1385 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1386 | return irq_trigger(idx); | |
1387 | } | |
1388 | } | |
1389 | /* | |
54168ed7 IM |
1390 | * nonexistent IRQs are edge default |
1391 | */ | |
d6c88a50 | 1392 | return 0; |
1d025192 | 1393 | } |
047c8fdb YL |
1394 | #else |
1395 | static inline int IO_APIC_irq_trigger(int irq) | |
1396 | { | |
54168ed7 | 1397 | return 1; |
047c8fdb YL |
1398 | } |
1399 | #endif | |
1d025192 | 1400 | |
3145e941 | 1401 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1402 | { |
199751d7 | 1403 | |
6ebcc00e | 1404 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1405 | trigger == IOAPIC_LEVEL) |
08678b08 | 1406 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1407 | else |
1408 | desc->status &= ~IRQ_LEVEL; | |
1409 | ||
54168ed7 IM |
1410 | #ifdef CONFIG_INTR_REMAP |
1411 | if (irq_remapped(irq)) { | |
1412 | desc->status |= IRQ_MOVE_PCNTXT; | |
1413 | if (trigger) | |
1414 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1415 | handle_fasteoi_irq, | |
1416 | "fasteoi"); | |
1417 | else | |
1418 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1419 | handle_edge_irq, "edge"); | |
1420 | return; | |
1421 | } | |
1422 | #endif | |
047c8fdb YL |
1423 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1424 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1425 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1426 | handle_fasteoi_irq, |
1427 | "fasteoi"); | |
047c8fdb | 1428 | else |
a460e745 | 1429 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1430 | handle_edge_irq, "edge"); |
1da177e4 LT |
1431 | } |
1432 | ||
497c9a19 YL |
1433 | static int setup_ioapic_entry(int apic, int irq, |
1434 | struct IO_APIC_route_entry *entry, | |
1435 | unsigned int destination, int trigger, | |
1436 | int polarity, int vector) | |
1da177e4 | 1437 | { |
497c9a19 YL |
1438 | /* |
1439 | * add it to the IO-APIC irq-routing table: | |
1440 | */ | |
1441 | memset(entry,0,sizeof(*entry)); | |
1442 | ||
54168ed7 IM |
1443 | #ifdef CONFIG_INTR_REMAP |
1444 | if (intr_remapping_enabled) { | |
1445 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1446 | struct irte irte; | |
1447 | struct IR_IO_APIC_route_entry *ir_entry = | |
1448 | (struct IR_IO_APIC_route_entry *) entry; | |
1449 | int index; | |
1450 | ||
1451 | if (!iommu) | |
1452 | panic("No mapping iommu for ioapic %d\n", apic); | |
1453 | ||
1454 | index = alloc_irte(iommu, irq, 1); | |
1455 | if (index < 0) | |
1456 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1457 | ||
1458 | memset(&irte, 0, sizeof(irte)); | |
1459 | ||
1460 | irte.present = 1; | |
1461 | irte.dst_mode = INT_DEST_MODE; | |
1462 | irte.trigger_mode = trigger; | |
1463 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1464 | irte.vector = vector; | |
1465 | irte.dest_id = IRTE_DEST(destination); | |
1466 | ||
1467 | modify_irte(irq, &irte); | |
1468 | ||
1469 | ir_entry->index2 = (index >> 15) & 0x1; | |
1470 | ir_entry->zero = 0; | |
1471 | ir_entry->format = 1; | |
1472 | ir_entry->index = (index & 0x7fff); | |
1473 | } else | |
1474 | #endif | |
1475 | { | |
1476 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1477 | entry->dest_mode = INT_DEST_MODE; | |
1478 | entry->dest = destination; | |
1479 | } | |
497c9a19 | 1480 | |
54168ed7 | 1481 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1482 | entry->trigger = trigger; |
1483 | entry->polarity = polarity; | |
1484 | entry->vector = vector; | |
1485 | ||
1486 | /* Mask level triggered irqs. | |
1487 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1488 | */ | |
1489 | if (trigger) | |
1490 | entry->mask = 1; | |
497c9a19 YL |
1491 | return 0; |
1492 | } | |
1493 | ||
3145e941 | 1494 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1495 | int trigger, int polarity) |
497c9a19 YL |
1496 | { |
1497 | struct irq_cfg *cfg; | |
1da177e4 | 1498 | struct IO_APIC_route_entry entry; |
497c9a19 YL |
1499 | cpumask_t mask; |
1500 | ||
1501 | if (!IO_APIC_IRQ(irq)) | |
1502 | return; | |
1503 | ||
3145e941 | 1504 | cfg = desc->chip_data; |
497c9a19 YL |
1505 | |
1506 | mask = TARGET_CPUS; | |
3145e941 | 1507 | if (assign_irq_vector(irq, cfg, mask)) |
497c9a19 YL |
1508 | return; |
1509 | ||
1510 | cpus_and(mask, cfg->domain, mask); | |
1511 | ||
1512 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1513 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1514 | "IRQ %d Mode:%i Active:%i)\n", | |
1515 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1516 | irq, trigger, polarity); | |
1517 | ||
1518 | ||
1519 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
1520 | cpu_mask_to_apicid(mask), trigger, polarity, | |
1521 | cfg->vector)) { | |
1522 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
1523 | mp_ioapics[apic].mp_apicid, pin); | |
3145e941 | 1524 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1525 | return; |
1526 | } | |
1527 | ||
3145e941 | 1528 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1529 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1530 | disable_8259A_irq(irq); |
1531 | ||
1532 | ioapic_write_entry(apic, pin, entry); | |
1533 | } | |
1534 | ||
1535 | static void __init setup_IO_APIC_irqs(void) | |
1536 | { | |
3c2cbd24 CG |
1537 | int apic, pin, idx, irq; |
1538 | int notcon = 0; | |
0b8f1efa | 1539 | struct irq_desc *desc; |
3145e941 | 1540 | struct irq_cfg *cfg; |
0b8f1efa | 1541 | int cpu = boot_cpu_id; |
1da177e4 LT |
1542 | |
1543 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1544 | ||
1545 | for (apic = 0; apic < nr_ioapics; apic++) { | |
3c2cbd24 | 1546 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
20d225b9 | 1547 | |
3c2cbd24 CG |
1548 | idx = find_irq_entry(apic, pin, mp_INT); |
1549 | if (idx == -1) { | |
2a554fb1 | 1550 | if (!notcon) { |
3c2cbd24 | 1551 | notcon = 1; |
2a554fb1 CG |
1552 | apic_printk(APIC_VERBOSE, |
1553 | KERN_DEBUG " %d-%d", | |
1554 | mp_ioapics[apic].mp_apicid, | |
1555 | pin); | |
1556 | } else | |
1557 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1558 | mp_ioapics[apic].mp_apicid, | |
1559 | pin); | |
3c2cbd24 CG |
1560 | continue; |
1561 | } | |
56ffa1a0 CG |
1562 | if (notcon) { |
1563 | apic_printk(APIC_VERBOSE, | |
1564 | " (apicid-pin) not connected\n"); | |
1565 | notcon = 0; | |
1566 | } | |
3c2cbd24 CG |
1567 | |
1568 | irq = pin_2_irq(idx, apic, pin); | |
54168ed7 | 1569 | #ifdef CONFIG_X86_32 |
3c2cbd24 CG |
1570 | if (multi_timer_check(apic, irq)) |
1571 | continue; | |
54168ed7 | 1572 | #endif |
0b8f1efa YL |
1573 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1574 | if (!desc) { | |
1575 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1576 | continue; | |
1577 | } | |
3145e941 YL |
1578 | cfg = desc->chip_data; |
1579 | add_pin_to_irq_cpu(cfg, cpu, apic, pin); | |
36062448 | 1580 | |
3145e941 | 1581 | setup_IO_APIC_irq(apic, pin, irq, desc, |
3c2cbd24 CG |
1582 | irq_trigger(idx), irq_polarity(idx)); |
1583 | } | |
1da177e4 LT |
1584 | } |
1585 | ||
3c2cbd24 CG |
1586 | if (notcon) |
1587 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1588 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1589 | } |
1590 | ||
1591 | /* | |
f7633ce5 | 1592 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1593 | */ |
f7633ce5 MR |
1594 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1595 | int vector) | |
1da177e4 LT |
1596 | { |
1597 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1598 | |
54168ed7 IM |
1599 | #ifdef CONFIG_INTR_REMAP |
1600 | if (intr_remapping_enabled) | |
1601 | return; | |
1602 | #endif | |
1603 | ||
36062448 | 1604 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1605 | |
1606 | /* | |
1607 | * We use logical delivery to get the timer IRQ | |
1608 | * to the first CPU. | |
1609 | */ | |
1610 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1611 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1612 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1613 | entry.delivery_mode = INT_DELIVERY_MODE; |
1614 | entry.polarity = 0; | |
1615 | entry.trigger = 0; | |
1616 | entry.vector = vector; | |
1617 | ||
1618 | /* | |
1619 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1620 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1621 | */ |
54168ed7 | 1622 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1623 | |
1624 | /* | |
1625 | * Add it to the IO-APIC irq-routing table: | |
1626 | */ | |
cf4c6a2f | 1627 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1628 | } |
1629 | ||
32f71aff MR |
1630 | |
1631 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1632 | { |
1633 | int apic, i; | |
1634 | union IO_APIC_reg_00 reg_00; | |
1635 | union IO_APIC_reg_01 reg_01; | |
1636 | union IO_APIC_reg_02 reg_02; | |
1637 | union IO_APIC_reg_03 reg_03; | |
1638 | unsigned long flags; | |
0f978f45 | 1639 | struct irq_cfg *cfg; |
0b8f1efa | 1640 | struct irq_desc *desc; |
8f09cd20 | 1641 | unsigned int irq; |
1da177e4 LT |
1642 | |
1643 | if (apic_verbosity == APIC_QUIET) | |
1644 | return; | |
1645 | ||
36062448 | 1646 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1647 | for (i = 0; i < nr_ioapics; i++) |
1648 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1649 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1650 | |
1651 | /* | |
1652 | * We are a bit conservative about what we expect. We have to | |
1653 | * know about every hardware change ASAP. | |
1654 | */ | |
1655 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1656 | ||
1657 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1658 | ||
1659 | spin_lock_irqsave(&ioapic_lock, flags); | |
1660 | reg_00.raw = io_apic_read(apic, 0); | |
1661 | reg_01.raw = io_apic_read(apic, 1); | |
1662 | if (reg_01.bits.version >= 0x10) | |
1663 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1664 | if (reg_01.bits.version >= 0x20) |
1665 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1666 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1667 | ||
54168ed7 | 1668 | printk("\n"); |
ec2cd0a2 | 1669 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1670 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1671 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1672 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1673 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1674 | |
54168ed7 | 1675 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1676 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1677 | |
1678 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1679 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1680 | |
1681 | /* | |
1682 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1683 | * but the value of reg_02 is read as the previous read register | |
1684 | * value, so ignore it if reg_02 == reg_01. | |
1685 | */ | |
1686 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1687 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1688 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1689 | } |
1690 | ||
1691 | /* | |
1692 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1693 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1694 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1695 | */ | |
1696 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1697 | reg_03.raw != reg_01.raw) { | |
1698 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1699 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1700 | } |
1701 | ||
1702 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1703 | ||
d83e94ac YL |
1704 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1705 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1706 | |
1707 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1708 | struct IO_APIC_route_entry entry; | |
1709 | ||
cf4c6a2f | 1710 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1711 | |
54168ed7 IM |
1712 | printk(KERN_DEBUG " %02x %03X ", |
1713 | i, | |
1714 | entry.dest | |
1715 | ); | |
1da177e4 LT |
1716 | |
1717 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1718 | entry.mask, | |
1719 | entry.trigger, | |
1720 | entry.irr, | |
1721 | entry.polarity, | |
1722 | entry.delivery_status, | |
1723 | entry.dest_mode, | |
1724 | entry.delivery_mode, | |
1725 | entry.vector | |
1726 | ); | |
1727 | } | |
1728 | } | |
1da177e4 | 1729 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1730 | for_each_irq_desc(irq, desc) { |
1731 | struct irq_pin_list *entry; | |
1732 | ||
1733 | if (!desc) | |
1734 | continue; | |
1735 | cfg = desc->chip_data; | |
1736 | entry = cfg->irq_2_pin; | |
0f978f45 | 1737 | if (!entry) |
1da177e4 | 1738 | continue; |
8f09cd20 | 1739 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1740 | for (;;) { |
1741 | printk("-> %d:%d", entry->apic, entry->pin); | |
1742 | if (!entry->next) | |
1743 | break; | |
0f978f45 | 1744 | entry = entry->next; |
1da177e4 LT |
1745 | } |
1746 | printk("\n"); | |
1747 | } | |
1748 | ||
1749 | printk(KERN_INFO ".................................... done.\n"); | |
1750 | ||
1751 | return; | |
1752 | } | |
1753 | ||
32f71aff | 1754 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1755 | { |
1756 | unsigned int v; | |
1757 | int i, j; | |
1758 | ||
1759 | if (apic_verbosity == APIC_QUIET) | |
1760 | return; | |
1761 | ||
1762 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1763 | for (i = 0; i < 8; i++) { | |
1764 | v = apic_read(base + i*0x10); | |
1765 | for (j = 0; j < 32; j++) { | |
1766 | if (v & (1<<j)) | |
1767 | printk("1"); | |
1768 | else | |
1769 | printk("0"); | |
1770 | } | |
1771 | printk("\n"); | |
1772 | } | |
1773 | } | |
1774 | ||
32f71aff | 1775 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1776 | { |
1777 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1778 | u64 icr; |
1da177e4 LT |
1779 | |
1780 | if (apic_verbosity == APIC_QUIET) | |
1781 | return; | |
1782 | ||
1783 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1784 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1785 | v = apic_read(APIC_ID); |
54168ed7 | 1786 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1787 | v = apic_read(APIC_LVR); |
1788 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1789 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1790 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1791 | |
1792 | v = apic_read(APIC_TASKPRI); | |
1793 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1794 | ||
54168ed7 | 1795 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1796 | if (!APIC_XAPIC(ver)) { |
1797 | v = apic_read(APIC_ARBPRI); | |
1798 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1799 | v & APIC_ARBPRI_MASK); | |
1800 | } | |
1da177e4 LT |
1801 | v = apic_read(APIC_PROCPRI); |
1802 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1803 | } | |
1804 | ||
a11b5abe YL |
1805 | /* |
1806 | * Remote read supported only in the 82489DX and local APIC for | |
1807 | * Pentium processors. | |
1808 | */ | |
1809 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1810 | v = apic_read(APIC_RRR); | |
1811 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1812 | } | |
1813 | ||
1da177e4 LT |
1814 | v = apic_read(APIC_LDR); |
1815 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1816 | if (!x2apic_enabled()) { |
1817 | v = apic_read(APIC_DFR); | |
1818 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1819 | } | |
1da177e4 LT |
1820 | v = apic_read(APIC_SPIV); |
1821 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1822 | ||
1823 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1824 | print_APIC_bitfield(APIC_ISR); | |
1825 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1826 | print_APIC_bitfield(APIC_TMR); | |
1827 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1828 | print_APIC_bitfield(APIC_IRR); | |
1829 | ||
54168ed7 IM |
1830 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1831 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1832 | apic_write(APIC_ESR, 0); |
54168ed7 | 1833 | |
1da177e4 LT |
1834 | v = apic_read(APIC_ESR); |
1835 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1836 | } | |
1837 | ||
7ab6af7a | 1838 | icr = apic_icr_read(); |
0c425cec IM |
1839 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1840 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1841 | |
1842 | v = apic_read(APIC_LVTT); | |
1843 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1844 | ||
1845 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1846 | v = apic_read(APIC_LVTPC); | |
1847 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1848 | } | |
1849 | v = apic_read(APIC_LVT0); | |
1850 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1851 | v = apic_read(APIC_LVT1); | |
1852 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1853 | ||
1854 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1855 | v = apic_read(APIC_LVTERR); | |
1856 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1857 | } | |
1858 | ||
1859 | v = apic_read(APIC_TMICT); | |
1860 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1861 | v = apic_read(APIC_TMCCT); | |
1862 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1863 | v = apic_read(APIC_TDCR); | |
1864 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1865 | printk("\n"); | |
1866 | } | |
1867 | ||
32f71aff | 1868 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1869 | { |
ffd5aae7 YL |
1870 | int cpu; |
1871 | ||
1872 | preempt_disable(); | |
1873 | for_each_online_cpu(cpu) | |
1874 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1875 | preempt_enable(); | |
1da177e4 LT |
1876 | } |
1877 | ||
32f71aff | 1878 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1879 | { |
1da177e4 LT |
1880 | unsigned int v; |
1881 | unsigned long flags; | |
1882 | ||
1883 | if (apic_verbosity == APIC_QUIET) | |
1884 | return; | |
1885 | ||
1886 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1887 | ||
1888 | spin_lock_irqsave(&i8259A_lock, flags); | |
1889 | ||
1890 | v = inb(0xa1) << 8 | inb(0x21); | |
1891 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1892 | ||
1893 | v = inb(0xa0) << 8 | inb(0x20); | |
1894 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1895 | ||
54168ed7 IM |
1896 | outb(0x0b,0xa0); |
1897 | outb(0x0b,0x20); | |
1da177e4 | 1898 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1899 | outb(0x0a,0xa0); |
1900 | outb(0x0a,0x20); | |
1da177e4 LT |
1901 | |
1902 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1903 | ||
1904 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1905 | ||
1906 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1907 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1908 | } | |
1909 | ||
32f71aff MR |
1910 | __apicdebuginit(int) print_all_ICs(void) |
1911 | { | |
1912 | print_PIC(); | |
1913 | print_all_local_APICs(); | |
1914 | print_IO_APIC(); | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
1919 | fs_initcall(print_all_ICs); | |
1920 | ||
1da177e4 | 1921 | |
efa2559f YL |
1922 | /* Where if anywhere is the i8259 connect in external int mode */ |
1923 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1924 | ||
54168ed7 | 1925 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1926 | { |
1927 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1928 | int i8259_apic, i8259_pin; |
54168ed7 | 1929 | int apic; |
1da177e4 LT |
1930 | unsigned long flags; |
1931 | ||
54168ed7 IM |
1932 | #ifdef CONFIG_X86_32 |
1933 | int i; | |
1da177e4 LT |
1934 | if (!pirqs_enabled) |
1935 | for (i = 0; i < MAX_PIRQS; i++) | |
1936 | pirq_entries[i] = -1; | |
54168ed7 | 1937 | #endif |
1da177e4 LT |
1938 | |
1939 | /* | |
1940 | * The number of IO-APIC IRQ registers (== #pins): | |
1941 | */ | |
fcfd636a | 1942 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1943 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1944 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1945 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1946 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1947 | } | |
54168ed7 | 1948 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1949 | int pin; |
1950 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1951 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1952 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1953 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1954 | |
fcfd636a EB |
1955 | /* If the interrupt line is enabled and in ExtInt mode |
1956 | * I have found the pin where the i8259 is connected. | |
1957 | */ | |
1958 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1959 | ioapic_i8259.apic = apic; | |
1960 | ioapic_i8259.pin = pin; | |
1961 | goto found_i8259; | |
1962 | } | |
1963 | } | |
1964 | } | |
1965 | found_i8259: | |
1966 | /* Look to see what if the MP table has reported the ExtINT */ | |
1967 | /* If we could not find the appropriate pin by looking at the ioapic | |
1968 | * the i8259 probably is not connected the ioapic but give the | |
1969 | * mptable a chance anyway. | |
1970 | */ | |
1971 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1972 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1973 | /* Trust the MP table if nothing is setup in the hardware */ | |
1974 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1975 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1976 | ioapic_i8259.pin = i8259_pin; | |
1977 | ioapic_i8259.apic = i8259_apic; | |
1978 | } | |
1979 | /* Complain if the MP table and the hardware disagree */ | |
1980 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1981 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1982 | { | |
1983 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1984 | } |
1985 | ||
1986 | /* | |
1987 | * Do not trust the IO-APIC being empty at bootup | |
1988 | */ | |
1989 | clear_IO_APIC(); | |
1990 | } | |
1991 | ||
1992 | /* | |
1993 | * Not an __init, needed by the reboot code | |
1994 | */ | |
1995 | void disable_IO_APIC(void) | |
1996 | { | |
1997 | /* | |
1998 | * Clear the IO-APIC before rebooting: | |
1999 | */ | |
2000 | clear_IO_APIC(); | |
2001 | ||
650927ef | 2002 | /* |
0b968d23 | 2003 | * If the i8259 is routed through an IOAPIC |
650927ef | 2004 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2005 | * so legacy interrupts can be delivered. |
650927ef | 2006 | */ |
fcfd636a | 2007 | if (ioapic_i8259.pin != -1) { |
650927ef | 2008 | struct IO_APIC_route_entry entry; |
650927ef EB |
2009 | |
2010 | memset(&entry, 0, sizeof(entry)); | |
2011 | entry.mask = 0; /* Enabled */ | |
2012 | entry.trigger = 0; /* Edge */ | |
2013 | entry.irr = 0; | |
2014 | entry.polarity = 0; /* High */ | |
2015 | entry.delivery_status = 0; | |
2016 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2017 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2018 | entry.vector = 0; |
54168ed7 | 2019 | entry.dest = read_apic_id(); |
650927ef EB |
2020 | |
2021 | /* | |
2022 | * Add it to the IO-APIC irq-routing table: | |
2023 | */ | |
cf4c6a2f | 2024 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2025 | } |
54168ed7 | 2026 | |
fcfd636a | 2027 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
2028 | } |
2029 | ||
54168ed7 | 2030 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2031 | /* |
2032 | * function to set the IO-APIC physical IDs based on the | |
2033 | * values stored in the MPC table. | |
2034 | * | |
2035 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2036 | */ | |
2037 | ||
1da177e4 LT |
2038 | static void __init setup_ioapic_ids_from_mpc(void) |
2039 | { | |
2040 | union IO_APIC_reg_00 reg_00; | |
2041 | physid_mask_t phys_id_present_map; | |
2042 | int apic; | |
2043 | int i; | |
2044 | unsigned char old_id; | |
2045 | unsigned long flags; | |
2046 | ||
a4dbc34d | 2047 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2048 | return; |
d49c4288 | 2049 | |
ca05fea6 NP |
2050 | /* |
2051 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2052 | * no meaning without the serial APIC bus. | |
2053 | */ | |
7c5c1e42 SL |
2054 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2055 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2056 | return; |
1da177e4 LT |
2057 | /* |
2058 | * This is broken; anything with a real cpu count has to | |
2059 | * circumvent this idiocy regardless. | |
2060 | */ | |
2061 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2062 | ||
2063 | /* | |
2064 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2065 | */ | |
2066 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2067 | ||
2068 | /* Read the register 0 value */ | |
2069 | spin_lock_irqsave(&ioapic_lock, flags); | |
2070 | reg_00.raw = io_apic_read(apic, 0); | |
2071 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 2072 | |
ec2cd0a2 | 2073 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2074 | |
ec2cd0a2 | 2075 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 2076 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 2077 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2078 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2079 | reg_00.bits.ID); | |
ec2cd0a2 | 2080 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
2081 | } |
2082 | ||
1da177e4 LT |
2083 | /* |
2084 | * Sanity check, is the ID really free? Every APIC in a | |
2085 | * system must have a unique ID or we get lots of nice | |
2086 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2087 | */ | |
2088 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 2089 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 2090 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 2091 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2092 | for (i = 0; i < get_physical_broadcast(); i++) |
2093 | if (!physid_isset(i, phys_id_present_map)) | |
2094 | break; | |
2095 | if (i >= get_physical_broadcast()) | |
2096 | panic("Max APIC ID exceeded!\n"); | |
2097 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2098 | i); | |
2099 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 2100 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
2101 | } else { |
2102 | physid_mask_t tmp; | |
ec2cd0a2 | 2103 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2104 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2105 | "phys_id_present_map\n", | |
ec2cd0a2 | 2106 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2107 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2108 | } | |
2109 | ||
2110 | ||
2111 | /* | |
2112 | * We need to adjust the IRQ routing table | |
2113 | * if the ID changed. | |
2114 | */ | |
ec2cd0a2 | 2115 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 2116 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
2117 | if (mp_irqs[i].mp_dstapic == old_id) |
2118 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 2119 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
2120 | |
2121 | /* | |
2122 | * Read the right value from the MPC table and | |
2123 | * write it into the ID register. | |
36062448 | 2124 | */ |
1da177e4 LT |
2125 | apic_printk(APIC_VERBOSE, KERN_INFO |
2126 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 2127 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 2128 | |
ec2cd0a2 | 2129 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2130 | spin_lock_irqsave(&ioapic_lock, flags); |
a2d332fa YL |
2131 | io_apic_write(apic, 0, reg_00.raw); |
2132 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1da177e4 LT |
2133 | |
2134 | /* | |
2135 | * Sanity check | |
2136 | */ | |
2137 | spin_lock_irqsave(&ioapic_lock, flags); | |
2138 | reg_00.raw = io_apic_read(apic, 0); | |
2139 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 2140 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
2141 | printk("could not set ID!\n"); |
2142 | else | |
2143 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2144 | } | |
2145 | } | |
54168ed7 | 2146 | #endif |
1da177e4 | 2147 | |
7ce0bcfd | 2148 | int no_timer_check __initdata; |
8542b200 ZA |
2149 | |
2150 | static int __init notimercheck(char *s) | |
2151 | { | |
2152 | no_timer_check = 1; | |
2153 | return 1; | |
2154 | } | |
2155 | __setup("no_timer_check", notimercheck); | |
2156 | ||
1da177e4 LT |
2157 | /* |
2158 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2159 | * about the timer IRQ. We do the following to work around the situation: | |
2160 | * | |
2161 | * - timer IRQ defaults to IO-APIC IRQ | |
2162 | * - if this function detects that timer IRQs are defunct, then we fall | |
2163 | * back to ISA timer IRQs | |
2164 | */ | |
f0a7a5c9 | 2165 | static int __init timer_irq_works(void) |
1da177e4 LT |
2166 | { |
2167 | unsigned long t1 = jiffies; | |
4aae0702 | 2168 | unsigned long flags; |
1da177e4 | 2169 | |
8542b200 ZA |
2170 | if (no_timer_check) |
2171 | return 1; | |
2172 | ||
4aae0702 | 2173 | local_save_flags(flags); |
1da177e4 LT |
2174 | local_irq_enable(); |
2175 | /* Let ten ticks pass... */ | |
2176 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2177 | local_irq_restore(flags); |
1da177e4 LT |
2178 | |
2179 | /* | |
2180 | * Expect a few ticks at least, to be sure some possible | |
2181 | * glue logic does not lock up after one or two first | |
2182 | * ticks in a non-ExtINT mode. Also the local APIC | |
2183 | * might have cached one ExtINT interrupt. Finally, at | |
2184 | * least one tick may be lost due to delays. | |
2185 | */ | |
54168ed7 IM |
2186 | |
2187 | /* jiffies wrap? */ | |
1d16b53e | 2188 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2189 | return 1; |
1da177e4 LT |
2190 | return 0; |
2191 | } | |
2192 | ||
2193 | /* | |
2194 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2195 | * number of pending IRQ events unhandled. These cases are very rare, | |
2196 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2197 | * better to do it this way as thus we do not have to be aware of | |
2198 | * 'pending' interrupts in the IRQ path, except at this point. | |
2199 | */ | |
2200 | /* | |
2201 | * Edge triggered needs to resend any interrupt | |
2202 | * that was delayed but this is now handled in the device | |
2203 | * independent code. | |
2204 | */ | |
2205 | ||
2206 | /* | |
2207 | * Starting up a edge-triggered IO-APIC interrupt is | |
2208 | * nasty - we need to make sure that we get the edge. | |
2209 | * If it is already asserted for some reason, we need | |
2210 | * return 1 to indicate that is was pending. | |
2211 | * | |
2212 | * This is not complete - we should be able to fake | |
2213 | * an edge even if it isn't on the 8259A... | |
2214 | */ | |
54168ed7 | 2215 | |
f5b9ed7a | 2216 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2217 | { |
2218 | int was_pending = 0; | |
2219 | unsigned long flags; | |
0b8f1efa | 2220 | struct irq_cfg *cfg; |
1da177e4 LT |
2221 | |
2222 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2223 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2224 | disable_8259A_irq(irq); |
2225 | if (i8259A_irq_pending(irq)) | |
2226 | was_pending = 1; | |
2227 | } | |
0b8f1efa | 2228 | cfg = irq_cfg(irq); |
3145e941 | 2229 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2230 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2231 | ||
2232 | return was_pending; | |
2233 | } | |
2234 | ||
54168ed7 | 2235 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2236 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2237 | { |
54168ed7 IM |
2238 | |
2239 | struct irq_cfg *cfg = irq_cfg(irq); | |
2240 | unsigned long flags; | |
2241 | ||
2242 | spin_lock_irqsave(&vector_lock, flags); | |
2243 | send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector); | |
2244 | spin_unlock_irqrestore(&vector_lock, flags); | |
c0ad90a3 IM |
2245 | |
2246 | return 1; | |
2247 | } | |
54168ed7 IM |
2248 | #else |
2249 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2250 | { |
d6c88a50 | 2251 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2252 | |
d6c88a50 | 2253 | return 1; |
54168ed7 IM |
2254 | } |
2255 | #endif | |
497c9a19 | 2256 | |
54168ed7 IM |
2257 | /* |
2258 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2259 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2260 | * handled with the level-triggered descriptor, but that one has slightly | |
2261 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2262 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2263 | * races. | |
2264 | */ | |
497c9a19 | 2265 | |
54168ed7 | 2266 | #ifdef CONFIG_SMP |
497c9a19 | 2267 | |
54168ed7 IM |
2268 | #ifdef CONFIG_INTR_REMAP |
2269 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2270 | |
54168ed7 | 2271 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2272 | |
54168ed7 IM |
2273 | /* |
2274 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2275 | * | |
2276 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2277 | * and cpu destination) of IRTE and flush the hardware cache. | |
2278 | * | |
2279 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2280 | * vector information, along with modifying IRTE with vector and destination. | |
2281 | * So irq migration for level triggered is little bit more complex compared to | |
2282 | * edge triggered migration. But the good news is, we use the same algorithm | |
2283 | * for level triggered migration as we have today, only difference being, | |
2284 | * we now initiate the irq migration from process context instead of the | |
2285 | * interrupt context. | |
2286 | * | |
2287 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2288 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2289 | * as simple as edge triggered migration and we can do the irq migration | |
2290 | * with a simple atomic update to IO-APIC RTE. | |
2291 | */ | |
3145e941 | 2292 | static void migrate_ioapic_irq_desc(struct irq_desc *desc, cpumask_t mask) |
497c9a19 | 2293 | { |
54168ed7 | 2294 | struct irq_cfg *cfg; |
54168ed7 IM |
2295 | cpumask_t tmp, cleanup_mask; |
2296 | struct irte irte; | |
2297 | int modify_ioapic_rte; | |
2298 | unsigned int dest; | |
2299 | unsigned long flags; | |
3145e941 | 2300 | unsigned int irq; |
497c9a19 | 2301 | |
54168ed7 IM |
2302 | cpus_and(tmp, mask, cpu_online_map); |
2303 | if (cpus_empty(tmp)) | |
497c9a19 YL |
2304 | return; |
2305 | ||
3145e941 | 2306 | irq = desc->irq; |
54168ed7 IM |
2307 | if (get_irte(irq, &irte)) |
2308 | return; | |
497c9a19 | 2309 | |
3145e941 YL |
2310 | cfg = desc->chip_data; |
2311 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
2312 | return; |
2313 | ||
3145e941 YL |
2314 | set_extra_move_desc(desc, mask); |
2315 | ||
54168ed7 IM |
2316 | cpus_and(tmp, cfg->domain, mask); |
2317 | dest = cpu_mask_to_apicid(tmp); | |
2318 | ||
54168ed7 IM |
2319 | modify_ioapic_rte = desc->status & IRQ_LEVEL; |
2320 | if (modify_ioapic_rte) { | |
2321 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 2322 | __target_IO_APIC_irq(irq, dest, cfg); |
54168ed7 IM |
2323 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2324 | } | |
2325 | ||
2326 | irte.vector = cfg->vector; | |
2327 | irte.dest_id = IRTE_DEST(dest); | |
2328 | ||
2329 | /* | |
2330 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2331 | */ | |
2332 | modify_irte(irq, &irte); | |
2333 | ||
2334 | if (cfg->move_in_progress) { | |
2335 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2336 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2337 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2338 | cfg->move_in_progress = 0; | |
2339 | } | |
2340 | ||
2341 | desc->affinity = mask; | |
2342 | } | |
2343 | ||
3145e941 | 2344 | static int migrate_irq_remapped_level_desc(struct irq_desc *desc) |
54168ed7 IM |
2345 | { |
2346 | int ret = -1; | |
3145e941 | 2347 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 2348 | |
3145e941 | 2349 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2350 | |
3145e941 | 2351 | if (io_apic_level_ack_pending(cfg)) { |
54168ed7 | 2352 | /* |
d6c88a50 | 2353 | * Interrupt in progress. Migrating irq now will change the |
54168ed7 IM |
2354 | * vector information in the IO-APIC RTE and that will confuse |
2355 | * the EOI broadcast performed by cpu. | |
2356 | * So, delay the irq migration to the next instance. | |
2357 | */ | |
2358 | schedule_delayed_work(&ir_migration_work, 1); | |
2359 | goto unmask; | |
2360 | } | |
2361 | ||
2362 | /* everthing is clear. we have right of way */ | |
3145e941 | 2363 | migrate_ioapic_irq_desc(desc, desc->pending_mask); |
54168ed7 IM |
2364 | |
2365 | ret = 0; | |
2366 | desc->status &= ~IRQ_MOVE_PENDING; | |
2367 | cpus_clear(desc->pending_mask); | |
2368 | ||
2369 | unmask: | |
3145e941 YL |
2370 | unmask_IO_APIC_irq_desc(desc); |
2371 | ||
54168ed7 IM |
2372 | return ret; |
2373 | } | |
2374 | ||
2375 | static void ir_irq_migration(struct work_struct *work) | |
2376 | { | |
2377 | unsigned int irq; | |
2378 | struct irq_desc *desc; | |
2379 | ||
2380 | for_each_irq_desc(irq, desc) { | |
0b8f1efa YL |
2381 | if (!desc) |
2382 | continue; | |
2383 | ||
54168ed7 IM |
2384 | if (desc->status & IRQ_MOVE_PENDING) { |
2385 | unsigned long flags; | |
2386 | ||
2387 | spin_lock_irqsave(&desc->lock, flags); | |
2388 | if (!desc->chip->set_affinity || | |
2389 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2390 | desc->status &= ~IRQ_MOVE_PENDING; | |
2391 | spin_unlock_irqrestore(&desc->lock, flags); | |
2392 | continue; | |
2393 | } | |
2394 | ||
2395 | desc->chip->set_affinity(irq, desc->pending_mask); | |
2396 | spin_unlock_irqrestore(&desc->lock, flags); | |
2397 | } | |
2398 | } | |
2399 | } | |
2400 | ||
2401 | /* | |
2402 | * Migrates the IRQ destination in the process context. | |
2403 | */ | |
3145e941 | 2404 | static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, cpumask_t mask) |
54168ed7 | 2405 | { |
54168ed7 IM |
2406 | if (desc->status & IRQ_LEVEL) { |
2407 | desc->status |= IRQ_MOVE_PENDING; | |
2408 | desc->pending_mask = mask; | |
3145e941 | 2409 | migrate_irq_remapped_level_desc(desc); |
54168ed7 IM |
2410 | return; |
2411 | } | |
2412 | ||
3145e941 YL |
2413 | migrate_ioapic_irq_desc(desc, mask); |
2414 | } | |
2415 | static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
2416 | { | |
2417 | struct irq_desc *desc = irq_to_desc(irq); | |
2418 | ||
2419 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
54168ed7 IM |
2420 | } |
2421 | #endif | |
2422 | ||
2423 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2424 | { | |
2425 | unsigned vector, me; | |
2426 | ack_APIC_irq(); | |
2427 | #ifdef CONFIG_X86_64 | |
2428 | exit_idle(); | |
2429 | #endif | |
2430 | irq_enter(); | |
2431 | ||
2432 | me = smp_processor_id(); | |
2433 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2434 | unsigned int irq; | |
2435 | struct irq_desc *desc; | |
2436 | struct irq_cfg *cfg; | |
2437 | irq = __get_cpu_var(vector_irq)[vector]; | |
2438 | ||
0b8f1efa YL |
2439 | if (irq == -1) |
2440 | continue; | |
2441 | ||
54168ed7 IM |
2442 | desc = irq_to_desc(irq); |
2443 | if (!desc) | |
2444 | continue; | |
2445 | ||
2446 | cfg = irq_cfg(irq); | |
2447 | spin_lock(&desc->lock); | |
2448 | if (!cfg->move_cleanup_count) | |
2449 | goto unlock; | |
2450 | ||
2451 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
2452 | goto unlock; | |
2453 | ||
2454 | __get_cpu_var(vector_irq)[vector] = -1; | |
2455 | cfg->move_cleanup_count--; | |
2456 | unlock: | |
2457 | spin_unlock(&desc->lock); | |
2458 | } | |
2459 | ||
2460 | irq_exit(); | |
2461 | } | |
2462 | ||
3145e941 | 2463 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2464 | { |
3145e941 YL |
2465 | struct irq_desc *desc = *descp; |
2466 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2467 | unsigned vector, me; |
2468 | ||
48a1b10a YL |
2469 | if (likely(!cfg->move_in_progress)) { |
2470 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | |
2471 | if (likely(!cfg->move_desc_pending)) | |
2472 | return; | |
2473 | ||
2474 | /* domain is not change, but affinity is changed */ | |
2475 | me = smp_processor_id(); | |
2476 | if (cpu_isset(me, desc->affinity)) { | |
2477 | *descp = desc = move_irq_desc(desc, me); | |
2478 | /* get the new one */ | |
2479 | cfg = desc->chip_data; | |
2480 | cfg->move_desc_pending = 0; | |
2481 | } | |
2482 | #endif | |
54168ed7 | 2483 | return; |
48a1b10a | 2484 | } |
54168ed7 IM |
2485 | |
2486 | vector = ~get_irq_regs()->orig_ax; | |
2487 | me = smp_processor_id(); | |
2488 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { | |
2489 | cpumask_t cleanup_mask; | |
2490 | ||
48a1b10a YL |
2491 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
2492 | *descp = desc = move_irq_desc(desc, me); | |
2493 | /* get the new one */ | |
2494 | cfg = desc->chip_data; | |
2495 | #endif | |
2496 | ||
54168ed7 IM |
2497 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); |
2498 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2499 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
497c9a19 YL |
2500 | cfg->move_in_progress = 0; |
2501 | } | |
2502 | } | |
2503 | #else | |
3145e941 | 2504 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2505 | #endif |
3145e941 | 2506 | |
54168ed7 IM |
2507 | #ifdef CONFIG_INTR_REMAP |
2508 | static void ack_x2apic_level(unsigned int irq) | |
2509 | { | |
2510 | ack_x2APIC_irq(); | |
2511 | } | |
2512 | ||
2513 | static void ack_x2apic_edge(unsigned int irq) | |
2514 | { | |
2515 | ack_x2APIC_irq(); | |
2516 | } | |
3145e941 | 2517 | |
54168ed7 | 2518 | #endif |
497c9a19 | 2519 | |
1d025192 YL |
2520 | static void ack_apic_edge(unsigned int irq) |
2521 | { | |
3145e941 YL |
2522 | struct irq_desc *desc = irq_to_desc(irq); |
2523 | ||
2524 | irq_complete_move(&desc); | |
1d025192 YL |
2525 | move_native_irq(irq); |
2526 | ack_APIC_irq(); | |
2527 | } | |
2528 | ||
3eb2cce8 | 2529 | atomic_t irq_mis_count; |
3eb2cce8 | 2530 | |
047c8fdb YL |
2531 | static void ack_apic_level(unsigned int irq) |
2532 | { | |
3145e941 YL |
2533 | struct irq_desc *desc = irq_to_desc(irq); |
2534 | ||
3eb2cce8 YL |
2535 | #ifdef CONFIG_X86_32 |
2536 | unsigned long v; | |
2537 | int i; | |
2538 | #endif | |
3145e941 | 2539 | struct irq_cfg *cfg; |
54168ed7 | 2540 | int do_unmask_irq = 0; |
047c8fdb | 2541 | |
3145e941 | 2542 | irq_complete_move(&desc); |
047c8fdb | 2543 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2544 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2545 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2546 | do_unmask_irq = 1; |
3145e941 | 2547 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2548 | } |
047c8fdb YL |
2549 | #endif |
2550 | ||
3eb2cce8 YL |
2551 | #ifdef CONFIG_X86_32 |
2552 | /* | |
2553 | * It appears there is an erratum which affects at least version 0x11 | |
2554 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2555 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2556 | * erroneously delivered as edge-triggered one but the respective IRR | |
2557 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2558 | * message but it will never arrive and further interrupts are blocked | |
2559 | * from the source. The exact reason is so far unknown, but the | |
2560 | * phenomenon was observed when two consecutive interrupt requests | |
2561 | * from a given source get delivered to the same CPU and the source is | |
2562 | * temporarily disabled in between. | |
2563 | * | |
2564 | * A workaround is to simulate an EOI message manually. We achieve it | |
2565 | * by setting the trigger mode to edge and then to level when the edge | |
2566 | * trigger mode gets detected in the TMR of a local APIC for a | |
2567 | * level-triggered interrupt. We mask the source for the time of the | |
2568 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2569 | * The idea is from Manfred Spraul. --macro | |
2570 | */ | |
3145e941 YL |
2571 | cfg = desc->chip_data; |
2572 | i = cfg->vector; | |
3eb2cce8 YL |
2573 | |
2574 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2575 | #endif | |
2576 | ||
54168ed7 IM |
2577 | /* |
2578 | * We must acknowledge the irq before we move it or the acknowledge will | |
2579 | * not propagate properly. | |
2580 | */ | |
2581 | ack_APIC_irq(); | |
2582 | ||
2583 | /* Now we can move and renable the irq */ | |
2584 | if (unlikely(do_unmask_irq)) { | |
2585 | /* Only migrate the irq if the ack has been received. | |
2586 | * | |
2587 | * On rare occasions the broadcast level triggered ack gets | |
2588 | * delayed going to ioapics, and if we reprogram the | |
2589 | * vector while Remote IRR is still set the irq will never | |
2590 | * fire again. | |
2591 | * | |
2592 | * To prevent this scenario we read the Remote IRR bit | |
2593 | * of the ioapic. This has two effects. | |
2594 | * - On any sane system the read of the ioapic will | |
2595 | * flush writes (and acks) going to the ioapic from | |
2596 | * this cpu. | |
2597 | * - We get to see if the ACK has actually been delivered. | |
2598 | * | |
2599 | * Based on failed experiments of reprogramming the | |
2600 | * ioapic entry from outside of irq context starting | |
2601 | * with masking the ioapic entry and then polling until | |
2602 | * Remote IRR was clear before reprogramming the | |
2603 | * ioapic I don't trust the Remote IRR bit to be | |
2604 | * completey accurate. | |
2605 | * | |
2606 | * However there appears to be no other way to plug | |
2607 | * this race, so if the Remote IRR bit is not | |
2608 | * accurate and is causing problems then it is a hardware bug | |
2609 | * and you can go talk to the chipset vendor about it. | |
2610 | */ | |
3145e941 YL |
2611 | cfg = desc->chip_data; |
2612 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2613 | move_masked_irq(irq); |
3145e941 | 2614 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2615 | } |
1d025192 | 2616 | |
3eb2cce8 | 2617 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2618 | if (!(v & (1 << (i & 0x1f)))) { |
2619 | atomic_inc(&irq_mis_count); | |
2620 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2621 | __mask_and_edge_IO_APIC_irq(cfg); |
2622 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2623 | spin_unlock(&ioapic_lock); |
2624 | } | |
047c8fdb | 2625 | #endif |
3eb2cce8 | 2626 | } |
1d025192 | 2627 | |
f5b9ed7a | 2628 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2629 | .name = "IO-APIC", |
2630 | .startup = startup_ioapic_irq, | |
2631 | .mask = mask_IO_APIC_irq, | |
2632 | .unmask = unmask_IO_APIC_irq, | |
2633 | .ack = ack_apic_edge, | |
2634 | .eoi = ack_apic_level, | |
54d5d424 | 2635 | #ifdef CONFIG_SMP |
d6c88a50 | 2636 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2637 | #endif |
ace80ab7 | 2638 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2639 | }; |
2640 | ||
54168ed7 IM |
2641 | #ifdef CONFIG_INTR_REMAP |
2642 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
d6c88a50 TG |
2643 | .name = "IR-IO-APIC", |
2644 | .startup = startup_ioapic_irq, | |
2645 | .mask = mask_IO_APIC_irq, | |
2646 | .unmask = unmask_IO_APIC_irq, | |
2647 | .ack = ack_x2apic_edge, | |
2648 | .eoi = ack_x2apic_level, | |
54168ed7 | 2649 | #ifdef CONFIG_SMP |
d6c88a50 | 2650 | .set_affinity = set_ir_ioapic_affinity_irq, |
54168ed7 IM |
2651 | #endif |
2652 | .retrigger = ioapic_retrigger_irq, | |
2653 | }; | |
2654 | #endif | |
1da177e4 LT |
2655 | |
2656 | static inline void init_IO_APIC_traps(void) | |
2657 | { | |
2658 | int irq; | |
08678b08 | 2659 | struct irq_desc *desc; |
da51a821 | 2660 | struct irq_cfg *cfg; |
1da177e4 LT |
2661 | |
2662 | /* | |
2663 | * NOTE! The local APIC isn't very good at handling | |
2664 | * multiple interrupts at the same interrupt level. | |
2665 | * As the interrupt level is determined by taking the | |
2666 | * vector number and shifting that right by 4, we | |
2667 | * want to spread these out a bit so that they don't | |
2668 | * all fall in the same interrupt level. | |
2669 | * | |
2670 | * Also, we've got to be careful not to trash gate | |
2671 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2672 | */ | |
0b8f1efa YL |
2673 | for_each_irq_desc(irq, desc) { |
2674 | if (!desc) | |
2675 | continue; | |
2676 | ||
2677 | cfg = desc->chip_data; | |
2678 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2679 | /* |
2680 | * Hmm.. We don't have an entry for this, | |
2681 | * so default to an old-fashioned 8259 | |
2682 | * interrupt if we can.. | |
2683 | */ | |
99d093d1 | 2684 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2685 | make_8259A_irq(irq); |
0b8f1efa | 2686 | else |
1da177e4 | 2687 | /* Strange. Oh, well.. */ |
08678b08 | 2688 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2689 | } |
2690 | } | |
2691 | } | |
2692 | ||
f5b9ed7a IM |
2693 | /* |
2694 | * The local APIC irq-chip implementation: | |
2695 | */ | |
1da177e4 | 2696 | |
36062448 | 2697 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2698 | { |
2699 | unsigned long v; | |
2700 | ||
2701 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2702 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2703 | } |
2704 | ||
36062448 | 2705 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2706 | { |
f5b9ed7a | 2707 | unsigned long v; |
1da177e4 | 2708 | |
f5b9ed7a | 2709 | v = apic_read(APIC_LVT0); |
593f4a78 | 2710 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2711 | } |
1da177e4 | 2712 | |
3145e941 | 2713 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2714 | { |
2715 | ack_APIC_irq(); | |
2716 | } | |
2717 | ||
f5b9ed7a | 2718 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2719 | .name = "local-APIC", |
f5b9ed7a IM |
2720 | .mask = mask_lapic_irq, |
2721 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2722 | .ack = ack_lapic_irq, |
1da177e4 LT |
2723 | }; |
2724 | ||
3145e941 | 2725 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2726 | { |
08678b08 | 2727 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2728 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2729 | "edge"); | |
c88ac1df MR |
2730 | } |
2731 | ||
e9427101 | 2732 | static void __init setup_nmi(void) |
1da177e4 LT |
2733 | { |
2734 | /* | |
36062448 | 2735 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2736 | * We put the 8259A master into AEOI mode and |
2737 | * unmask on all local APICs LVT0 as NMI. | |
2738 | * | |
2739 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2740 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2741 | * the NMI handler or the timer interrupt. | |
36062448 | 2742 | */ |
1da177e4 LT |
2743 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2744 | ||
e9427101 | 2745 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2746 | |
2747 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2748 | } | |
2749 | ||
2750 | /* | |
2751 | * This looks a bit hackish but it's about the only one way of sending | |
2752 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2753 | * not support the ExtINT mode, unfortunately. We need to send these | |
2754 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2755 | * 8259A interrupt line asserted until INTA. --macro | |
2756 | */ | |
28acf285 | 2757 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2758 | { |
fcfd636a | 2759 | int apic, pin, i; |
1da177e4 LT |
2760 | struct IO_APIC_route_entry entry0, entry1; |
2761 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2762 | |
fcfd636a | 2763 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2764 | if (pin == -1) { |
2765 | WARN_ON_ONCE(1); | |
2766 | return; | |
2767 | } | |
fcfd636a | 2768 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2769 | if (apic == -1) { |
2770 | WARN_ON_ONCE(1); | |
1da177e4 | 2771 | return; |
956fb531 | 2772 | } |
1da177e4 | 2773 | |
cf4c6a2f | 2774 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2775 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2776 | |
2777 | memset(&entry1, 0, sizeof(entry1)); | |
2778 | ||
2779 | entry1.dest_mode = 0; /* physical delivery */ | |
2780 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2781 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2782 | entry1.delivery_mode = dest_ExtINT; |
2783 | entry1.polarity = entry0.polarity; | |
2784 | entry1.trigger = 0; | |
2785 | entry1.vector = 0; | |
2786 | ||
cf4c6a2f | 2787 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2788 | |
2789 | save_control = CMOS_READ(RTC_CONTROL); | |
2790 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2791 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2792 | RTC_FREQ_SELECT); | |
2793 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2794 | ||
2795 | i = 100; | |
2796 | while (i-- > 0) { | |
2797 | mdelay(10); | |
2798 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2799 | i -= 10; | |
2800 | } | |
2801 | ||
2802 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2803 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2804 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2805 | |
cf4c6a2f | 2806 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2807 | } |
2808 | ||
efa2559f | 2809 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2810 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2811 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2812 | { |
2813 | disable_timer_pin_1 = 1; | |
2814 | return 0; | |
2815 | } | |
54168ed7 | 2816 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2817 | |
2818 | int timer_through_8259 __initdata; | |
2819 | ||
1da177e4 LT |
2820 | /* |
2821 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2822 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2823 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2824 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2825 | * |
2826 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2827 | */ |
8542b200 | 2828 | static inline void __init check_timer(void) |
1da177e4 | 2829 | { |
3145e941 YL |
2830 | struct irq_desc *desc = irq_to_desc(0); |
2831 | struct irq_cfg *cfg = desc->chip_data; | |
2832 | int cpu = boot_cpu_id; | |
fcfd636a | 2833 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2834 | unsigned long flags; |
047c8fdb YL |
2835 | unsigned int ver; |
2836 | int no_pin1 = 0; | |
4aae0702 IM |
2837 | |
2838 | local_irq_save(flags); | |
d4d25dec | 2839 | |
d6c88a50 TG |
2840 | ver = apic_read(APIC_LVR); |
2841 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2842 | |
1da177e4 LT |
2843 | /* |
2844 | * get/set the timer IRQ vector: | |
2845 | */ | |
2846 | disable_8259A_irq(0); | |
3145e941 | 2847 | assign_irq_vector(0, cfg, TARGET_CPUS); |
1da177e4 LT |
2848 | |
2849 | /* | |
d11d5794 MR |
2850 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2851 | * wire has to be disabled in the local APIC. Also | |
2852 | * timer interrupts need to be acknowledged manually in | |
2853 | * the 8259A for the i82489DX when using the NMI | |
2854 | * watchdog as that APIC treats NMIs as level-triggered. | |
2855 | * The AEOI mode will finish them in the 8259A | |
2856 | * automatically. | |
1da177e4 | 2857 | */ |
593f4a78 | 2858 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2859 | init_8259A(1); |
54168ed7 | 2860 | #ifdef CONFIG_X86_32 |
d11d5794 | 2861 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2862 | #endif |
1da177e4 | 2863 | |
fcfd636a EB |
2864 | pin1 = find_isa_irq_pin(0, mp_INT); |
2865 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2866 | pin2 = ioapic_i8259.pin; | |
2867 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2868 | |
49a66a0b MR |
2869 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2870 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2871 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2872 | |
691874fa MR |
2873 | /* |
2874 | * Some BIOS writers are clueless and report the ExtINTA | |
2875 | * I/O APIC input from the cascaded 8259A as the timer | |
2876 | * interrupt input. So just in case, if only one pin | |
2877 | * was found above, try it both directly and through the | |
2878 | * 8259A. | |
2879 | */ | |
2880 | if (pin1 == -1) { | |
54168ed7 IM |
2881 | #ifdef CONFIG_INTR_REMAP |
2882 | if (intr_remapping_enabled) | |
2883 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2884 | #endif | |
691874fa MR |
2885 | pin1 = pin2; |
2886 | apic1 = apic2; | |
2887 | no_pin1 = 1; | |
2888 | } else if (pin2 == -1) { | |
2889 | pin2 = pin1; | |
2890 | apic2 = apic1; | |
2891 | } | |
2892 | ||
1da177e4 LT |
2893 | if (pin1 != -1) { |
2894 | /* | |
2895 | * Ok, does IRQ0 through the IOAPIC work? | |
2896 | */ | |
691874fa | 2897 | if (no_pin1) { |
3145e941 | 2898 | add_pin_to_irq_cpu(cfg, cpu, apic1, pin1); |
497c9a19 | 2899 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2900 | } |
3145e941 | 2901 | unmask_IO_APIC_irq_desc(desc); |
1da177e4 LT |
2902 | if (timer_irq_works()) { |
2903 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2904 | setup_nmi(); |
2905 | enable_8259A_irq(0); | |
1da177e4 | 2906 | } |
66759a01 CE |
2907 | if (disable_timer_pin_1 > 0) |
2908 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2909 | goto out; |
1da177e4 | 2910 | } |
54168ed7 IM |
2911 | #ifdef CONFIG_INTR_REMAP |
2912 | if (intr_remapping_enabled) | |
2913 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2914 | #endif | |
fcfd636a | 2915 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2916 | if (!no_pin1) |
49a66a0b MR |
2917 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2918 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2919 | |
49a66a0b MR |
2920 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2921 | "(IRQ0) through the 8259A ...\n"); | |
2922 | apic_printk(APIC_QUIET, KERN_INFO | |
2923 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2924 | /* |
2925 | * legacy devices should be connected to IO APIC #0 | |
2926 | */ | |
3145e941 | 2927 | replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2); |
497c9a19 | 2928 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
3145e941 | 2929 | unmask_IO_APIC_irq_desc(desc); |
ecd29476 | 2930 | enable_8259A_irq(0); |
1da177e4 | 2931 | if (timer_irq_works()) { |
49a66a0b | 2932 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2933 | timer_through_8259 = 1; |
1da177e4 | 2934 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2935 | disable_8259A_irq(0); |
1da177e4 | 2936 | setup_nmi(); |
60134ebe | 2937 | enable_8259A_irq(0); |
1da177e4 | 2938 | } |
4aae0702 | 2939 | goto out; |
1da177e4 LT |
2940 | } |
2941 | /* | |
2942 | * Cleanup, just in case ... | |
2943 | */ | |
ecd29476 | 2944 | disable_8259A_irq(0); |
fcfd636a | 2945 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2946 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2947 | } |
1da177e4 LT |
2948 | |
2949 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2950 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2951 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2952 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2953 | } |
54168ed7 | 2954 | #ifdef CONFIG_X86_32 |
d11d5794 | 2955 | timer_ack = 0; |
54168ed7 | 2956 | #endif |
1da177e4 | 2957 | |
49a66a0b MR |
2958 | apic_printk(APIC_QUIET, KERN_INFO |
2959 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2960 | |
3145e941 | 2961 | lapic_register_intr(0, desc); |
497c9a19 | 2962 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2963 | enable_8259A_irq(0); |
2964 | ||
2965 | if (timer_irq_works()) { | |
49a66a0b | 2966 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2967 | goto out; |
1da177e4 | 2968 | } |
e67465f1 | 2969 | disable_8259A_irq(0); |
497c9a19 | 2970 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2971 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2972 | |
49a66a0b MR |
2973 | apic_printk(APIC_QUIET, KERN_INFO |
2974 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2975 | |
1da177e4 LT |
2976 | init_8259A(0); |
2977 | make_8259A_irq(0); | |
593f4a78 | 2978 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2979 | |
2980 | unlock_ExtINT_logic(); | |
2981 | ||
2982 | if (timer_irq_works()) { | |
49a66a0b | 2983 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2984 | goto out; |
1da177e4 | 2985 | } |
49a66a0b | 2986 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2987 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2988 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2989 | out: |
2990 | local_irq_restore(flags); | |
1da177e4 LT |
2991 | } |
2992 | ||
2993 | /* | |
af174783 MR |
2994 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2995 | * to devices. However there may be an I/O APIC pin available for | |
2996 | * this interrupt regardless. The pin may be left unconnected, but | |
2997 | * typically it will be reused as an ExtINT cascade interrupt for | |
2998 | * the master 8259A. In the MPS case such a pin will normally be | |
2999 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3000 | * there is no provision for ExtINT interrupts, and in the absence | |
3001 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3002 | * interrupt, that is edge-triggered and unmasked by default. We | |
3003 | * used to do this, but it caused problems on some systems because | |
3004 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3005 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3006 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3007 | * the I/O APIC in all cases now. No actual device should request | |
3008 | * it anyway. --macro | |
1da177e4 LT |
3009 | */ |
3010 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3011 | ||
3012 | void __init setup_IO_APIC(void) | |
3013 | { | |
54168ed7 IM |
3014 | |
3015 | #ifdef CONFIG_X86_32 | |
1da177e4 | 3016 | enable_IO_APIC(); |
54168ed7 IM |
3017 | #else |
3018 | /* | |
3019 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3020 | */ | |
3021 | #endif | |
1da177e4 | 3022 | |
af174783 | 3023 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3024 | |
54168ed7 | 3025 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3026 | /* |
54168ed7 IM |
3027 | * Set up IO-APIC IRQ routing. |
3028 | */ | |
3029 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3030 | if (!acpi_ioapic) |
3031 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3032 | #endif |
1da177e4 LT |
3033 | sync_Arb_IDs(); |
3034 | setup_IO_APIC_irqs(); | |
3035 | init_IO_APIC_traps(); | |
1e4c85f9 | 3036 | check_timer(); |
1da177e4 LT |
3037 | } |
3038 | ||
3039 | /* | |
54168ed7 IM |
3040 | * Called after all the initialization is done. If we didnt find any |
3041 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3042 | */ |
36062448 | 3043 | |
1da177e4 LT |
3044 | static int __init io_apic_bug_finalize(void) |
3045 | { | |
d6c88a50 TG |
3046 | if (sis_apic_bug == -1) |
3047 | sis_apic_bug = 0; | |
3048 | return 0; | |
1da177e4 LT |
3049 | } |
3050 | ||
3051 | late_initcall(io_apic_bug_finalize); | |
3052 | ||
3053 | struct sysfs_ioapic_data { | |
3054 | struct sys_device dev; | |
3055 | struct IO_APIC_route_entry entry[0]; | |
3056 | }; | |
54168ed7 | 3057 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3058 | |
438510f6 | 3059 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3060 | { |
3061 | struct IO_APIC_route_entry *entry; | |
3062 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3063 | int i; |
36062448 | 3064 | |
1da177e4 LT |
3065 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3066 | entry = data->entry; | |
54168ed7 IM |
3067 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3068 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3069 | |
3070 | return 0; | |
3071 | } | |
3072 | ||
3073 | static int ioapic_resume(struct sys_device *dev) | |
3074 | { | |
3075 | struct IO_APIC_route_entry *entry; | |
3076 | struct sysfs_ioapic_data *data; | |
3077 | unsigned long flags; | |
3078 | union IO_APIC_reg_00 reg_00; | |
3079 | int i; | |
36062448 | 3080 | |
1da177e4 LT |
3081 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3082 | entry = data->entry; | |
3083 | ||
3084 | spin_lock_irqsave(&ioapic_lock, flags); | |
3085 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
3086 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
3087 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
3088 | io_apic_write(dev->id, 0, reg_00.raw); |
3089 | } | |
1da177e4 | 3090 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3091 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3092 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3093 | |
3094 | return 0; | |
3095 | } | |
3096 | ||
3097 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3098 | .name = "ioapic", |
1da177e4 LT |
3099 | .suspend = ioapic_suspend, |
3100 | .resume = ioapic_resume, | |
3101 | }; | |
3102 | ||
3103 | static int __init ioapic_init_sysfs(void) | |
3104 | { | |
54168ed7 IM |
3105 | struct sys_device * dev; |
3106 | int i, size, error; | |
1da177e4 LT |
3107 | |
3108 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3109 | if (error) | |
3110 | return error; | |
3111 | ||
54168ed7 | 3112 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3113 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3114 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3115 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3116 | if (!mp_ioapic_data[i]) { |
3117 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3118 | continue; | |
3119 | } | |
1da177e4 | 3120 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3121 | dev->id = i; |
1da177e4 LT |
3122 | dev->cls = &ioapic_sysdev_class; |
3123 | error = sysdev_register(dev); | |
3124 | if (error) { | |
3125 | kfree(mp_ioapic_data[i]); | |
3126 | mp_ioapic_data[i] = NULL; | |
3127 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3128 | continue; | |
3129 | } | |
3130 | } | |
3131 | ||
3132 | return 0; | |
3133 | } | |
3134 | ||
3135 | device_initcall(ioapic_init_sysfs); | |
3136 | ||
3fc471ed | 3137 | /* |
95d77884 | 3138 | * Dynamic irq allocate and deallocation |
3fc471ed | 3139 | */ |
199751d7 | 3140 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3141 | { |
ace80ab7 | 3142 | /* Allocate an unused irq */ |
54168ed7 IM |
3143 | unsigned int irq; |
3144 | unsigned int new; | |
3fc471ed | 3145 | unsigned long flags; |
0b8f1efa YL |
3146 | struct irq_cfg *cfg_new = NULL; |
3147 | int cpu = boot_cpu_id; | |
3148 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
3149 | |
3150 | irq = 0; | |
ace80ab7 | 3151 | spin_lock_irqsave(&vector_lock, flags); |
be5d5350 | 3152 | for (new = irq_want; new < NR_IRQS; new++) { |
ace80ab7 EB |
3153 | if (platform_legacy_irq(new)) |
3154 | continue; | |
0b8f1efa YL |
3155 | |
3156 | desc_new = irq_to_desc_alloc_cpu(new, cpu); | |
3157 | if (!desc_new) { | |
3158 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
3159 | continue; | |
3160 | } | |
3161 | cfg_new = desc_new->chip_data; | |
3162 | ||
3163 | if (cfg_new->vector != 0) | |
ace80ab7 | 3164 | continue; |
3145e941 | 3165 | if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0) |
ace80ab7 EB |
3166 | irq = new; |
3167 | break; | |
3168 | } | |
3169 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3170 | |
199751d7 | 3171 | if (irq > 0) { |
3fc471ed | 3172 | dynamic_irq_init(irq); |
0b8f1efa YL |
3173 | /* restore it, in case dynamic_irq_init clear it */ |
3174 | if (desc_new) | |
3175 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3176 | } |
3177 | return irq; | |
3178 | } | |
3179 | ||
be5d5350 | 3180 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
199751d7 YL |
3181 | int create_irq(void) |
3182 | { | |
be5d5350 | 3183 | unsigned int irq_want; |
54168ed7 IM |
3184 | int irq; |
3185 | ||
be5d5350 YL |
3186 | irq_want = nr_irqs_gsi; |
3187 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3188 | |
3189 | if (irq == 0) | |
3190 | irq = -1; | |
3191 | ||
3192 | return irq; | |
199751d7 YL |
3193 | } |
3194 | ||
3fc471ed EB |
3195 | void destroy_irq(unsigned int irq) |
3196 | { | |
3197 | unsigned long flags; | |
0b8f1efa YL |
3198 | struct irq_cfg *cfg; |
3199 | struct irq_desc *desc; | |
3fc471ed | 3200 | |
0b8f1efa YL |
3201 | /* store it, in case dynamic_irq_cleanup clear it */ |
3202 | desc = irq_to_desc(irq); | |
3203 | cfg = desc->chip_data; | |
3fc471ed | 3204 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3205 | /* connect back irq_cfg */ |
3206 | if (desc) | |
3207 | desc->chip_data = cfg; | |
3fc471ed | 3208 | |
54168ed7 IM |
3209 | #ifdef CONFIG_INTR_REMAP |
3210 | free_irte(irq); | |
3211 | #endif | |
3fc471ed | 3212 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3213 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3214 | spin_unlock_irqrestore(&vector_lock, flags); |
3215 | } | |
3fc471ed | 3216 | |
2d3fcc1c | 3217 | /* |
27b46d76 | 3218 | * MSI message composition |
2d3fcc1c EB |
3219 | */ |
3220 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3221 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3222 | { |
497c9a19 YL |
3223 | struct irq_cfg *cfg; |
3224 | int err; | |
2d3fcc1c | 3225 | unsigned dest; |
497c9a19 | 3226 | cpumask_t tmp; |
2d3fcc1c | 3227 | |
3145e941 | 3228 | cfg = irq_cfg(irq); |
497c9a19 | 3229 | tmp = TARGET_CPUS; |
3145e941 | 3230 | err = assign_irq_vector(irq, cfg, tmp); |
497c9a19 YL |
3231 | if (err) |
3232 | return err; | |
2d3fcc1c | 3233 | |
497c9a19 YL |
3234 | cpus_and(tmp, cfg->domain, tmp); |
3235 | dest = cpu_mask_to_apicid(tmp); | |
3236 | ||
54168ed7 IM |
3237 | #ifdef CONFIG_INTR_REMAP |
3238 | if (irq_remapped(irq)) { | |
3239 | struct irte irte; | |
3240 | int ir_index; | |
3241 | u16 sub_handle; | |
3242 | ||
3243 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3244 | BUG_ON(ir_index == -1); | |
3245 | ||
3246 | memset (&irte, 0, sizeof(irte)); | |
3247 | ||
3248 | irte.present = 1; | |
3249 | irte.dst_mode = INT_DEST_MODE; | |
3250 | irte.trigger_mode = 0; /* edge */ | |
3251 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
3252 | irte.vector = cfg->vector; | |
3253 | irte.dest_id = IRTE_DEST(dest); | |
3254 | ||
3255 | modify_irte(irq, &irte); | |
3256 | ||
3257 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3258 | msg->data = sub_handle; | |
3259 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3260 | MSI_ADDR_IR_SHV | | |
3261 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3262 | MSI_ADDR_IR_INDEX2(ir_index); | |
3263 | } else | |
3264 | #endif | |
3265 | { | |
3266 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3267 | msg->address_lo = | |
3268 | MSI_ADDR_BASE_LO | | |
3269 | ((INT_DEST_MODE == 0) ? | |
3270 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3271 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3272 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3273 | MSI_ADDR_REDIRECTION_CPU: | |
3274 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3275 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3276 | |
54168ed7 IM |
3277 | msg->data = |
3278 | MSI_DATA_TRIGGER_EDGE | | |
3279 | MSI_DATA_LEVEL_ASSERT | | |
3280 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3281 | MSI_DATA_DELIVERY_FIXED: | |
3282 | MSI_DATA_DELIVERY_LOWPRI) | | |
3283 | MSI_DATA_VECTOR(cfg->vector); | |
3284 | } | |
497c9a19 | 3285 | return err; |
2d3fcc1c EB |
3286 | } |
3287 | ||
3b7d1921 EB |
3288 | #ifdef CONFIG_SMP |
3289 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 3290 | { |
3145e941 | 3291 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3292 | struct irq_cfg *cfg; |
3b7d1921 EB |
3293 | struct msi_msg msg; |
3294 | unsigned int dest; | |
3295 | cpumask_t tmp; | |
3b7d1921 EB |
3296 | |
3297 | cpus_and(tmp, mask, cpu_online_map); | |
3298 | if (cpus_empty(tmp)) | |
497c9a19 | 3299 | return; |
2d3fcc1c | 3300 | |
3145e941 YL |
3301 | cfg = desc->chip_data; |
3302 | if (assign_irq_vector(irq, cfg, mask)) | |
3b7d1921 | 3303 | return; |
2d3fcc1c | 3304 | |
3145e941 YL |
3305 | set_extra_move_desc(desc, mask); |
3306 | ||
497c9a19 YL |
3307 | cpus_and(tmp, cfg->domain, mask); |
3308 | dest = cpu_mask_to_apicid(tmp); | |
3b7d1921 | 3309 | |
3145e941 | 3310 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3311 | |
3312 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3313 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3314 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3315 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3316 | ||
3145e941 | 3317 | write_msi_msg_desc(desc, &msg); |
54168ed7 | 3318 | desc->affinity = mask; |
2d3fcc1c | 3319 | } |
54168ed7 IM |
3320 | #ifdef CONFIG_INTR_REMAP |
3321 | /* | |
3322 | * Migrate the MSI irq to another cpumask. This migration is | |
3323 | * done in the process context using interrupt-remapping hardware. | |
3324 | */ | |
3325 | static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
3326 | { | |
3145e941 | 3327 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3328 | struct irq_cfg *cfg; |
3329 | unsigned int dest; | |
3330 | cpumask_t tmp, cleanup_mask; | |
3331 | struct irte irte; | |
54168ed7 IM |
3332 | |
3333 | cpus_and(tmp, mask, cpu_online_map); | |
3334 | if (cpus_empty(tmp)) | |
3335 | return; | |
3336 | ||
3337 | if (get_irte(irq, &irte)) | |
3338 | return; | |
3339 | ||
3145e941 YL |
3340 | cfg = desc->chip_data; |
3341 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
3342 | return; |
3343 | ||
3145e941 YL |
3344 | set_extra_move_desc(desc, mask); |
3345 | ||
54168ed7 IM |
3346 | cpus_and(tmp, cfg->domain, mask); |
3347 | dest = cpu_mask_to_apicid(tmp); | |
3348 | ||
3349 | irte.vector = cfg->vector; | |
3350 | irte.dest_id = IRTE_DEST(dest); | |
3351 | ||
3352 | /* | |
3353 | * atomically update the IRTE with the new destination and vector. | |
3354 | */ | |
3355 | modify_irte(irq, &irte); | |
3356 | ||
3357 | /* | |
3358 | * After this point, all the interrupts will start arriving | |
3359 | * at the new destination. So, time to cleanup the previous | |
3360 | * vector allocation. | |
3361 | */ | |
3362 | if (cfg->move_in_progress) { | |
3363 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
3364 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
3365 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
3366 | cfg->move_in_progress = 0; | |
3367 | } | |
3368 | ||
54168ed7 IM |
3369 | desc->affinity = mask; |
3370 | } | |
3145e941 | 3371 | |
54168ed7 | 3372 | #endif |
3b7d1921 | 3373 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3374 | |
3b7d1921 EB |
3375 | /* |
3376 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3377 | * which implement the MSI or MSI-X Capability Structure. | |
3378 | */ | |
3379 | static struct irq_chip msi_chip = { | |
3380 | .name = "PCI-MSI", | |
3381 | .unmask = unmask_msi_irq, | |
3382 | .mask = mask_msi_irq, | |
1d025192 | 3383 | .ack = ack_apic_edge, |
3b7d1921 EB |
3384 | #ifdef CONFIG_SMP |
3385 | .set_affinity = set_msi_irq_affinity, | |
3386 | #endif | |
3387 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3388 | }; |
3389 | ||
54168ed7 IM |
3390 | #ifdef CONFIG_INTR_REMAP |
3391 | static struct irq_chip msi_ir_chip = { | |
3392 | .name = "IR-PCI-MSI", | |
3393 | .unmask = unmask_msi_irq, | |
3394 | .mask = mask_msi_irq, | |
3395 | .ack = ack_x2apic_edge, | |
3396 | #ifdef CONFIG_SMP | |
3397 | .set_affinity = ir_set_msi_irq_affinity, | |
3398 | #endif | |
3399 | .retrigger = ioapic_retrigger_irq, | |
3400 | }; | |
3401 | ||
3402 | /* | |
3403 | * Map the PCI dev to the corresponding remapping hardware unit | |
3404 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3405 | * in it. | |
3406 | */ | |
3407 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3408 | { | |
3409 | struct intel_iommu *iommu; | |
3410 | int index; | |
3411 | ||
3412 | iommu = map_dev_to_ir(dev); | |
3413 | if (!iommu) { | |
3414 | printk(KERN_ERR | |
3415 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3416 | return -ENOENT; | |
3417 | } | |
3418 | ||
3419 | index = alloc_irte(iommu, irq, nvec); | |
3420 | if (index < 0) { | |
3421 | printk(KERN_ERR | |
3422 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3423 | pci_name(dev)); |
54168ed7 IM |
3424 | return -ENOSPC; |
3425 | } | |
3426 | return index; | |
3427 | } | |
3428 | #endif | |
1d025192 | 3429 | |
3145e941 | 3430 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3431 | { |
3432 | int ret; | |
3433 | struct msi_msg msg; | |
3434 | ||
3435 | ret = msi_compose_msg(dev, irq, &msg); | |
3436 | if (ret < 0) | |
3437 | return ret; | |
3438 | ||
3145e941 | 3439 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3440 | write_msi_msg(irq, &msg); |
3441 | ||
54168ed7 IM |
3442 | #ifdef CONFIG_INTR_REMAP |
3443 | if (irq_remapped(irq)) { | |
3444 | struct irq_desc *desc = irq_to_desc(irq); | |
3445 | /* | |
3446 | * irq migration in process context | |
3447 | */ | |
3448 | desc->status |= IRQ_MOVE_PCNTXT; | |
3449 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3450 | } else | |
3451 | #endif | |
3452 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 | 3453 | |
c81bba49 YL |
3454 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3455 | ||
1d025192 YL |
3456 | return 0; |
3457 | } | |
3458 | ||
0b8f1efa | 3459 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc) |
3b7d1921 | 3460 | { |
54168ed7 IM |
3461 | unsigned int irq; |
3462 | int ret; | |
199751d7 YL |
3463 | unsigned int irq_want; |
3464 | ||
be5d5350 | 3465 | irq_want = nr_irqs_gsi; |
199751d7 | 3466 | irq = create_irq_nr(irq_want); |
199751d7 YL |
3467 | if (irq == 0) |
3468 | return -1; | |
f7feaca7 | 3469 | |
54168ed7 IM |
3470 | #ifdef CONFIG_INTR_REMAP |
3471 | if (!intr_remapping_enabled) | |
3472 | goto no_ir; | |
3473 | ||
3474 | ret = msi_alloc_irte(dev, irq, 1); | |
3475 | if (ret < 0) | |
3476 | goto error; | |
3477 | no_ir: | |
3478 | #endif | |
0b8f1efa | 3479 | ret = setup_msi_irq(dev, msidesc, irq); |
f7feaca7 EB |
3480 | if (ret < 0) { |
3481 | destroy_irq(irq); | |
3b7d1921 | 3482 | return ret; |
54168ed7 | 3483 | } |
7fe3730d | 3484 | return 0; |
54168ed7 IM |
3485 | |
3486 | #ifdef CONFIG_INTR_REMAP | |
3487 | error: | |
3488 | destroy_irq(irq); | |
3489 | return ret; | |
3490 | #endif | |
3b7d1921 EB |
3491 | } |
3492 | ||
047c8fdb YL |
3493 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3494 | { | |
54168ed7 IM |
3495 | unsigned int irq; |
3496 | int ret, sub_handle; | |
0b8f1efa | 3497 | struct msi_desc *msidesc; |
54168ed7 IM |
3498 | unsigned int irq_want; |
3499 | ||
3500 | #ifdef CONFIG_INTR_REMAP | |
3501 | struct intel_iommu *iommu = 0; | |
3502 | int index = 0; | |
3503 | #endif | |
3504 | ||
be5d5350 | 3505 | irq_want = nr_irqs_gsi; |
54168ed7 | 3506 | sub_handle = 0; |
0b8f1efa YL |
3507 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3508 | irq = create_irq_nr(irq_want); | |
be5d5350 | 3509 | irq_want++; |
54168ed7 IM |
3510 | if (irq == 0) |
3511 | return -1; | |
3512 | #ifdef CONFIG_INTR_REMAP | |
3513 | if (!intr_remapping_enabled) | |
3514 | goto no_ir; | |
3515 | ||
3516 | if (!sub_handle) { | |
3517 | /* | |
3518 | * allocate the consecutive block of IRTE's | |
3519 | * for 'nvec' | |
3520 | */ | |
3521 | index = msi_alloc_irte(dev, irq, nvec); | |
3522 | if (index < 0) { | |
3523 | ret = index; | |
3524 | goto error; | |
3525 | } | |
3526 | } else { | |
3527 | iommu = map_dev_to_ir(dev); | |
3528 | if (!iommu) { | |
3529 | ret = -ENOENT; | |
3530 | goto error; | |
3531 | } | |
3532 | /* | |
3533 | * setup the mapping between the irq and the IRTE | |
3534 | * base index, the sub_handle pointing to the | |
3535 | * appropriate interrupt remap table entry. | |
3536 | */ | |
3537 | set_irte_irq(irq, iommu, index, sub_handle); | |
3538 | } | |
3539 | no_ir: | |
3540 | #endif | |
0b8f1efa | 3541 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3542 | if (ret < 0) |
3543 | goto error; | |
3544 | sub_handle++; | |
3545 | } | |
3546 | return 0; | |
047c8fdb YL |
3547 | |
3548 | error: | |
54168ed7 IM |
3549 | destroy_irq(irq); |
3550 | return ret; | |
047c8fdb YL |
3551 | } |
3552 | ||
3b7d1921 EB |
3553 | void arch_teardown_msi_irq(unsigned int irq) |
3554 | { | |
f7feaca7 | 3555 | destroy_irq(irq); |
3b7d1921 EB |
3556 | } |
3557 | ||
54168ed7 IM |
3558 | #ifdef CONFIG_DMAR |
3559 | #ifdef CONFIG_SMP | |
3560 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
3561 | { | |
3145e941 | 3562 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3563 | struct irq_cfg *cfg; |
3564 | struct msi_msg msg; | |
3565 | unsigned int dest; | |
3566 | cpumask_t tmp; | |
54168ed7 IM |
3567 | |
3568 | cpus_and(tmp, mask, cpu_online_map); | |
3569 | if (cpus_empty(tmp)) | |
3570 | return; | |
3571 | ||
3145e941 YL |
3572 | cfg = desc->chip_data; |
3573 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
3574 | return; |
3575 | ||
3145e941 YL |
3576 | set_extra_move_desc(desc, mask); |
3577 | ||
54168ed7 IM |
3578 | cpus_and(tmp, cfg->domain, mask); |
3579 | dest = cpu_mask_to_apicid(tmp); | |
3580 | ||
3581 | dmar_msi_read(irq, &msg); | |
3582 | ||
3583 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3584 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3585 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3586 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3587 | ||
3588 | dmar_msi_write(irq, &msg); | |
54168ed7 IM |
3589 | desc->affinity = mask; |
3590 | } | |
3145e941 | 3591 | |
54168ed7 IM |
3592 | #endif /* CONFIG_SMP */ |
3593 | ||
3594 | struct irq_chip dmar_msi_type = { | |
3595 | .name = "DMAR_MSI", | |
3596 | .unmask = dmar_msi_unmask, | |
3597 | .mask = dmar_msi_mask, | |
3598 | .ack = ack_apic_edge, | |
3599 | #ifdef CONFIG_SMP | |
3600 | .set_affinity = dmar_msi_set_affinity, | |
3601 | #endif | |
3602 | .retrigger = ioapic_retrigger_irq, | |
3603 | }; | |
3604 | ||
3605 | int arch_setup_dmar_msi(unsigned int irq) | |
3606 | { | |
3607 | int ret; | |
3608 | struct msi_msg msg; | |
2d3fcc1c | 3609 | |
54168ed7 IM |
3610 | ret = msi_compose_msg(NULL, irq, &msg); |
3611 | if (ret < 0) | |
3612 | return ret; | |
3613 | dmar_msi_write(irq, &msg); | |
3614 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3615 | "edge"); | |
3616 | return 0; | |
3617 | } | |
3618 | #endif | |
3619 | ||
58ac1e76 | 3620 | #ifdef CONFIG_HPET_TIMER |
3621 | ||
3622 | #ifdef CONFIG_SMP | |
3623 | static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
3624 | { | |
3145e941 | 3625 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3626 | struct irq_cfg *cfg; |
58ac1e76 | 3627 | struct msi_msg msg; |
3628 | unsigned int dest; | |
3629 | cpumask_t tmp; | |
3630 | ||
3631 | cpus_and(tmp, mask, cpu_online_map); | |
3632 | if (cpus_empty(tmp)) | |
3633 | return; | |
3634 | ||
3145e941 YL |
3635 | cfg = desc->chip_data; |
3636 | if (assign_irq_vector(irq, cfg, mask)) | |
58ac1e76 | 3637 | return; |
3638 | ||
3145e941 YL |
3639 | set_extra_move_desc(desc, mask); |
3640 | ||
58ac1e76 | 3641 | cpus_and(tmp, cfg->domain, mask); |
3642 | dest = cpu_mask_to_apicid(tmp); | |
3643 | ||
3644 | hpet_msi_read(irq, &msg); | |
3645 | ||
3646 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3647 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3648 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3649 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3650 | ||
3651 | hpet_msi_write(irq, &msg); | |
58ac1e76 | 3652 | desc->affinity = mask; |
3653 | } | |
3145e941 | 3654 | |
58ac1e76 | 3655 | #endif /* CONFIG_SMP */ |
3656 | ||
3657 | struct irq_chip hpet_msi_type = { | |
3658 | .name = "HPET_MSI", | |
3659 | .unmask = hpet_msi_unmask, | |
3660 | .mask = hpet_msi_mask, | |
3661 | .ack = ack_apic_edge, | |
3662 | #ifdef CONFIG_SMP | |
3663 | .set_affinity = hpet_msi_set_affinity, | |
3664 | #endif | |
3665 | .retrigger = ioapic_retrigger_irq, | |
3666 | }; | |
3667 | ||
3668 | int arch_setup_hpet_msi(unsigned int irq) | |
3669 | { | |
3670 | int ret; | |
3671 | struct msi_msg msg; | |
3672 | ||
3673 | ret = msi_compose_msg(NULL, irq, &msg); | |
3674 | if (ret < 0) | |
3675 | return ret; | |
3676 | ||
3677 | hpet_msi_write(irq, &msg); | |
3678 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3679 | "edge"); | |
c81bba49 | 3680 | |
58ac1e76 | 3681 | return 0; |
3682 | } | |
3683 | #endif | |
3684 | ||
54168ed7 | 3685 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3686 | /* |
3687 | * Hypertransport interrupt support | |
3688 | */ | |
3689 | #ifdef CONFIG_HT_IRQ | |
3690 | ||
3691 | #ifdef CONFIG_SMP | |
3692 | ||
497c9a19 | 3693 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3694 | { |
ec68307c EB |
3695 | struct ht_irq_msg msg; |
3696 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3697 | |
497c9a19 | 3698 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3699 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3700 | |
497c9a19 | 3701 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3702 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3703 | |
ec68307c | 3704 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3705 | } |
3706 | ||
3707 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
3708 | { | |
3145e941 | 3709 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3710 | struct irq_cfg *cfg; |
8b955b0d EB |
3711 | unsigned int dest; |
3712 | cpumask_t tmp; | |
3713 | ||
3714 | cpus_and(tmp, mask, cpu_online_map); | |
3715 | if (cpus_empty(tmp)) | |
497c9a19 | 3716 | return; |
8b955b0d | 3717 | |
3145e941 YL |
3718 | cfg = desc->chip_data; |
3719 | if (assign_irq_vector(irq, cfg, mask)) | |
497c9a19 | 3720 | return; |
8b955b0d | 3721 | |
3145e941 YL |
3722 | set_extra_move_desc(desc, mask); |
3723 | ||
497c9a19 YL |
3724 | cpus_and(tmp, cfg->domain, mask); |
3725 | dest = cpu_mask_to_apicid(tmp); | |
8b955b0d | 3726 | |
497c9a19 | 3727 | target_ht_irq(irq, dest, cfg->vector); |
54168ed7 | 3728 | desc->affinity = mask; |
8b955b0d | 3729 | } |
3145e941 | 3730 | |
8b955b0d EB |
3731 | #endif |
3732 | ||
c37e108d | 3733 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3734 | .name = "PCI-HT", |
3735 | .mask = mask_ht_irq, | |
3736 | .unmask = unmask_ht_irq, | |
1d025192 | 3737 | .ack = ack_apic_edge, |
8b955b0d EB |
3738 | #ifdef CONFIG_SMP |
3739 | .set_affinity = set_ht_irq_affinity, | |
3740 | #endif | |
3741 | .retrigger = ioapic_retrigger_irq, | |
3742 | }; | |
3743 | ||
3744 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3745 | { | |
497c9a19 YL |
3746 | struct irq_cfg *cfg; |
3747 | int err; | |
3748 | cpumask_t tmp; | |
8b955b0d | 3749 | |
3145e941 | 3750 | cfg = irq_cfg(irq); |
497c9a19 | 3751 | tmp = TARGET_CPUS; |
3145e941 | 3752 | err = assign_irq_vector(irq, cfg, tmp); |
54168ed7 | 3753 | if (!err) { |
ec68307c | 3754 | struct ht_irq_msg msg; |
8b955b0d | 3755 | unsigned dest; |
8b955b0d | 3756 | |
497c9a19 | 3757 | cpus_and(tmp, cfg->domain, tmp); |
8b955b0d EB |
3758 | dest = cpu_mask_to_apicid(tmp); |
3759 | ||
ec68307c | 3760 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3761 | |
ec68307c EB |
3762 | msg.address_lo = |
3763 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3764 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3765 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3766 | ((INT_DEST_MODE == 0) ? |
3767 | HT_IRQ_LOW_DM_PHYSICAL : | |
3768 | HT_IRQ_LOW_DM_LOGICAL) | | |
3769 | HT_IRQ_LOW_RQEOI_EDGE | | |
3770 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3771 | HT_IRQ_LOW_MT_FIXED : | |
3772 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3773 | HT_IRQ_LOW_IRQ_MASKED; | |
3774 | ||
ec68307c | 3775 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3776 | |
a460e745 IM |
3777 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3778 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3779 | |
3780 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3781 | } |
497c9a19 | 3782 | return err; |
8b955b0d EB |
3783 | } |
3784 | #endif /* CONFIG_HT_IRQ */ | |
3785 | ||
4173a0e7 DN |
3786 | #ifdef CONFIG_X86_64 |
3787 | /* | |
3788 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3789 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3790 | */ | |
3791 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3792 | unsigned long mmr_offset) | |
3793 | { | |
3794 | const cpumask_t *eligible_cpu = get_cpu_mask(cpu); | |
3795 | struct irq_cfg *cfg; | |
3796 | int mmr_pnode; | |
3797 | unsigned long mmr_value; | |
3798 | struct uv_IO_APIC_route_entry *entry; | |
3799 | unsigned long flags; | |
3800 | int err; | |
3801 | ||
3145e941 YL |
3802 | cfg = irq_cfg(irq); |
3803 | ||
3804 | err = assign_irq_vector(irq, cfg, *eligible_cpu); | |
4173a0e7 DN |
3805 | if (err != 0) |
3806 | return err; | |
3807 | ||
3808 | spin_lock_irqsave(&vector_lock, flags); | |
3809 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3810 | irq_name); | |
3811 | spin_unlock_irqrestore(&vector_lock, flags); | |
3812 | ||
4173a0e7 DN |
3813 | mmr_value = 0; |
3814 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3815 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3816 | ||
3817 | entry->vector = cfg->vector; | |
3818 | entry->delivery_mode = INT_DELIVERY_MODE; | |
3819 | entry->dest_mode = INT_DEST_MODE; | |
3820 | entry->polarity = 0; | |
3821 | entry->trigger = 0; | |
3822 | entry->mask = 0; | |
3823 | entry->dest = cpu_mask_to_apicid(*eligible_cpu); | |
3824 | ||
3825 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3826 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3827 | ||
3828 | return irq; | |
3829 | } | |
3830 | ||
3831 | /* | |
3832 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3833 | * longer allowed to be sent. | |
3834 | */ | |
3835 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3836 | { | |
3837 | unsigned long mmr_value; | |
3838 | struct uv_IO_APIC_route_entry *entry; | |
3839 | int mmr_pnode; | |
3840 | ||
3841 | mmr_value = 0; | |
3842 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3843 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3844 | ||
3845 | entry->mask = 1; | |
3846 | ||
3847 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3848 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3849 | } | |
3850 | #endif /* CONFIG_X86_64 */ | |
3851 | ||
9d6a4d08 YL |
3852 | int __init io_apic_get_redir_entries (int ioapic) |
3853 | { | |
3854 | union IO_APIC_reg_01 reg_01; | |
3855 | unsigned long flags; | |
3856 | ||
3857 | spin_lock_irqsave(&ioapic_lock, flags); | |
3858 | reg_01.raw = io_apic_read(ioapic, 1); | |
3859 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3860 | ||
3861 | return reg_01.bits.entries; | |
3862 | } | |
3863 | ||
be5d5350 | 3864 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3865 | { |
be5d5350 YL |
3866 | int idx; |
3867 | int nr = 0; | |
3868 | ||
3869 | for (idx = 0; idx < nr_ioapics; idx++) | |
3870 | nr += io_apic_get_redir_entries(idx) + 1; | |
3871 | ||
3872 | if (nr > nr_irqs_gsi) | |
3873 | nr_irqs_gsi = nr; | |
9d6a4d08 YL |
3874 | } |
3875 | ||
1da177e4 | 3876 | /* -------------------------------------------------------------------------- |
54168ed7 | 3877 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3878 | -------------------------------------------------------------------------- */ |
3879 | ||
888ba6c6 | 3880 | #ifdef CONFIG_ACPI |
1da177e4 | 3881 | |
54168ed7 | 3882 | #ifdef CONFIG_X86_32 |
36062448 | 3883 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3884 | { |
3885 | union IO_APIC_reg_00 reg_00; | |
3886 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3887 | physid_mask_t tmp; | |
3888 | unsigned long flags; | |
3889 | int i = 0; | |
3890 | ||
3891 | /* | |
36062448 PC |
3892 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3893 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3894 | * supports up to 16 on one shared APIC bus. |
36062448 | 3895 | * |
1da177e4 LT |
3896 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3897 | * advantage of new APIC bus architecture. | |
3898 | */ | |
3899 | ||
3900 | if (physids_empty(apic_id_map)) | |
3901 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3902 | ||
3903 | spin_lock_irqsave(&ioapic_lock, flags); | |
3904 | reg_00.raw = io_apic_read(ioapic, 0); | |
3905 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3906 | ||
3907 | if (apic_id >= get_physical_broadcast()) { | |
3908 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3909 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3910 | apic_id = reg_00.bits.ID; | |
3911 | } | |
3912 | ||
3913 | /* | |
36062448 | 3914 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3915 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3916 | */ | |
3917 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3918 | ||
3919 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3920 | if (!check_apicid_used(apic_id_map, i)) | |
3921 | break; | |
3922 | } | |
3923 | ||
3924 | if (i == get_physical_broadcast()) | |
3925 | panic("Max apic_id exceeded!\n"); | |
3926 | ||
3927 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3928 | "trying %d\n", ioapic, apic_id, i); | |
3929 | ||
3930 | apic_id = i; | |
36062448 | 3931 | } |
1da177e4 LT |
3932 | |
3933 | tmp = apicid_to_cpu_present(apic_id); | |
3934 | physids_or(apic_id_map, apic_id_map, tmp); | |
3935 | ||
3936 | if (reg_00.bits.ID != apic_id) { | |
3937 | reg_00.bits.ID = apic_id; | |
3938 | ||
3939 | spin_lock_irqsave(&ioapic_lock, flags); | |
3940 | io_apic_write(ioapic, 0, reg_00.raw); | |
3941 | reg_00.raw = io_apic_read(ioapic, 0); | |
3942 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3943 | ||
3944 | /* Sanity check */ | |
6070f9ec AD |
3945 | if (reg_00.bits.ID != apic_id) { |
3946 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3947 | return -1; | |
3948 | } | |
1da177e4 LT |
3949 | } |
3950 | ||
3951 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3952 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3953 | ||
3954 | return apic_id; | |
3955 | } | |
3956 | ||
36062448 | 3957 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3958 | { |
3959 | union IO_APIC_reg_01 reg_01; | |
3960 | unsigned long flags; | |
3961 | ||
3962 | spin_lock_irqsave(&ioapic_lock, flags); | |
3963 | reg_01.raw = io_apic_read(ioapic, 1); | |
3964 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3965 | ||
3966 | return reg_01.bits.version; | |
3967 | } | |
54168ed7 | 3968 | #endif |
1da177e4 | 3969 | |
54168ed7 | 3970 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3971 | { |
0b8f1efa YL |
3972 | struct irq_desc *desc; |
3973 | struct irq_cfg *cfg; | |
3974 | int cpu = boot_cpu_id; | |
3975 | ||
1da177e4 | 3976 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3977 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3978 | ioapic); |
3979 | return -EINVAL; | |
3980 | } | |
3981 | ||
0b8f1efa YL |
3982 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
3983 | if (!desc) { | |
3984 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3985 | return 0; | |
3986 | } | |
3987 | ||
1da177e4 LT |
3988 | /* |
3989 | * IRQs < 16 are already in the irq_2_pin[] map | |
3990 | */ | |
99d093d1 | 3991 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3992 | cfg = desc->chip_data; |
3145e941 | 3993 | add_pin_to_irq_cpu(cfg, cpu, ioapic, pin); |
0b8f1efa | 3994 | } |
1da177e4 | 3995 | |
3145e941 | 3996 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3997 | |
3998 | return 0; | |
3999 | } | |
4000 | ||
54168ed7 | 4001 | |
61fd47e0 SL |
4002 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
4003 | { | |
4004 | int i; | |
4005 | ||
4006 | if (skip_ioapic_setup) | |
4007 | return -1; | |
4008 | ||
4009 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
4010 | if (mp_irqs[i].mp_irqtype == mp_INT && |
4011 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
4012 | break; |
4013 | if (i >= mp_irq_entries) | |
4014 | return -1; | |
4015 | ||
4016 | *trigger = irq_trigger(i); | |
4017 | *polarity = irq_polarity(i); | |
4018 | return 0; | |
4019 | } | |
4020 | ||
888ba6c6 | 4021 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4022 | |
497c9a19 YL |
4023 | /* |
4024 | * This function currently is only a helper for the i386 smp boot process where | |
4025 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
4026 | * so mask in all cases should simply be TARGET_CPUS | |
4027 | */ | |
4028 | #ifdef CONFIG_SMP | |
4029 | void __init setup_ioapic_dest(void) | |
4030 | { | |
4031 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4032 | struct irq_desc *desc; |
497c9a19 | 4033 | struct irq_cfg *cfg; |
6c2e9403 | 4034 | cpumask_t mask; |
497c9a19 YL |
4035 | |
4036 | if (skip_ioapic_setup == 1) | |
4037 | return; | |
4038 | ||
4039 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4040 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4041 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4042 | if (irq_entry == -1) | |
4043 | continue; | |
4044 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4045 | ||
4046 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4047 | * when you have too many devices, because at that time only boot | |
4048 | * cpu is online. | |
4049 | */ | |
0b8f1efa YL |
4050 | desc = irq_to_desc(irq); |
4051 | cfg = desc->chip_data; | |
6c2e9403 | 4052 | if (!cfg->vector) { |
3145e941 | 4053 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4054 | irq_trigger(irq_entry), |
4055 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4056 | continue; |
4057 | ||
4058 | } | |
4059 | ||
4060 | /* | |
4061 | * Honour affinities which have been set in early boot | |
4062 | */ | |
6c2e9403 TG |
4063 | if (desc->status & |
4064 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
4065 | mask = desc->affinity; | |
4066 | else | |
4067 | mask = TARGET_CPUS; | |
4068 | ||
54168ed7 | 4069 | #ifdef CONFIG_INTR_REMAP |
6c2e9403 | 4070 | if (intr_remapping_enabled) |
3145e941 | 4071 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4072 | else |
6c2e9403 | 4073 | #endif |
3145e941 | 4074 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4075 | } |
4076 | ||
4077 | } | |
4078 | } | |
4079 | #endif | |
4080 | ||
54168ed7 IM |
4081 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4082 | ||
4083 | static struct resource *ioapic_resources; | |
4084 | ||
4085 | static struct resource * __init ioapic_setup_resources(void) | |
4086 | { | |
4087 | unsigned long n; | |
4088 | struct resource *res; | |
4089 | char *mem; | |
4090 | int i; | |
4091 | ||
4092 | if (nr_ioapics <= 0) | |
4093 | return NULL; | |
4094 | ||
4095 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4096 | n *= nr_ioapics; | |
4097 | ||
4098 | mem = alloc_bootmem(n); | |
4099 | res = (void *)mem; | |
4100 | ||
4101 | if (mem != NULL) { | |
4102 | mem += sizeof(struct resource) * nr_ioapics; | |
4103 | ||
4104 | for (i = 0; i < nr_ioapics; i++) { | |
4105 | res[i].name = mem; | |
4106 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4107 | sprintf(mem, "IOAPIC %u", i); | |
4108 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4109 | } | |
4110 | } | |
4111 | ||
4112 | ioapic_resources = res; | |
4113 | ||
4114 | return res; | |
4115 | } | |
54168ed7 | 4116 | |
f3294a33 YL |
4117 | void __init ioapic_init_mappings(void) |
4118 | { | |
4119 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4120 | struct resource *ioapic_res; |
d6c88a50 | 4121 | int i; |
f3294a33 | 4122 | |
54168ed7 | 4123 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4124 | for (i = 0; i < nr_ioapics; i++) { |
4125 | if (smp_found_config) { | |
4126 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
54168ed7 | 4127 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4128 | if (!ioapic_phys) { |
4129 | printk(KERN_ERR | |
4130 | "WARNING: bogus zero IO-APIC " | |
4131 | "address found in MPTABLE, " | |
4132 | "disabling IO/APIC support!\n"); | |
4133 | smp_found_config = 0; | |
4134 | skip_ioapic_setup = 1; | |
4135 | goto fake_ioapic_page; | |
4136 | } | |
54168ed7 | 4137 | #endif |
f3294a33 | 4138 | } else { |
54168ed7 | 4139 | #ifdef CONFIG_X86_32 |
f3294a33 | 4140 | fake_ioapic_page: |
54168ed7 | 4141 | #endif |
f3294a33 | 4142 | ioapic_phys = (unsigned long) |
54168ed7 | 4143 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4144 | ioapic_phys = __pa(ioapic_phys); |
4145 | } | |
4146 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4147 | apic_printk(APIC_VERBOSE, |
4148 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4149 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4150 | idx++; |
54168ed7 | 4151 | |
54168ed7 IM |
4152 | if (ioapic_res != NULL) { |
4153 | ioapic_res->start = ioapic_phys; | |
4154 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4155 | ioapic_res++; | |
4156 | } | |
f3294a33 YL |
4157 | } |
4158 | } | |
4159 | ||
54168ed7 IM |
4160 | static int __init ioapic_insert_resources(void) |
4161 | { | |
4162 | int i; | |
4163 | struct resource *r = ioapic_resources; | |
4164 | ||
4165 | if (!r) { | |
4166 | printk(KERN_ERR | |
4167 | "IO APIC resources could be not be allocated.\n"); | |
4168 | return -1; | |
4169 | } | |
4170 | ||
4171 | for (i = 0; i < nr_ioapics; i++) { | |
4172 | insert_resource(&iomem_resource, r); | |
4173 | r++; | |
4174 | } | |
4175 | ||
4176 | return 0; | |
4177 | } | |
4178 | ||
4179 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4180 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4181 | late_initcall(ioapic_insert_resources); |