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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
6d652ea1 | 49 | #include <asm/cpu.h> |
1da177e4 | 50 | #include <asm/desc.h> |
d4057bdb YL |
51 | #include <asm/proto.h> |
52 | #include <asm/acpi.h> | |
53 | #include <asm/dma.h> | |
1da177e4 | 54 | #include <asm/timer.h> |
306e440d | 55 | #include <asm/i8259.h> |
3e4ff115 | 56 | #include <asm/nmi.h> |
2d3fcc1c | 57 | #include <asm/msidef.h> |
8b955b0d | 58 | #include <asm/hypertransport.h> |
a4dbc34d | 59 | #include <asm/setup.h> |
d4057bdb | 60 | #include <asm/irq_remapping.h> |
58ac1e76 | 61 | #include <asm/hpet.h> |
4173a0e7 DN |
62 | #include <asm/uv/uv_hub.h> |
63 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 64 | |
497c9a19 | 65 | #include <mach_ipi.h> |
1da177e4 | 66 | #include <mach_apic.h> |
874c4fe3 | 67 | #include <mach_apicdef.h> |
1da177e4 | 68 | |
32f71aff MR |
69 | #define __apicdebuginit(type) static type __init |
70 | ||
1da177e4 | 71 | /* |
54168ed7 IM |
72 | * Is the SiS APIC rmw bug present ? |
73 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
74 | */ |
75 | int sis_apic_bug = -1; | |
76 | ||
efa2559f YL |
77 | static DEFINE_SPINLOCK(ioapic_lock); |
78 | static DEFINE_SPINLOCK(vector_lock); | |
79 | ||
1da177e4 LT |
80 | /* |
81 | * # of IRQ routing registers | |
82 | */ | |
83 | int nr_ioapic_registers[MAX_IO_APICS]; | |
84 | ||
9f640ccb | 85 | /* I/O APIC entries */ |
b5ba7e6d | 86 | struct mpc_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
87 | int nr_ioapics; |
88 | ||
584f734d | 89 | /* MP IRQ source entries */ |
c2c21745 | 90 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
91 | |
92 | /* # of MP IRQ source entries */ | |
93 | int mp_irq_entries; | |
94 | ||
8732fc4b AS |
95 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
96 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
97 | #endif | |
98 | ||
99 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
100 | ||
efa2559f YL |
101 | int skip_ioapic_setup; |
102 | ||
54168ed7 | 103 | static int __init parse_noapic(char *str) |
efa2559f YL |
104 | { |
105 | /* disable IO-APIC */ | |
106 | disable_ioapic_setup(); | |
107 | return 0; | |
108 | } | |
109 | early_param("noapic", parse_noapic); | |
66759a01 | 110 | |
0f978f45 | 111 | struct irq_pin_list; |
0b8f1efa YL |
112 | |
113 | /* | |
114 | * This is performance-critical, we want to do it O(1) | |
115 | * | |
116 | * the indexing order of this array favors 1:1 mappings | |
117 | * between pins and IRQs. | |
118 | */ | |
119 | ||
120 | struct irq_pin_list { | |
121 | int apic, pin; | |
122 | struct irq_pin_list *next; | |
123 | }; | |
124 | ||
125 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
126 | { | |
127 | struct irq_pin_list *pin; | |
128 | int node; | |
129 | ||
130 | node = cpu_to_node(cpu); | |
131 | ||
132 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
133 | |
134 | return pin; | |
135 | } | |
136 | ||
a1420f39 | 137 | struct irq_cfg { |
0f978f45 | 138 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
139 | cpumask_var_t domain; |
140 | cpumask_var_t old_domain; | |
497c9a19 | 141 | unsigned move_cleanup_count; |
a1420f39 | 142 | u8 vector; |
497c9a19 | 143 | u8 move_in_progress : 1; |
48a1b10a YL |
144 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
145 | u8 move_desc_pending : 1; | |
146 | #endif | |
a1420f39 YL |
147 | }; |
148 | ||
a1420f39 | 149 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
150 | #ifdef CONFIG_SPARSE_IRQ |
151 | static struct irq_cfg irq_cfgx[] = { | |
152 | #else | |
d6c88a50 | 153 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 154 | #endif |
22f65d31 MT |
155 | [0] = { .vector = IRQ0_VECTOR, }, |
156 | [1] = { .vector = IRQ1_VECTOR, }, | |
157 | [2] = { .vector = IRQ2_VECTOR, }, | |
158 | [3] = { .vector = IRQ3_VECTOR, }, | |
159 | [4] = { .vector = IRQ4_VECTOR, }, | |
160 | [5] = { .vector = IRQ5_VECTOR, }, | |
161 | [6] = { .vector = IRQ6_VECTOR, }, | |
162 | [7] = { .vector = IRQ7_VECTOR, }, | |
163 | [8] = { .vector = IRQ8_VECTOR, }, | |
164 | [9] = { .vector = IRQ9_VECTOR, }, | |
165 | [10] = { .vector = IRQ10_VECTOR, }, | |
166 | [11] = { .vector = IRQ11_VECTOR, }, | |
167 | [12] = { .vector = IRQ12_VECTOR, }, | |
168 | [13] = { .vector = IRQ13_VECTOR, }, | |
169 | [14] = { .vector = IRQ14_VECTOR, }, | |
170 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
171 | }; |
172 | ||
13a0c3c2 | 173 | int __init arch_early_irq_init(void) |
8f09cd20 | 174 | { |
0b8f1efa YL |
175 | struct irq_cfg *cfg; |
176 | struct irq_desc *desc; | |
177 | int count; | |
178 | int i; | |
d6c88a50 | 179 | |
0b8f1efa YL |
180 | cfg = irq_cfgx; |
181 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 182 | |
0b8f1efa YL |
183 | for (i = 0; i < count; i++) { |
184 | desc = irq_to_desc(i); | |
185 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
186 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
187 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
188 | if (i < NR_IRQS_LEGACY) | |
189 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 190 | } |
13a0c3c2 YL |
191 | |
192 | return 0; | |
0b8f1efa | 193 | } |
8f09cd20 | 194 | |
0b8f1efa | 195 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 196 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 197 | { |
0b8f1efa YL |
198 | struct irq_cfg *cfg = NULL; |
199 | struct irq_desc *desc; | |
1da177e4 | 200 | |
0b8f1efa YL |
201 | desc = irq_to_desc(irq); |
202 | if (desc) | |
203 | cfg = desc->chip_data; | |
0f978f45 | 204 | |
0b8f1efa | 205 | return cfg; |
8f09cd20 | 206 | } |
d6c88a50 | 207 | |
0b8f1efa | 208 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
8f09cd20 | 209 | { |
0b8f1efa YL |
210 | struct irq_cfg *cfg; |
211 | int node; | |
212 | ||
213 | node = cpu_to_node(cpu); | |
0f978f45 | 214 | |
0b8f1efa | 215 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 216 | if (cfg) { |
80855f73 | 217 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
218 | kfree(cfg); |
219 | cfg = NULL; | |
80855f73 MT |
220 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
221 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
222 | free_cpumask_var(cfg->domain); |
223 | kfree(cfg); | |
224 | cfg = NULL; | |
225 | } else { | |
226 | cpumask_clear(cfg->domain); | |
227 | cpumask_clear(cfg->old_domain); | |
228 | } | |
229 | } | |
0f978f45 | 230 | |
0b8f1efa | 231 | return cfg; |
8f09cd20 YL |
232 | } |
233 | ||
13a0c3c2 | 234 | int arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 235 | { |
0b8f1efa | 236 | struct irq_cfg *cfg; |
d6c88a50 | 237 | |
0b8f1efa YL |
238 | cfg = desc->chip_data; |
239 | if (!cfg) { | |
240 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
241 | if (!desc->chip_data) { | |
242 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
243 | BUG_ON(1); | |
244 | } | |
245 | } | |
1da177e4 | 246 | |
13a0c3c2 | 247 | return 0; |
0b8f1efa | 248 | } |
0f978f45 | 249 | |
48a1b10a | 250 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
d6c88a50 | 251 | |
48a1b10a YL |
252 | static void |
253 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu) | |
0f978f45 | 254 | { |
48a1b10a YL |
255 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
256 | ||
257 | cfg->irq_2_pin = NULL; | |
258 | old_entry = old_cfg->irq_2_pin; | |
259 | if (!old_entry) | |
260 | return; | |
0f978f45 | 261 | |
48a1b10a YL |
262 | entry = get_one_free_irq_2_pin(cpu); |
263 | if (!entry) | |
264 | return; | |
0f978f45 | 265 | |
48a1b10a YL |
266 | entry->apic = old_entry->apic; |
267 | entry->pin = old_entry->pin; | |
268 | head = entry; | |
269 | tail = entry; | |
270 | old_entry = old_entry->next; | |
271 | while (old_entry) { | |
272 | entry = get_one_free_irq_2_pin(cpu); | |
273 | if (!entry) { | |
274 | entry = head; | |
275 | while (entry) { | |
276 | head = entry->next; | |
277 | kfree(entry); | |
278 | entry = head; | |
279 | } | |
280 | /* still use the old one */ | |
281 | return; | |
282 | } | |
283 | entry->apic = old_entry->apic; | |
284 | entry->pin = old_entry->pin; | |
285 | tail->next = entry; | |
286 | tail = entry; | |
287 | old_entry = old_entry->next; | |
288 | } | |
0f978f45 | 289 | |
48a1b10a YL |
290 | tail->next = NULL; |
291 | cfg->irq_2_pin = head; | |
0f978f45 | 292 | } |
0f978f45 | 293 | |
48a1b10a | 294 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 295 | { |
48a1b10a | 296 | struct irq_pin_list *entry, *next; |
0f978f45 | 297 | |
48a1b10a YL |
298 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
299 | return; | |
301e6190 | 300 | |
48a1b10a | 301 | entry = old_cfg->irq_2_pin; |
0f978f45 | 302 | |
48a1b10a YL |
303 | while (entry) { |
304 | next = entry->next; | |
305 | kfree(entry); | |
306 | entry = next; | |
307 | } | |
308 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 309 | } |
0f978f45 | 310 | |
48a1b10a YL |
311 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
312 | struct irq_desc *desc, int cpu) | |
0f978f45 | 313 | { |
48a1b10a YL |
314 | struct irq_cfg *cfg; |
315 | struct irq_cfg *old_cfg; | |
0f978f45 | 316 | |
48a1b10a | 317 | cfg = get_one_free_irq_cfg(cpu); |
301e6190 | 318 | |
48a1b10a YL |
319 | if (!cfg) |
320 | return; | |
321 | ||
322 | desc->chip_data = cfg; | |
323 | ||
324 | old_cfg = old_desc->chip_data; | |
325 | ||
326 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
327 | ||
328 | init_copy_irq_2_pin(old_cfg, cfg, cpu); | |
0f978f45 | 329 | } |
1da177e4 | 330 | |
48a1b10a YL |
331 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
332 | { | |
333 | kfree(old_cfg); | |
334 | } | |
335 | ||
336 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
337 | { | |
338 | struct irq_cfg *old_cfg, *cfg; | |
339 | ||
340 | old_cfg = old_desc->chip_data; | |
341 | cfg = desc->chip_data; | |
342 | ||
343 | if (old_cfg == cfg) | |
344 | return; | |
345 | ||
346 | if (old_cfg) { | |
347 | free_irq_2_pin(old_cfg, cfg); | |
348 | free_irq_cfg(old_cfg); | |
349 | old_desc->chip_data = NULL; | |
350 | } | |
351 | } | |
352 | ||
d733e00d IM |
353 | static void |
354 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
48a1b10a YL |
355 | { |
356 | struct irq_cfg *cfg = desc->chip_data; | |
357 | ||
358 | if (!cfg->move_in_progress) { | |
359 | /* it means that domain is not changed */ | |
7f7ace0c | 360 | if (!cpumask_intersects(desc->affinity, mask)) |
48a1b10a YL |
361 | cfg->move_desc_pending = 1; |
362 | } | |
0f978f45 | 363 | } |
48a1b10a YL |
364 | #endif |
365 | ||
0b8f1efa YL |
366 | #else |
367 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
368 | { | |
369 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 370 | } |
1da177e4 | 371 | |
0b8f1efa YL |
372 | #endif |
373 | ||
48a1b10a | 374 | #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC |
e7986739 MT |
375 | static inline void |
376 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
3145e941 YL |
377 | { |
378 | } | |
48a1b10a | 379 | #endif |
1da177e4 | 380 | |
130fe05d LT |
381 | struct io_apic { |
382 | unsigned int index; | |
383 | unsigned int unused[3]; | |
384 | unsigned int data; | |
385 | }; | |
386 | ||
387 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
388 | { | |
389 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
b5ba7e6d | 390 | + (mp_ioapics[idx].apicaddr & ~PAGE_MASK); |
130fe05d LT |
391 | } |
392 | ||
393 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
394 | { | |
395 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
396 | writel(reg, &io_apic->index); | |
397 | return readl(&io_apic->data); | |
398 | } | |
399 | ||
400 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
401 | { | |
402 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
403 | writel(reg, &io_apic->index); | |
404 | writel(value, &io_apic->data); | |
405 | } | |
406 | ||
407 | /* | |
408 | * Re-write a value: to be used for read-modify-write | |
409 | * cycles where the read already set up the index register. | |
410 | * | |
411 | * Older SiS APIC requires we rewrite the index register | |
412 | */ | |
413 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
414 | { | |
54168ed7 | 415 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
416 | |
417 | if (sis_apic_bug) | |
418 | writel(reg, &io_apic->index); | |
130fe05d LT |
419 | writel(value, &io_apic->data); |
420 | } | |
421 | ||
3145e941 | 422 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
423 | { |
424 | struct irq_pin_list *entry; | |
425 | unsigned long flags; | |
047c8fdb YL |
426 | |
427 | spin_lock_irqsave(&ioapic_lock, flags); | |
428 | entry = cfg->irq_2_pin; | |
429 | for (;;) { | |
430 | unsigned int reg; | |
431 | int pin; | |
432 | ||
433 | if (!entry) | |
434 | break; | |
435 | pin = entry->pin; | |
436 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
437 | /* Is the remote IRR bit set? */ | |
438 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
439 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
440 | return true; | |
441 | } | |
442 | if (!entry->next) | |
443 | break; | |
444 | entry = entry->next; | |
445 | } | |
446 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
447 | ||
448 | return false; | |
449 | } | |
047c8fdb | 450 | |
cf4c6a2f AK |
451 | union entry_union { |
452 | struct { u32 w1, w2; }; | |
453 | struct IO_APIC_route_entry entry; | |
454 | }; | |
455 | ||
456 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
457 | { | |
458 | union entry_union eu; | |
459 | unsigned long flags; | |
460 | spin_lock_irqsave(&ioapic_lock, flags); | |
461 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
462 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
463 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
464 | return eu.entry; | |
465 | } | |
466 | ||
f9dadfa7 LT |
467 | /* |
468 | * When we write a new IO APIC routing entry, we need to write the high | |
469 | * word first! If the mask bit in the low word is clear, we will enable | |
470 | * the interrupt, and we need to make sure the entry is fully populated | |
471 | * before that happens. | |
472 | */ | |
d15512f4 AK |
473 | static void |
474 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 475 | { |
cf4c6a2f AK |
476 | union entry_union eu; |
477 | eu.entry = e; | |
f9dadfa7 LT |
478 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
479 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
480 | } |
481 | ||
482 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
483 | { | |
484 | unsigned long flags; | |
485 | spin_lock_irqsave(&ioapic_lock, flags); | |
486 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
487 | spin_unlock_irqrestore(&ioapic_lock, flags); |
488 | } | |
489 | ||
490 | /* | |
491 | * When we mask an IO APIC routing entry, we need to write the low | |
492 | * word first, in order to set the mask bit before we change the | |
493 | * high bits! | |
494 | */ | |
495 | static void ioapic_mask_entry(int apic, int pin) | |
496 | { | |
497 | unsigned long flags; | |
498 | union entry_union eu = { .entry.mask = 1 }; | |
499 | ||
cf4c6a2f AK |
500 | spin_lock_irqsave(&ioapic_lock, flags); |
501 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
502 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
503 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
504 | } | |
505 | ||
497c9a19 | 506 | #ifdef CONFIG_SMP |
22f65d31 MT |
507 | static void send_cleanup_vector(struct irq_cfg *cfg) |
508 | { | |
509 | cpumask_var_t cleanup_mask; | |
510 | ||
511 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
512 | unsigned int i; | |
513 | cfg->move_cleanup_count = 0; | |
514 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
515 | cfg->move_cleanup_count++; | |
516 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
517 | send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
518 | } else { | |
519 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
520 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
521 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
522 | free_cpumask_var(cleanup_mask); | |
523 | } | |
524 | cfg->move_in_progress = 0; | |
525 | } | |
526 | ||
3145e941 | 527 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
528 | { |
529 | int apic, pin; | |
497c9a19 | 530 | struct irq_pin_list *entry; |
3145e941 | 531 | u8 vector = cfg->vector; |
497c9a19 | 532 | |
497c9a19 YL |
533 | entry = cfg->irq_2_pin; |
534 | for (;;) { | |
535 | unsigned int reg; | |
536 | ||
537 | if (!entry) | |
538 | break; | |
539 | ||
540 | apic = entry->apic; | |
541 | pin = entry->pin; | |
54168ed7 IM |
542 | #ifdef CONFIG_INTR_REMAP |
543 | /* | |
544 | * With interrupt-remapping, destination information comes | |
545 | * from interrupt-remapping table entry. | |
546 | */ | |
547 | if (!irq_remapped(irq)) | |
548 | io_apic_write(apic, 0x11 + pin*2, dest); | |
549 | #else | |
497c9a19 | 550 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 551 | #endif |
497c9a19 YL |
552 | reg = io_apic_read(apic, 0x10 + pin*2); |
553 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
554 | reg |= vector; | |
54168ed7 | 555 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
556 | if (!entry->next) |
557 | break; | |
558 | entry = entry->next; | |
559 | } | |
560 | } | |
efa2559f | 561 | |
e7986739 MT |
562 | static int |
563 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
efa2559f | 564 | |
22f65d31 MT |
565 | /* |
566 | * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid | |
567 | * of that, or returns BAD_APICID and leaves desc->affinity untouched. | |
568 | */ | |
569 | static unsigned int | |
570 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
571 | { |
572 | struct irq_cfg *cfg; | |
3145e941 | 573 | unsigned int irq; |
497c9a19 | 574 | |
0de26520 | 575 | if (!cpumask_intersects(mask, cpu_online_mask)) |
22f65d31 | 576 | return BAD_APICID; |
497c9a19 | 577 | |
3145e941 YL |
578 | irq = desc->irq; |
579 | cfg = desc->chip_data; | |
580 | if (assign_irq_vector(irq, cfg, mask)) | |
22f65d31 | 581 | return BAD_APICID; |
497c9a19 | 582 | |
7f7ace0c | 583 | cpumask_and(desc->affinity, cfg->domain, mask); |
3145e941 | 584 | set_extra_move_desc(desc, mask); |
7f7ace0c | 585 | return cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask); |
22f65d31 | 586 | } |
3145e941 | 587 | |
22f65d31 MT |
588 | static void |
589 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
590 | { |
591 | struct irq_cfg *cfg; | |
592 | unsigned long flags; | |
593 | unsigned int dest; | |
22f65d31 | 594 | unsigned int irq; |
497c9a19 | 595 | |
22f65d31 MT |
596 | irq = desc->irq; |
597 | cfg = desc->chip_data; | |
497c9a19 | 598 | |
497c9a19 | 599 | spin_lock_irqsave(&ioapic_lock, flags); |
22f65d31 MT |
600 | dest = set_desc_affinity(desc, mask); |
601 | if (dest != BAD_APICID) { | |
602 | /* Only the high 8 bits are valid. */ | |
603 | dest = SET_APIC_LOGICAL_ID(dest); | |
604 | __target_IO_APIC_irq(irq, dest, cfg); | |
605 | } | |
497c9a19 YL |
606 | spin_unlock_irqrestore(&ioapic_lock, flags); |
607 | } | |
497c9a19 | 608 | |
22f65d31 MT |
609 | static void |
610 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) | |
3145e941 YL |
611 | { |
612 | struct irq_desc *desc; | |
497c9a19 | 613 | |
54168ed7 | 614 | desc = irq_to_desc(irq); |
3145e941 YL |
615 | |
616 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 617 | } |
497c9a19 YL |
618 | #endif /* CONFIG_SMP */ |
619 | ||
1da177e4 LT |
620 | /* |
621 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
622 | * shared ISA-space IRQs, so we have to support them. We are super | |
623 | * fast in the common case, and fast for shared ISA-space IRQs. | |
624 | */ | |
3145e941 | 625 | static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin) |
1da177e4 | 626 | { |
0f978f45 YL |
627 | struct irq_pin_list *entry; |
628 | ||
0f978f45 YL |
629 | entry = cfg->irq_2_pin; |
630 | if (!entry) { | |
0b8f1efa YL |
631 | entry = get_one_free_irq_2_pin(cpu); |
632 | if (!entry) { | |
633 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
634 | apic, pin); | |
635 | return; | |
636 | } | |
0f978f45 YL |
637 | cfg->irq_2_pin = entry; |
638 | entry->apic = apic; | |
639 | entry->pin = pin; | |
0f978f45 YL |
640 | return; |
641 | } | |
1da177e4 | 642 | |
0f978f45 YL |
643 | while (entry->next) { |
644 | /* not again, please */ | |
645 | if (entry->apic == apic && entry->pin == pin) | |
646 | return; | |
1da177e4 | 647 | |
0f978f45 | 648 | entry = entry->next; |
1da177e4 | 649 | } |
0f978f45 | 650 | |
0b8f1efa | 651 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 652 | entry = entry->next; |
1da177e4 LT |
653 | entry->apic = apic; |
654 | entry->pin = pin; | |
655 | } | |
656 | ||
657 | /* | |
658 | * Reroute an IRQ to a different pin. | |
659 | */ | |
3145e941 | 660 | static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu, |
1da177e4 LT |
661 | int oldapic, int oldpin, |
662 | int newapic, int newpin) | |
663 | { | |
0f978f45 YL |
664 | struct irq_pin_list *entry = cfg->irq_2_pin; |
665 | int replaced = 0; | |
1da177e4 | 666 | |
0f978f45 | 667 | while (entry) { |
1da177e4 LT |
668 | if (entry->apic == oldapic && entry->pin == oldpin) { |
669 | entry->apic = newapic; | |
670 | entry->pin = newpin; | |
0f978f45 YL |
671 | replaced = 1; |
672 | /* every one is different, right? */ | |
1da177e4 | 673 | break; |
0f978f45 YL |
674 | } |
675 | entry = entry->next; | |
1da177e4 | 676 | } |
0f978f45 YL |
677 | |
678 | /* why? call replace before add? */ | |
679 | if (!replaced) | |
3145e941 | 680 | add_pin_to_irq_cpu(cfg, cpu, newapic, newpin); |
1da177e4 LT |
681 | } |
682 | ||
3145e941 | 683 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
684 | int mask_and, int mask_or, |
685 | void (*final)(struct irq_pin_list *entry)) | |
686 | { | |
687 | int pin; | |
87783be4 | 688 | struct irq_pin_list *entry; |
047c8fdb | 689 | |
87783be4 CG |
690 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
691 | unsigned int reg; | |
692 | pin = entry->pin; | |
693 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
694 | reg &= mask_and; | |
695 | reg |= mask_or; | |
696 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
697 | if (final) | |
698 | final(entry); | |
699 | } | |
700 | } | |
047c8fdb | 701 | |
3145e941 | 702 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 703 | { |
3145e941 | 704 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 705 | } |
047c8fdb | 706 | |
4e738e2f | 707 | #ifdef CONFIG_X86_64 |
7f3e632f | 708 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 709 | { |
87783be4 CG |
710 | /* |
711 | * Synchronize the IO-APIC and the CPU by doing | |
712 | * a dummy read from the IO-APIC | |
713 | */ | |
714 | struct io_apic __iomem *io_apic; | |
715 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 716 | readl(&io_apic->data); |
1da177e4 LT |
717 | } |
718 | ||
3145e941 | 719 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 720 | { |
3145e941 | 721 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
722 | } |
723 | #else /* CONFIG_X86_32 */ | |
3145e941 | 724 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 725 | { |
3145e941 | 726 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 727 | } |
1da177e4 | 728 | |
3145e941 | 729 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 730 | { |
3145e941 | 731 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
732 | IO_APIC_REDIR_MASKED, NULL); |
733 | } | |
1da177e4 | 734 | |
3145e941 | 735 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 736 | { |
3145e941 | 737 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
738 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
739 | } | |
740 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 741 | |
3145e941 | 742 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 743 | { |
3145e941 | 744 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
745 | unsigned long flags; |
746 | ||
3145e941 YL |
747 | BUG_ON(!cfg); |
748 | ||
1da177e4 | 749 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 750 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
751 | spin_unlock_irqrestore(&ioapic_lock, flags); |
752 | } | |
753 | ||
3145e941 | 754 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 755 | { |
3145e941 | 756 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
757 | unsigned long flags; |
758 | ||
759 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 760 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
761 | spin_unlock_irqrestore(&ioapic_lock, flags); |
762 | } | |
763 | ||
3145e941 YL |
764 | static void mask_IO_APIC_irq(unsigned int irq) |
765 | { | |
766 | struct irq_desc *desc = irq_to_desc(irq); | |
767 | ||
768 | mask_IO_APIC_irq_desc(desc); | |
769 | } | |
770 | static void unmask_IO_APIC_irq(unsigned int irq) | |
771 | { | |
772 | struct irq_desc *desc = irq_to_desc(irq); | |
773 | ||
774 | unmask_IO_APIC_irq_desc(desc); | |
775 | } | |
776 | ||
1da177e4 LT |
777 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
778 | { | |
779 | struct IO_APIC_route_entry entry; | |
36062448 | 780 | |
1da177e4 | 781 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 782 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
783 | if (entry.delivery_mode == dest_SMI) |
784 | return; | |
1da177e4 LT |
785 | /* |
786 | * Disable it in the IO-APIC irq-routing table: | |
787 | */ | |
f9dadfa7 | 788 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
789 | } |
790 | ||
54168ed7 | 791 | static void clear_IO_APIC (void) |
1da177e4 LT |
792 | { |
793 | int apic, pin; | |
794 | ||
795 | for (apic = 0; apic < nr_ioapics; apic++) | |
796 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
797 | clear_IO_APIC_pin(apic, pin); | |
798 | } | |
799 | ||
54168ed7 | 800 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 801 | void send_IPI_self(int vector) |
1da177e4 LT |
802 | { |
803 | unsigned int cfg; | |
804 | ||
805 | /* | |
806 | * Wait for idle. | |
807 | */ | |
808 | apic_wait_icr_idle(); | |
809 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
810 | /* | |
811 | * Send the IPI. The write to APIC_ICR fires this off. | |
812 | */ | |
593f4a78 | 813 | apic_write(APIC_ICR, cfg); |
1da177e4 | 814 | } |
54168ed7 | 815 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 816 | |
54168ed7 | 817 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
818 | /* |
819 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
820 | * specific CPU-side IRQs. | |
821 | */ | |
822 | ||
823 | #define MAX_PIRQS 8 | |
824 | static int pirq_entries [MAX_PIRQS]; | |
825 | static int pirqs_enabled; | |
1da177e4 | 826 | |
1da177e4 LT |
827 | static int __init ioapic_pirq_setup(char *str) |
828 | { | |
829 | int i, max; | |
830 | int ints[MAX_PIRQS+1]; | |
831 | ||
832 | get_options(str, ARRAY_SIZE(ints), ints); | |
833 | ||
834 | for (i = 0; i < MAX_PIRQS; i++) | |
835 | pirq_entries[i] = -1; | |
836 | ||
837 | pirqs_enabled = 1; | |
838 | apic_printk(APIC_VERBOSE, KERN_INFO | |
839 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
840 | max = MAX_PIRQS; | |
841 | if (ints[0] < MAX_PIRQS) | |
842 | max = ints[0]; | |
843 | ||
844 | for (i = 0; i < max; i++) { | |
845 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
846 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
847 | /* | |
848 | * PIRQs are mapped upside down, usually. | |
849 | */ | |
850 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
851 | } | |
852 | return 1; | |
853 | } | |
854 | ||
855 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
856 | #endif /* CONFIG_X86_32 */ |
857 | ||
858 | #ifdef CONFIG_INTR_REMAP | |
859 | /* I/O APIC RTE contents at the OS boot up */ | |
860 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
861 | ||
862 | /* | |
863 | * Saves and masks all the unmasked IO-APIC RTE's | |
864 | */ | |
865 | int save_mask_IO_APIC_setup(void) | |
866 | { | |
867 | union IO_APIC_reg_01 reg_01; | |
868 | unsigned long flags; | |
869 | int apic, pin; | |
870 | ||
871 | /* | |
872 | * The number of IO-APIC IRQ registers (== #pins): | |
873 | */ | |
874 | for (apic = 0; apic < nr_ioapics; apic++) { | |
875 | spin_lock_irqsave(&ioapic_lock, flags); | |
876 | reg_01.raw = io_apic_read(apic, 1); | |
877 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
878 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
879 | } | |
880 | ||
881 | for (apic = 0; apic < nr_ioapics; apic++) { | |
882 | early_ioapic_entries[apic] = | |
883 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
884 | nr_ioapic_registers[apic], GFP_KERNEL); | |
885 | if (!early_ioapic_entries[apic]) | |
5ffa4eb2 | 886 | goto nomem; |
54168ed7 IM |
887 | } |
888 | ||
889 | for (apic = 0; apic < nr_ioapics; apic++) | |
890 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
891 | struct IO_APIC_route_entry entry; | |
892 | ||
893 | entry = early_ioapic_entries[apic][pin] = | |
894 | ioapic_read_entry(apic, pin); | |
895 | if (!entry.mask) { | |
896 | entry.mask = 1; | |
897 | ioapic_write_entry(apic, pin, entry); | |
898 | } | |
899 | } | |
5ffa4eb2 | 900 | |
54168ed7 | 901 | return 0; |
5ffa4eb2 CG |
902 | |
903 | nomem: | |
c1370b49 CG |
904 | while (apic >= 0) |
905 | kfree(early_ioapic_entries[apic--]); | |
5ffa4eb2 CG |
906 | memset(early_ioapic_entries, 0, |
907 | ARRAY_SIZE(early_ioapic_entries)); | |
908 | ||
909 | return -ENOMEM; | |
54168ed7 IM |
910 | } |
911 | ||
912 | void restore_IO_APIC_setup(void) | |
913 | { | |
914 | int apic, pin; | |
915 | ||
5ffa4eb2 CG |
916 | for (apic = 0; apic < nr_ioapics; apic++) { |
917 | if (!early_ioapic_entries[apic]) | |
918 | break; | |
54168ed7 IM |
919 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
920 | ioapic_write_entry(apic, pin, | |
921 | early_ioapic_entries[apic][pin]); | |
5ffa4eb2 CG |
922 | kfree(early_ioapic_entries[apic]); |
923 | early_ioapic_entries[apic] = NULL; | |
924 | } | |
54168ed7 IM |
925 | } |
926 | ||
927 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
928 | { | |
929 | /* | |
930 | * for now plain restore of previous settings. | |
931 | * TBD: In the case of OS enabling interrupt-remapping, | |
932 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
933 | * table entries. for now, do a plain restore, and wait for | |
934 | * the setup_IO_APIC_irqs() to do proper initialization. | |
935 | */ | |
936 | restore_IO_APIC_setup(); | |
937 | } | |
938 | #endif | |
1da177e4 LT |
939 | |
940 | /* | |
941 | * Find the IRQ entry number of a certain pin. | |
942 | */ | |
943 | static int find_irq_entry(int apic, int pin, int type) | |
944 | { | |
945 | int i; | |
946 | ||
947 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
948 | if (mp_irqs[i].irqtype == type && |
949 | (mp_irqs[i].dstapic == mp_ioapics[apic].apicid || | |
950 | mp_irqs[i].dstapic == MP_APIC_ALL) && | |
951 | mp_irqs[i].dstirq == pin) | |
1da177e4 LT |
952 | return i; |
953 | ||
954 | return -1; | |
955 | } | |
956 | ||
957 | /* | |
958 | * Find the pin to which IRQ[irq] (ISA) is connected | |
959 | */ | |
fcfd636a | 960 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
961 | { |
962 | int i; | |
963 | ||
964 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 965 | int lbus = mp_irqs[i].srcbus; |
1da177e4 | 966 | |
d27e2b8e | 967 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
968 | (mp_irqs[i].irqtype == type) && |
969 | (mp_irqs[i].srcbusirq == irq)) | |
1da177e4 | 970 | |
c2c21745 | 971 | return mp_irqs[i].dstirq; |
1da177e4 LT |
972 | } |
973 | return -1; | |
974 | } | |
975 | ||
fcfd636a EB |
976 | static int __init find_isa_irq_apic(int irq, int type) |
977 | { | |
978 | int i; | |
979 | ||
980 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 981 | int lbus = mp_irqs[i].srcbus; |
fcfd636a | 982 | |
73b2961b | 983 | if (test_bit(lbus, mp_bus_not_pci) && |
c2c21745 JSR |
984 | (mp_irqs[i].irqtype == type) && |
985 | (mp_irqs[i].srcbusirq == irq)) | |
fcfd636a EB |
986 | break; |
987 | } | |
988 | if (i < mp_irq_entries) { | |
989 | int apic; | |
54168ed7 | 990 | for(apic = 0; apic < nr_ioapics; apic++) { |
c2c21745 | 991 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic) |
fcfd636a EB |
992 | return apic; |
993 | } | |
994 | } | |
995 | ||
996 | return -1; | |
997 | } | |
998 | ||
1da177e4 LT |
999 | /* |
1000 | * Find a specific PCI IRQ entry. | |
1001 | * Not an __init, possibly needed by modules | |
1002 | */ | |
1003 | static int pin_2_irq(int idx, int apic, int pin); | |
1004 | ||
1005 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
1006 | { | |
1007 | int apic, i, best_guess = -1; | |
1008 | ||
54168ed7 IM |
1009 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
1010 | bus, slot, pin); | |
ce6444d3 | 1011 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 1012 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
1013 | return -1; |
1014 | } | |
1015 | for (i = 0; i < mp_irq_entries; i++) { | |
c2c21745 | 1016 | int lbus = mp_irqs[i].srcbus; |
1da177e4 LT |
1017 | |
1018 | for (apic = 0; apic < nr_ioapics; apic++) | |
c2c21745 JSR |
1019 | if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic || |
1020 | mp_irqs[i].dstapic == MP_APIC_ALL) | |
1da177e4 LT |
1021 | break; |
1022 | ||
47cab822 | 1023 | if (!test_bit(lbus, mp_bus_not_pci) && |
c2c21745 | 1024 | !mp_irqs[i].irqtype && |
1da177e4 | 1025 | (bus == lbus) && |
c2c21745 JSR |
1026 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { |
1027 | int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); | |
1da177e4 LT |
1028 | |
1029 | if (!(apic || IO_APIC_IRQ(irq))) | |
1030 | continue; | |
1031 | ||
c2c21745 | 1032 | if (pin == (mp_irqs[i].srcbusirq & 3)) |
1da177e4 LT |
1033 | return irq; |
1034 | /* | |
1035 | * Use the first all-but-pin matching entry as a | |
1036 | * best-guess fuzzy result for broken mptables. | |
1037 | */ | |
1038 | if (best_guess < 0) | |
1039 | best_guess = irq; | |
1040 | } | |
1041 | } | |
1042 | return best_guess; | |
1043 | } | |
54168ed7 | 1044 | |
129f6946 | 1045 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 1046 | |
c0a282c2 | 1047 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1048 | /* |
1049 | * EISA Edge/Level control register, ELCR | |
1050 | */ | |
1051 | static int EISA_ELCR(unsigned int irq) | |
1052 | { | |
99d093d1 | 1053 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
1054 | unsigned int port = 0x4d0 + (irq >> 3); |
1055 | return (inb(port) >> (irq & 7)) & 1; | |
1056 | } | |
1057 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1058 | "Broken MPtable reports ISA irq %d\n", irq); | |
1059 | return 0; | |
1060 | } | |
54168ed7 | 1061 | |
c0a282c2 | 1062 | #endif |
1da177e4 | 1063 | |
6728801d AS |
1064 | /* ISA interrupts are always polarity zero edge triggered, |
1065 | * when listed as conforming in the MP table. */ | |
1066 | ||
1067 | #define default_ISA_trigger(idx) (0) | |
1068 | #define default_ISA_polarity(idx) (0) | |
1069 | ||
1da177e4 LT |
1070 | /* EISA interrupts are always polarity zero and can be edge or level |
1071 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1072 | * EISA conforming in the MP table, that means its trigger type must | |
1073 | * be read in from the ELCR */ | |
1074 | ||
c2c21745 | 1075 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
6728801d | 1076 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1077 | |
1078 | /* PCI interrupts are always polarity one level triggered, | |
1079 | * when listed as conforming in the MP table. */ | |
1080 | ||
1081 | #define default_PCI_trigger(idx) (1) | |
1082 | #define default_PCI_polarity(idx) (1) | |
1083 | ||
1084 | /* MCA interrupts are always polarity zero level triggered, | |
1085 | * when listed as conforming in the MP table. */ | |
1086 | ||
1087 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1088 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1089 | |
61fd47e0 | 1090 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1091 | { |
c2c21745 | 1092 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1093 | int polarity; |
1094 | ||
1095 | /* | |
1096 | * Determine IRQ line polarity (high active or low active): | |
1097 | */ | |
c2c21745 | 1098 | switch (mp_irqs[idx].irqflag & 3) |
36062448 | 1099 | { |
54168ed7 IM |
1100 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1101 | if (test_bit(bus, mp_bus_not_pci)) | |
1102 | polarity = default_ISA_polarity(idx); | |
1103 | else | |
1104 | polarity = default_PCI_polarity(idx); | |
1105 | break; | |
1106 | case 1: /* high active */ | |
1107 | { | |
1108 | polarity = 0; | |
1109 | break; | |
1110 | } | |
1111 | case 2: /* reserved */ | |
1112 | { | |
1113 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1114 | polarity = 1; | |
1115 | break; | |
1116 | } | |
1117 | case 3: /* low active */ | |
1118 | { | |
1119 | polarity = 1; | |
1120 | break; | |
1121 | } | |
1122 | default: /* invalid */ | |
1123 | { | |
1124 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1125 | polarity = 1; | |
1126 | break; | |
1127 | } | |
1da177e4 LT |
1128 | } |
1129 | return polarity; | |
1130 | } | |
1131 | ||
1132 | static int MPBIOS_trigger(int idx) | |
1133 | { | |
c2c21745 | 1134 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1135 | int trigger; |
1136 | ||
1137 | /* | |
1138 | * Determine IRQ trigger mode (edge or level sensitive): | |
1139 | */ | |
c2c21745 | 1140 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
1da177e4 | 1141 | { |
54168ed7 IM |
1142 | case 0: /* conforms, ie. bus-type dependent */ |
1143 | if (test_bit(bus, mp_bus_not_pci)) | |
1144 | trigger = default_ISA_trigger(idx); | |
1145 | else | |
1146 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1147 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1148 | switch (mp_bus_id_to_type[bus]) { |
1149 | case MP_BUS_ISA: /* ISA pin */ | |
1150 | { | |
1151 | /* set before the switch */ | |
1152 | break; | |
1153 | } | |
1154 | case MP_BUS_EISA: /* EISA pin */ | |
1155 | { | |
1156 | trigger = default_EISA_trigger(idx); | |
1157 | break; | |
1158 | } | |
1159 | case MP_BUS_PCI: /* PCI pin */ | |
1160 | { | |
1161 | /* set before the switch */ | |
1162 | break; | |
1163 | } | |
1164 | case MP_BUS_MCA: /* MCA pin */ | |
1165 | { | |
1166 | trigger = default_MCA_trigger(idx); | |
1167 | break; | |
1168 | } | |
1169 | default: | |
1170 | { | |
1171 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1172 | trigger = 1; | |
1173 | break; | |
1174 | } | |
1175 | } | |
1176 | #endif | |
1da177e4 | 1177 | break; |
54168ed7 | 1178 | case 1: /* edge */ |
1da177e4 | 1179 | { |
54168ed7 | 1180 | trigger = 0; |
1da177e4 LT |
1181 | break; |
1182 | } | |
54168ed7 | 1183 | case 2: /* reserved */ |
1da177e4 | 1184 | { |
54168ed7 IM |
1185 | printk(KERN_WARNING "broken BIOS!!\n"); |
1186 | trigger = 1; | |
1da177e4 LT |
1187 | break; |
1188 | } | |
54168ed7 | 1189 | case 3: /* level */ |
1da177e4 | 1190 | { |
54168ed7 | 1191 | trigger = 1; |
1da177e4 LT |
1192 | break; |
1193 | } | |
54168ed7 | 1194 | default: /* invalid */ |
1da177e4 LT |
1195 | { |
1196 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1197 | trigger = 0; |
1da177e4 LT |
1198 | break; |
1199 | } | |
1200 | } | |
1201 | return trigger; | |
1202 | } | |
1203 | ||
1204 | static inline int irq_polarity(int idx) | |
1205 | { | |
1206 | return MPBIOS_polarity(idx); | |
1207 | } | |
1208 | ||
1209 | static inline int irq_trigger(int idx) | |
1210 | { | |
1211 | return MPBIOS_trigger(idx); | |
1212 | } | |
1213 | ||
efa2559f | 1214 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1215 | static int pin_2_irq(int idx, int apic, int pin) |
1216 | { | |
1217 | int irq, i; | |
c2c21745 | 1218 | int bus = mp_irqs[idx].srcbus; |
1da177e4 LT |
1219 | |
1220 | /* | |
1221 | * Debugging check, we are in big trouble if this message pops up! | |
1222 | */ | |
c2c21745 | 1223 | if (mp_irqs[idx].dstirq != pin) |
1da177e4 LT |
1224 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1225 | ||
54168ed7 | 1226 | if (test_bit(bus, mp_bus_not_pci)) { |
c2c21745 | 1227 | irq = mp_irqs[idx].srcbusirq; |
54168ed7 | 1228 | } else { |
643befed AS |
1229 | /* |
1230 | * PCI IRQs are mapped in order | |
1231 | */ | |
1232 | i = irq = 0; | |
1233 | while (i < apic) | |
1234 | irq += nr_ioapic_registers[i++]; | |
1235 | irq += pin; | |
d6c88a50 | 1236 | /* |
54168ed7 IM |
1237 | * For MPS mode, so far only needed by ES7000 platform |
1238 | */ | |
d6c88a50 TG |
1239 | if (ioapic_renumber_irq) |
1240 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1241 | } |
1242 | ||
54168ed7 | 1243 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1244 | /* |
1245 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1246 | */ | |
1247 | if ((pin >= 16) && (pin <= 23)) { | |
1248 | if (pirq_entries[pin-16] != -1) { | |
1249 | if (!pirq_entries[pin-16]) { | |
1250 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1251 | "disabling PIRQ%d\n", pin-16); | |
1252 | } else { | |
1253 | irq = pirq_entries[pin-16]; | |
1254 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1255 | "using PIRQ%d -> IRQ %d\n", | |
1256 | pin-16, irq); | |
1257 | } | |
1258 | } | |
1259 | } | |
54168ed7 IM |
1260 | #endif |
1261 | ||
1da177e4 LT |
1262 | return irq; |
1263 | } | |
1264 | ||
497c9a19 YL |
1265 | void lock_vector_lock(void) |
1266 | { | |
1267 | /* Used to the online set of cpus does not change | |
1268 | * during assign_irq_vector. | |
1269 | */ | |
1270 | spin_lock(&vector_lock); | |
1271 | } | |
1da177e4 | 1272 | |
497c9a19 | 1273 | void unlock_vector_lock(void) |
1da177e4 | 1274 | { |
497c9a19 YL |
1275 | spin_unlock(&vector_lock); |
1276 | } | |
1da177e4 | 1277 | |
e7986739 MT |
1278 | static int |
1279 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1280 | { |
047c8fdb YL |
1281 | /* |
1282 | * NOTE! The local APIC isn't very good at handling | |
1283 | * multiple interrupts at the same interrupt level. | |
1284 | * As the interrupt level is determined by taking the | |
1285 | * vector number and shifting that right by 4, we | |
1286 | * want to spread these out a bit so that they don't | |
1287 | * all fall in the same interrupt level. | |
1288 | * | |
1289 | * Also, we've got to be careful not to trash gate | |
1290 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1291 | */ | |
54168ed7 IM |
1292 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1293 | unsigned int old_vector; | |
22f65d31 MT |
1294 | int cpu, err; |
1295 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1296 | |
54168ed7 IM |
1297 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1298 | return -EBUSY; | |
0a1ad60d | 1299 | |
22f65d31 MT |
1300 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1301 | return -ENOMEM; | |
ace80ab7 | 1302 | |
54168ed7 IM |
1303 | old_vector = cfg->vector; |
1304 | if (old_vector) { | |
22f65d31 MT |
1305 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1306 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1307 | if (!cpumask_empty(tmp_mask)) { | |
1308 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1309 | return 0; |
22f65d31 | 1310 | } |
54168ed7 | 1311 | } |
497c9a19 | 1312 | |
e7986739 | 1313 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1314 | err = -ENOSPC; |
1315 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1316 | int new_cpu; |
1317 | int vector, offset; | |
497c9a19 | 1318 | |
22f65d31 | 1319 | vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1320 | |
54168ed7 IM |
1321 | vector = current_vector; |
1322 | offset = current_offset; | |
497c9a19 | 1323 | next: |
54168ed7 IM |
1324 | vector += 8; |
1325 | if (vector >= first_system_vector) { | |
e7986739 | 1326 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1327 | offset = (offset + 1) % 8; |
1328 | vector = FIRST_DEVICE_VECTOR + offset; | |
1329 | } | |
1330 | if (unlikely(current_vector == vector)) | |
1331 | continue; | |
b77b881f YL |
1332 | |
1333 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1334 | goto next; |
b77b881f | 1335 | |
22f65d31 | 1336 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1337 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1338 | goto next; | |
1339 | /* Found one! */ | |
1340 | current_vector = vector; | |
1341 | current_offset = offset; | |
1342 | if (old_vector) { | |
1343 | cfg->move_in_progress = 1; | |
22f65d31 | 1344 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1345 | } |
22f65d31 | 1346 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1347 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1348 | cfg->vector = vector; | |
22f65d31 MT |
1349 | cpumask_copy(cfg->domain, tmp_mask); |
1350 | err = 0; | |
1351 | break; | |
54168ed7 | 1352 | } |
22f65d31 MT |
1353 | free_cpumask_var(tmp_mask); |
1354 | return err; | |
497c9a19 YL |
1355 | } |
1356 | ||
e7986739 MT |
1357 | static int |
1358 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1359 | { |
1360 | int err; | |
ace80ab7 | 1361 | unsigned long flags; |
ace80ab7 EB |
1362 | |
1363 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1364 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1365 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1366 | return err; |
1367 | } | |
1368 | ||
3145e941 | 1369 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1370 | { |
497c9a19 YL |
1371 | int cpu, vector; |
1372 | ||
497c9a19 YL |
1373 | BUG_ON(!cfg->vector); |
1374 | ||
1375 | vector = cfg->vector; | |
22f65d31 | 1376 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1377 | per_cpu(vector_irq, cpu)[vector] = -1; |
1378 | ||
1379 | cfg->vector = 0; | |
22f65d31 | 1380 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1381 | |
1382 | if (likely(!cfg->move_in_progress)) | |
1383 | return; | |
22f65d31 | 1384 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1385 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1386 | vector++) { | |
1387 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1388 | continue; | |
1389 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1390 | break; | |
1391 | } | |
1392 | } | |
1393 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1394 | } |
1395 | ||
1396 | void __setup_vector_irq(int cpu) | |
1397 | { | |
1398 | /* Initialize vector_irq on a new cpu */ | |
1399 | /* This function must be called with vector_lock held */ | |
1400 | int irq, vector; | |
1401 | struct irq_cfg *cfg; | |
0b8f1efa | 1402 | struct irq_desc *desc; |
497c9a19 YL |
1403 | |
1404 | /* Mark the inuse vectors */ | |
0b8f1efa | 1405 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1406 | cfg = desc->chip_data; |
22f65d31 | 1407 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1408 | continue; |
1409 | vector = cfg->vector; | |
497c9a19 YL |
1410 | per_cpu(vector_irq, cpu)[vector] = irq; |
1411 | } | |
1412 | /* Mark the free vectors */ | |
1413 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1414 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1415 | if (irq < 0) | |
1416 | continue; | |
1417 | ||
1418 | cfg = irq_cfg(irq); | |
22f65d31 | 1419 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1420 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1421 | } |
1da177e4 | 1422 | } |
3fde6900 | 1423 | |
f5b9ed7a | 1424 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1425 | #ifdef CONFIG_INTR_REMAP |
1426 | static struct irq_chip ir_ioapic_chip; | |
1427 | #endif | |
1da177e4 | 1428 | |
54168ed7 IM |
1429 | #define IOAPIC_AUTO -1 |
1430 | #define IOAPIC_EDGE 0 | |
1431 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1432 | |
047c8fdb | 1433 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1434 | static inline int IO_APIC_irq_trigger(int irq) |
1435 | { | |
d6c88a50 | 1436 | int apic, idx, pin; |
1d025192 | 1437 | |
d6c88a50 TG |
1438 | for (apic = 0; apic < nr_ioapics; apic++) { |
1439 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1440 | idx = find_irq_entry(apic, pin, mp_INT); | |
1441 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1442 | return irq_trigger(idx); | |
1443 | } | |
1444 | } | |
1445 | /* | |
54168ed7 IM |
1446 | * nonexistent IRQs are edge default |
1447 | */ | |
d6c88a50 | 1448 | return 0; |
1d025192 | 1449 | } |
047c8fdb YL |
1450 | #else |
1451 | static inline int IO_APIC_irq_trigger(int irq) | |
1452 | { | |
54168ed7 | 1453 | return 1; |
047c8fdb YL |
1454 | } |
1455 | #endif | |
1d025192 | 1456 | |
3145e941 | 1457 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1458 | { |
199751d7 | 1459 | |
6ebcc00e | 1460 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1461 | trigger == IOAPIC_LEVEL) |
08678b08 | 1462 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1463 | else |
1464 | desc->status &= ~IRQ_LEVEL; | |
1465 | ||
54168ed7 IM |
1466 | #ifdef CONFIG_INTR_REMAP |
1467 | if (irq_remapped(irq)) { | |
1468 | desc->status |= IRQ_MOVE_PCNTXT; | |
1469 | if (trigger) | |
1470 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1471 | handle_fasteoi_irq, | |
1472 | "fasteoi"); | |
1473 | else | |
1474 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1475 | handle_edge_irq, "edge"); | |
1476 | return; | |
1477 | } | |
1478 | #endif | |
047c8fdb YL |
1479 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1480 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1481 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1482 | handle_fasteoi_irq, |
1483 | "fasteoi"); | |
047c8fdb | 1484 | else |
a460e745 | 1485 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1486 | handle_edge_irq, "edge"); |
1da177e4 LT |
1487 | } |
1488 | ||
c8d46cf0 | 1489 | static int setup_ioapic_entry(int apic_id, int irq, |
497c9a19 YL |
1490 | struct IO_APIC_route_entry *entry, |
1491 | unsigned int destination, int trigger, | |
1492 | int polarity, int vector) | |
1da177e4 | 1493 | { |
497c9a19 YL |
1494 | /* |
1495 | * add it to the IO-APIC irq-routing table: | |
1496 | */ | |
1497 | memset(entry,0,sizeof(*entry)); | |
1498 | ||
54168ed7 IM |
1499 | #ifdef CONFIG_INTR_REMAP |
1500 | if (intr_remapping_enabled) { | |
c8d46cf0 | 1501 | struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); |
54168ed7 IM |
1502 | struct irte irte; |
1503 | struct IR_IO_APIC_route_entry *ir_entry = | |
1504 | (struct IR_IO_APIC_route_entry *) entry; | |
1505 | int index; | |
1506 | ||
1507 | if (!iommu) | |
c8d46cf0 | 1508 | panic("No mapping iommu for ioapic %d\n", apic_id); |
54168ed7 IM |
1509 | |
1510 | index = alloc_irte(iommu, irq, 1); | |
1511 | if (index < 0) | |
c8d46cf0 | 1512 | panic("Failed to allocate IRTE for ioapic %d\n", apic_id); |
54168ed7 IM |
1513 | |
1514 | memset(&irte, 0, sizeof(irte)); | |
1515 | ||
1516 | irte.present = 1; | |
9b5bc8dc | 1517 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 1518 | irte.trigger_mode = trigger; |
9b5bc8dc | 1519 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
1520 | irte.vector = vector; |
1521 | irte.dest_id = IRTE_DEST(destination); | |
1522 | ||
1523 | modify_irte(irq, &irte); | |
1524 | ||
1525 | ir_entry->index2 = (index >> 15) & 0x1; | |
1526 | ir_entry->zero = 0; | |
1527 | ir_entry->format = 1; | |
1528 | ir_entry->index = (index & 0x7fff); | |
1529 | } else | |
1530 | #endif | |
1531 | { | |
9b5bc8dc IM |
1532 | entry->delivery_mode = apic->irq_delivery_mode; |
1533 | entry->dest_mode = apic->irq_dest_mode; | |
54168ed7 IM |
1534 | entry->dest = destination; |
1535 | } | |
497c9a19 | 1536 | |
54168ed7 | 1537 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1538 | entry->trigger = trigger; |
1539 | entry->polarity = polarity; | |
1540 | entry->vector = vector; | |
1541 | ||
1542 | /* Mask level triggered irqs. | |
1543 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1544 | */ | |
1545 | if (trigger) | |
1546 | entry->mask = 1; | |
497c9a19 YL |
1547 | return 0; |
1548 | } | |
1549 | ||
c8d46cf0 | 1550 | static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1551 | int trigger, int polarity) |
497c9a19 YL |
1552 | { |
1553 | struct irq_cfg *cfg; | |
1da177e4 | 1554 | struct IO_APIC_route_entry entry; |
22f65d31 | 1555 | unsigned int dest; |
497c9a19 YL |
1556 | |
1557 | if (!IO_APIC_IRQ(irq)) | |
1558 | return; | |
1559 | ||
3145e941 | 1560 | cfg = desc->chip_data; |
497c9a19 | 1561 | |
22f65d31 | 1562 | if (assign_irq_vector(irq, cfg, TARGET_CPUS)) |
497c9a19 YL |
1563 | return; |
1564 | ||
22f65d31 | 1565 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
497c9a19 YL |
1566 | |
1567 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1568 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1569 | "IRQ %d Mode:%i Active:%i)\n", | |
c8d46cf0 | 1570 | apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector, |
497c9a19 YL |
1571 | irq, trigger, polarity); |
1572 | ||
1573 | ||
c8d46cf0 | 1574 | if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry, |
22f65d31 | 1575 | dest, trigger, polarity, cfg->vector)) { |
497c9a19 | 1576 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
c8d46cf0 | 1577 | mp_ioapics[apic_id].apicid, pin); |
3145e941 | 1578 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1579 | return; |
1580 | } | |
1581 | ||
3145e941 | 1582 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1583 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1584 | disable_8259A_irq(irq); |
1585 | ||
c8d46cf0 | 1586 | ioapic_write_entry(apic_id, pin, entry); |
497c9a19 YL |
1587 | } |
1588 | ||
1589 | static void __init setup_IO_APIC_irqs(void) | |
1590 | { | |
c8d46cf0 | 1591 | int apic_id, pin, idx, irq; |
3c2cbd24 | 1592 | int notcon = 0; |
0b8f1efa | 1593 | struct irq_desc *desc; |
3145e941 | 1594 | struct irq_cfg *cfg; |
0b8f1efa | 1595 | int cpu = boot_cpu_id; |
1da177e4 LT |
1596 | |
1597 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1598 | ||
c8d46cf0 IM |
1599 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1600 | for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) { | |
20d225b9 | 1601 | |
c8d46cf0 | 1602 | idx = find_irq_entry(apic_id, pin, mp_INT); |
3c2cbd24 | 1603 | if (idx == -1) { |
2a554fb1 | 1604 | if (!notcon) { |
3c2cbd24 | 1605 | notcon = 1; |
2a554fb1 CG |
1606 | apic_printk(APIC_VERBOSE, |
1607 | KERN_DEBUG " %d-%d", | |
c8d46cf0 | 1608 | mp_ioapics[apic_id].apicid, pin); |
2a554fb1 CG |
1609 | } else |
1610 | apic_printk(APIC_VERBOSE, " %d-%d", | |
c8d46cf0 | 1611 | mp_ioapics[apic_id].apicid, pin); |
3c2cbd24 CG |
1612 | continue; |
1613 | } | |
56ffa1a0 CG |
1614 | if (notcon) { |
1615 | apic_printk(APIC_VERBOSE, | |
1616 | " (apicid-pin) not connected\n"); | |
1617 | notcon = 0; | |
1618 | } | |
3c2cbd24 | 1619 | |
c8d46cf0 | 1620 | irq = pin_2_irq(idx, apic_id, pin); |
54168ed7 | 1621 | #ifdef CONFIG_X86_32 |
c8d46cf0 | 1622 | if (multi_timer_check(apic_id, irq)) |
3c2cbd24 | 1623 | continue; |
54168ed7 | 1624 | #endif |
0b8f1efa YL |
1625 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1626 | if (!desc) { | |
1627 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1628 | continue; | |
1629 | } | |
3145e941 | 1630 | cfg = desc->chip_data; |
c8d46cf0 | 1631 | add_pin_to_irq_cpu(cfg, cpu, apic_id, pin); |
36062448 | 1632 | |
c8d46cf0 | 1633 | setup_IO_APIC_irq(apic_id, pin, irq, desc, |
3c2cbd24 CG |
1634 | irq_trigger(idx), irq_polarity(idx)); |
1635 | } | |
1da177e4 LT |
1636 | } |
1637 | ||
3c2cbd24 CG |
1638 | if (notcon) |
1639 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1640 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1641 | } |
1642 | ||
1643 | /* | |
f7633ce5 | 1644 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1645 | */ |
c8d46cf0 | 1646 | static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, |
f7633ce5 | 1647 | int vector) |
1da177e4 LT |
1648 | { |
1649 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1650 | |
54168ed7 IM |
1651 | #ifdef CONFIG_INTR_REMAP |
1652 | if (intr_remapping_enabled) | |
1653 | return; | |
1654 | #endif | |
1655 | ||
36062448 | 1656 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1657 | |
1658 | /* | |
1659 | * We use logical delivery to get the timer IRQ | |
1660 | * to the first CPU. | |
1661 | */ | |
9b5bc8dc | 1662 | entry.dest_mode = apic->irq_dest_mode; |
03be7505 | 1663 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1664 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
9b5bc8dc | 1665 | entry.delivery_mode = apic->irq_delivery_mode; |
1da177e4 LT |
1666 | entry.polarity = 0; |
1667 | entry.trigger = 0; | |
1668 | entry.vector = vector; | |
1669 | ||
1670 | /* | |
1671 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1672 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1673 | */ |
54168ed7 | 1674 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1675 | |
1676 | /* | |
1677 | * Add it to the IO-APIC irq-routing table: | |
1678 | */ | |
c8d46cf0 | 1679 | ioapic_write_entry(apic_id, pin, entry); |
1da177e4 LT |
1680 | } |
1681 | ||
32f71aff MR |
1682 | |
1683 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1684 | { |
1685 | int apic, i; | |
1686 | union IO_APIC_reg_00 reg_00; | |
1687 | union IO_APIC_reg_01 reg_01; | |
1688 | union IO_APIC_reg_02 reg_02; | |
1689 | union IO_APIC_reg_03 reg_03; | |
1690 | unsigned long flags; | |
0f978f45 | 1691 | struct irq_cfg *cfg; |
0b8f1efa | 1692 | struct irq_desc *desc; |
8f09cd20 | 1693 | unsigned int irq; |
1da177e4 LT |
1694 | |
1695 | if (apic_verbosity == APIC_QUIET) | |
1696 | return; | |
1697 | ||
36062448 | 1698 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1699 | for (i = 0; i < nr_ioapics; i++) |
1700 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
b5ba7e6d | 1701 | mp_ioapics[i].apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1702 | |
1703 | /* | |
1704 | * We are a bit conservative about what we expect. We have to | |
1705 | * know about every hardware change ASAP. | |
1706 | */ | |
1707 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1708 | ||
1709 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1710 | ||
1711 | spin_lock_irqsave(&ioapic_lock, flags); | |
1712 | reg_00.raw = io_apic_read(apic, 0); | |
1713 | reg_01.raw = io_apic_read(apic, 1); | |
1714 | if (reg_01.bits.version >= 0x10) | |
1715 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1716 | if (reg_01.bits.version >= 0x20) |
1717 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1718 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1719 | ||
54168ed7 | 1720 | printk("\n"); |
b5ba7e6d | 1721 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid); |
1da177e4 LT |
1722 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1723 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1724 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1725 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1726 | |
54168ed7 | 1727 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1728 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1729 | |
1730 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1731 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1732 | |
1733 | /* | |
1734 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1735 | * but the value of reg_02 is read as the previous read register | |
1736 | * value, so ignore it if reg_02 == reg_01. | |
1737 | */ | |
1738 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1739 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1740 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1741 | } |
1742 | ||
1743 | /* | |
1744 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1745 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1746 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1747 | */ | |
1748 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1749 | reg_03.raw != reg_01.raw) { | |
1750 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1751 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1752 | } |
1753 | ||
1754 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1755 | ||
d83e94ac YL |
1756 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1757 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1758 | |
1759 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1760 | struct IO_APIC_route_entry entry; | |
1761 | ||
cf4c6a2f | 1762 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1763 | |
54168ed7 IM |
1764 | printk(KERN_DEBUG " %02x %03X ", |
1765 | i, | |
1766 | entry.dest | |
1767 | ); | |
1da177e4 LT |
1768 | |
1769 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1770 | entry.mask, | |
1771 | entry.trigger, | |
1772 | entry.irr, | |
1773 | entry.polarity, | |
1774 | entry.delivery_status, | |
1775 | entry.dest_mode, | |
1776 | entry.delivery_mode, | |
1777 | entry.vector | |
1778 | ); | |
1779 | } | |
1780 | } | |
1da177e4 | 1781 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1782 | for_each_irq_desc(irq, desc) { |
1783 | struct irq_pin_list *entry; | |
1784 | ||
0b8f1efa YL |
1785 | cfg = desc->chip_data; |
1786 | entry = cfg->irq_2_pin; | |
0f978f45 | 1787 | if (!entry) |
1da177e4 | 1788 | continue; |
8f09cd20 | 1789 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1790 | for (;;) { |
1791 | printk("-> %d:%d", entry->apic, entry->pin); | |
1792 | if (!entry->next) | |
1793 | break; | |
0f978f45 | 1794 | entry = entry->next; |
1da177e4 LT |
1795 | } |
1796 | printk("\n"); | |
1797 | } | |
1798 | ||
1799 | printk(KERN_INFO ".................................... done.\n"); | |
1800 | ||
1801 | return; | |
1802 | } | |
1803 | ||
32f71aff | 1804 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1805 | { |
1806 | unsigned int v; | |
1807 | int i, j; | |
1808 | ||
1809 | if (apic_verbosity == APIC_QUIET) | |
1810 | return; | |
1811 | ||
1812 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1813 | for (i = 0; i < 8; i++) { | |
1814 | v = apic_read(base + i*0x10); | |
1815 | for (j = 0; j < 32; j++) { | |
1816 | if (v & (1<<j)) | |
1817 | printk("1"); | |
1818 | else | |
1819 | printk("0"); | |
1820 | } | |
1821 | printk("\n"); | |
1822 | } | |
1823 | } | |
1824 | ||
32f71aff | 1825 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1826 | { |
1827 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1828 | u64 icr; |
1da177e4 LT |
1829 | |
1830 | if (apic_verbosity == APIC_QUIET) | |
1831 | return; | |
1832 | ||
1833 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1834 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1835 | v = apic_read(APIC_ID); |
54168ed7 | 1836 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1837 | v = apic_read(APIC_LVR); |
1838 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1839 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1840 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1841 | |
1842 | v = apic_read(APIC_TASKPRI); | |
1843 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1844 | ||
54168ed7 | 1845 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1846 | if (!APIC_XAPIC(ver)) { |
1847 | v = apic_read(APIC_ARBPRI); | |
1848 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1849 | v & APIC_ARBPRI_MASK); | |
1850 | } | |
1da177e4 LT |
1851 | v = apic_read(APIC_PROCPRI); |
1852 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1853 | } | |
1854 | ||
a11b5abe YL |
1855 | /* |
1856 | * Remote read supported only in the 82489DX and local APIC for | |
1857 | * Pentium processors. | |
1858 | */ | |
1859 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1860 | v = apic_read(APIC_RRR); | |
1861 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1862 | } | |
1863 | ||
1da177e4 LT |
1864 | v = apic_read(APIC_LDR); |
1865 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1866 | if (!x2apic_enabled()) { |
1867 | v = apic_read(APIC_DFR); | |
1868 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1869 | } | |
1da177e4 LT |
1870 | v = apic_read(APIC_SPIV); |
1871 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1872 | ||
1873 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1874 | print_APIC_bitfield(APIC_ISR); | |
1875 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1876 | print_APIC_bitfield(APIC_TMR); | |
1877 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1878 | print_APIC_bitfield(APIC_IRR); | |
1879 | ||
54168ed7 IM |
1880 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1881 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1882 | apic_write(APIC_ESR, 0); |
54168ed7 | 1883 | |
1da177e4 LT |
1884 | v = apic_read(APIC_ESR); |
1885 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1886 | } | |
1887 | ||
7ab6af7a | 1888 | icr = apic_icr_read(); |
0c425cec IM |
1889 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1890 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1891 | |
1892 | v = apic_read(APIC_LVTT); | |
1893 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1894 | ||
1895 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1896 | v = apic_read(APIC_LVTPC); | |
1897 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1898 | } | |
1899 | v = apic_read(APIC_LVT0); | |
1900 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1901 | v = apic_read(APIC_LVT1); | |
1902 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1903 | ||
1904 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1905 | v = apic_read(APIC_LVTERR); | |
1906 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1907 | } | |
1908 | ||
1909 | v = apic_read(APIC_TMICT); | |
1910 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1911 | v = apic_read(APIC_TMCCT); | |
1912 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1913 | v = apic_read(APIC_TDCR); | |
1914 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1915 | printk("\n"); | |
1916 | } | |
1917 | ||
32f71aff | 1918 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1919 | { |
ffd5aae7 YL |
1920 | int cpu; |
1921 | ||
1922 | preempt_disable(); | |
1923 | for_each_online_cpu(cpu) | |
1924 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1925 | preempt_enable(); | |
1da177e4 LT |
1926 | } |
1927 | ||
32f71aff | 1928 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1929 | { |
1da177e4 LT |
1930 | unsigned int v; |
1931 | unsigned long flags; | |
1932 | ||
1933 | if (apic_verbosity == APIC_QUIET) | |
1934 | return; | |
1935 | ||
1936 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1937 | ||
1938 | spin_lock_irqsave(&i8259A_lock, flags); | |
1939 | ||
1940 | v = inb(0xa1) << 8 | inb(0x21); | |
1941 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1942 | ||
1943 | v = inb(0xa0) << 8 | inb(0x20); | |
1944 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1945 | ||
54168ed7 IM |
1946 | outb(0x0b,0xa0); |
1947 | outb(0x0b,0x20); | |
1da177e4 | 1948 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1949 | outb(0x0a,0xa0); |
1950 | outb(0x0a,0x20); | |
1da177e4 LT |
1951 | |
1952 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1953 | ||
1954 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1955 | ||
1956 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1957 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1958 | } | |
1959 | ||
32f71aff MR |
1960 | __apicdebuginit(int) print_all_ICs(void) |
1961 | { | |
1962 | print_PIC(); | |
1963 | print_all_local_APICs(); | |
1964 | print_IO_APIC(); | |
1965 | ||
1966 | return 0; | |
1967 | } | |
1968 | ||
1969 | fs_initcall(print_all_ICs); | |
1970 | ||
1da177e4 | 1971 | |
efa2559f YL |
1972 | /* Where if anywhere is the i8259 connect in external int mode */ |
1973 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1974 | ||
54168ed7 | 1975 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1976 | { |
1977 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1978 | int i8259_apic, i8259_pin; |
54168ed7 | 1979 | int apic; |
1da177e4 LT |
1980 | unsigned long flags; |
1981 | ||
54168ed7 IM |
1982 | #ifdef CONFIG_X86_32 |
1983 | int i; | |
1da177e4 LT |
1984 | if (!pirqs_enabled) |
1985 | for (i = 0; i < MAX_PIRQS; i++) | |
1986 | pirq_entries[i] = -1; | |
54168ed7 | 1987 | #endif |
1da177e4 LT |
1988 | |
1989 | /* | |
1990 | * The number of IO-APIC IRQ registers (== #pins): | |
1991 | */ | |
fcfd636a | 1992 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1993 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1994 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1995 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1996 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1997 | } | |
54168ed7 | 1998 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1999 | int pin; |
2000 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 2001 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 2002 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 2003 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 2004 | |
fcfd636a EB |
2005 | /* If the interrupt line is enabled and in ExtInt mode |
2006 | * I have found the pin where the i8259 is connected. | |
2007 | */ | |
2008 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
2009 | ioapic_i8259.apic = apic; | |
2010 | ioapic_i8259.pin = pin; | |
2011 | goto found_i8259; | |
2012 | } | |
2013 | } | |
2014 | } | |
2015 | found_i8259: | |
2016 | /* Look to see what if the MP table has reported the ExtINT */ | |
2017 | /* If we could not find the appropriate pin by looking at the ioapic | |
2018 | * the i8259 probably is not connected the ioapic but give the | |
2019 | * mptable a chance anyway. | |
2020 | */ | |
2021 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
2022 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
2023 | /* Trust the MP table if nothing is setup in the hardware */ | |
2024 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
2025 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
2026 | ioapic_i8259.pin = i8259_pin; | |
2027 | ioapic_i8259.apic = i8259_apic; | |
2028 | } | |
2029 | /* Complain if the MP table and the hardware disagree */ | |
2030 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2031 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2032 | { | |
2033 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2034 | } |
2035 | ||
2036 | /* | |
2037 | * Do not trust the IO-APIC being empty at bootup | |
2038 | */ | |
2039 | clear_IO_APIC(); | |
2040 | } | |
2041 | ||
2042 | /* | |
2043 | * Not an __init, needed by the reboot code | |
2044 | */ | |
2045 | void disable_IO_APIC(void) | |
2046 | { | |
2047 | /* | |
2048 | * Clear the IO-APIC before rebooting: | |
2049 | */ | |
2050 | clear_IO_APIC(); | |
2051 | ||
650927ef | 2052 | /* |
0b968d23 | 2053 | * If the i8259 is routed through an IOAPIC |
650927ef | 2054 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2055 | * so legacy interrupts can be delivered. |
650927ef | 2056 | */ |
fcfd636a | 2057 | if (ioapic_i8259.pin != -1) { |
650927ef | 2058 | struct IO_APIC_route_entry entry; |
650927ef EB |
2059 | |
2060 | memset(&entry, 0, sizeof(entry)); | |
2061 | entry.mask = 0; /* Enabled */ | |
2062 | entry.trigger = 0; /* Edge */ | |
2063 | entry.irr = 0; | |
2064 | entry.polarity = 0; /* High */ | |
2065 | entry.delivery_status = 0; | |
2066 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2067 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2068 | entry.vector = 0; |
54168ed7 | 2069 | entry.dest = read_apic_id(); |
650927ef EB |
2070 | |
2071 | /* | |
2072 | * Add it to the IO-APIC irq-routing table: | |
2073 | */ | |
cf4c6a2f | 2074 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2075 | } |
54168ed7 | 2076 | |
fcfd636a | 2077 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
2078 | } |
2079 | ||
54168ed7 | 2080 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2081 | /* |
2082 | * function to set the IO-APIC physical IDs based on the | |
2083 | * values stored in the MPC table. | |
2084 | * | |
2085 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2086 | */ | |
2087 | ||
1da177e4 LT |
2088 | static void __init setup_ioapic_ids_from_mpc(void) |
2089 | { | |
2090 | union IO_APIC_reg_00 reg_00; | |
2091 | physid_mask_t phys_id_present_map; | |
c8d46cf0 | 2092 | int apic_id; |
1da177e4 LT |
2093 | int i; |
2094 | unsigned char old_id; | |
2095 | unsigned long flags; | |
2096 | ||
a4dbc34d | 2097 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2098 | return; |
d49c4288 | 2099 | |
ca05fea6 NP |
2100 | /* |
2101 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2102 | * no meaning without the serial APIC bus. | |
2103 | */ | |
7c5c1e42 SL |
2104 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2105 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2106 | return; |
1da177e4 LT |
2107 | /* |
2108 | * This is broken; anything with a real cpu count has to | |
2109 | * circumvent this idiocy regardless. | |
2110 | */ | |
2111 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2112 | ||
2113 | /* | |
2114 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2115 | */ | |
c8d46cf0 | 2116 | for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { |
1da177e4 LT |
2117 | |
2118 | /* Read the register 0 value */ | |
2119 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2120 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2121 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2122 | |
c8d46cf0 | 2123 | old_id = mp_ioapics[apic_id].apicid; |
1da177e4 | 2124 | |
c8d46cf0 | 2125 | if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) { |
1da177e4 | 2126 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
c8d46cf0 | 2127 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2128 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2129 | reg_00.bits.ID); | |
c8d46cf0 | 2130 | mp_ioapics[apic_id].apicid = reg_00.bits.ID; |
1da177e4 LT |
2131 | } |
2132 | ||
1da177e4 LT |
2133 | /* |
2134 | * Sanity check, is the ID really free? Every APIC in a | |
2135 | * system must have a unique ID or we get lots of nice | |
2136 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2137 | */ | |
2138 | if (check_apicid_used(phys_id_present_map, | |
c8d46cf0 | 2139 | mp_ioapics[apic_id].apicid)) { |
1da177e4 | 2140 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
c8d46cf0 | 2141 | apic_id, mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2142 | for (i = 0; i < get_physical_broadcast(); i++) |
2143 | if (!physid_isset(i, phys_id_present_map)) | |
2144 | break; | |
2145 | if (i >= get_physical_broadcast()) | |
2146 | panic("Max APIC ID exceeded!\n"); | |
2147 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2148 | i); | |
2149 | physid_set(i, phys_id_present_map); | |
c8d46cf0 | 2150 | mp_ioapics[apic_id].apicid = i; |
1da177e4 LT |
2151 | } else { |
2152 | physid_mask_t tmp; | |
c8d46cf0 | 2153 | tmp = apicid_to_cpu_present(mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2154 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2155 | "phys_id_present_map\n", | |
c8d46cf0 | 2156 | mp_ioapics[apic_id].apicid); |
1da177e4 LT |
2157 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2158 | } | |
2159 | ||
2160 | ||
2161 | /* | |
2162 | * We need to adjust the IRQ routing table | |
2163 | * if the ID changed. | |
2164 | */ | |
c8d46cf0 | 2165 | if (old_id != mp_ioapics[apic_id].apicid) |
1da177e4 | 2166 | for (i = 0; i < mp_irq_entries; i++) |
c2c21745 JSR |
2167 | if (mp_irqs[i].dstapic == old_id) |
2168 | mp_irqs[i].dstapic | |
c8d46cf0 | 2169 | = mp_ioapics[apic_id].apicid; |
1da177e4 LT |
2170 | |
2171 | /* | |
2172 | * Read the right value from the MPC table and | |
2173 | * write it into the ID register. | |
36062448 | 2174 | */ |
1da177e4 LT |
2175 | apic_printk(APIC_VERBOSE, KERN_INFO |
2176 | "...changing IO-APIC physical APIC ID to %d ...", | |
c8d46cf0 | 2177 | mp_ioapics[apic_id].apicid); |
1da177e4 | 2178 | |
c8d46cf0 | 2179 | reg_00.bits.ID = mp_ioapics[apic_id].apicid; |
1da177e4 | 2180 | spin_lock_irqsave(&ioapic_lock, flags); |
c8d46cf0 | 2181 | io_apic_write(apic_id, 0, reg_00.raw); |
a2d332fa | 2182 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1da177e4 LT |
2183 | |
2184 | /* | |
2185 | * Sanity check | |
2186 | */ | |
2187 | spin_lock_irqsave(&ioapic_lock, flags); | |
c8d46cf0 | 2188 | reg_00.raw = io_apic_read(apic_id, 0); |
1da177e4 | 2189 | spin_unlock_irqrestore(&ioapic_lock, flags); |
c8d46cf0 | 2190 | if (reg_00.bits.ID != mp_ioapics[apic_id].apicid) |
1da177e4 LT |
2191 | printk("could not set ID!\n"); |
2192 | else | |
2193 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2194 | } | |
2195 | } | |
54168ed7 | 2196 | #endif |
1da177e4 | 2197 | |
7ce0bcfd | 2198 | int no_timer_check __initdata; |
8542b200 ZA |
2199 | |
2200 | static int __init notimercheck(char *s) | |
2201 | { | |
2202 | no_timer_check = 1; | |
2203 | return 1; | |
2204 | } | |
2205 | __setup("no_timer_check", notimercheck); | |
2206 | ||
1da177e4 LT |
2207 | /* |
2208 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2209 | * about the timer IRQ. We do the following to work around the situation: | |
2210 | * | |
2211 | * - timer IRQ defaults to IO-APIC IRQ | |
2212 | * - if this function detects that timer IRQs are defunct, then we fall | |
2213 | * back to ISA timer IRQs | |
2214 | */ | |
f0a7a5c9 | 2215 | static int __init timer_irq_works(void) |
1da177e4 LT |
2216 | { |
2217 | unsigned long t1 = jiffies; | |
4aae0702 | 2218 | unsigned long flags; |
1da177e4 | 2219 | |
8542b200 ZA |
2220 | if (no_timer_check) |
2221 | return 1; | |
2222 | ||
4aae0702 | 2223 | local_save_flags(flags); |
1da177e4 LT |
2224 | local_irq_enable(); |
2225 | /* Let ten ticks pass... */ | |
2226 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2227 | local_irq_restore(flags); |
1da177e4 LT |
2228 | |
2229 | /* | |
2230 | * Expect a few ticks at least, to be sure some possible | |
2231 | * glue logic does not lock up after one or two first | |
2232 | * ticks in a non-ExtINT mode. Also the local APIC | |
2233 | * might have cached one ExtINT interrupt. Finally, at | |
2234 | * least one tick may be lost due to delays. | |
2235 | */ | |
54168ed7 IM |
2236 | |
2237 | /* jiffies wrap? */ | |
1d16b53e | 2238 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2239 | return 1; |
1da177e4 LT |
2240 | return 0; |
2241 | } | |
2242 | ||
2243 | /* | |
2244 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2245 | * number of pending IRQ events unhandled. These cases are very rare, | |
2246 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2247 | * better to do it this way as thus we do not have to be aware of | |
2248 | * 'pending' interrupts in the IRQ path, except at this point. | |
2249 | */ | |
2250 | /* | |
2251 | * Edge triggered needs to resend any interrupt | |
2252 | * that was delayed but this is now handled in the device | |
2253 | * independent code. | |
2254 | */ | |
2255 | ||
2256 | /* | |
2257 | * Starting up a edge-triggered IO-APIC interrupt is | |
2258 | * nasty - we need to make sure that we get the edge. | |
2259 | * If it is already asserted for some reason, we need | |
2260 | * return 1 to indicate that is was pending. | |
2261 | * | |
2262 | * This is not complete - we should be able to fake | |
2263 | * an edge even if it isn't on the 8259A... | |
2264 | */ | |
54168ed7 | 2265 | |
f5b9ed7a | 2266 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2267 | { |
2268 | int was_pending = 0; | |
2269 | unsigned long flags; | |
0b8f1efa | 2270 | struct irq_cfg *cfg; |
1da177e4 LT |
2271 | |
2272 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2273 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2274 | disable_8259A_irq(irq); |
2275 | if (i8259A_irq_pending(irq)) | |
2276 | was_pending = 1; | |
2277 | } | |
0b8f1efa | 2278 | cfg = irq_cfg(irq); |
3145e941 | 2279 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2280 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2281 | ||
2282 | return was_pending; | |
2283 | } | |
2284 | ||
54168ed7 | 2285 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2286 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2287 | { |
54168ed7 IM |
2288 | |
2289 | struct irq_cfg *cfg = irq_cfg(irq); | |
2290 | unsigned long flags; | |
2291 | ||
2292 | spin_lock_irqsave(&vector_lock, flags); | |
22f65d31 | 2293 | send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2294 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2295 | |
2296 | return 1; | |
2297 | } | |
54168ed7 IM |
2298 | #else |
2299 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2300 | { |
d6c88a50 | 2301 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2302 | |
d6c88a50 | 2303 | return 1; |
54168ed7 IM |
2304 | } |
2305 | #endif | |
497c9a19 | 2306 | |
54168ed7 IM |
2307 | /* |
2308 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2309 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2310 | * handled with the level-triggered descriptor, but that one has slightly | |
2311 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2312 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2313 | * races. | |
2314 | */ | |
497c9a19 | 2315 | |
54168ed7 | 2316 | #ifdef CONFIG_SMP |
497c9a19 | 2317 | |
54168ed7 IM |
2318 | #ifdef CONFIG_INTR_REMAP |
2319 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2320 | |
54168ed7 | 2321 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2322 | |
54168ed7 IM |
2323 | /* |
2324 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2325 | * | |
2326 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2327 | * and cpu destination) of IRTE and flush the hardware cache. | |
2328 | * | |
2329 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2330 | * vector information, along with modifying IRTE with vector and destination. | |
2331 | * So irq migration for level triggered is little bit more complex compared to | |
2332 | * edge triggered migration. But the good news is, we use the same algorithm | |
2333 | * for level triggered migration as we have today, only difference being, | |
2334 | * we now initiate the irq migration from process context instead of the | |
2335 | * interrupt context. | |
2336 | * | |
2337 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2338 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2339 | * as simple as edge triggered migration and we can do the irq migration | |
2340 | * with a simple atomic update to IO-APIC RTE. | |
2341 | */ | |
e7986739 MT |
2342 | static void |
2343 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 | 2344 | { |
54168ed7 | 2345 | struct irq_cfg *cfg; |
54168ed7 IM |
2346 | struct irte irte; |
2347 | int modify_ioapic_rte; | |
2348 | unsigned int dest; | |
2349 | unsigned long flags; | |
3145e941 | 2350 | unsigned int irq; |
497c9a19 | 2351 | |
22f65d31 | 2352 | if (!cpumask_intersects(mask, cpu_online_mask)) |
497c9a19 YL |
2353 | return; |
2354 | ||
3145e941 | 2355 | irq = desc->irq; |
54168ed7 IM |
2356 | if (get_irte(irq, &irte)) |
2357 | return; | |
497c9a19 | 2358 | |
3145e941 YL |
2359 | cfg = desc->chip_data; |
2360 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
2361 | return; |
2362 | ||
3145e941 YL |
2363 | set_extra_move_desc(desc, mask); |
2364 | ||
22f65d31 | 2365 | dest = cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2366 | |
54168ed7 IM |
2367 | modify_ioapic_rte = desc->status & IRQ_LEVEL; |
2368 | if (modify_ioapic_rte) { | |
2369 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 2370 | __target_IO_APIC_irq(irq, dest, cfg); |
54168ed7 IM |
2371 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2372 | } | |
2373 | ||
2374 | irte.vector = cfg->vector; | |
2375 | irte.dest_id = IRTE_DEST(dest); | |
2376 | ||
2377 | /* | |
2378 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2379 | */ | |
2380 | modify_irte(irq, &irte); | |
2381 | ||
22f65d31 MT |
2382 | if (cfg->move_in_progress) |
2383 | send_cleanup_vector(cfg); | |
54168ed7 | 2384 | |
7f7ace0c | 2385 | cpumask_copy(desc->affinity, mask); |
54168ed7 IM |
2386 | } |
2387 | ||
3145e941 | 2388 | static int migrate_irq_remapped_level_desc(struct irq_desc *desc) |
54168ed7 IM |
2389 | { |
2390 | int ret = -1; | |
3145e941 | 2391 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 2392 | |
3145e941 | 2393 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2394 | |
3145e941 | 2395 | if (io_apic_level_ack_pending(cfg)) { |
54168ed7 | 2396 | /* |
d6c88a50 | 2397 | * Interrupt in progress. Migrating irq now will change the |
54168ed7 IM |
2398 | * vector information in the IO-APIC RTE and that will confuse |
2399 | * the EOI broadcast performed by cpu. | |
2400 | * So, delay the irq migration to the next instance. | |
2401 | */ | |
2402 | schedule_delayed_work(&ir_migration_work, 1); | |
2403 | goto unmask; | |
2404 | } | |
2405 | ||
2406 | /* everthing is clear. we have right of way */ | |
7f7ace0c | 2407 | migrate_ioapic_irq_desc(desc, desc->pending_mask); |
54168ed7 IM |
2408 | |
2409 | ret = 0; | |
2410 | desc->status &= ~IRQ_MOVE_PENDING; | |
7f7ace0c | 2411 | cpumask_clear(desc->pending_mask); |
54168ed7 IM |
2412 | |
2413 | unmask: | |
3145e941 YL |
2414 | unmask_IO_APIC_irq_desc(desc); |
2415 | ||
54168ed7 IM |
2416 | return ret; |
2417 | } | |
2418 | ||
2419 | static void ir_irq_migration(struct work_struct *work) | |
2420 | { | |
2421 | unsigned int irq; | |
2422 | struct irq_desc *desc; | |
2423 | ||
2424 | for_each_irq_desc(irq, desc) { | |
2425 | if (desc->status & IRQ_MOVE_PENDING) { | |
2426 | unsigned long flags; | |
2427 | ||
2428 | spin_lock_irqsave(&desc->lock, flags); | |
2429 | if (!desc->chip->set_affinity || | |
2430 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2431 | desc->status &= ~IRQ_MOVE_PENDING; | |
2432 | spin_unlock_irqrestore(&desc->lock, flags); | |
2433 | continue; | |
2434 | } | |
2435 | ||
7f7ace0c | 2436 | desc->chip->set_affinity(irq, desc->pending_mask); |
54168ed7 IM |
2437 | spin_unlock_irqrestore(&desc->lock, flags); |
2438 | } | |
2439 | } | |
2440 | } | |
2441 | ||
2442 | /* | |
2443 | * Migrates the IRQ destination in the process context. | |
2444 | */ | |
968ea6d8 RR |
2445 | static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
2446 | const struct cpumask *mask) | |
54168ed7 | 2447 | { |
54168ed7 IM |
2448 | if (desc->status & IRQ_LEVEL) { |
2449 | desc->status |= IRQ_MOVE_PENDING; | |
7f7ace0c | 2450 | cpumask_copy(desc->pending_mask, mask); |
3145e941 | 2451 | migrate_irq_remapped_level_desc(desc); |
54168ed7 IM |
2452 | return; |
2453 | } | |
2454 | ||
3145e941 YL |
2455 | migrate_ioapic_irq_desc(desc, mask); |
2456 | } | |
968ea6d8 RR |
2457 | static void set_ir_ioapic_affinity_irq(unsigned int irq, |
2458 | const struct cpumask *mask) | |
3145e941 YL |
2459 | { |
2460 | struct irq_desc *desc = irq_to_desc(irq); | |
2461 | ||
2462 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
54168ed7 IM |
2463 | } |
2464 | #endif | |
2465 | ||
2466 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2467 | { | |
2468 | unsigned vector, me; | |
8f2466f4 | 2469 | |
54168ed7 | 2470 | ack_APIC_irq(); |
54168ed7 | 2471 | exit_idle(); |
54168ed7 IM |
2472 | irq_enter(); |
2473 | ||
2474 | me = smp_processor_id(); | |
2475 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2476 | unsigned int irq; | |
2477 | struct irq_desc *desc; | |
2478 | struct irq_cfg *cfg; | |
2479 | irq = __get_cpu_var(vector_irq)[vector]; | |
2480 | ||
0b8f1efa YL |
2481 | if (irq == -1) |
2482 | continue; | |
2483 | ||
54168ed7 IM |
2484 | desc = irq_to_desc(irq); |
2485 | if (!desc) | |
2486 | continue; | |
2487 | ||
2488 | cfg = irq_cfg(irq); | |
2489 | spin_lock(&desc->lock); | |
2490 | if (!cfg->move_cleanup_count) | |
2491 | goto unlock; | |
2492 | ||
22f65d31 | 2493 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2494 | goto unlock; |
2495 | ||
2496 | __get_cpu_var(vector_irq)[vector] = -1; | |
2497 | cfg->move_cleanup_count--; | |
2498 | unlock: | |
2499 | spin_unlock(&desc->lock); | |
2500 | } | |
2501 | ||
2502 | irq_exit(); | |
2503 | } | |
2504 | ||
3145e941 | 2505 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2506 | { |
3145e941 YL |
2507 | struct irq_desc *desc = *descp; |
2508 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2509 | unsigned vector, me; |
2510 | ||
48a1b10a YL |
2511 | if (likely(!cfg->move_in_progress)) { |
2512 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | |
2513 | if (likely(!cfg->move_desc_pending)) | |
2514 | return; | |
2515 | ||
b9098957 | 2516 | /* domain has not changed, but affinity did */ |
48a1b10a | 2517 | me = smp_processor_id(); |
7f7ace0c | 2518 | if (cpumask_test_cpu(me, desc->affinity)) { |
48a1b10a YL |
2519 | *descp = desc = move_irq_desc(desc, me); |
2520 | /* get the new one */ | |
2521 | cfg = desc->chip_data; | |
2522 | cfg->move_desc_pending = 0; | |
2523 | } | |
2524 | #endif | |
54168ed7 | 2525 | return; |
48a1b10a | 2526 | } |
54168ed7 IM |
2527 | |
2528 | vector = ~get_irq_regs()->orig_ax; | |
2529 | me = smp_processor_id(); | |
48a1b10a YL |
2530 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
2531 | *descp = desc = move_irq_desc(desc, me); | |
2532 | /* get the new one */ | |
2533 | cfg = desc->chip_data; | |
2534 | #endif | |
54168ed7 | 2535 | |
22f65d31 MT |
2536 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
2537 | send_cleanup_vector(cfg); | |
497c9a19 YL |
2538 | } |
2539 | #else | |
3145e941 | 2540 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2541 | #endif |
3145e941 | 2542 | |
54168ed7 IM |
2543 | #ifdef CONFIG_INTR_REMAP |
2544 | static void ack_x2apic_level(unsigned int irq) | |
2545 | { | |
2546 | ack_x2APIC_irq(); | |
2547 | } | |
2548 | ||
2549 | static void ack_x2apic_edge(unsigned int irq) | |
2550 | { | |
2551 | ack_x2APIC_irq(); | |
2552 | } | |
3145e941 | 2553 | |
54168ed7 | 2554 | #endif |
497c9a19 | 2555 | |
1d025192 YL |
2556 | static void ack_apic_edge(unsigned int irq) |
2557 | { | |
3145e941 YL |
2558 | struct irq_desc *desc = irq_to_desc(irq); |
2559 | ||
2560 | irq_complete_move(&desc); | |
1d025192 YL |
2561 | move_native_irq(irq); |
2562 | ack_APIC_irq(); | |
2563 | } | |
2564 | ||
3eb2cce8 | 2565 | atomic_t irq_mis_count; |
3eb2cce8 | 2566 | |
047c8fdb YL |
2567 | static void ack_apic_level(unsigned int irq) |
2568 | { | |
3145e941 YL |
2569 | struct irq_desc *desc = irq_to_desc(irq); |
2570 | ||
3eb2cce8 YL |
2571 | #ifdef CONFIG_X86_32 |
2572 | unsigned long v; | |
2573 | int i; | |
2574 | #endif | |
3145e941 | 2575 | struct irq_cfg *cfg; |
54168ed7 | 2576 | int do_unmask_irq = 0; |
047c8fdb | 2577 | |
3145e941 | 2578 | irq_complete_move(&desc); |
047c8fdb | 2579 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2580 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2581 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2582 | do_unmask_irq = 1; |
3145e941 | 2583 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2584 | } |
047c8fdb YL |
2585 | #endif |
2586 | ||
3eb2cce8 YL |
2587 | #ifdef CONFIG_X86_32 |
2588 | /* | |
2589 | * It appears there is an erratum which affects at least version 0x11 | |
2590 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2591 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2592 | * erroneously delivered as edge-triggered one but the respective IRR | |
2593 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2594 | * message but it will never arrive and further interrupts are blocked | |
2595 | * from the source. The exact reason is so far unknown, but the | |
2596 | * phenomenon was observed when two consecutive interrupt requests | |
2597 | * from a given source get delivered to the same CPU and the source is | |
2598 | * temporarily disabled in between. | |
2599 | * | |
2600 | * A workaround is to simulate an EOI message manually. We achieve it | |
2601 | * by setting the trigger mode to edge and then to level when the edge | |
2602 | * trigger mode gets detected in the TMR of a local APIC for a | |
2603 | * level-triggered interrupt. We mask the source for the time of the | |
2604 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2605 | * The idea is from Manfred Spraul. --macro | |
2606 | */ | |
3145e941 YL |
2607 | cfg = desc->chip_data; |
2608 | i = cfg->vector; | |
3eb2cce8 YL |
2609 | |
2610 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2611 | #endif | |
2612 | ||
54168ed7 IM |
2613 | /* |
2614 | * We must acknowledge the irq before we move it or the acknowledge will | |
2615 | * not propagate properly. | |
2616 | */ | |
2617 | ack_APIC_irq(); | |
2618 | ||
2619 | /* Now we can move and renable the irq */ | |
2620 | if (unlikely(do_unmask_irq)) { | |
2621 | /* Only migrate the irq if the ack has been received. | |
2622 | * | |
2623 | * On rare occasions the broadcast level triggered ack gets | |
2624 | * delayed going to ioapics, and if we reprogram the | |
2625 | * vector while Remote IRR is still set the irq will never | |
2626 | * fire again. | |
2627 | * | |
2628 | * To prevent this scenario we read the Remote IRR bit | |
2629 | * of the ioapic. This has two effects. | |
2630 | * - On any sane system the read of the ioapic will | |
2631 | * flush writes (and acks) going to the ioapic from | |
2632 | * this cpu. | |
2633 | * - We get to see if the ACK has actually been delivered. | |
2634 | * | |
2635 | * Based on failed experiments of reprogramming the | |
2636 | * ioapic entry from outside of irq context starting | |
2637 | * with masking the ioapic entry and then polling until | |
2638 | * Remote IRR was clear before reprogramming the | |
2639 | * ioapic I don't trust the Remote IRR bit to be | |
2640 | * completey accurate. | |
2641 | * | |
2642 | * However there appears to be no other way to plug | |
2643 | * this race, so if the Remote IRR bit is not | |
2644 | * accurate and is causing problems then it is a hardware bug | |
2645 | * and you can go talk to the chipset vendor about it. | |
2646 | */ | |
3145e941 YL |
2647 | cfg = desc->chip_data; |
2648 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2649 | move_masked_irq(irq); |
3145e941 | 2650 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2651 | } |
1d025192 | 2652 | |
3eb2cce8 | 2653 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2654 | if (!(v & (1 << (i & 0x1f)))) { |
2655 | atomic_inc(&irq_mis_count); | |
2656 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2657 | __mask_and_edge_IO_APIC_irq(cfg); |
2658 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2659 | spin_unlock(&ioapic_lock); |
2660 | } | |
047c8fdb | 2661 | #endif |
3eb2cce8 | 2662 | } |
1d025192 | 2663 | |
f5b9ed7a | 2664 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2665 | .name = "IO-APIC", |
2666 | .startup = startup_ioapic_irq, | |
2667 | .mask = mask_IO_APIC_irq, | |
2668 | .unmask = unmask_IO_APIC_irq, | |
2669 | .ack = ack_apic_edge, | |
2670 | .eoi = ack_apic_level, | |
54d5d424 | 2671 | #ifdef CONFIG_SMP |
d6c88a50 | 2672 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2673 | #endif |
ace80ab7 | 2674 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2675 | }; |
2676 | ||
54168ed7 IM |
2677 | #ifdef CONFIG_INTR_REMAP |
2678 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
d6c88a50 TG |
2679 | .name = "IR-IO-APIC", |
2680 | .startup = startup_ioapic_irq, | |
2681 | .mask = mask_IO_APIC_irq, | |
2682 | .unmask = unmask_IO_APIC_irq, | |
2683 | .ack = ack_x2apic_edge, | |
2684 | .eoi = ack_x2apic_level, | |
54168ed7 | 2685 | #ifdef CONFIG_SMP |
d6c88a50 | 2686 | .set_affinity = set_ir_ioapic_affinity_irq, |
54168ed7 IM |
2687 | #endif |
2688 | .retrigger = ioapic_retrigger_irq, | |
2689 | }; | |
2690 | #endif | |
1da177e4 LT |
2691 | |
2692 | static inline void init_IO_APIC_traps(void) | |
2693 | { | |
2694 | int irq; | |
08678b08 | 2695 | struct irq_desc *desc; |
da51a821 | 2696 | struct irq_cfg *cfg; |
1da177e4 LT |
2697 | |
2698 | /* | |
2699 | * NOTE! The local APIC isn't very good at handling | |
2700 | * multiple interrupts at the same interrupt level. | |
2701 | * As the interrupt level is determined by taking the | |
2702 | * vector number and shifting that right by 4, we | |
2703 | * want to spread these out a bit so that they don't | |
2704 | * all fall in the same interrupt level. | |
2705 | * | |
2706 | * Also, we've got to be careful not to trash gate | |
2707 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2708 | */ | |
0b8f1efa | 2709 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2710 | cfg = desc->chip_data; |
2711 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2712 | /* |
2713 | * Hmm.. We don't have an entry for this, | |
2714 | * so default to an old-fashioned 8259 | |
2715 | * interrupt if we can.. | |
2716 | */ | |
99d093d1 | 2717 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2718 | make_8259A_irq(irq); |
0b8f1efa | 2719 | else |
1da177e4 | 2720 | /* Strange. Oh, well.. */ |
08678b08 | 2721 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2722 | } |
2723 | } | |
2724 | } | |
2725 | ||
f5b9ed7a IM |
2726 | /* |
2727 | * The local APIC irq-chip implementation: | |
2728 | */ | |
1da177e4 | 2729 | |
36062448 | 2730 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2731 | { |
2732 | unsigned long v; | |
2733 | ||
2734 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2735 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2736 | } |
2737 | ||
36062448 | 2738 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2739 | { |
f5b9ed7a | 2740 | unsigned long v; |
1da177e4 | 2741 | |
f5b9ed7a | 2742 | v = apic_read(APIC_LVT0); |
593f4a78 | 2743 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2744 | } |
1da177e4 | 2745 | |
3145e941 | 2746 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2747 | { |
2748 | ack_APIC_irq(); | |
2749 | } | |
2750 | ||
f5b9ed7a | 2751 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2752 | .name = "local-APIC", |
f5b9ed7a IM |
2753 | .mask = mask_lapic_irq, |
2754 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2755 | .ack = ack_lapic_irq, |
1da177e4 LT |
2756 | }; |
2757 | ||
3145e941 | 2758 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2759 | { |
08678b08 | 2760 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2761 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2762 | "edge"); | |
c88ac1df MR |
2763 | } |
2764 | ||
e9427101 | 2765 | static void __init setup_nmi(void) |
1da177e4 LT |
2766 | { |
2767 | /* | |
36062448 | 2768 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2769 | * We put the 8259A master into AEOI mode and |
2770 | * unmask on all local APICs LVT0 as NMI. | |
2771 | * | |
2772 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2773 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2774 | * the NMI handler or the timer interrupt. | |
36062448 | 2775 | */ |
1da177e4 LT |
2776 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2777 | ||
e9427101 | 2778 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2779 | |
2780 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2781 | } | |
2782 | ||
2783 | /* | |
2784 | * This looks a bit hackish but it's about the only one way of sending | |
2785 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2786 | * not support the ExtINT mode, unfortunately. We need to send these | |
2787 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2788 | * 8259A interrupt line asserted until INTA. --macro | |
2789 | */ | |
28acf285 | 2790 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2791 | { |
fcfd636a | 2792 | int apic, pin, i; |
1da177e4 LT |
2793 | struct IO_APIC_route_entry entry0, entry1; |
2794 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2795 | |
fcfd636a | 2796 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2797 | if (pin == -1) { |
2798 | WARN_ON_ONCE(1); | |
2799 | return; | |
2800 | } | |
fcfd636a | 2801 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2802 | if (apic == -1) { |
2803 | WARN_ON_ONCE(1); | |
1da177e4 | 2804 | return; |
956fb531 | 2805 | } |
1da177e4 | 2806 | |
cf4c6a2f | 2807 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2808 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2809 | |
2810 | memset(&entry1, 0, sizeof(entry1)); | |
2811 | ||
2812 | entry1.dest_mode = 0; /* physical delivery */ | |
2813 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2814 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2815 | entry1.delivery_mode = dest_ExtINT; |
2816 | entry1.polarity = entry0.polarity; | |
2817 | entry1.trigger = 0; | |
2818 | entry1.vector = 0; | |
2819 | ||
cf4c6a2f | 2820 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2821 | |
2822 | save_control = CMOS_READ(RTC_CONTROL); | |
2823 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2824 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2825 | RTC_FREQ_SELECT); | |
2826 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2827 | ||
2828 | i = 100; | |
2829 | while (i-- > 0) { | |
2830 | mdelay(10); | |
2831 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2832 | i -= 10; | |
2833 | } | |
2834 | ||
2835 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2836 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2837 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2838 | |
cf4c6a2f | 2839 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2840 | } |
2841 | ||
efa2559f | 2842 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2843 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2844 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2845 | { |
2846 | disable_timer_pin_1 = 1; | |
2847 | return 0; | |
2848 | } | |
54168ed7 | 2849 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2850 | |
2851 | int timer_through_8259 __initdata; | |
2852 | ||
1da177e4 LT |
2853 | /* |
2854 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2855 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2856 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2857 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2858 | * |
2859 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2860 | */ |
8542b200 | 2861 | static inline void __init check_timer(void) |
1da177e4 | 2862 | { |
3145e941 YL |
2863 | struct irq_desc *desc = irq_to_desc(0); |
2864 | struct irq_cfg *cfg = desc->chip_data; | |
2865 | int cpu = boot_cpu_id; | |
fcfd636a | 2866 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2867 | unsigned long flags; |
047c8fdb YL |
2868 | unsigned int ver; |
2869 | int no_pin1 = 0; | |
4aae0702 IM |
2870 | |
2871 | local_irq_save(flags); | |
d4d25dec | 2872 | |
d6c88a50 TG |
2873 | ver = apic_read(APIC_LVR); |
2874 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2875 | |
1da177e4 LT |
2876 | /* |
2877 | * get/set the timer IRQ vector: | |
2878 | */ | |
2879 | disable_8259A_irq(0); | |
3145e941 | 2880 | assign_irq_vector(0, cfg, TARGET_CPUS); |
1da177e4 LT |
2881 | |
2882 | /* | |
d11d5794 MR |
2883 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2884 | * wire has to be disabled in the local APIC. Also | |
2885 | * timer interrupts need to be acknowledged manually in | |
2886 | * the 8259A for the i82489DX when using the NMI | |
2887 | * watchdog as that APIC treats NMIs as level-triggered. | |
2888 | * The AEOI mode will finish them in the 8259A | |
2889 | * automatically. | |
1da177e4 | 2890 | */ |
593f4a78 | 2891 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2892 | init_8259A(1); |
54168ed7 | 2893 | #ifdef CONFIG_X86_32 |
d11d5794 | 2894 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2895 | #endif |
1da177e4 | 2896 | |
fcfd636a EB |
2897 | pin1 = find_isa_irq_pin(0, mp_INT); |
2898 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2899 | pin2 = ioapic_i8259.pin; | |
2900 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2901 | |
49a66a0b MR |
2902 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2903 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2904 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2905 | |
691874fa MR |
2906 | /* |
2907 | * Some BIOS writers are clueless and report the ExtINTA | |
2908 | * I/O APIC input from the cascaded 8259A as the timer | |
2909 | * interrupt input. So just in case, if only one pin | |
2910 | * was found above, try it both directly and through the | |
2911 | * 8259A. | |
2912 | */ | |
2913 | if (pin1 == -1) { | |
54168ed7 IM |
2914 | #ifdef CONFIG_INTR_REMAP |
2915 | if (intr_remapping_enabled) | |
2916 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2917 | #endif | |
691874fa MR |
2918 | pin1 = pin2; |
2919 | apic1 = apic2; | |
2920 | no_pin1 = 1; | |
2921 | } else if (pin2 == -1) { | |
2922 | pin2 = pin1; | |
2923 | apic2 = apic1; | |
2924 | } | |
2925 | ||
1da177e4 LT |
2926 | if (pin1 != -1) { |
2927 | /* | |
2928 | * Ok, does IRQ0 through the IOAPIC work? | |
2929 | */ | |
691874fa | 2930 | if (no_pin1) { |
3145e941 | 2931 | add_pin_to_irq_cpu(cfg, cpu, apic1, pin1); |
497c9a19 | 2932 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2933 | } |
3145e941 | 2934 | unmask_IO_APIC_irq_desc(desc); |
1da177e4 LT |
2935 | if (timer_irq_works()) { |
2936 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2937 | setup_nmi(); |
2938 | enable_8259A_irq(0); | |
1da177e4 | 2939 | } |
66759a01 CE |
2940 | if (disable_timer_pin_1 > 0) |
2941 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2942 | goto out; |
1da177e4 | 2943 | } |
54168ed7 IM |
2944 | #ifdef CONFIG_INTR_REMAP |
2945 | if (intr_remapping_enabled) | |
2946 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2947 | #endif | |
fcfd636a | 2948 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2949 | if (!no_pin1) |
49a66a0b MR |
2950 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2951 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2952 | |
49a66a0b MR |
2953 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2954 | "(IRQ0) through the 8259A ...\n"); | |
2955 | apic_printk(APIC_QUIET, KERN_INFO | |
2956 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2957 | /* |
2958 | * legacy devices should be connected to IO APIC #0 | |
2959 | */ | |
3145e941 | 2960 | replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2); |
497c9a19 | 2961 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
3145e941 | 2962 | unmask_IO_APIC_irq_desc(desc); |
ecd29476 | 2963 | enable_8259A_irq(0); |
1da177e4 | 2964 | if (timer_irq_works()) { |
49a66a0b | 2965 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2966 | timer_through_8259 = 1; |
1da177e4 | 2967 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2968 | disable_8259A_irq(0); |
1da177e4 | 2969 | setup_nmi(); |
60134ebe | 2970 | enable_8259A_irq(0); |
1da177e4 | 2971 | } |
4aae0702 | 2972 | goto out; |
1da177e4 LT |
2973 | } |
2974 | /* | |
2975 | * Cleanup, just in case ... | |
2976 | */ | |
ecd29476 | 2977 | disable_8259A_irq(0); |
fcfd636a | 2978 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2979 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2980 | } |
1da177e4 LT |
2981 | |
2982 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2983 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2984 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2985 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2986 | } |
54168ed7 | 2987 | #ifdef CONFIG_X86_32 |
d11d5794 | 2988 | timer_ack = 0; |
54168ed7 | 2989 | #endif |
1da177e4 | 2990 | |
49a66a0b MR |
2991 | apic_printk(APIC_QUIET, KERN_INFO |
2992 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2993 | |
3145e941 | 2994 | lapic_register_intr(0, desc); |
497c9a19 | 2995 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2996 | enable_8259A_irq(0); |
2997 | ||
2998 | if (timer_irq_works()) { | |
49a66a0b | 2999 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3000 | goto out; |
1da177e4 | 3001 | } |
e67465f1 | 3002 | disable_8259A_irq(0); |
497c9a19 | 3003 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3004 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3005 | |
49a66a0b MR |
3006 | apic_printk(APIC_QUIET, KERN_INFO |
3007 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3008 | |
1da177e4 LT |
3009 | init_8259A(0); |
3010 | make_8259A_irq(0); | |
593f4a78 | 3011 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3012 | |
3013 | unlock_ExtINT_logic(); | |
3014 | ||
3015 | if (timer_irq_works()) { | |
49a66a0b | 3016 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3017 | goto out; |
1da177e4 | 3018 | } |
49a66a0b | 3019 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3020 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3021 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3022 | out: |
3023 | local_irq_restore(flags); | |
1da177e4 LT |
3024 | } |
3025 | ||
3026 | /* | |
af174783 MR |
3027 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3028 | * to devices. However there may be an I/O APIC pin available for | |
3029 | * this interrupt regardless. The pin may be left unconnected, but | |
3030 | * typically it will be reused as an ExtINT cascade interrupt for | |
3031 | * the master 8259A. In the MPS case such a pin will normally be | |
3032 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3033 | * there is no provision for ExtINT interrupts, and in the absence | |
3034 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3035 | * interrupt, that is edge-triggered and unmasked by default. We | |
3036 | * used to do this, but it caused problems on some systems because | |
3037 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3038 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3039 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3040 | * the I/O APIC in all cases now. No actual device should request | |
3041 | * it anyway. --macro | |
1da177e4 LT |
3042 | */ |
3043 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3044 | ||
3045 | void __init setup_IO_APIC(void) | |
3046 | { | |
54168ed7 IM |
3047 | |
3048 | #ifdef CONFIG_X86_32 | |
1da177e4 | 3049 | enable_IO_APIC(); |
54168ed7 IM |
3050 | #else |
3051 | /* | |
3052 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3053 | */ | |
3054 | #endif | |
1da177e4 | 3055 | |
af174783 | 3056 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3057 | |
54168ed7 | 3058 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3059 | /* |
54168ed7 IM |
3060 | * Set up IO-APIC IRQ routing. |
3061 | */ | |
3062 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3063 | if (!acpi_ioapic) |
3064 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3065 | #endif |
1da177e4 LT |
3066 | sync_Arb_IDs(); |
3067 | setup_IO_APIC_irqs(); | |
3068 | init_IO_APIC_traps(); | |
1e4c85f9 | 3069 | check_timer(); |
1da177e4 LT |
3070 | } |
3071 | ||
3072 | /* | |
54168ed7 IM |
3073 | * Called after all the initialization is done. If we didnt find any |
3074 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3075 | */ |
36062448 | 3076 | |
1da177e4 LT |
3077 | static int __init io_apic_bug_finalize(void) |
3078 | { | |
d6c88a50 TG |
3079 | if (sis_apic_bug == -1) |
3080 | sis_apic_bug = 0; | |
3081 | return 0; | |
1da177e4 LT |
3082 | } |
3083 | ||
3084 | late_initcall(io_apic_bug_finalize); | |
3085 | ||
3086 | struct sysfs_ioapic_data { | |
3087 | struct sys_device dev; | |
3088 | struct IO_APIC_route_entry entry[0]; | |
3089 | }; | |
54168ed7 | 3090 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3091 | |
438510f6 | 3092 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3093 | { |
3094 | struct IO_APIC_route_entry *entry; | |
3095 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3096 | int i; |
36062448 | 3097 | |
1da177e4 LT |
3098 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3099 | entry = data->entry; | |
54168ed7 IM |
3100 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3101 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3102 | |
3103 | return 0; | |
3104 | } | |
3105 | ||
3106 | static int ioapic_resume(struct sys_device *dev) | |
3107 | { | |
3108 | struct IO_APIC_route_entry *entry; | |
3109 | struct sysfs_ioapic_data *data; | |
3110 | unsigned long flags; | |
3111 | union IO_APIC_reg_00 reg_00; | |
3112 | int i; | |
36062448 | 3113 | |
1da177e4 LT |
3114 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3115 | entry = data->entry; | |
3116 | ||
3117 | spin_lock_irqsave(&ioapic_lock, flags); | |
3118 | reg_00.raw = io_apic_read(dev->id, 0); | |
b5ba7e6d JSR |
3119 | if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) { |
3120 | reg_00.bits.ID = mp_ioapics[dev->id].apicid; | |
1da177e4 LT |
3121 | io_apic_write(dev->id, 0, reg_00.raw); |
3122 | } | |
1da177e4 | 3123 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3124 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3125 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3126 | |
3127 | return 0; | |
3128 | } | |
3129 | ||
3130 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3131 | .name = "ioapic", |
1da177e4 LT |
3132 | .suspend = ioapic_suspend, |
3133 | .resume = ioapic_resume, | |
3134 | }; | |
3135 | ||
3136 | static int __init ioapic_init_sysfs(void) | |
3137 | { | |
54168ed7 IM |
3138 | struct sys_device * dev; |
3139 | int i, size, error; | |
1da177e4 LT |
3140 | |
3141 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3142 | if (error) | |
3143 | return error; | |
3144 | ||
54168ed7 | 3145 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3146 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3147 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3148 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3149 | if (!mp_ioapic_data[i]) { |
3150 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3151 | continue; | |
3152 | } | |
1da177e4 | 3153 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3154 | dev->id = i; |
1da177e4 LT |
3155 | dev->cls = &ioapic_sysdev_class; |
3156 | error = sysdev_register(dev); | |
3157 | if (error) { | |
3158 | kfree(mp_ioapic_data[i]); | |
3159 | mp_ioapic_data[i] = NULL; | |
3160 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3161 | continue; | |
3162 | } | |
3163 | } | |
3164 | ||
3165 | return 0; | |
3166 | } | |
3167 | ||
3168 | device_initcall(ioapic_init_sysfs); | |
3169 | ||
3fc471ed | 3170 | /* |
95d77884 | 3171 | * Dynamic irq allocate and deallocation |
3fc471ed | 3172 | */ |
199751d7 | 3173 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3174 | { |
ace80ab7 | 3175 | /* Allocate an unused irq */ |
54168ed7 IM |
3176 | unsigned int irq; |
3177 | unsigned int new; | |
3fc471ed | 3178 | unsigned long flags; |
0b8f1efa YL |
3179 | struct irq_cfg *cfg_new = NULL; |
3180 | int cpu = boot_cpu_id; | |
3181 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
3182 | |
3183 | irq = 0; | |
ace80ab7 | 3184 | spin_lock_irqsave(&vector_lock, flags); |
9594949b | 3185 | for (new = irq_want; new < nr_irqs; new++) { |
ace80ab7 EB |
3186 | if (platform_legacy_irq(new)) |
3187 | continue; | |
0b8f1efa YL |
3188 | |
3189 | desc_new = irq_to_desc_alloc_cpu(new, cpu); | |
3190 | if (!desc_new) { | |
3191 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3192 | continue; |
0b8f1efa YL |
3193 | } |
3194 | cfg_new = desc_new->chip_data; | |
3195 | ||
3196 | if (cfg_new->vector != 0) | |
ace80ab7 | 3197 | continue; |
3145e941 | 3198 | if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0) |
ace80ab7 EB |
3199 | irq = new; |
3200 | break; | |
3201 | } | |
3202 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3203 | |
199751d7 | 3204 | if (irq > 0) { |
3fc471ed | 3205 | dynamic_irq_init(irq); |
0b8f1efa YL |
3206 | /* restore it, in case dynamic_irq_init clear it */ |
3207 | if (desc_new) | |
3208 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3209 | } |
3210 | return irq; | |
3211 | } | |
3212 | ||
be5d5350 | 3213 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
199751d7 YL |
3214 | int create_irq(void) |
3215 | { | |
be5d5350 | 3216 | unsigned int irq_want; |
54168ed7 IM |
3217 | int irq; |
3218 | ||
be5d5350 YL |
3219 | irq_want = nr_irqs_gsi; |
3220 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3221 | |
3222 | if (irq == 0) | |
3223 | irq = -1; | |
3224 | ||
3225 | return irq; | |
199751d7 YL |
3226 | } |
3227 | ||
3fc471ed EB |
3228 | void destroy_irq(unsigned int irq) |
3229 | { | |
3230 | unsigned long flags; | |
0b8f1efa YL |
3231 | struct irq_cfg *cfg; |
3232 | struct irq_desc *desc; | |
3fc471ed | 3233 | |
0b8f1efa YL |
3234 | /* store it, in case dynamic_irq_cleanup clear it */ |
3235 | desc = irq_to_desc(irq); | |
3236 | cfg = desc->chip_data; | |
3fc471ed | 3237 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3238 | /* connect back irq_cfg */ |
3239 | if (desc) | |
3240 | desc->chip_data = cfg; | |
3fc471ed | 3241 | |
54168ed7 IM |
3242 | #ifdef CONFIG_INTR_REMAP |
3243 | free_irte(irq); | |
3244 | #endif | |
3fc471ed | 3245 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3246 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3247 | spin_unlock_irqrestore(&vector_lock, flags); |
3248 | } | |
3fc471ed | 3249 | |
2d3fcc1c | 3250 | /* |
27b46d76 | 3251 | * MSI message composition |
2d3fcc1c EB |
3252 | */ |
3253 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3254 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3255 | { |
497c9a19 YL |
3256 | struct irq_cfg *cfg; |
3257 | int err; | |
2d3fcc1c EB |
3258 | unsigned dest; |
3259 | ||
f1182638 JB |
3260 | if (disable_apic) |
3261 | return -ENXIO; | |
3262 | ||
3145e941 | 3263 | cfg = irq_cfg(irq); |
22f65d31 | 3264 | err = assign_irq_vector(irq, cfg, TARGET_CPUS); |
497c9a19 YL |
3265 | if (err) |
3266 | return err; | |
2d3fcc1c | 3267 | |
22f65d31 | 3268 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
497c9a19 | 3269 | |
54168ed7 IM |
3270 | #ifdef CONFIG_INTR_REMAP |
3271 | if (irq_remapped(irq)) { | |
3272 | struct irte irte; | |
3273 | int ir_index; | |
3274 | u16 sub_handle; | |
3275 | ||
3276 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3277 | BUG_ON(ir_index == -1); | |
3278 | ||
3279 | memset (&irte, 0, sizeof(irte)); | |
3280 | ||
3281 | irte.present = 1; | |
9b5bc8dc | 3282 | irte.dst_mode = apic->irq_dest_mode; |
54168ed7 | 3283 | irte.trigger_mode = 0; /* edge */ |
9b5bc8dc | 3284 | irte.dlvry_mode = apic->irq_delivery_mode; |
54168ed7 IM |
3285 | irte.vector = cfg->vector; |
3286 | irte.dest_id = IRTE_DEST(dest); | |
3287 | ||
3288 | modify_irte(irq, &irte); | |
3289 | ||
3290 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3291 | msg->data = sub_handle; | |
3292 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3293 | MSI_ADDR_IR_SHV | | |
3294 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3295 | MSI_ADDR_IR_INDEX2(ir_index); | |
3296 | } else | |
3297 | #endif | |
3298 | { | |
3299 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3300 | msg->address_lo = | |
3301 | MSI_ADDR_BASE_LO | | |
9b5bc8dc | 3302 | ((apic->irq_dest_mode == 0) ? |
54168ed7 IM |
3303 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3304 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
9b5bc8dc | 3305 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3306 | MSI_ADDR_REDIRECTION_CPU: |
3307 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3308 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3309 | |
54168ed7 IM |
3310 | msg->data = |
3311 | MSI_DATA_TRIGGER_EDGE | | |
3312 | MSI_DATA_LEVEL_ASSERT | | |
9b5bc8dc | 3313 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
54168ed7 IM |
3314 | MSI_DATA_DELIVERY_FIXED: |
3315 | MSI_DATA_DELIVERY_LOWPRI) | | |
3316 | MSI_DATA_VECTOR(cfg->vector); | |
3317 | } | |
497c9a19 | 3318 | return err; |
2d3fcc1c EB |
3319 | } |
3320 | ||
3b7d1921 | 3321 | #ifdef CONFIG_SMP |
0de26520 | 3322 | static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3323 | { |
3145e941 | 3324 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3325 | struct irq_cfg *cfg; |
3b7d1921 EB |
3326 | struct msi_msg msg; |
3327 | unsigned int dest; | |
3b7d1921 | 3328 | |
22f65d31 MT |
3329 | dest = set_desc_affinity(desc, mask); |
3330 | if (dest == BAD_APICID) | |
497c9a19 | 3331 | return; |
2d3fcc1c | 3332 | |
3145e941 | 3333 | cfg = desc->chip_data; |
2d3fcc1c | 3334 | |
3145e941 | 3335 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3336 | |
3337 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3338 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3339 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3340 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3341 | ||
3145e941 | 3342 | write_msi_msg_desc(desc, &msg); |
2d3fcc1c | 3343 | } |
54168ed7 IM |
3344 | #ifdef CONFIG_INTR_REMAP |
3345 | /* | |
3346 | * Migrate the MSI irq to another cpumask. This migration is | |
3347 | * done in the process context using interrupt-remapping hardware. | |
3348 | */ | |
e7986739 MT |
3349 | static void |
3350 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) | |
54168ed7 | 3351 | { |
3145e941 | 3352 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3353 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3354 | unsigned int dest; |
54168ed7 | 3355 | struct irte irte; |
54168ed7 IM |
3356 | |
3357 | if (get_irte(irq, &irte)) | |
3358 | return; | |
3359 | ||
22f65d31 MT |
3360 | dest = set_desc_affinity(desc, mask); |
3361 | if (dest == BAD_APICID) | |
54168ed7 IM |
3362 | return; |
3363 | ||
54168ed7 IM |
3364 | irte.vector = cfg->vector; |
3365 | irte.dest_id = IRTE_DEST(dest); | |
3366 | ||
3367 | /* | |
3368 | * atomically update the IRTE with the new destination and vector. | |
3369 | */ | |
3370 | modify_irte(irq, &irte); | |
3371 | ||
3372 | /* | |
3373 | * After this point, all the interrupts will start arriving | |
3374 | * at the new destination. So, time to cleanup the previous | |
3375 | * vector allocation. | |
3376 | */ | |
22f65d31 MT |
3377 | if (cfg->move_in_progress) |
3378 | send_cleanup_vector(cfg); | |
54168ed7 | 3379 | } |
3145e941 | 3380 | |
54168ed7 | 3381 | #endif |
3b7d1921 | 3382 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3383 | |
3b7d1921 EB |
3384 | /* |
3385 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3386 | * which implement the MSI or MSI-X Capability Structure. | |
3387 | */ | |
3388 | static struct irq_chip msi_chip = { | |
3389 | .name = "PCI-MSI", | |
3390 | .unmask = unmask_msi_irq, | |
3391 | .mask = mask_msi_irq, | |
1d025192 | 3392 | .ack = ack_apic_edge, |
3b7d1921 EB |
3393 | #ifdef CONFIG_SMP |
3394 | .set_affinity = set_msi_irq_affinity, | |
3395 | #endif | |
3396 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3397 | }; |
3398 | ||
54168ed7 IM |
3399 | #ifdef CONFIG_INTR_REMAP |
3400 | static struct irq_chip msi_ir_chip = { | |
3401 | .name = "IR-PCI-MSI", | |
3402 | .unmask = unmask_msi_irq, | |
3403 | .mask = mask_msi_irq, | |
3404 | .ack = ack_x2apic_edge, | |
3405 | #ifdef CONFIG_SMP | |
3406 | .set_affinity = ir_set_msi_irq_affinity, | |
3407 | #endif | |
3408 | .retrigger = ioapic_retrigger_irq, | |
3409 | }; | |
3410 | ||
3411 | /* | |
3412 | * Map the PCI dev to the corresponding remapping hardware unit | |
3413 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3414 | * in it. | |
3415 | */ | |
3416 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3417 | { | |
3418 | struct intel_iommu *iommu; | |
3419 | int index; | |
3420 | ||
3421 | iommu = map_dev_to_ir(dev); | |
3422 | if (!iommu) { | |
3423 | printk(KERN_ERR | |
3424 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3425 | return -ENOENT; | |
3426 | } | |
3427 | ||
3428 | index = alloc_irte(iommu, irq, nvec); | |
3429 | if (index < 0) { | |
3430 | printk(KERN_ERR | |
3431 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3432 | pci_name(dev)); |
54168ed7 IM |
3433 | return -ENOSPC; |
3434 | } | |
3435 | return index; | |
3436 | } | |
3437 | #endif | |
1d025192 | 3438 | |
3145e941 | 3439 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3440 | { |
3441 | int ret; | |
3442 | struct msi_msg msg; | |
3443 | ||
3444 | ret = msi_compose_msg(dev, irq, &msg); | |
3445 | if (ret < 0) | |
3446 | return ret; | |
3447 | ||
3145e941 | 3448 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3449 | write_msi_msg(irq, &msg); |
3450 | ||
54168ed7 IM |
3451 | #ifdef CONFIG_INTR_REMAP |
3452 | if (irq_remapped(irq)) { | |
3453 | struct irq_desc *desc = irq_to_desc(irq); | |
3454 | /* | |
3455 | * irq migration in process context | |
3456 | */ | |
3457 | desc->status |= IRQ_MOVE_PCNTXT; | |
3458 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3459 | } else | |
3460 | #endif | |
3461 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 | 3462 | |
c81bba49 YL |
3463 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3464 | ||
1d025192 YL |
3465 | return 0; |
3466 | } | |
3467 | ||
047c8fdb YL |
3468 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3469 | { | |
54168ed7 IM |
3470 | unsigned int irq; |
3471 | int ret, sub_handle; | |
0b8f1efa | 3472 | struct msi_desc *msidesc; |
54168ed7 IM |
3473 | unsigned int irq_want; |
3474 | ||
3475 | #ifdef CONFIG_INTR_REMAP | |
3476 | struct intel_iommu *iommu = 0; | |
3477 | int index = 0; | |
3478 | #endif | |
3479 | ||
be5d5350 | 3480 | irq_want = nr_irqs_gsi; |
54168ed7 | 3481 | sub_handle = 0; |
0b8f1efa YL |
3482 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3483 | irq = create_irq_nr(irq_want); | |
be5d5350 | 3484 | irq_want++; |
54168ed7 IM |
3485 | if (irq == 0) |
3486 | return -1; | |
3487 | #ifdef CONFIG_INTR_REMAP | |
3488 | if (!intr_remapping_enabled) | |
3489 | goto no_ir; | |
3490 | ||
3491 | if (!sub_handle) { | |
3492 | /* | |
3493 | * allocate the consecutive block of IRTE's | |
3494 | * for 'nvec' | |
3495 | */ | |
3496 | index = msi_alloc_irte(dev, irq, nvec); | |
3497 | if (index < 0) { | |
3498 | ret = index; | |
3499 | goto error; | |
3500 | } | |
3501 | } else { | |
3502 | iommu = map_dev_to_ir(dev); | |
3503 | if (!iommu) { | |
3504 | ret = -ENOENT; | |
3505 | goto error; | |
3506 | } | |
3507 | /* | |
3508 | * setup the mapping between the irq and the IRTE | |
3509 | * base index, the sub_handle pointing to the | |
3510 | * appropriate interrupt remap table entry. | |
3511 | */ | |
3512 | set_irte_irq(irq, iommu, index, sub_handle); | |
3513 | } | |
3514 | no_ir: | |
3515 | #endif | |
0b8f1efa | 3516 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3517 | if (ret < 0) |
3518 | goto error; | |
3519 | sub_handle++; | |
3520 | } | |
3521 | return 0; | |
047c8fdb YL |
3522 | |
3523 | error: | |
54168ed7 IM |
3524 | destroy_irq(irq); |
3525 | return ret; | |
047c8fdb YL |
3526 | } |
3527 | ||
3b7d1921 EB |
3528 | void arch_teardown_msi_irq(unsigned int irq) |
3529 | { | |
f7feaca7 | 3530 | destroy_irq(irq); |
3b7d1921 EB |
3531 | } |
3532 | ||
54168ed7 IM |
3533 | #ifdef CONFIG_DMAR |
3534 | #ifdef CONFIG_SMP | |
22f65d31 | 3535 | static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3536 | { |
3145e941 | 3537 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3538 | struct irq_cfg *cfg; |
3539 | struct msi_msg msg; | |
3540 | unsigned int dest; | |
54168ed7 | 3541 | |
22f65d31 MT |
3542 | dest = set_desc_affinity(desc, mask); |
3543 | if (dest == BAD_APICID) | |
54168ed7 IM |
3544 | return; |
3545 | ||
3145e941 | 3546 | cfg = desc->chip_data; |
54168ed7 IM |
3547 | |
3548 | dmar_msi_read(irq, &msg); | |
3549 | ||
3550 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3551 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3552 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3553 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3554 | ||
3555 | dmar_msi_write(irq, &msg); | |
54168ed7 | 3556 | } |
3145e941 | 3557 | |
54168ed7 IM |
3558 | #endif /* CONFIG_SMP */ |
3559 | ||
3560 | struct irq_chip dmar_msi_type = { | |
3561 | .name = "DMAR_MSI", | |
3562 | .unmask = dmar_msi_unmask, | |
3563 | .mask = dmar_msi_mask, | |
3564 | .ack = ack_apic_edge, | |
3565 | #ifdef CONFIG_SMP | |
3566 | .set_affinity = dmar_msi_set_affinity, | |
3567 | #endif | |
3568 | .retrigger = ioapic_retrigger_irq, | |
3569 | }; | |
3570 | ||
3571 | int arch_setup_dmar_msi(unsigned int irq) | |
3572 | { | |
3573 | int ret; | |
3574 | struct msi_msg msg; | |
2d3fcc1c | 3575 | |
54168ed7 IM |
3576 | ret = msi_compose_msg(NULL, irq, &msg); |
3577 | if (ret < 0) | |
3578 | return ret; | |
3579 | dmar_msi_write(irq, &msg); | |
3580 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3581 | "edge"); | |
3582 | return 0; | |
3583 | } | |
3584 | #endif | |
3585 | ||
58ac1e76 | 3586 | #ifdef CONFIG_HPET_TIMER |
3587 | ||
3588 | #ifdef CONFIG_SMP | |
22f65d31 | 3589 | static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3590 | { |
3145e941 | 3591 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3592 | struct irq_cfg *cfg; |
58ac1e76 | 3593 | struct msi_msg msg; |
3594 | unsigned int dest; | |
58ac1e76 | 3595 | |
22f65d31 MT |
3596 | dest = set_desc_affinity(desc, mask); |
3597 | if (dest == BAD_APICID) | |
58ac1e76 | 3598 | return; |
3599 | ||
3145e941 | 3600 | cfg = desc->chip_data; |
58ac1e76 | 3601 | |
3602 | hpet_msi_read(irq, &msg); | |
3603 | ||
3604 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3605 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3606 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3607 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3608 | ||
3609 | hpet_msi_write(irq, &msg); | |
58ac1e76 | 3610 | } |
3145e941 | 3611 | |
58ac1e76 | 3612 | #endif /* CONFIG_SMP */ |
3613 | ||
3614 | struct irq_chip hpet_msi_type = { | |
3615 | .name = "HPET_MSI", | |
3616 | .unmask = hpet_msi_unmask, | |
3617 | .mask = hpet_msi_mask, | |
3618 | .ack = ack_apic_edge, | |
3619 | #ifdef CONFIG_SMP | |
3620 | .set_affinity = hpet_msi_set_affinity, | |
3621 | #endif | |
3622 | .retrigger = ioapic_retrigger_irq, | |
3623 | }; | |
3624 | ||
3625 | int arch_setup_hpet_msi(unsigned int irq) | |
3626 | { | |
3627 | int ret; | |
3628 | struct msi_msg msg; | |
3629 | ||
3630 | ret = msi_compose_msg(NULL, irq, &msg); | |
3631 | if (ret < 0) | |
3632 | return ret; | |
3633 | ||
3634 | hpet_msi_write(irq, &msg); | |
3635 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3636 | "edge"); | |
c81bba49 | 3637 | |
58ac1e76 | 3638 | return 0; |
3639 | } | |
3640 | #endif | |
3641 | ||
54168ed7 | 3642 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3643 | /* |
3644 | * Hypertransport interrupt support | |
3645 | */ | |
3646 | #ifdef CONFIG_HT_IRQ | |
3647 | ||
3648 | #ifdef CONFIG_SMP | |
3649 | ||
497c9a19 | 3650 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3651 | { |
ec68307c EB |
3652 | struct ht_irq_msg msg; |
3653 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3654 | |
497c9a19 | 3655 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3656 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3657 | |
497c9a19 | 3658 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3659 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3660 | |
ec68307c | 3661 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3662 | } |
3663 | ||
22f65d31 | 3664 | static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3665 | { |
3145e941 | 3666 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3667 | struct irq_cfg *cfg; |
8b955b0d | 3668 | unsigned int dest; |
8b955b0d | 3669 | |
22f65d31 MT |
3670 | dest = set_desc_affinity(desc, mask); |
3671 | if (dest == BAD_APICID) | |
497c9a19 | 3672 | return; |
8b955b0d | 3673 | |
3145e941 | 3674 | cfg = desc->chip_data; |
8b955b0d | 3675 | |
497c9a19 | 3676 | target_ht_irq(irq, dest, cfg->vector); |
8b955b0d | 3677 | } |
3145e941 | 3678 | |
8b955b0d EB |
3679 | #endif |
3680 | ||
c37e108d | 3681 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3682 | .name = "PCI-HT", |
3683 | .mask = mask_ht_irq, | |
3684 | .unmask = unmask_ht_irq, | |
1d025192 | 3685 | .ack = ack_apic_edge, |
8b955b0d EB |
3686 | #ifdef CONFIG_SMP |
3687 | .set_affinity = set_ht_irq_affinity, | |
3688 | #endif | |
3689 | .retrigger = ioapic_retrigger_irq, | |
3690 | }; | |
3691 | ||
3692 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3693 | { | |
497c9a19 YL |
3694 | struct irq_cfg *cfg; |
3695 | int err; | |
8b955b0d | 3696 | |
f1182638 JB |
3697 | if (disable_apic) |
3698 | return -ENXIO; | |
3699 | ||
3145e941 | 3700 | cfg = irq_cfg(irq); |
e7986739 | 3701 | err = assign_irq_vector(irq, cfg, TARGET_CPUS); |
54168ed7 | 3702 | if (!err) { |
ec68307c | 3703 | struct ht_irq_msg msg; |
8b955b0d | 3704 | unsigned dest; |
8b955b0d | 3705 | |
22f65d31 | 3706 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
8b955b0d | 3707 | |
ec68307c | 3708 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3709 | |
ec68307c EB |
3710 | msg.address_lo = |
3711 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3712 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3713 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
9b5bc8dc | 3714 | ((apic->irq_dest_mode == 0) ? |
8b955b0d EB |
3715 | HT_IRQ_LOW_DM_PHYSICAL : |
3716 | HT_IRQ_LOW_DM_LOGICAL) | | |
3717 | HT_IRQ_LOW_RQEOI_EDGE | | |
9b5bc8dc | 3718 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
8b955b0d EB |
3719 | HT_IRQ_LOW_MT_FIXED : |
3720 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3721 | HT_IRQ_LOW_IRQ_MASKED; | |
3722 | ||
ec68307c | 3723 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3724 | |
a460e745 IM |
3725 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3726 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3727 | |
3728 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3729 | } |
497c9a19 | 3730 | return err; |
8b955b0d EB |
3731 | } |
3732 | #endif /* CONFIG_HT_IRQ */ | |
3733 | ||
03b48632 | 3734 | #ifdef CONFIG_X86_UV |
4173a0e7 DN |
3735 | /* |
3736 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3737 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3738 | */ | |
3739 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3740 | unsigned long mmr_offset) | |
3741 | { | |
22f65d31 | 3742 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3743 | struct irq_cfg *cfg; |
3744 | int mmr_pnode; | |
3745 | unsigned long mmr_value; | |
3746 | struct uv_IO_APIC_route_entry *entry; | |
3747 | unsigned long flags; | |
3748 | int err; | |
3749 | ||
3145e941 YL |
3750 | cfg = irq_cfg(irq); |
3751 | ||
e7986739 | 3752 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3753 | if (err != 0) |
3754 | return err; | |
3755 | ||
3756 | spin_lock_irqsave(&vector_lock, flags); | |
3757 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3758 | irq_name); | |
3759 | spin_unlock_irqrestore(&vector_lock, flags); | |
3760 | ||
4173a0e7 DN |
3761 | mmr_value = 0; |
3762 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3763 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3764 | ||
3765 | entry->vector = cfg->vector; | |
9b5bc8dc IM |
3766 | entry->delivery_mode = apic->irq_delivery_mode; |
3767 | entry->dest_mode = apic->irq_dest_mode; | |
4173a0e7 DN |
3768 | entry->polarity = 0; |
3769 | entry->trigger = 0; | |
3770 | entry->mask = 0; | |
e7986739 | 3771 | entry->dest = cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3772 | |
3773 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3774 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3775 | ||
3776 | return irq; | |
3777 | } | |
3778 | ||
3779 | /* | |
3780 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3781 | * longer allowed to be sent. | |
3782 | */ | |
3783 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3784 | { | |
3785 | unsigned long mmr_value; | |
3786 | struct uv_IO_APIC_route_entry *entry; | |
3787 | int mmr_pnode; | |
3788 | ||
3789 | mmr_value = 0; | |
3790 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3791 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3792 | ||
3793 | entry->mask = 1; | |
3794 | ||
3795 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3796 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3797 | } | |
3798 | #endif /* CONFIG_X86_64 */ | |
3799 | ||
9d6a4d08 YL |
3800 | int __init io_apic_get_redir_entries (int ioapic) |
3801 | { | |
3802 | union IO_APIC_reg_01 reg_01; | |
3803 | unsigned long flags; | |
3804 | ||
3805 | spin_lock_irqsave(&ioapic_lock, flags); | |
3806 | reg_01.raw = io_apic_read(ioapic, 1); | |
3807 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3808 | ||
3809 | return reg_01.bits.entries; | |
3810 | } | |
3811 | ||
be5d5350 | 3812 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3813 | { |
be5d5350 YL |
3814 | int idx; |
3815 | int nr = 0; | |
3816 | ||
3817 | for (idx = 0; idx < nr_ioapics; idx++) | |
3818 | nr += io_apic_get_redir_entries(idx) + 1; | |
3819 | ||
3820 | if (nr > nr_irqs_gsi) | |
3821 | nr_irqs_gsi = nr; | |
9d6a4d08 YL |
3822 | } |
3823 | ||
4a046d17 YL |
3824 | #ifdef CONFIG_SPARSE_IRQ |
3825 | int __init arch_probe_nr_irqs(void) | |
3826 | { | |
3827 | int nr; | |
3828 | ||
3829 | nr = ((8 * nr_cpu_ids) > (32 * nr_ioapics) ? | |
3830 | (NR_VECTORS + (8 * nr_cpu_ids)) : | |
3831 | (NR_VECTORS + (32 * nr_ioapics))); | |
3832 | ||
3833 | if (nr < nr_irqs && nr > nr_irqs_gsi) | |
3834 | nr_irqs = nr; | |
3835 | ||
3836 | return 0; | |
3837 | } | |
3838 | #endif | |
3839 | ||
1da177e4 | 3840 | /* -------------------------------------------------------------------------- |
54168ed7 | 3841 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3842 | -------------------------------------------------------------------------- */ |
3843 | ||
888ba6c6 | 3844 | #ifdef CONFIG_ACPI |
1da177e4 | 3845 | |
54168ed7 | 3846 | #ifdef CONFIG_X86_32 |
36062448 | 3847 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3848 | { |
3849 | union IO_APIC_reg_00 reg_00; | |
3850 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3851 | physid_mask_t tmp; | |
3852 | unsigned long flags; | |
3853 | int i = 0; | |
3854 | ||
3855 | /* | |
36062448 PC |
3856 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3857 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3858 | * supports up to 16 on one shared APIC bus. |
36062448 | 3859 | * |
1da177e4 LT |
3860 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3861 | * advantage of new APIC bus architecture. | |
3862 | */ | |
3863 | ||
3864 | if (physids_empty(apic_id_map)) | |
3865 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3866 | ||
3867 | spin_lock_irqsave(&ioapic_lock, flags); | |
3868 | reg_00.raw = io_apic_read(ioapic, 0); | |
3869 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3870 | ||
3871 | if (apic_id >= get_physical_broadcast()) { | |
3872 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3873 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3874 | apic_id = reg_00.bits.ID; | |
3875 | } | |
3876 | ||
3877 | /* | |
36062448 | 3878 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3879 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3880 | */ | |
3881 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3882 | ||
3883 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3884 | if (!check_apicid_used(apic_id_map, i)) | |
3885 | break; | |
3886 | } | |
3887 | ||
3888 | if (i == get_physical_broadcast()) | |
3889 | panic("Max apic_id exceeded!\n"); | |
3890 | ||
3891 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3892 | "trying %d\n", ioapic, apic_id, i); | |
3893 | ||
3894 | apic_id = i; | |
36062448 | 3895 | } |
1da177e4 LT |
3896 | |
3897 | tmp = apicid_to_cpu_present(apic_id); | |
3898 | physids_or(apic_id_map, apic_id_map, tmp); | |
3899 | ||
3900 | if (reg_00.bits.ID != apic_id) { | |
3901 | reg_00.bits.ID = apic_id; | |
3902 | ||
3903 | spin_lock_irqsave(&ioapic_lock, flags); | |
3904 | io_apic_write(ioapic, 0, reg_00.raw); | |
3905 | reg_00.raw = io_apic_read(ioapic, 0); | |
3906 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3907 | ||
3908 | /* Sanity check */ | |
6070f9ec AD |
3909 | if (reg_00.bits.ID != apic_id) { |
3910 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3911 | return -1; | |
3912 | } | |
1da177e4 LT |
3913 | } |
3914 | ||
3915 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3916 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3917 | ||
3918 | return apic_id; | |
3919 | } | |
3920 | ||
36062448 | 3921 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3922 | { |
3923 | union IO_APIC_reg_01 reg_01; | |
3924 | unsigned long flags; | |
3925 | ||
3926 | spin_lock_irqsave(&ioapic_lock, flags); | |
3927 | reg_01.raw = io_apic_read(ioapic, 1); | |
3928 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3929 | ||
3930 | return reg_01.bits.version; | |
3931 | } | |
54168ed7 | 3932 | #endif |
1da177e4 | 3933 | |
54168ed7 | 3934 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3935 | { |
0b8f1efa YL |
3936 | struct irq_desc *desc; |
3937 | struct irq_cfg *cfg; | |
3938 | int cpu = boot_cpu_id; | |
3939 | ||
1da177e4 | 3940 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3941 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3942 | ioapic); |
3943 | return -EINVAL; | |
3944 | } | |
3945 | ||
0b8f1efa YL |
3946 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
3947 | if (!desc) { | |
3948 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3949 | return 0; | |
3950 | } | |
3951 | ||
1da177e4 LT |
3952 | /* |
3953 | * IRQs < 16 are already in the irq_2_pin[] map | |
3954 | */ | |
99d093d1 | 3955 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3956 | cfg = desc->chip_data; |
3145e941 | 3957 | add_pin_to_irq_cpu(cfg, cpu, ioapic, pin); |
0b8f1efa | 3958 | } |
1da177e4 | 3959 | |
3145e941 | 3960 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3961 | |
3962 | return 0; | |
3963 | } | |
3964 | ||
54168ed7 | 3965 | |
61fd47e0 SL |
3966 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3967 | { | |
3968 | int i; | |
3969 | ||
3970 | if (skip_ioapic_setup) | |
3971 | return -1; | |
3972 | ||
3973 | for (i = 0; i < mp_irq_entries; i++) | |
c2c21745 JSR |
3974 | if (mp_irqs[i].irqtype == mp_INT && |
3975 | mp_irqs[i].srcbusirq == bus_irq) | |
61fd47e0 SL |
3976 | break; |
3977 | if (i >= mp_irq_entries) | |
3978 | return -1; | |
3979 | ||
3980 | *trigger = irq_trigger(i); | |
3981 | *polarity = irq_polarity(i); | |
3982 | return 0; | |
3983 | } | |
3984 | ||
888ba6c6 | 3985 | #endif /* CONFIG_ACPI */ |
1a3f239d | 3986 | |
497c9a19 YL |
3987 | /* |
3988 | * This function currently is only a helper for the i386 smp boot process where | |
3989 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
3990 | * so mask in all cases should simply be TARGET_CPUS | |
3991 | */ | |
3992 | #ifdef CONFIG_SMP | |
3993 | void __init setup_ioapic_dest(void) | |
3994 | { | |
3995 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 3996 | struct irq_desc *desc; |
497c9a19 | 3997 | struct irq_cfg *cfg; |
22f65d31 | 3998 | const struct cpumask *mask; |
497c9a19 YL |
3999 | |
4000 | if (skip_ioapic_setup == 1) | |
4001 | return; | |
4002 | ||
4003 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4004 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4005 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4006 | if (irq_entry == -1) | |
4007 | continue; | |
4008 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4009 | ||
4010 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4011 | * when you have too many devices, because at that time only boot | |
4012 | * cpu is online. | |
4013 | */ | |
0b8f1efa YL |
4014 | desc = irq_to_desc(irq); |
4015 | cfg = desc->chip_data; | |
6c2e9403 | 4016 | if (!cfg->vector) { |
3145e941 | 4017 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4018 | irq_trigger(irq_entry), |
4019 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4020 | continue; |
4021 | ||
4022 | } | |
4023 | ||
4024 | /* | |
4025 | * Honour affinities which have been set in early boot | |
4026 | */ | |
6c2e9403 TG |
4027 | if (desc->status & |
4028 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
7f7ace0c | 4029 | mask = desc->affinity; |
6c2e9403 TG |
4030 | else |
4031 | mask = TARGET_CPUS; | |
4032 | ||
54168ed7 | 4033 | #ifdef CONFIG_INTR_REMAP |
6c2e9403 | 4034 | if (intr_remapping_enabled) |
3145e941 | 4035 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4036 | else |
6c2e9403 | 4037 | #endif |
3145e941 | 4038 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4039 | } |
4040 | ||
4041 | } | |
4042 | } | |
4043 | #endif | |
4044 | ||
54168ed7 IM |
4045 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4046 | ||
4047 | static struct resource *ioapic_resources; | |
4048 | ||
4049 | static struct resource * __init ioapic_setup_resources(void) | |
4050 | { | |
4051 | unsigned long n; | |
4052 | struct resource *res; | |
4053 | char *mem; | |
4054 | int i; | |
4055 | ||
4056 | if (nr_ioapics <= 0) | |
4057 | return NULL; | |
4058 | ||
4059 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4060 | n *= nr_ioapics; | |
4061 | ||
4062 | mem = alloc_bootmem(n); | |
4063 | res = (void *)mem; | |
4064 | ||
4065 | if (mem != NULL) { | |
4066 | mem += sizeof(struct resource) * nr_ioapics; | |
4067 | ||
4068 | for (i = 0; i < nr_ioapics; i++) { | |
4069 | res[i].name = mem; | |
4070 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4071 | sprintf(mem, "IOAPIC %u", i); | |
4072 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4073 | } | |
4074 | } | |
4075 | ||
4076 | ioapic_resources = res; | |
4077 | ||
4078 | return res; | |
4079 | } | |
54168ed7 | 4080 | |
f3294a33 YL |
4081 | void __init ioapic_init_mappings(void) |
4082 | { | |
4083 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4084 | struct resource *ioapic_res; |
d6c88a50 | 4085 | int i; |
f3294a33 | 4086 | |
54168ed7 | 4087 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4088 | for (i = 0; i < nr_ioapics; i++) { |
4089 | if (smp_found_config) { | |
b5ba7e6d | 4090 | ioapic_phys = mp_ioapics[i].apicaddr; |
54168ed7 | 4091 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4092 | if (!ioapic_phys) { |
4093 | printk(KERN_ERR | |
4094 | "WARNING: bogus zero IO-APIC " | |
4095 | "address found in MPTABLE, " | |
4096 | "disabling IO/APIC support!\n"); | |
4097 | smp_found_config = 0; | |
4098 | skip_ioapic_setup = 1; | |
4099 | goto fake_ioapic_page; | |
4100 | } | |
54168ed7 | 4101 | #endif |
f3294a33 | 4102 | } else { |
54168ed7 | 4103 | #ifdef CONFIG_X86_32 |
f3294a33 | 4104 | fake_ioapic_page: |
54168ed7 | 4105 | #endif |
f3294a33 | 4106 | ioapic_phys = (unsigned long) |
54168ed7 | 4107 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4108 | ioapic_phys = __pa(ioapic_phys); |
4109 | } | |
4110 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4111 | apic_printk(APIC_VERBOSE, |
4112 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4113 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4114 | idx++; |
54168ed7 | 4115 | |
54168ed7 IM |
4116 | if (ioapic_res != NULL) { |
4117 | ioapic_res->start = ioapic_phys; | |
4118 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4119 | ioapic_res++; | |
4120 | } | |
f3294a33 YL |
4121 | } |
4122 | } | |
4123 | ||
54168ed7 IM |
4124 | static int __init ioapic_insert_resources(void) |
4125 | { | |
4126 | int i; | |
4127 | struct resource *r = ioapic_resources; | |
4128 | ||
4129 | if (!r) { | |
4130 | printk(KERN_ERR | |
4131 | "IO APIC resources could be not be allocated.\n"); | |
4132 | return -1; | |
4133 | } | |
4134 | ||
4135 | for (i = 0; i < nr_ioapics; i++) { | |
4136 | insert_resource(&iomem_resource, r); | |
4137 | r++; | |
4138 | } | |
4139 | ||
4140 | return 0; | |
4141 | } | |
4142 | ||
4143 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4144 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4145 | late_initcall(ioapic_insert_resources); |