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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
49 | #include <asm/desc.h> | |
d4057bdb YL |
50 | #include <asm/proto.h> |
51 | #include <asm/acpi.h> | |
52 | #include <asm/dma.h> | |
1da177e4 | 53 | #include <asm/timer.h> |
306e440d | 54 | #include <asm/i8259.h> |
3e4ff115 | 55 | #include <asm/nmi.h> |
2d3fcc1c | 56 | #include <asm/msidef.h> |
8b955b0d | 57 | #include <asm/hypertransport.h> |
a4dbc34d | 58 | #include <asm/setup.h> |
d4057bdb | 59 | #include <asm/irq_remapping.h> |
58ac1e76 | 60 | #include <asm/hpet.h> |
4173a0e7 DN |
61 | #include <asm/uv/uv_hub.h> |
62 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 63 | |
497c9a19 | 64 | #include <mach_ipi.h> |
1da177e4 | 65 | #include <mach_apic.h> |
874c4fe3 | 66 | #include <mach_apicdef.h> |
1da177e4 | 67 | |
32f71aff MR |
68 | #define __apicdebuginit(type) static type __init |
69 | ||
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
ec2cd0a2 | 85 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
584f734d | 88 | /* MP IRQ source entries */ |
2fddb6e2 | 89 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
90 | |
91 | /* # of MP IRQ source entries */ | |
92 | int mp_irq_entries; | |
93 | ||
8732fc4b AS |
94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
96 | #endif | |
97 | ||
98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
99 | ||
efa2559f YL |
100 | int skip_ioapic_setup; |
101 | ||
54168ed7 | 102 | static int __init parse_noapic(char *str) |
efa2559f YL |
103 | { |
104 | /* disable IO-APIC */ | |
105 | disable_ioapic_setup(); | |
106 | return 0; | |
107 | } | |
108 | early_param("noapic", parse_noapic); | |
66759a01 | 109 | |
0f978f45 | 110 | struct irq_pin_list; |
0b8f1efa YL |
111 | |
112 | /* | |
113 | * This is performance-critical, we want to do it O(1) | |
114 | * | |
115 | * the indexing order of this array favors 1:1 mappings | |
116 | * between pins and IRQs. | |
117 | */ | |
118 | ||
119 | struct irq_pin_list { | |
120 | int apic, pin; | |
121 | struct irq_pin_list *next; | |
122 | }; | |
123 | ||
124 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
125 | { | |
126 | struct irq_pin_list *pin; | |
127 | int node; | |
128 | ||
129 | node = cpu_to_node(cpu); | |
130 | ||
131 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
132 | printk(KERN_DEBUG " alloc irq_2_pin on cpu %d node %d\n", cpu, node); | |
133 | ||
134 | return pin; | |
135 | } | |
136 | ||
a1420f39 | 137 | struct irq_cfg { |
0f978f45 | 138 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
139 | cpumask_var_t domain; |
140 | cpumask_var_t old_domain; | |
497c9a19 | 141 | unsigned move_cleanup_count; |
a1420f39 | 142 | u8 vector; |
497c9a19 | 143 | u8 move_in_progress : 1; |
48a1b10a YL |
144 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
145 | u8 move_desc_pending : 1; | |
146 | #endif | |
a1420f39 YL |
147 | }; |
148 | ||
a1420f39 | 149 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
150 | #ifdef CONFIG_SPARSE_IRQ |
151 | static struct irq_cfg irq_cfgx[] = { | |
152 | #else | |
d6c88a50 | 153 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 154 | #endif |
22f65d31 MT |
155 | [0] = { .vector = IRQ0_VECTOR, }, |
156 | [1] = { .vector = IRQ1_VECTOR, }, | |
157 | [2] = { .vector = IRQ2_VECTOR, }, | |
158 | [3] = { .vector = IRQ3_VECTOR, }, | |
159 | [4] = { .vector = IRQ4_VECTOR, }, | |
160 | [5] = { .vector = IRQ5_VECTOR, }, | |
161 | [6] = { .vector = IRQ6_VECTOR, }, | |
162 | [7] = { .vector = IRQ7_VECTOR, }, | |
163 | [8] = { .vector = IRQ8_VECTOR, }, | |
164 | [9] = { .vector = IRQ9_VECTOR, }, | |
165 | [10] = { .vector = IRQ10_VECTOR, }, | |
166 | [11] = { .vector = IRQ11_VECTOR, }, | |
167 | [12] = { .vector = IRQ12_VECTOR, }, | |
168 | [13] = { .vector = IRQ13_VECTOR, }, | |
169 | [14] = { .vector = IRQ14_VECTOR, }, | |
170 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
171 | }; |
172 | ||
0b8f1efa | 173 | void __init arch_early_irq_init(void) |
8f09cd20 | 174 | { |
0b8f1efa YL |
175 | struct irq_cfg *cfg; |
176 | struct irq_desc *desc; | |
177 | int count; | |
178 | int i; | |
d6c88a50 | 179 | |
0b8f1efa YL |
180 | cfg = irq_cfgx; |
181 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 182 | |
0b8f1efa YL |
183 | for (i = 0; i < count; i++) { |
184 | desc = irq_to_desc(i); | |
185 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
186 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
187 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
188 | if (i < NR_IRQS_LEGACY) | |
189 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 190 | } |
8f09cd20 | 191 | } |
d6c88a50 | 192 | |
0b8f1efa YL |
193 | #ifdef CONFIG_SPARSE_IRQ |
194 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
8f09cd20 | 195 | { |
0b8f1efa YL |
196 | struct irq_cfg *cfg = NULL; |
197 | struct irq_desc *desc; | |
1da177e4 | 198 | |
0b8f1efa YL |
199 | desc = irq_to_desc(irq); |
200 | if (desc) | |
201 | cfg = desc->chip_data; | |
0f978f45 | 202 | |
0b8f1efa | 203 | return cfg; |
8f09cd20 YL |
204 | } |
205 | ||
0b8f1efa | 206 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
0f978f45 | 207 | { |
0b8f1efa YL |
208 | struct irq_cfg *cfg; |
209 | int node; | |
d6c88a50 | 210 | |
0b8f1efa | 211 | node = cpu_to_node(cpu); |
1da177e4 | 212 | |
0b8f1efa | 213 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 MT |
214 | if (cfg) { |
215 | /* FIXME: needs alloc_cpumask_var_node() */ | |
216 | if (!alloc_cpumask_var(&cfg->domain, GFP_ATOMIC)) { | |
217 | kfree(cfg); | |
218 | cfg = NULL; | |
219 | } else if (!alloc_cpumask_var(&cfg->old_domain, GFP_ATOMIC)) { | |
220 | free_cpumask_var(cfg->domain); | |
221 | kfree(cfg); | |
222 | cfg = NULL; | |
223 | } else { | |
224 | cpumask_clear(cfg->domain); | |
225 | cpumask_clear(cfg->old_domain); | |
226 | } | |
227 | } | |
0b8f1efa | 228 | printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node); |
0f978f45 | 229 | |
0b8f1efa | 230 | return cfg; |
0f978f45 | 231 | } |
d6c88a50 | 232 | |
0b8f1efa | 233 | void arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 234 | { |
0b8f1efa | 235 | struct irq_cfg *cfg; |
0f978f45 | 236 | |
0b8f1efa YL |
237 | cfg = desc->chip_data; |
238 | if (!cfg) { | |
239 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
240 | if (!desc->chip_data) { | |
241 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
242 | BUG_ON(1); | |
243 | } | |
244 | } | |
0f978f45 | 245 | } |
0f978f45 | 246 | |
48a1b10a YL |
247 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
248 | ||
249 | static void | |
250 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu) | |
251 | { | |
252 | struct irq_pin_list *old_entry, *head, *tail, *entry; | |
253 | ||
254 | cfg->irq_2_pin = NULL; | |
255 | old_entry = old_cfg->irq_2_pin; | |
256 | if (!old_entry) | |
257 | return; | |
258 | ||
259 | entry = get_one_free_irq_2_pin(cpu); | |
260 | if (!entry) | |
261 | return; | |
262 | ||
263 | entry->apic = old_entry->apic; | |
264 | entry->pin = old_entry->pin; | |
265 | head = entry; | |
266 | tail = entry; | |
267 | old_entry = old_entry->next; | |
268 | while (old_entry) { | |
269 | entry = get_one_free_irq_2_pin(cpu); | |
270 | if (!entry) { | |
271 | entry = head; | |
272 | while (entry) { | |
273 | head = entry->next; | |
274 | kfree(entry); | |
275 | entry = head; | |
276 | } | |
277 | /* still use the old one */ | |
278 | return; | |
279 | } | |
280 | entry->apic = old_entry->apic; | |
281 | entry->pin = old_entry->pin; | |
282 | tail->next = entry; | |
283 | tail = entry; | |
284 | old_entry = old_entry->next; | |
285 | } | |
286 | ||
287 | tail->next = NULL; | |
288 | cfg->irq_2_pin = head; | |
289 | } | |
290 | ||
291 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) | |
292 | { | |
293 | struct irq_pin_list *entry, *next; | |
294 | ||
295 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) | |
296 | return; | |
297 | ||
298 | entry = old_cfg->irq_2_pin; | |
299 | ||
300 | while (entry) { | |
301 | next = entry->next; | |
302 | kfree(entry); | |
303 | entry = next; | |
304 | } | |
305 | old_cfg->irq_2_pin = NULL; | |
306 | } | |
307 | ||
308 | void arch_init_copy_chip_data(struct irq_desc *old_desc, | |
309 | struct irq_desc *desc, int cpu) | |
310 | { | |
311 | struct irq_cfg *cfg; | |
312 | struct irq_cfg *old_cfg; | |
313 | ||
314 | cfg = get_one_free_irq_cfg(cpu); | |
315 | ||
316 | if (!cfg) | |
317 | return; | |
318 | ||
319 | desc->chip_data = cfg; | |
320 | ||
321 | old_cfg = old_desc->chip_data; | |
322 | ||
323 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
324 | ||
325 | init_copy_irq_2_pin(old_cfg, cfg, cpu); | |
326 | } | |
327 | ||
328 | static void free_irq_cfg(struct irq_cfg *old_cfg) | |
329 | { | |
330 | kfree(old_cfg); | |
331 | } | |
332 | ||
333 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
334 | { | |
335 | struct irq_cfg *old_cfg, *cfg; | |
336 | ||
337 | old_cfg = old_desc->chip_data; | |
338 | cfg = desc->chip_data; | |
339 | ||
340 | if (old_cfg == cfg) | |
341 | return; | |
342 | ||
343 | if (old_cfg) { | |
344 | free_irq_2_pin(old_cfg, cfg); | |
345 | free_irq_cfg(old_cfg); | |
346 | old_desc->chip_data = NULL; | |
347 | } | |
348 | } | |
349 | ||
350 | static void set_extra_move_desc(struct irq_desc *desc, cpumask_t mask) | |
351 | { | |
352 | struct irq_cfg *cfg = desc->chip_data; | |
353 | ||
354 | if (!cfg->move_in_progress) { | |
355 | /* it means that domain is not changed */ | |
356 | if (!cpus_intersects(desc->affinity, mask)) | |
357 | cfg->move_desc_pending = 1; | |
358 | } | |
359 | } | |
360 | #endif | |
361 | ||
0b8f1efa YL |
362 | #else |
363 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
0f978f45 | 364 | { |
0b8f1efa | 365 | return irq < nr_irqs ? irq_cfgx + irq : NULL; |
0f978f45 | 366 | } |
0f978f45 | 367 | |
0b8f1efa | 368 | #endif |
301e6190 | 369 | |
48a1b10a | 370 | #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC |
e7986739 MT |
371 | static inline void |
372 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
3145e941 | 373 | { |
0f978f45 | 374 | } |
48a1b10a | 375 | #endif |
1da177e4 | 376 | |
130fe05d LT |
377 | struct io_apic { |
378 | unsigned int index; | |
379 | unsigned int unused[3]; | |
380 | unsigned int data; | |
381 | }; | |
382 | ||
383 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
384 | { | |
385 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 386 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
387 | } |
388 | ||
389 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
390 | { | |
391 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
392 | writel(reg, &io_apic->index); | |
393 | return readl(&io_apic->data); | |
394 | } | |
395 | ||
396 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
397 | { | |
398 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
399 | writel(reg, &io_apic->index); | |
400 | writel(value, &io_apic->data); | |
401 | } | |
402 | ||
403 | /* | |
404 | * Re-write a value: to be used for read-modify-write | |
405 | * cycles where the read already set up the index register. | |
406 | * | |
407 | * Older SiS APIC requires we rewrite the index register | |
408 | */ | |
409 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
410 | { | |
54168ed7 | 411 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
412 | |
413 | if (sis_apic_bug) | |
414 | writel(reg, &io_apic->index); | |
130fe05d LT |
415 | writel(value, &io_apic->data); |
416 | } | |
417 | ||
3145e941 | 418 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
419 | { |
420 | struct irq_pin_list *entry; | |
421 | unsigned long flags; | |
047c8fdb YL |
422 | |
423 | spin_lock_irqsave(&ioapic_lock, flags); | |
424 | entry = cfg->irq_2_pin; | |
425 | for (;;) { | |
426 | unsigned int reg; | |
427 | int pin; | |
428 | ||
429 | if (!entry) | |
430 | break; | |
431 | pin = entry->pin; | |
432 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
433 | /* Is the remote IRR bit set? */ | |
434 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
435 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
436 | return true; | |
437 | } | |
438 | if (!entry->next) | |
439 | break; | |
440 | entry = entry->next; | |
441 | } | |
442 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
443 | ||
444 | return false; | |
445 | } | |
047c8fdb | 446 | |
cf4c6a2f AK |
447 | union entry_union { |
448 | struct { u32 w1, w2; }; | |
449 | struct IO_APIC_route_entry entry; | |
450 | }; | |
451 | ||
452 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
453 | { | |
454 | union entry_union eu; | |
455 | unsigned long flags; | |
456 | spin_lock_irqsave(&ioapic_lock, flags); | |
457 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
458 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
459 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
460 | return eu.entry; | |
461 | } | |
462 | ||
f9dadfa7 LT |
463 | /* |
464 | * When we write a new IO APIC routing entry, we need to write the high | |
465 | * word first! If the mask bit in the low word is clear, we will enable | |
466 | * the interrupt, and we need to make sure the entry is fully populated | |
467 | * before that happens. | |
468 | */ | |
d15512f4 AK |
469 | static void |
470 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 471 | { |
cf4c6a2f AK |
472 | union entry_union eu; |
473 | eu.entry = e; | |
f9dadfa7 LT |
474 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
475 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
476 | } |
477 | ||
478 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
479 | { | |
480 | unsigned long flags; | |
481 | spin_lock_irqsave(&ioapic_lock, flags); | |
482 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
483 | spin_unlock_irqrestore(&ioapic_lock, flags); |
484 | } | |
485 | ||
486 | /* | |
487 | * When we mask an IO APIC routing entry, we need to write the low | |
488 | * word first, in order to set the mask bit before we change the | |
489 | * high bits! | |
490 | */ | |
491 | static void ioapic_mask_entry(int apic, int pin) | |
492 | { | |
493 | unsigned long flags; | |
494 | union entry_union eu = { .entry.mask = 1 }; | |
495 | ||
cf4c6a2f AK |
496 | spin_lock_irqsave(&ioapic_lock, flags); |
497 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
498 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
499 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
500 | } | |
501 | ||
497c9a19 | 502 | #ifdef CONFIG_SMP |
22f65d31 MT |
503 | static void send_cleanup_vector(struct irq_cfg *cfg) |
504 | { | |
505 | cpumask_var_t cleanup_mask; | |
506 | ||
507 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
508 | unsigned int i; | |
509 | cfg->move_cleanup_count = 0; | |
510 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
511 | cfg->move_cleanup_count++; | |
512 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
513 | send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
514 | } else { | |
515 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
516 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
517 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
518 | free_cpumask_var(cleanup_mask); | |
519 | } | |
520 | cfg->move_in_progress = 0; | |
521 | } | |
522 | ||
3145e941 | 523 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
524 | { |
525 | int apic, pin; | |
497c9a19 | 526 | struct irq_pin_list *entry; |
3145e941 | 527 | u8 vector = cfg->vector; |
497c9a19 | 528 | |
497c9a19 YL |
529 | entry = cfg->irq_2_pin; |
530 | for (;;) { | |
531 | unsigned int reg; | |
532 | ||
533 | if (!entry) | |
534 | break; | |
535 | ||
536 | apic = entry->apic; | |
537 | pin = entry->pin; | |
54168ed7 IM |
538 | #ifdef CONFIG_INTR_REMAP |
539 | /* | |
540 | * With interrupt-remapping, destination information comes | |
541 | * from interrupt-remapping table entry. | |
542 | */ | |
543 | if (!irq_remapped(irq)) | |
544 | io_apic_write(apic, 0x11 + pin*2, dest); | |
545 | #else | |
497c9a19 | 546 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 547 | #endif |
497c9a19 YL |
548 | reg = io_apic_read(apic, 0x10 + pin*2); |
549 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
550 | reg |= vector; | |
54168ed7 | 551 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
552 | if (!entry->next) |
553 | break; | |
554 | entry = entry->next; | |
555 | } | |
556 | } | |
efa2559f | 557 | |
e7986739 MT |
558 | static int |
559 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
efa2559f | 560 | |
22f65d31 MT |
561 | /* |
562 | * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid | |
563 | * of that, or returns BAD_APICID and leaves desc->affinity untouched. | |
564 | */ | |
565 | static unsigned int | |
566 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
567 | { |
568 | struct irq_cfg *cfg; | |
3145e941 | 569 | unsigned int irq; |
497c9a19 | 570 | |
0de26520 | 571 | if (!cpumask_intersects(mask, cpu_online_mask)) |
22f65d31 | 572 | return BAD_APICID; |
497c9a19 | 573 | |
3145e941 YL |
574 | irq = desc->irq; |
575 | cfg = desc->chip_data; | |
e7986739 | 576 | if (assign_irq_vector(irq, cfg, mask)) |
22f65d31 | 577 | return BAD_APICID; |
497c9a19 | 578 | |
22f65d31 | 579 | cpumask_and(&desc->affinity, cfg->domain, mask); |
e7986739 | 580 | set_extra_move_desc(desc, mask); |
22f65d31 MT |
581 | return cpu_mask_to_apicid_and(&desc->affinity, cpu_online_mask); |
582 | } | |
3145e941 | 583 | |
22f65d31 MT |
584 | static void |
585 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
586 | { | |
587 | struct irq_cfg *cfg; | |
588 | unsigned long flags; | |
589 | unsigned int dest; | |
590 | unsigned int irq; | |
591 | ||
592 | irq = desc->irq; | |
593 | cfg = desc->chip_data; | |
497c9a19 YL |
594 | |
595 | spin_lock_irqsave(&ioapic_lock, flags); | |
22f65d31 MT |
596 | dest = set_desc_affinity(desc, mask); |
597 | if (dest != BAD_APICID) { | |
598 | /* Only the high 8 bits are valid. */ | |
599 | dest = SET_APIC_LOGICAL_ID(dest); | |
600 | __target_IO_APIC_irq(irq, dest, cfg); | |
601 | } | |
497c9a19 YL |
602 | spin_unlock_irqrestore(&ioapic_lock, flags); |
603 | } | |
3145e941 | 604 | |
22f65d31 MT |
605 | static void |
606 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) | |
3145e941 YL |
607 | { |
608 | struct irq_desc *desc; | |
609 | ||
610 | desc = irq_to_desc(irq); | |
611 | ||
612 | set_ioapic_affinity_irq_desc(desc, mask); | |
613 | } | |
497c9a19 YL |
614 | #endif /* CONFIG_SMP */ |
615 | ||
1da177e4 LT |
616 | /* |
617 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
618 | * shared ISA-space IRQs, so we have to support them. We are super | |
619 | * fast in the common case, and fast for shared ISA-space IRQs. | |
620 | */ | |
3145e941 | 621 | static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin) |
1da177e4 | 622 | { |
0f978f45 YL |
623 | struct irq_pin_list *entry; |
624 | ||
0f978f45 YL |
625 | entry = cfg->irq_2_pin; |
626 | if (!entry) { | |
0b8f1efa YL |
627 | entry = get_one_free_irq_2_pin(cpu); |
628 | if (!entry) { | |
629 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
630 | apic, pin); | |
631 | return; | |
632 | } | |
0f978f45 YL |
633 | cfg->irq_2_pin = entry; |
634 | entry->apic = apic; | |
635 | entry->pin = pin; | |
0f978f45 YL |
636 | return; |
637 | } | |
1da177e4 | 638 | |
0f978f45 YL |
639 | while (entry->next) { |
640 | /* not again, please */ | |
641 | if (entry->apic == apic && entry->pin == pin) | |
642 | return; | |
1da177e4 | 643 | |
0f978f45 | 644 | entry = entry->next; |
1da177e4 | 645 | } |
0f978f45 | 646 | |
0b8f1efa | 647 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 648 | entry = entry->next; |
1da177e4 LT |
649 | entry->apic = apic; |
650 | entry->pin = pin; | |
651 | } | |
652 | ||
653 | /* | |
654 | * Reroute an IRQ to a different pin. | |
655 | */ | |
3145e941 | 656 | static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu, |
1da177e4 LT |
657 | int oldapic, int oldpin, |
658 | int newapic, int newpin) | |
659 | { | |
0f978f45 YL |
660 | struct irq_pin_list *entry = cfg->irq_2_pin; |
661 | int replaced = 0; | |
1da177e4 | 662 | |
0f978f45 | 663 | while (entry) { |
1da177e4 LT |
664 | if (entry->apic == oldapic && entry->pin == oldpin) { |
665 | entry->apic = newapic; | |
666 | entry->pin = newpin; | |
0f978f45 YL |
667 | replaced = 1; |
668 | /* every one is different, right? */ | |
1da177e4 | 669 | break; |
0f978f45 YL |
670 | } |
671 | entry = entry->next; | |
1da177e4 | 672 | } |
0f978f45 YL |
673 | |
674 | /* why? call replace before add? */ | |
675 | if (!replaced) | |
3145e941 | 676 | add_pin_to_irq_cpu(cfg, cpu, newapic, newpin); |
1da177e4 LT |
677 | } |
678 | ||
3145e941 | 679 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
680 | int mask_and, int mask_or, |
681 | void (*final)(struct irq_pin_list *entry)) | |
682 | { | |
683 | int pin; | |
87783be4 | 684 | struct irq_pin_list *entry; |
047c8fdb | 685 | |
87783be4 CG |
686 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
687 | unsigned int reg; | |
688 | pin = entry->pin; | |
689 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
690 | reg &= mask_and; | |
691 | reg |= mask_or; | |
692 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
693 | if (final) | |
694 | final(entry); | |
695 | } | |
696 | } | |
047c8fdb | 697 | |
3145e941 | 698 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 699 | { |
3145e941 | 700 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 701 | } |
047c8fdb | 702 | |
4e738e2f | 703 | #ifdef CONFIG_X86_64 |
87783be4 | 704 | void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 705 | { |
87783be4 CG |
706 | /* |
707 | * Synchronize the IO-APIC and the CPU by doing | |
708 | * a dummy read from the IO-APIC | |
709 | */ | |
710 | struct io_apic __iomem *io_apic; | |
711 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 712 | readl(&io_apic->data); |
1da177e4 LT |
713 | } |
714 | ||
3145e941 | 715 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 716 | { |
3145e941 | 717 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
718 | } |
719 | #else /* CONFIG_X86_32 */ | |
3145e941 | 720 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 721 | { |
3145e941 | 722 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 723 | } |
1da177e4 | 724 | |
3145e941 | 725 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 726 | { |
3145e941 | 727 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
728 | IO_APIC_REDIR_MASKED, NULL); |
729 | } | |
1da177e4 | 730 | |
3145e941 | 731 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 732 | { |
3145e941 | 733 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
734 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
735 | } | |
736 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 737 | |
3145e941 | 738 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 739 | { |
3145e941 | 740 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
741 | unsigned long flags; |
742 | ||
3145e941 YL |
743 | BUG_ON(!cfg); |
744 | ||
1da177e4 | 745 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 746 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
747 | spin_unlock_irqrestore(&ioapic_lock, flags); |
748 | } | |
749 | ||
3145e941 | 750 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 751 | { |
3145e941 | 752 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
753 | unsigned long flags; |
754 | ||
755 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 756 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
757 | spin_unlock_irqrestore(&ioapic_lock, flags); |
758 | } | |
759 | ||
3145e941 YL |
760 | static void mask_IO_APIC_irq(unsigned int irq) |
761 | { | |
762 | struct irq_desc *desc = irq_to_desc(irq); | |
763 | ||
764 | mask_IO_APIC_irq_desc(desc); | |
765 | } | |
766 | static void unmask_IO_APIC_irq(unsigned int irq) | |
767 | { | |
768 | struct irq_desc *desc = irq_to_desc(irq); | |
769 | ||
770 | unmask_IO_APIC_irq_desc(desc); | |
771 | } | |
772 | ||
1da177e4 LT |
773 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
774 | { | |
775 | struct IO_APIC_route_entry entry; | |
36062448 | 776 | |
1da177e4 | 777 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 778 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
779 | if (entry.delivery_mode == dest_SMI) |
780 | return; | |
1da177e4 LT |
781 | /* |
782 | * Disable it in the IO-APIC irq-routing table: | |
783 | */ | |
f9dadfa7 | 784 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
785 | } |
786 | ||
54168ed7 | 787 | static void clear_IO_APIC (void) |
1da177e4 LT |
788 | { |
789 | int apic, pin; | |
790 | ||
791 | for (apic = 0; apic < nr_ioapics; apic++) | |
792 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
793 | clear_IO_APIC_pin(apic, pin); | |
794 | } | |
795 | ||
54168ed7 | 796 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 797 | void send_IPI_self(int vector) |
1da177e4 LT |
798 | { |
799 | unsigned int cfg; | |
800 | ||
801 | /* | |
802 | * Wait for idle. | |
803 | */ | |
804 | apic_wait_icr_idle(); | |
805 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
806 | /* | |
807 | * Send the IPI. The write to APIC_ICR fires this off. | |
808 | */ | |
593f4a78 | 809 | apic_write(APIC_ICR, cfg); |
1da177e4 | 810 | } |
54168ed7 | 811 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 812 | |
54168ed7 | 813 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
814 | /* |
815 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
816 | * specific CPU-side IRQs. | |
817 | */ | |
818 | ||
819 | #define MAX_PIRQS 8 | |
820 | static int pirq_entries [MAX_PIRQS]; | |
821 | static int pirqs_enabled; | |
1da177e4 | 822 | |
1da177e4 LT |
823 | static int __init ioapic_pirq_setup(char *str) |
824 | { | |
825 | int i, max; | |
826 | int ints[MAX_PIRQS+1]; | |
827 | ||
828 | get_options(str, ARRAY_SIZE(ints), ints); | |
829 | ||
830 | for (i = 0; i < MAX_PIRQS; i++) | |
831 | pirq_entries[i] = -1; | |
832 | ||
833 | pirqs_enabled = 1; | |
834 | apic_printk(APIC_VERBOSE, KERN_INFO | |
835 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
836 | max = MAX_PIRQS; | |
837 | if (ints[0] < MAX_PIRQS) | |
838 | max = ints[0]; | |
839 | ||
840 | for (i = 0; i < max; i++) { | |
841 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
842 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
843 | /* | |
844 | * PIRQs are mapped upside down, usually. | |
845 | */ | |
846 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
847 | } | |
848 | return 1; | |
849 | } | |
850 | ||
851 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
852 | #endif /* CONFIG_X86_32 */ |
853 | ||
854 | #ifdef CONFIG_INTR_REMAP | |
855 | /* I/O APIC RTE contents at the OS boot up */ | |
856 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
857 | ||
858 | /* | |
859 | * Saves and masks all the unmasked IO-APIC RTE's | |
860 | */ | |
861 | int save_mask_IO_APIC_setup(void) | |
862 | { | |
863 | union IO_APIC_reg_01 reg_01; | |
864 | unsigned long flags; | |
865 | int apic, pin; | |
866 | ||
867 | /* | |
868 | * The number of IO-APIC IRQ registers (== #pins): | |
869 | */ | |
870 | for (apic = 0; apic < nr_ioapics; apic++) { | |
871 | spin_lock_irqsave(&ioapic_lock, flags); | |
872 | reg_01.raw = io_apic_read(apic, 1); | |
873 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
874 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
875 | } | |
876 | ||
877 | for (apic = 0; apic < nr_ioapics; apic++) { | |
878 | early_ioapic_entries[apic] = | |
879 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
880 | nr_ioapic_registers[apic], GFP_KERNEL); | |
881 | if (!early_ioapic_entries[apic]) | |
5ffa4eb2 | 882 | goto nomem; |
54168ed7 IM |
883 | } |
884 | ||
885 | for (apic = 0; apic < nr_ioapics; apic++) | |
886 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
887 | struct IO_APIC_route_entry entry; | |
888 | ||
889 | entry = early_ioapic_entries[apic][pin] = | |
890 | ioapic_read_entry(apic, pin); | |
891 | if (!entry.mask) { | |
892 | entry.mask = 1; | |
893 | ioapic_write_entry(apic, pin, entry); | |
894 | } | |
895 | } | |
5ffa4eb2 | 896 | |
54168ed7 | 897 | return 0; |
5ffa4eb2 CG |
898 | |
899 | nomem: | |
c1370b49 CG |
900 | while (apic >= 0) |
901 | kfree(early_ioapic_entries[apic--]); | |
5ffa4eb2 CG |
902 | memset(early_ioapic_entries, 0, |
903 | ARRAY_SIZE(early_ioapic_entries)); | |
904 | ||
905 | return -ENOMEM; | |
54168ed7 IM |
906 | } |
907 | ||
908 | void restore_IO_APIC_setup(void) | |
909 | { | |
910 | int apic, pin; | |
911 | ||
5ffa4eb2 CG |
912 | for (apic = 0; apic < nr_ioapics; apic++) { |
913 | if (!early_ioapic_entries[apic]) | |
914 | break; | |
54168ed7 IM |
915 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
916 | ioapic_write_entry(apic, pin, | |
917 | early_ioapic_entries[apic][pin]); | |
5ffa4eb2 CG |
918 | kfree(early_ioapic_entries[apic]); |
919 | early_ioapic_entries[apic] = NULL; | |
920 | } | |
54168ed7 IM |
921 | } |
922 | ||
923 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
924 | { | |
925 | /* | |
926 | * for now plain restore of previous settings. | |
927 | * TBD: In the case of OS enabling interrupt-remapping, | |
928 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
929 | * table entries. for now, do a plain restore, and wait for | |
930 | * the setup_IO_APIC_irqs() to do proper initialization. | |
931 | */ | |
932 | restore_IO_APIC_setup(); | |
933 | } | |
934 | #endif | |
1da177e4 LT |
935 | |
936 | /* | |
937 | * Find the IRQ entry number of a certain pin. | |
938 | */ | |
939 | static int find_irq_entry(int apic, int pin, int type) | |
940 | { | |
941 | int i; | |
942 | ||
943 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
944 | if (mp_irqs[i].mp_irqtype == type && |
945 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
946 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
947 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
948 | return i; |
949 | ||
950 | return -1; | |
951 | } | |
952 | ||
953 | /* | |
954 | * Find the pin to which IRQ[irq] (ISA) is connected | |
955 | */ | |
fcfd636a | 956 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
957 | { |
958 | int i; | |
959 | ||
960 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 961 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 962 | |
d27e2b8e | 963 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
964 | (mp_irqs[i].mp_irqtype == type) && |
965 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 966 | |
2fddb6e2 | 967 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
968 | } |
969 | return -1; | |
970 | } | |
971 | ||
fcfd636a EB |
972 | static int __init find_isa_irq_apic(int irq, int type) |
973 | { | |
974 | int i; | |
975 | ||
976 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 977 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 978 | |
73b2961b | 979 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
980 | (mp_irqs[i].mp_irqtype == type) && |
981 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
982 | break; |
983 | } | |
984 | if (i < mp_irq_entries) { | |
985 | int apic; | |
54168ed7 | 986 | for(apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 987 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
988 | return apic; |
989 | } | |
990 | } | |
991 | ||
992 | return -1; | |
993 | } | |
994 | ||
1da177e4 LT |
995 | /* |
996 | * Find a specific PCI IRQ entry. | |
997 | * Not an __init, possibly needed by modules | |
998 | */ | |
999 | static int pin_2_irq(int idx, int apic, int pin); | |
1000 | ||
1001 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
1002 | { | |
1003 | int apic, i, best_guess = -1; | |
1004 | ||
54168ed7 IM |
1005 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
1006 | bus, slot, pin); | |
ce6444d3 | 1007 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 1008 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
1009 | return -1; |
1010 | } | |
1011 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 1012 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
1013 | |
1014 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
1015 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
1016 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
1017 | break; |
1018 | ||
47cab822 | 1019 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 1020 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 1021 | (bus == lbus) && |
2fddb6e2 | 1022 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
54168ed7 | 1023 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
1da177e4 LT |
1024 | |
1025 | if (!(apic || IO_APIC_IRQ(irq))) | |
1026 | continue; | |
1027 | ||
2fddb6e2 | 1028 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
1029 | return irq; |
1030 | /* | |
1031 | * Use the first all-but-pin matching entry as a | |
1032 | * best-guess fuzzy result for broken mptables. | |
1033 | */ | |
1034 | if (best_guess < 0) | |
1035 | best_guess = irq; | |
1036 | } | |
1037 | } | |
1038 | return best_guess; | |
1039 | } | |
54168ed7 | 1040 | |
129f6946 | 1041 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 1042 | |
c0a282c2 | 1043 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1044 | /* |
1045 | * EISA Edge/Level control register, ELCR | |
1046 | */ | |
1047 | static int EISA_ELCR(unsigned int irq) | |
1048 | { | |
99d093d1 | 1049 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
1050 | unsigned int port = 0x4d0 + (irq >> 3); |
1051 | return (inb(port) >> (irq & 7)) & 1; | |
1052 | } | |
1053 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1054 | "Broken MPtable reports ISA irq %d\n", irq); | |
1055 | return 0; | |
1056 | } | |
54168ed7 | 1057 | |
c0a282c2 | 1058 | #endif |
1da177e4 | 1059 | |
6728801d AS |
1060 | /* ISA interrupts are always polarity zero edge triggered, |
1061 | * when listed as conforming in the MP table. */ | |
1062 | ||
1063 | #define default_ISA_trigger(idx) (0) | |
1064 | #define default_ISA_polarity(idx) (0) | |
1065 | ||
1da177e4 LT |
1066 | /* EISA interrupts are always polarity zero and can be edge or level |
1067 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1068 | * EISA conforming in the MP table, that means its trigger type must | |
1069 | * be read in from the ELCR */ | |
1070 | ||
2fddb6e2 | 1071 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 1072 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1073 | |
1074 | /* PCI interrupts are always polarity one level triggered, | |
1075 | * when listed as conforming in the MP table. */ | |
1076 | ||
1077 | #define default_PCI_trigger(idx) (1) | |
1078 | #define default_PCI_polarity(idx) (1) | |
1079 | ||
1080 | /* MCA interrupts are always polarity zero level triggered, | |
1081 | * when listed as conforming in the MP table. */ | |
1082 | ||
1083 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1084 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1085 | |
61fd47e0 | 1086 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1087 | { |
2fddb6e2 | 1088 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1089 | int polarity; |
1090 | ||
1091 | /* | |
1092 | * Determine IRQ line polarity (high active or low active): | |
1093 | */ | |
54168ed7 | 1094 | switch (mp_irqs[idx].mp_irqflag & 3) |
36062448 | 1095 | { |
54168ed7 IM |
1096 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1097 | if (test_bit(bus, mp_bus_not_pci)) | |
1098 | polarity = default_ISA_polarity(idx); | |
1099 | else | |
1100 | polarity = default_PCI_polarity(idx); | |
1101 | break; | |
1102 | case 1: /* high active */ | |
1103 | { | |
1104 | polarity = 0; | |
1105 | break; | |
1106 | } | |
1107 | case 2: /* reserved */ | |
1108 | { | |
1109 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1110 | polarity = 1; | |
1111 | break; | |
1112 | } | |
1113 | case 3: /* low active */ | |
1114 | { | |
1115 | polarity = 1; | |
1116 | break; | |
1117 | } | |
1118 | default: /* invalid */ | |
1119 | { | |
1120 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1121 | polarity = 1; | |
1122 | break; | |
1123 | } | |
1da177e4 LT |
1124 | } |
1125 | return polarity; | |
1126 | } | |
1127 | ||
1128 | static int MPBIOS_trigger(int idx) | |
1129 | { | |
2fddb6e2 | 1130 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1131 | int trigger; |
1132 | ||
1133 | /* | |
1134 | * Determine IRQ trigger mode (edge or level sensitive): | |
1135 | */ | |
54168ed7 | 1136 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 | 1137 | { |
54168ed7 IM |
1138 | case 0: /* conforms, ie. bus-type dependent */ |
1139 | if (test_bit(bus, mp_bus_not_pci)) | |
1140 | trigger = default_ISA_trigger(idx); | |
1141 | else | |
1142 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1143 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1144 | switch (mp_bus_id_to_type[bus]) { |
1145 | case MP_BUS_ISA: /* ISA pin */ | |
1146 | { | |
1147 | /* set before the switch */ | |
1148 | break; | |
1149 | } | |
1150 | case MP_BUS_EISA: /* EISA pin */ | |
1151 | { | |
1152 | trigger = default_EISA_trigger(idx); | |
1153 | break; | |
1154 | } | |
1155 | case MP_BUS_PCI: /* PCI pin */ | |
1156 | { | |
1157 | /* set before the switch */ | |
1158 | break; | |
1159 | } | |
1160 | case MP_BUS_MCA: /* MCA pin */ | |
1161 | { | |
1162 | trigger = default_MCA_trigger(idx); | |
1163 | break; | |
1164 | } | |
1165 | default: | |
1166 | { | |
1167 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1168 | trigger = 1; | |
1169 | break; | |
1170 | } | |
1171 | } | |
1172 | #endif | |
1da177e4 | 1173 | break; |
54168ed7 | 1174 | case 1: /* edge */ |
1da177e4 | 1175 | { |
54168ed7 | 1176 | trigger = 0; |
1da177e4 LT |
1177 | break; |
1178 | } | |
54168ed7 | 1179 | case 2: /* reserved */ |
1da177e4 | 1180 | { |
54168ed7 IM |
1181 | printk(KERN_WARNING "broken BIOS!!\n"); |
1182 | trigger = 1; | |
1da177e4 LT |
1183 | break; |
1184 | } | |
54168ed7 | 1185 | case 3: /* level */ |
1da177e4 | 1186 | { |
54168ed7 | 1187 | trigger = 1; |
1da177e4 LT |
1188 | break; |
1189 | } | |
54168ed7 | 1190 | default: /* invalid */ |
1da177e4 LT |
1191 | { |
1192 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1193 | trigger = 0; |
1da177e4 LT |
1194 | break; |
1195 | } | |
1196 | } | |
1197 | return trigger; | |
1198 | } | |
1199 | ||
1200 | static inline int irq_polarity(int idx) | |
1201 | { | |
1202 | return MPBIOS_polarity(idx); | |
1203 | } | |
1204 | ||
1205 | static inline int irq_trigger(int idx) | |
1206 | { | |
1207 | return MPBIOS_trigger(idx); | |
1208 | } | |
1209 | ||
efa2559f | 1210 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1211 | static int pin_2_irq(int idx, int apic, int pin) |
1212 | { | |
1213 | int irq, i; | |
2fddb6e2 | 1214 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1215 | |
1216 | /* | |
1217 | * Debugging check, we are in big trouble if this message pops up! | |
1218 | */ | |
2fddb6e2 | 1219 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1220 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1221 | ||
54168ed7 | 1222 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 1223 | irq = mp_irqs[idx].mp_srcbusirq; |
54168ed7 | 1224 | } else { |
643befed AS |
1225 | /* |
1226 | * PCI IRQs are mapped in order | |
1227 | */ | |
1228 | i = irq = 0; | |
1229 | while (i < apic) | |
1230 | irq += nr_ioapic_registers[i++]; | |
1231 | irq += pin; | |
d6c88a50 | 1232 | /* |
54168ed7 IM |
1233 | * For MPS mode, so far only needed by ES7000 platform |
1234 | */ | |
d6c88a50 TG |
1235 | if (ioapic_renumber_irq) |
1236 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1237 | } |
1238 | ||
54168ed7 | 1239 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1240 | /* |
1241 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1242 | */ | |
1243 | if ((pin >= 16) && (pin <= 23)) { | |
1244 | if (pirq_entries[pin-16] != -1) { | |
1245 | if (!pirq_entries[pin-16]) { | |
1246 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1247 | "disabling PIRQ%d\n", pin-16); | |
1248 | } else { | |
1249 | irq = pirq_entries[pin-16]; | |
1250 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1251 | "using PIRQ%d -> IRQ %d\n", | |
1252 | pin-16, irq); | |
1253 | } | |
1254 | } | |
1255 | } | |
54168ed7 IM |
1256 | #endif |
1257 | ||
1da177e4 LT |
1258 | return irq; |
1259 | } | |
1260 | ||
497c9a19 YL |
1261 | void lock_vector_lock(void) |
1262 | { | |
1263 | /* Used to the online set of cpus does not change | |
1264 | * during assign_irq_vector. | |
1265 | */ | |
1266 | spin_lock(&vector_lock); | |
1267 | } | |
1da177e4 | 1268 | |
497c9a19 | 1269 | void unlock_vector_lock(void) |
1da177e4 | 1270 | { |
497c9a19 YL |
1271 | spin_unlock(&vector_lock); |
1272 | } | |
1da177e4 | 1273 | |
e7986739 MT |
1274 | static int |
1275 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1276 | { |
047c8fdb YL |
1277 | /* |
1278 | * NOTE! The local APIC isn't very good at handling | |
1279 | * multiple interrupts at the same interrupt level. | |
1280 | * As the interrupt level is determined by taking the | |
1281 | * vector number and shifting that right by 4, we | |
1282 | * want to spread these out a bit so that they don't | |
1283 | * all fall in the same interrupt level. | |
1284 | * | |
1285 | * Also, we've got to be careful not to trash gate | |
1286 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1287 | */ | |
54168ed7 IM |
1288 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1289 | unsigned int old_vector; | |
22f65d31 MT |
1290 | int cpu, err; |
1291 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1292 | |
3145e941 YL |
1293 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1294 | return -EBUSY; | |
8339f000 | 1295 | |
22f65d31 MT |
1296 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1297 | return -ENOMEM; | |
1298 | ||
54168ed7 IM |
1299 | old_vector = cfg->vector; |
1300 | if (old_vector) { | |
22f65d31 MT |
1301 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1302 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1303 | if (!cpumask_empty(tmp_mask)) { | |
1304 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1305 | return 0; |
22f65d31 | 1306 | } |
54168ed7 | 1307 | } |
497c9a19 | 1308 | |
e7986739 | 1309 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1310 | err = -ENOSPC; |
1311 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1312 | int new_cpu; |
1313 | int vector, offset; | |
497c9a19 | 1314 | |
22f65d31 | 1315 | vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1316 | |
54168ed7 IM |
1317 | vector = current_vector; |
1318 | offset = current_offset; | |
497c9a19 | 1319 | next: |
54168ed7 IM |
1320 | vector += 8; |
1321 | if (vector >= first_system_vector) { | |
e7986739 | 1322 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1323 | offset = (offset + 1) % 8; |
1324 | vector = FIRST_DEVICE_VECTOR + offset; | |
1325 | } | |
1326 | if (unlikely(current_vector == vector)) | |
1327 | continue; | |
047c8fdb | 1328 | #ifdef CONFIG_X86_64 |
54168ed7 IM |
1329 | if (vector == IA32_SYSCALL_VECTOR) |
1330 | goto next; | |
047c8fdb | 1331 | #else |
54168ed7 IM |
1332 | if (vector == SYSCALL_VECTOR) |
1333 | goto next; | |
047c8fdb | 1334 | #endif |
22f65d31 | 1335 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1336 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1337 | goto next; | |
1338 | /* Found one! */ | |
1339 | current_vector = vector; | |
1340 | current_offset = offset; | |
1341 | if (old_vector) { | |
1342 | cfg->move_in_progress = 1; | |
22f65d31 | 1343 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1344 | } |
22f65d31 | 1345 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1346 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1347 | cfg->vector = vector; | |
22f65d31 MT |
1348 | cpumask_copy(cfg->domain, tmp_mask); |
1349 | err = 0; | |
1350 | break; | |
54168ed7 | 1351 | } |
22f65d31 MT |
1352 | free_cpumask_var(tmp_mask); |
1353 | return err; | |
497c9a19 YL |
1354 | } |
1355 | ||
e7986739 MT |
1356 | static int |
1357 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1358 | { |
1359 | int err; | |
ace80ab7 | 1360 | unsigned long flags; |
ace80ab7 EB |
1361 | |
1362 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1363 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1364 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1365 | return err; |
1366 | } | |
1367 | ||
3145e941 | 1368 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1369 | { |
497c9a19 YL |
1370 | int cpu, vector; |
1371 | ||
497c9a19 YL |
1372 | BUG_ON(!cfg->vector); |
1373 | ||
1374 | vector = cfg->vector; | |
22f65d31 | 1375 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1376 | per_cpu(vector_irq, cpu)[vector] = -1; |
1377 | ||
1378 | cfg->vector = 0; | |
22f65d31 | 1379 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1380 | |
1381 | if (likely(!cfg->move_in_progress)) | |
1382 | return; | |
22f65d31 | 1383 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1384 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1385 | vector++) { | |
1386 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1387 | continue; | |
1388 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1389 | break; | |
1390 | } | |
1391 | } | |
1392 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1393 | } |
1394 | ||
1395 | void __setup_vector_irq(int cpu) | |
1396 | { | |
1397 | /* Initialize vector_irq on a new cpu */ | |
1398 | /* This function must be called with vector_lock held */ | |
1399 | int irq, vector; | |
1400 | struct irq_cfg *cfg; | |
0b8f1efa | 1401 | struct irq_desc *desc; |
497c9a19 YL |
1402 | |
1403 | /* Mark the inuse vectors */ | |
0b8f1efa YL |
1404 | for_each_irq_desc(irq, desc) { |
1405 | if (!desc) | |
1406 | continue; | |
1407 | cfg = desc->chip_data; | |
22f65d31 | 1408 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1409 | continue; |
1410 | vector = cfg->vector; | |
497c9a19 YL |
1411 | per_cpu(vector_irq, cpu)[vector] = irq; |
1412 | } | |
1413 | /* Mark the free vectors */ | |
1414 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1415 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1416 | if (irq < 0) | |
1417 | continue; | |
1418 | ||
1419 | cfg = irq_cfg(irq); | |
22f65d31 | 1420 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1421 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1422 | } |
1da177e4 | 1423 | } |
3fde6900 | 1424 | |
f5b9ed7a | 1425 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1426 | #ifdef CONFIG_INTR_REMAP |
1427 | static struct irq_chip ir_ioapic_chip; | |
1428 | #endif | |
1da177e4 | 1429 | |
54168ed7 IM |
1430 | #define IOAPIC_AUTO -1 |
1431 | #define IOAPIC_EDGE 0 | |
1432 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1433 | |
047c8fdb | 1434 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1435 | static inline int IO_APIC_irq_trigger(int irq) |
1436 | { | |
d6c88a50 | 1437 | int apic, idx, pin; |
1d025192 | 1438 | |
d6c88a50 TG |
1439 | for (apic = 0; apic < nr_ioapics; apic++) { |
1440 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1441 | idx = find_irq_entry(apic, pin, mp_INT); | |
1442 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1443 | return irq_trigger(idx); | |
1444 | } | |
1445 | } | |
1446 | /* | |
54168ed7 IM |
1447 | * nonexistent IRQs are edge default |
1448 | */ | |
d6c88a50 | 1449 | return 0; |
1d025192 | 1450 | } |
047c8fdb YL |
1451 | #else |
1452 | static inline int IO_APIC_irq_trigger(int irq) | |
1453 | { | |
54168ed7 | 1454 | return 1; |
047c8fdb YL |
1455 | } |
1456 | #endif | |
1d025192 | 1457 | |
3145e941 | 1458 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1459 | { |
199751d7 | 1460 | |
6ebcc00e | 1461 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1462 | trigger == IOAPIC_LEVEL) |
08678b08 | 1463 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1464 | else |
1465 | desc->status &= ~IRQ_LEVEL; | |
1466 | ||
54168ed7 IM |
1467 | #ifdef CONFIG_INTR_REMAP |
1468 | if (irq_remapped(irq)) { | |
1469 | desc->status |= IRQ_MOVE_PCNTXT; | |
1470 | if (trigger) | |
1471 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1472 | handle_fasteoi_irq, | |
1473 | "fasteoi"); | |
1474 | else | |
1475 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1476 | handle_edge_irq, "edge"); | |
1477 | return; | |
1478 | } | |
1479 | #endif | |
047c8fdb YL |
1480 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1481 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1482 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1483 | handle_fasteoi_irq, |
1484 | "fasteoi"); | |
047c8fdb | 1485 | else |
a460e745 | 1486 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1487 | handle_edge_irq, "edge"); |
1da177e4 LT |
1488 | } |
1489 | ||
497c9a19 YL |
1490 | static int setup_ioapic_entry(int apic, int irq, |
1491 | struct IO_APIC_route_entry *entry, | |
1492 | unsigned int destination, int trigger, | |
1493 | int polarity, int vector) | |
1da177e4 | 1494 | { |
497c9a19 YL |
1495 | /* |
1496 | * add it to the IO-APIC irq-routing table: | |
1497 | */ | |
1498 | memset(entry,0,sizeof(*entry)); | |
1499 | ||
54168ed7 IM |
1500 | #ifdef CONFIG_INTR_REMAP |
1501 | if (intr_remapping_enabled) { | |
1502 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1503 | struct irte irte; | |
1504 | struct IR_IO_APIC_route_entry *ir_entry = | |
1505 | (struct IR_IO_APIC_route_entry *) entry; | |
1506 | int index; | |
1507 | ||
1508 | if (!iommu) | |
1509 | panic("No mapping iommu for ioapic %d\n", apic); | |
1510 | ||
1511 | index = alloc_irte(iommu, irq, 1); | |
1512 | if (index < 0) | |
1513 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1514 | ||
1515 | memset(&irte, 0, sizeof(irte)); | |
1516 | ||
1517 | irte.present = 1; | |
1518 | irte.dst_mode = INT_DEST_MODE; | |
1519 | irte.trigger_mode = trigger; | |
1520 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1521 | irte.vector = vector; | |
1522 | irte.dest_id = IRTE_DEST(destination); | |
1523 | ||
1524 | modify_irte(irq, &irte); | |
1525 | ||
1526 | ir_entry->index2 = (index >> 15) & 0x1; | |
1527 | ir_entry->zero = 0; | |
1528 | ir_entry->format = 1; | |
1529 | ir_entry->index = (index & 0x7fff); | |
1530 | } else | |
1531 | #endif | |
1532 | { | |
1533 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1534 | entry->dest_mode = INT_DEST_MODE; | |
1535 | entry->dest = destination; | |
1536 | } | |
497c9a19 | 1537 | |
54168ed7 | 1538 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1539 | entry->trigger = trigger; |
1540 | entry->polarity = polarity; | |
1541 | entry->vector = vector; | |
1542 | ||
1543 | /* Mask level triggered irqs. | |
1544 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1545 | */ | |
1546 | if (trigger) | |
1547 | entry->mask = 1; | |
497c9a19 YL |
1548 | return 0; |
1549 | } | |
1550 | ||
3145e941 | 1551 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1552 | int trigger, int polarity) |
497c9a19 YL |
1553 | { |
1554 | struct irq_cfg *cfg; | |
1da177e4 | 1555 | struct IO_APIC_route_entry entry; |
22f65d31 | 1556 | unsigned int dest; |
497c9a19 YL |
1557 | |
1558 | if (!IO_APIC_IRQ(irq)) | |
1559 | return; | |
1560 | ||
3145e941 | 1561 | cfg = desc->chip_data; |
497c9a19 | 1562 | |
22f65d31 | 1563 | if (assign_irq_vector(irq, cfg, TARGET_CPUS)) |
497c9a19 YL |
1564 | return; |
1565 | ||
22f65d31 | 1566 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
497c9a19 YL |
1567 | |
1568 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1569 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1570 | "IRQ %d Mode:%i Active:%i)\n", | |
1571 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1572 | irq, trigger, polarity); | |
1573 | ||
1574 | ||
1575 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
22f65d31 | 1576 | dest, trigger, polarity, cfg->vector)) { |
497c9a19 YL |
1577 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
1578 | mp_ioapics[apic].mp_apicid, pin); | |
3145e941 | 1579 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1580 | return; |
1581 | } | |
1582 | ||
3145e941 | 1583 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1584 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1585 | disable_8259A_irq(irq); |
1586 | ||
1587 | ioapic_write_entry(apic, pin, entry); | |
1588 | } | |
1589 | ||
1590 | static void __init setup_IO_APIC_irqs(void) | |
1591 | { | |
3c2cbd24 CG |
1592 | int apic, pin, idx, irq; |
1593 | int notcon = 0; | |
0b8f1efa | 1594 | struct irq_desc *desc; |
3145e941 | 1595 | struct irq_cfg *cfg; |
0b8f1efa | 1596 | int cpu = boot_cpu_id; |
1da177e4 LT |
1597 | |
1598 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1599 | ||
1600 | for (apic = 0; apic < nr_ioapics; apic++) { | |
3c2cbd24 | 1601 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
20d225b9 | 1602 | |
3c2cbd24 CG |
1603 | idx = find_irq_entry(apic, pin, mp_INT); |
1604 | if (idx == -1) { | |
2a554fb1 | 1605 | if (!notcon) { |
3c2cbd24 | 1606 | notcon = 1; |
2a554fb1 CG |
1607 | apic_printk(APIC_VERBOSE, |
1608 | KERN_DEBUG " %d-%d", | |
1609 | mp_ioapics[apic].mp_apicid, | |
1610 | pin); | |
1611 | } else | |
1612 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1613 | mp_ioapics[apic].mp_apicid, | |
1614 | pin); | |
3c2cbd24 CG |
1615 | continue; |
1616 | } | |
56ffa1a0 CG |
1617 | if (notcon) { |
1618 | apic_printk(APIC_VERBOSE, | |
1619 | " (apicid-pin) not connected\n"); | |
1620 | notcon = 0; | |
1621 | } | |
3c2cbd24 CG |
1622 | |
1623 | irq = pin_2_irq(idx, apic, pin); | |
54168ed7 | 1624 | #ifdef CONFIG_X86_32 |
3c2cbd24 CG |
1625 | if (multi_timer_check(apic, irq)) |
1626 | continue; | |
54168ed7 | 1627 | #endif |
0b8f1efa YL |
1628 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1629 | if (!desc) { | |
1630 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1631 | continue; | |
1632 | } | |
3145e941 YL |
1633 | cfg = desc->chip_data; |
1634 | add_pin_to_irq_cpu(cfg, cpu, apic, pin); | |
36062448 | 1635 | |
3145e941 | 1636 | setup_IO_APIC_irq(apic, pin, irq, desc, |
3c2cbd24 CG |
1637 | irq_trigger(idx), irq_polarity(idx)); |
1638 | } | |
1da177e4 LT |
1639 | } |
1640 | ||
3c2cbd24 CG |
1641 | if (notcon) |
1642 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1643 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1644 | } |
1645 | ||
1646 | /* | |
f7633ce5 | 1647 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1648 | */ |
f7633ce5 MR |
1649 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1650 | int vector) | |
1da177e4 LT |
1651 | { |
1652 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1653 | |
54168ed7 IM |
1654 | #ifdef CONFIG_INTR_REMAP |
1655 | if (intr_remapping_enabled) | |
1656 | return; | |
1657 | #endif | |
1658 | ||
36062448 | 1659 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1660 | |
1661 | /* | |
1662 | * We use logical delivery to get the timer IRQ | |
1663 | * to the first CPU. | |
1664 | */ | |
1665 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1666 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1667 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1668 | entry.delivery_mode = INT_DELIVERY_MODE; |
1669 | entry.polarity = 0; | |
1670 | entry.trigger = 0; | |
1671 | entry.vector = vector; | |
1672 | ||
1673 | /* | |
1674 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1675 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1676 | */ |
54168ed7 | 1677 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1678 | |
1679 | /* | |
1680 | * Add it to the IO-APIC irq-routing table: | |
1681 | */ | |
cf4c6a2f | 1682 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1683 | } |
1684 | ||
32f71aff MR |
1685 | |
1686 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1687 | { |
1688 | int apic, i; | |
1689 | union IO_APIC_reg_00 reg_00; | |
1690 | union IO_APIC_reg_01 reg_01; | |
1691 | union IO_APIC_reg_02 reg_02; | |
1692 | union IO_APIC_reg_03 reg_03; | |
1693 | unsigned long flags; | |
0f978f45 | 1694 | struct irq_cfg *cfg; |
0b8f1efa | 1695 | struct irq_desc *desc; |
8f09cd20 | 1696 | unsigned int irq; |
1da177e4 LT |
1697 | |
1698 | if (apic_verbosity == APIC_QUIET) | |
1699 | return; | |
1700 | ||
36062448 | 1701 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1702 | for (i = 0; i < nr_ioapics; i++) |
1703 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1704 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1705 | |
1706 | /* | |
1707 | * We are a bit conservative about what we expect. We have to | |
1708 | * know about every hardware change ASAP. | |
1709 | */ | |
1710 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1711 | ||
1712 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1713 | ||
1714 | spin_lock_irqsave(&ioapic_lock, flags); | |
1715 | reg_00.raw = io_apic_read(apic, 0); | |
1716 | reg_01.raw = io_apic_read(apic, 1); | |
1717 | if (reg_01.bits.version >= 0x10) | |
1718 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1719 | if (reg_01.bits.version >= 0x20) |
1720 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1721 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1722 | ||
54168ed7 | 1723 | printk("\n"); |
ec2cd0a2 | 1724 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1725 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1726 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1727 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1728 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1729 | |
54168ed7 | 1730 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1731 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1732 | |
1733 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1734 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1735 | |
1736 | /* | |
1737 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1738 | * but the value of reg_02 is read as the previous read register | |
1739 | * value, so ignore it if reg_02 == reg_01. | |
1740 | */ | |
1741 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1742 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1743 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1744 | } |
1745 | ||
1746 | /* | |
1747 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1748 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1749 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1750 | */ | |
1751 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1752 | reg_03.raw != reg_01.raw) { | |
1753 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1754 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1755 | } |
1756 | ||
1757 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1758 | ||
d83e94ac YL |
1759 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1760 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1761 | |
1762 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1763 | struct IO_APIC_route_entry entry; | |
1764 | ||
cf4c6a2f | 1765 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1766 | |
54168ed7 IM |
1767 | printk(KERN_DEBUG " %02x %03X ", |
1768 | i, | |
1769 | entry.dest | |
1770 | ); | |
1da177e4 LT |
1771 | |
1772 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1773 | entry.mask, | |
1774 | entry.trigger, | |
1775 | entry.irr, | |
1776 | entry.polarity, | |
1777 | entry.delivery_status, | |
1778 | entry.dest_mode, | |
1779 | entry.delivery_mode, | |
1780 | entry.vector | |
1781 | ); | |
1782 | } | |
1783 | } | |
1da177e4 | 1784 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1785 | for_each_irq_desc(irq, desc) { |
1786 | struct irq_pin_list *entry; | |
1787 | ||
1788 | if (!desc) | |
1789 | continue; | |
1790 | cfg = desc->chip_data; | |
1791 | entry = cfg->irq_2_pin; | |
0f978f45 | 1792 | if (!entry) |
1da177e4 | 1793 | continue; |
8f09cd20 | 1794 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1795 | for (;;) { |
1796 | printk("-> %d:%d", entry->apic, entry->pin); | |
1797 | if (!entry->next) | |
1798 | break; | |
0f978f45 | 1799 | entry = entry->next; |
1da177e4 LT |
1800 | } |
1801 | printk("\n"); | |
1802 | } | |
1803 | ||
1804 | printk(KERN_INFO ".................................... done.\n"); | |
1805 | ||
1806 | return; | |
1807 | } | |
1808 | ||
32f71aff | 1809 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1810 | { |
1811 | unsigned int v; | |
1812 | int i, j; | |
1813 | ||
1814 | if (apic_verbosity == APIC_QUIET) | |
1815 | return; | |
1816 | ||
1817 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1818 | for (i = 0; i < 8; i++) { | |
1819 | v = apic_read(base + i*0x10); | |
1820 | for (j = 0; j < 32; j++) { | |
1821 | if (v & (1<<j)) | |
1822 | printk("1"); | |
1823 | else | |
1824 | printk("0"); | |
1825 | } | |
1826 | printk("\n"); | |
1827 | } | |
1828 | } | |
1829 | ||
32f71aff | 1830 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1831 | { |
1832 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1833 | u64 icr; |
1da177e4 LT |
1834 | |
1835 | if (apic_verbosity == APIC_QUIET) | |
1836 | return; | |
1837 | ||
1838 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1839 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1840 | v = apic_read(APIC_ID); |
54168ed7 | 1841 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1842 | v = apic_read(APIC_LVR); |
1843 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1844 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1845 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1846 | |
1847 | v = apic_read(APIC_TASKPRI); | |
1848 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1849 | ||
54168ed7 | 1850 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1851 | if (!APIC_XAPIC(ver)) { |
1852 | v = apic_read(APIC_ARBPRI); | |
1853 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1854 | v & APIC_ARBPRI_MASK); | |
1855 | } | |
1da177e4 LT |
1856 | v = apic_read(APIC_PROCPRI); |
1857 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1858 | } | |
1859 | ||
a11b5abe YL |
1860 | /* |
1861 | * Remote read supported only in the 82489DX and local APIC for | |
1862 | * Pentium processors. | |
1863 | */ | |
1864 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1865 | v = apic_read(APIC_RRR); | |
1866 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1867 | } | |
1868 | ||
1da177e4 LT |
1869 | v = apic_read(APIC_LDR); |
1870 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1871 | if (!x2apic_enabled()) { |
1872 | v = apic_read(APIC_DFR); | |
1873 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1874 | } | |
1da177e4 LT |
1875 | v = apic_read(APIC_SPIV); |
1876 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1877 | ||
1878 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1879 | print_APIC_bitfield(APIC_ISR); | |
1880 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1881 | print_APIC_bitfield(APIC_TMR); | |
1882 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1883 | print_APIC_bitfield(APIC_IRR); | |
1884 | ||
54168ed7 IM |
1885 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1886 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1887 | apic_write(APIC_ESR, 0); |
54168ed7 | 1888 | |
1da177e4 LT |
1889 | v = apic_read(APIC_ESR); |
1890 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1891 | } | |
1892 | ||
7ab6af7a | 1893 | icr = apic_icr_read(); |
0c425cec IM |
1894 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1895 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1896 | |
1897 | v = apic_read(APIC_LVTT); | |
1898 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1899 | ||
1900 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1901 | v = apic_read(APIC_LVTPC); | |
1902 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1903 | } | |
1904 | v = apic_read(APIC_LVT0); | |
1905 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1906 | v = apic_read(APIC_LVT1); | |
1907 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1908 | ||
1909 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1910 | v = apic_read(APIC_LVTERR); | |
1911 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1912 | } | |
1913 | ||
1914 | v = apic_read(APIC_TMICT); | |
1915 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1916 | v = apic_read(APIC_TMCCT); | |
1917 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1918 | v = apic_read(APIC_TDCR); | |
1919 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1920 | printk("\n"); | |
1921 | } | |
1922 | ||
32f71aff | 1923 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1924 | { |
ffd5aae7 YL |
1925 | int cpu; |
1926 | ||
1927 | preempt_disable(); | |
1928 | for_each_online_cpu(cpu) | |
1929 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1930 | preempt_enable(); | |
1da177e4 LT |
1931 | } |
1932 | ||
32f71aff | 1933 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1934 | { |
1da177e4 LT |
1935 | unsigned int v; |
1936 | unsigned long flags; | |
1937 | ||
1938 | if (apic_verbosity == APIC_QUIET) | |
1939 | return; | |
1940 | ||
1941 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1942 | ||
1943 | spin_lock_irqsave(&i8259A_lock, flags); | |
1944 | ||
1945 | v = inb(0xa1) << 8 | inb(0x21); | |
1946 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1947 | ||
1948 | v = inb(0xa0) << 8 | inb(0x20); | |
1949 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1950 | ||
54168ed7 IM |
1951 | outb(0x0b,0xa0); |
1952 | outb(0x0b,0x20); | |
1da177e4 | 1953 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1954 | outb(0x0a,0xa0); |
1955 | outb(0x0a,0x20); | |
1da177e4 LT |
1956 | |
1957 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1958 | ||
1959 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1960 | ||
1961 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1962 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1963 | } | |
1964 | ||
32f71aff MR |
1965 | __apicdebuginit(int) print_all_ICs(void) |
1966 | { | |
1967 | print_PIC(); | |
1968 | print_all_local_APICs(); | |
1969 | print_IO_APIC(); | |
1970 | ||
1971 | return 0; | |
1972 | } | |
1973 | ||
1974 | fs_initcall(print_all_ICs); | |
1975 | ||
1da177e4 | 1976 | |
efa2559f YL |
1977 | /* Where if anywhere is the i8259 connect in external int mode */ |
1978 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1979 | ||
54168ed7 | 1980 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1981 | { |
1982 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1983 | int i8259_apic, i8259_pin; |
54168ed7 | 1984 | int apic; |
1da177e4 LT |
1985 | unsigned long flags; |
1986 | ||
54168ed7 IM |
1987 | #ifdef CONFIG_X86_32 |
1988 | int i; | |
1da177e4 LT |
1989 | if (!pirqs_enabled) |
1990 | for (i = 0; i < MAX_PIRQS; i++) | |
1991 | pirq_entries[i] = -1; | |
54168ed7 | 1992 | #endif |
1da177e4 LT |
1993 | |
1994 | /* | |
1995 | * The number of IO-APIC IRQ registers (== #pins): | |
1996 | */ | |
fcfd636a | 1997 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1998 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1999 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 2000 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
2001 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
2002 | } | |
54168ed7 | 2003 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
2004 | int pin; |
2005 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 2006 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 2007 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 2008 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 2009 | |
fcfd636a EB |
2010 | /* If the interrupt line is enabled and in ExtInt mode |
2011 | * I have found the pin where the i8259 is connected. | |
2012 | */ | |
2013 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
2014 | ioapic_i8259.apic = apic; | |
2015 | ioapic_i8259.pin = pin; | |
2016 | goto found_i8259; | |
2017 | } | |
2018 | } | |
2019 | } | |
2020 | found_i8259: | |
2021 | /* Look to see what if the MP table has reported the ExtINT */ | |
2022 | /* If we could not find the appropriate pin by looking at the ioapic | |
2023 | * the i8259 probably is not connected the ioapic but give the | |
2024 | * mptable a chance anyway. | |
2025 | */ | |
2026 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
2027 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
2028 | /* Trust the MP table if nothing is setup in the hardware */ | |
2029 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
2030 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
2031 | ioapic_i8259.pin = i8259_pin; | |
2032 | ioapic_i8259.apic = i8259_apic; | |
2033 | } | |
2034 | /* Complain if the MP table and the hardware disagree */ | |
2035 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2036 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2037 | { | |
2038 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2039 | } |
2040 | ||
2041 | /* | |
2042 | * Do not trust the IO-APIC being empty at bootup | |
2043 | */ | |
2044 | clear_IO_APIC(); | |
2045 | } | |
2046 | ||
2047 | /* | |
2048 | * Not an __init, needed by the reboot code | |
2049 | */ | |
2050 | void disable_IO_APIC(void) | |
2051 | { | |
2052 | /* | |
2053 | * Clear the IO-APIC before rebooting: | |
2054 | */ | |
2055 | clear_IO_APIC(); | |
2056 | ||
650927ef | 2057 | /* |
0b968d23 | 2058 | * If the i8259 is routed through an IOAPIC |
650927ef | 2059 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2060 | * so legacy interrupts can be delivered. |
650927ef | 2061 | */ |
fcfd636a | 2062 | if (ioapic_i8259.pin != -1) { |
650927ef | 2063 | struct IO_APIC_route_entry entry; |
650927ef EB |
2064 | |
2065 | memset(&entry, 0, sizeof(entry)); | |
2066 | entry.mask = 0; /* Enabled */ | |
2067 | entry.trigger = 0; /* Edge */ | |
2068 | entry.irr = 0; | |
2069 | entry.polarity = 0; /* High */ | |
2070 | entry.delivery_status = 0; | |
2071 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2072 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2073 | entry.vector = 0; |
54168ed7 | 2074 | entry.dest = read_apic_id(); |
650927ef EB |
2075 | |
2076 | /* | |
2077 | * Add it to the IO-APIC irq-routing table: | |
2078 | */ | |
cf4c6a2f | 2079 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2080 | } |
54168ed7 | 2081 | |
fcfd636a | 2082 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
2083 | } |
2084 | ||
54168ed7 | 2085 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2086 | /* |
2087 | * function to set the IO-APIC physical IDs based on the | |
2088 | * values stored in the MPC table. | |
2089 | * | |
2090 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2091 | */ | |
2092 | ||
1da177e4 LT |
2093 | static void __init setup_ioapic_ids_from_mpc(void) |
2094 | { | |
2095 | union IO_APIC_reg_00 reg_00; | |
2096 | physid_mask_t phys_id_present_map; | |
2097 | int apic; | |
2098 | int i; | |
2099 | unsigned char old_id; | |
2100 | unsigned long flags; | |
2101 | ||
a4dbc34d | 2102 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2103 | return; |
d49c4288 | 2104 | |
ca05fea6 NP |
2105 | /* |
2106 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2107 | * no meaning without the serial APIC bus. | |
2108 | */ | |
7c5c1e42 SL |
2109 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2110 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2111 | return; |
1da177e4 LT |
2112 | /* |
2113 | * This is broken; anything with a real cpu count has to | |
2114 | * circumvent this idiocy regardless. | |
2115 | */ | |
2116 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2117 | ||
2118 | /* | |
2119 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2120 | */ | |
2121 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2122 | ||
2123 | /* Read the register 0 value */ | |
2124 | spin_lock_irqsave(&ioapic_lock, flags); | |
2125 | reg_00.raw = io_apic_read(apic, 0); | |
2126 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 2127 | |
ec2cd0a2 | 2128 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2129 | |
ec2cd0a2 | 2130 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 2131 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 2132 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2133 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2134 | reg_00.bits.ID); | |
ec2cd0a2 | 2135 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
2136 | } |
2137 | ||
1da177e4 LT |
2138 | /* |
2139 | * Sanity check, is the ID really free? Every APIC in a | |
2140 | * system must have a unique ID or we get lots of nice | |
2141 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2142 | */ | |
2143 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 2144 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 2145 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 2146 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2147 | for (i = 0; i < get_physical_broadcast(); i++) |
2148 | if (!physid_isset(i, phys_id_present_map)) | |
2149 | break; | |
2150 | if (i >= get_physical_broadcast()) | |
2151 | panic("Max APIC ID exceeded!\n"); | |
2152 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2153 | i); | |
2154 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 2155 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
2156 | } else { |
2157 | physid_mask_t tmp; | |
ec2cd0a2 | 2158 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2159 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2160 | "phys_id_present_map\n", | |
ec2cd0a2 | 2161 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2162 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2163 | } | |
2164 | ||
2165 | ||
2166 | /* | |
2167 | * We need to adjust the IRQ routing table | |
2168 | * if the ID changed. | |
2169 | */ | |
ec2cd0a2 | 2170 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 2171 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
2172 | if (mp_irqs[i].mp_dstapic == old_id) |
2173 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 2174 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
2175 | |
2176 | /* | |
2177 | * Read the right value from the MPC table and | |
2178 | * write it into the ID register. | |
36062448 | 2179 | */ |
1da177e4 LT |
2180 | apic_printk(APIC_VERBOSE, KERN_INFO |
2181 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 2182 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 2183 | |
ec2cd0a2 | 2184 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2185 | spin_lock_irqsave(&ioapic_lock, flags); |
a2d332fa YL |
2186 | io_apic_write(apic, 0, reg_00.raw); |
2187 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1da177e4 LT |
2188 | |
2189 | /* | |
2190 | * Sanity check | |
2191 | */ | |
2192 | spin_lock_irqsave(&ioapic_lock, flags); | |
2193 | reg_00.raw = io_apic_read(apic, 0); | |
2194 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 2195 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
2196 | printk("could not set ID!\n"); |
2197 | else | |
2198 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2199 | } | |
2200 | } | |
54168ed7 | 2201 | #endif |
1da177e4 | 2202 | |
7ce0bcfd | 2203 | int no_timer_check __initdata; |
8542b200 ZA |
2204 | |
2205 | static int __init notimercheck(char *s) | |
2206 | { | |
2207 | no_timer_check = 1; | |
2208 | return 1; | |
2209 | } | |
2210 | __setup("no_timer_check", notimercheck); | |
2211 | ||
1da177e4 LT |
2212 | /* |
2213 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2214 | * about the timer IRQ. We do the following to work around the situation: | |
2215 | * | |
2216 | * - timer IRQ defaults to IO-APIC IRQ | |
2217 | * - if this function detects that timer IRQs are defunct, then we fall | |
2218 | * back to ISA timer IRQs | |
2219 | */ | |
f0a7a5c9 | 2220 | static int __init timer_irq_works(void) |
1da177e4 LT |
2221 | { |
2222 | unsigned long t1 = jiffies; | |
4aae0702 | 2223 | unsigned long flags; |
1da177e4 | 2224 | |
8542b200 ZA |
2225 | if (no_timer_check) |
2226 | return 1; | |
2227 | ||
4aae0702 | 2228 | local_save_flags(flags); |
1da177e4 LT |
2229 | local_irq_enable(); |
2230 | /* Let ten ticks pass... */ | |
2231 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2232 | local_irq_restore(flags); |
1da177e4 LT |
2233 | |
2234 | /* | |
2235 | * Expect a few ticks at least, to be sure some possible | |
2236 | * glue logic does not lock up after one or two first | |
2237 | * ticks in a non-ExtINT mode. Also the local APIC | |
2238 | * might have cached one ExtINT interrupt. Finally, at | |
2239 | * least one tick may be lost due to delays. | |
2240 | */ | |
54168ed7 IM |
2241 | |
2242 | /* jiffies wrap? */ | |
1d16b53e | 2243 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2244 | return 1; |
1da177e4 LT |
2245 | return 0; |
2246 | } | |
2247 | ||
2248 | /* | |
2249 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2250 | * number of pending IRQ events unhandled. These cases are very rare, | |
2251 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2252 | * better to do it this way as thus we do not have to be aware of | |
2253 | * 'pending' interrupts in the IRQ path, except at this point. | |
2254 | */ | |
2255 | /* | |
2256 | * Edge triggered needs to resend any interrupt | |
2257 | * that was delayed but this is now handled in the device | |
2258 | * independent code. | |
2259 | */ | |
2260 | ||
2261 | /* | |
2262 | * Starting up a edge-triggered IO-APIC interrupt is | |
2263 | * nasty - we need to make sure that we get the edge. | |
2264 | * If it is already asserted for some reason, we need | |
2265 | * return 1 to indicate that is was pending. | |
2266 | * | |
2267 | * This is not complete - we should be able to fake | |
2268 | * an edge even if it isn't on the 8259A... | |
2269 | */ | |
54168ed7 | 2270 | |
f5b9ed7a | 2271 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2272 | { |
2273 | int was_pending = 0; | |
2274 | unsigned long flags; | |
0b8f1efa | 2275 | struct irq_cfg *cfg; |
1da177e4 LT |
2276 | |
2277 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2278 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2279 | disable_8259A_irq(irq); |
2280 | if (i8259A_irq_pending(irq)) | |
2281 | was_pending = 1; | |
2282 | } | |
0b8f1efa | 2283 | cfg = irq_cfg(irq); |
3145e941 | 2284 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2285 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2286 | ||
2287 | return was_pending; | |
2288 | } | |
2289 | ||
54168ed7 | 2290 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2291 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2292 | { |
54168ed7 IM |
2293 | |
2294 | struct irq_cfg *cfg = irq_cfg(irq); | |
2295 | unsigned long flags; | |
2296 | ||
2297 | spin_lock_irqsave(&vector_lock, flags); | |
22f65d31 | 2298 | send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2299 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2300 | |
2301 | return 1; | |
2302 | } | |
54168ed7 IM |
2303 | #else |
2304 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2305 | { |
d6c88a50 | 2306 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2307 | |
d6c88a50 | 2308 | return 1; |
54168ed7 IM |
2309 | } |
2310 | #endif | |
497c9a19 | 2311 | |
54168ed7 IM |
2312 | /* |
2313 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2314 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2315 | * handled with the level-triggered descriptor, but that one has slightly | |
2316 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2317 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2318 | * races. | |
2319 | */ | |
497c9a19 | 2320 | |
54168ed7 | 2321 | #ifdef CONFIG_SMP |
497c9a19 | 2322 | |
54168ed7 IM |
2323 | #ifdef CONFIG_INTR_REMAP |
2324 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2325 | |
54168ed7 | 2326 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2327 | |
54168ed7 IM |
2328 | /* |
2329 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2330 | * | |
2331 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2332 | * and cpu destination) of IRTE and flush the hardware cache. | |
2333 | * | |
2334 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2335 | * vector information, along with modifying IRTE with vector and destination. | |
2336 | * So irq migration for level triggered is little bit more complex compared to | |
2337 | * edge triggered migration. But the good news is, we use the same algorithm | |
2338 | * for level triggered migration as we have today, only difference being, | |
2339 | * we now initiate the irq migration from process context instead of the | |
2340 | * interrupt context. | |
2341 | * | |
2342 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2343 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2344 | * as simple as edge triggered migration and we can do the irq migration | |
2345 | * with a simple atomic update to IO-APIC RTE. | |
2346 | */ | |
e7986739 MT |
2347 | static void |
2348 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 | 2349 | { |
54168ed7 | 2350 | struct irq_cfg *cfg; |
54168ed7 IM |
2351 | struct irte irte; |
2352 | int modify_ioapic_rte; | |
2353 | unsigned int dest; | |
2354 | unsigned long flags; | |
3145e941 | 2355 | unsigned int irq; |
497c9a19 | 2356 | |
22f65d31 | 2357 | if (!cpumask_intersects(mask, cpu_online_mask)) |
497c9a19 YL |
2358 | return; |
2359 | ||
3145e941 | 2360 | irq = desc->irq; |
54168ed7 IM |
2361 | if (get_irte(irq, &irte)) |
2362 | return; | |
497c9a19 | 2363 | |
3145e941 YL |
2364 | cfg = desc->chip_data; |
2365 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
2366 | return; |
2367 | ||
3145e941 YL |
2368 | set_extra_move_desc(desc, mask); |
2369 | ||
22f65d31 | 2370 | dest = cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2371 | |
54168ed7 IM |
2372 | modify_ioapic_rte = desc->status & IRQ_LEVEL; |
2373 | if (modify_ioapic_rte) { | |
2374 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 2375 | __target_IO_APIC_irq(irq, dest, cfg); |
54168ed7 IM |
2376 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2377 | } | |
2378 | ||
2379 | irte.vector = cfg->vector; | |
2380 | irte.dest_id = IRTE_DEST(dest); | |
2381 | ||
2382 | /* | |
2383 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2384 | */ | |
2385 | modify_irte(irq, &irte); | |
2386 | ||
22f65d31 MT |
2387 | if (cfg->move_in_progress) |
2388 | send_cleanup_vector(cfg); | |
54168ed7 | 2389 | |
22f65d31 | 2390 | cpumask_copy(&desc->affinity, mask); |
54168ed7 IM |
2391 | } |
2392 | ||
3145e941 | 2393 | static int migrate_irq_remapped_level_desc(struct irq_desc *desc) |
54168ed7 IM |
2394 | { |
2395 | int ret = -1; | |
3145e941 | 2396 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 2397 | |
3145e941 | 2398 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2399 | |
3145e941 | 2400 | if (io_apic_level_ack_pending(cfg)) { |
54168ed7 | 2401 | /* |
d6c88a50 | 2402 | * Interrupt in progress. Migrating irq now will change the |
54168ed7 IM |
2403 | * vector information in the IO-APIC RTE and that will confuse |
2404 | * the EOI broadcast performed by cpu. | |
2405 | * So, delay the irq migration to the next instance. | |
2406 | */ | |
2407 | schedule_delayed_work(&ir_migration_work, 1); | |
2408 | goto unmask; | |
2409 | } | |
2410 | ||
2411 | /* everthing is clear. we have right of way */ | |
e7986739 | 2412 | migrate_ioapic_irq_desc(desc, &desc->pending_mask); |
54168ed7 IM |
2413 | |
2414 | ret = 0; | |
2415 | desc->status &= ~IRQ_MOVE_PENDING; | |
22f65d31 | 2416 | cpumask_clear(&desc->pending_mask); |
54168ed7 IM |
2417 | |
2418 | unmask: | |
3145e941 YL |
2419 | unmask_IO_APIC_irq_desc(desc); |
2420 | ||
54168ed7 IM |
2421 | return ret; |
2422 | } | |
2423 | ||
2424 | static void ir_irq_migration(struct work_struct *work) | |
2425 | { | |
2426 | unsigned int irq; | |
2427 | struct irq_desc *desc; | |
2428 | ||
2429 | for_each_irq_desc(irq, desc) { | |
0b8f1efa YL |
2430 | if (!desc) |
2431 | continue; | |
2432 | ||
54168ed7 IM |
2433 | if (desc->status & IRQ_MOVE_PENDING) { |
2434 | unsigned long flags; | |
2435 | ||
2436 | spin_lock_irqsave(&desc->lock, flags); | |
2437 | if (!desc->chip->set_affinity || | |
2438 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2439 | desc->status &= ~IRQ_MOVE_PENDING; | |
2440 | spin_unlock_irqrestore(&desc->lock, flags); | |
2441 | continue; | |
2442 | } | |
2443 | ||
0de26520 | 2444 | desc->chip->set_affinity(irq, &desc->pending_mask); |
54168ed7 IM |
2445 | spin_unlock_irqrestore(&desc->lock, flags); |
2446 | } | |
2447 | } | |
2448 | } | |
2449 | ||
2450 | /* | |
2451 | * Migrates the IRQ destination in the process context. | |
2452 | */ | |
968ea6d8 RR |
2453 | static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
2454 | const struct cpumask *mask) | |
54168ed7 | 2455 | { |
54168ed7 IM |
2456 | if (desc->status & IRQ_LEVEL) { |
2457 | desc->status |= IRQ_MOVE_PENDING; | |
0de26520 | 2458 | cpumask_copy(&desc->pending_mask, mask); |
3145e941 | 2459 | migrate_irq_remapped_level_desc(desc); |
54168ed7 IM |
2460 | return; |
2461 | } | |
2462 | ||
e7986739 | 2463 | migrate_ioapic_irq_desc(desc, mask); |
3145e941 | 2464 | } |
968ea6d8 RR |
2465 | static void set_ir_ioapic_affinity_irq(unsigned int irq, |
2466 | const struct cpumask *mask) | |
3145e941 YL |
2467 | { |
2468 | struct irq_desc *desc = irq_to_desc(irq); | |
2469 | ||
2470 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
54168ed7 IM |
2471 | } |
2472 | #endif | |
2473 | ||
2474 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2475 | { | |
2476 | unsigned vector, me; | |
2477 | ack_APIC_irq(); | |
2478 | #ifdef CONFIG_X86_64 | |
2479 | exit_idle(); | |
2480 | #endif | |
2481 | irq_enter(); | |
2482 | ||
2483 | me = smp_processor_id(); | |
2484 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2485 | unsigned int irq; | |
2486 | struct irq_desc *desc; | |
2487 | struct irq_cfg *cfg; | |
2488 | irq = __get_cpu_var(vector_irq)[vector]; | |
2489 | ||
0b8f1efa YL |
2490 | if (irq == -1) |
2491 | continue; | |
2492 | ||
54168ed7 IM |
2493 | desc = irq_to_desc(irq); |
2494 | if (!desc) | |
2495 | continue; | |
2496 | ||
2497 | cfg = irq_cfg(irq); | |
2498 | spin_lock(&desc->lock); | |
2499 | if (!cfg->move_cleanup_count) | |
2500 | goto unlock; | |
2501 | ||
22f65d31 | 2502 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2503 | goto unlock; |
2504 | ||
2505 | __get_cpu_var(vector_irq)[vector] = -1; | |
2506 | cfg->move_cleanup_count--; | |
2507 | unlock: | |
2508 | spin_unlock(&desc->lock); | |
2509 | } | |
2510 | ||
2511 | irq_exit(); | |
2512 | } | |
2513 | ||
3145e941 | 2514 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2515 | { |
3145e941 YL |
2516 | struct irq_desc *desc = *descp; |
2517 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2518 | unsigned vector, me; |
2519 | ||
48a1b10a YL |
2520 | if (likely(!cfg->move_in_progress)) { |
2521 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | |
2522 | if (likely(!cfg->move_desc_pending)) | |
2523 | return; | |
2524 | ||
2525 | /* domain is not change, but affinity is changed */ | |
2526 | me = smp_processor_id(); | |
2527 | if (cpu_isset(me, desc->affinity)) { | |
2528 | *descp = desc = move_irq_desc(desc, me); | |
2529 | /* get the new one */ | |
2530 | cfg = desc->chip_data; | |
2531 | cfg->move_desc_pending = 0; | |
2532 | } | |
2533 | #endif | |
54168ed7 | 2534 | return; |
48a1b10a | 2535 | } |
54168ed7 IM |
2536 | |
2537 | vector = ~get_irq_regs()->orig_ax; | |
2538 | me = smp_processor_id(); | |
48a1b10a YL |
2539 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
2540 | *descp = desc = move_irq_desc(desc, me); | |
2541 | /* get the new one */ | |
2542 | cfg = desc->chip_data; | |
2543 | #endif | |
2544 | ||
22f65d31 MT |
2545 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
2546 | send_cleanup_vector(cfg); | |
497c9a19 YL |
2547 | } |
2548 | #else | |
3145e941 | 2549 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2550 | #endif |
3145e941 | 2551 | |
54168ed7 IM |
2552 | #ifdef CONFIG_INTR_REMAP |
2553 | static void ack_x2apic_level(unsigned int irq) | |
2554 | { | |
2555 | ack_x2APIC_irq(); | |
2556 | } | |
2557 | ||
2558 | static void ack_x2apic_edge(unsigned int irq) | |
2559 | { | |
2560 | ack_x2APIC_irq(); | |
2561 | } | |
3145e941 | 2562 | |
54168ed7 | 2563 | #endif |
497c9a19 | 2564 | |
1d025192 YL |
2565 | static void ack_apic_edge(unsigned int irq) |
2566 | { | |
3145e941 YL |
2567 | struct irq_desc *desc = irq_to_desc(irq); |
2568 | ||
2569 | irq_complete_move(&desc); | |
1d025192 YL |
2570 | move_native_irq(irq); |
2571 | ack_APIC_irq(); | |
2572 | } | |
2573 | ||
3eb2cce8 | 2574 | atomic_t irq_mis_count; |
3eb2cce8 | 2575 | |
047c8fdb YL |
2576 | static void ack_apic_level(unsigned int irq) |
2577 | { | |
3145e941 YL |
2578 | struct irq_desc *desc = irq_to_desc(irq); |
2579 | ||
3eb2cce8 YL |
2580 | #ifdef CONFIG_X86_32 |
2581 | unsigned long v; | |
2582 | int i; | |
2583 | #endif | |
3145e941 | 2584 | struct irq_cfg *cfg; |
54168ed7 | 2585 | int do_unmask_irq = 0; |
047c8fdb | 2586 | |
3145e941 | 2587 | irq_complete_move(&desc); |
047c8fdb | 2588 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2589 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2590 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2591 | do_unmask_irq = 1; |
3145e941 | 2592 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2593 | } |
047c8fdb YL |
2594 | #endif |
2595 | ||
3eb2cce8 YL |
2596 | #ifdef CONFIG_X86_32 |
2597 | /* | |
2598 | * It appears there is an erratum which affects at least version 0x11 | |
2599 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2600 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2601 | * erroneously delivered as edge-triggered one but the respective IRR | |
2602 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2603 | * message but it will never arrive and further interrupts are blocked | |
2604 | * from the source. The exact reason is so far unknown, but the | |
2605 | * phenomenon was observed when two consecutive interrupt requests | |
2606 | * from a given source get delivered to the same CPU and the source is | |
2607 | * temporarily disabled in between. | |
2608 | * | |
2609 | * A workaround is to simulate an EOI message manually. We achieve it | |
2610 | * by setting the trigger mode to edge and then to level when the edge | |
2611 | * trigger mode gets detected in the TMR of a local APIC for a | |
2612 | * level-triggered interrupt. We mask the source for the time of the | |
2613 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2614 | * The idea is from Manfred Spraul. --macro | |
2615 | */ | |
3145e941 YL |
2616 | cfg = desc->chip_data; |
2617 | i = cfg->vector; | |
3eb2cce8 YL |
2618 | |
2619 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2620 | #endif | |
2621 | ||
54168ed7 IM |
2622 | /* |
2623 | * We must acknowledge the irq before we move it or the acknowledge will | |
2624 | * not propagate properly. | |
2625 | */ | |
2626 | ack_APIC_irq(); | |
2627 | ||
2628 | /* Now we can move and renable the irq */ | |
2629 | if (unlikely(do_unmask_irq)) { | |
2630 | /* Only migrate the irq if the ack has been received. | |
2631 | * | |
2632 | * On rare occasions the broadcast level triggered ack gets | |
2633 | * delayed going to ioapics, and if we reprogram the | |
2634 | * vector while Remote IRR is still set the irq will never | |
2635 | * fire again. | |
2636 | * | |
2637 | * To prevent this scenario we read the Remote IRR bit | |
2638 | * of the ioapic. This has two effects. | |
2639 | * - On any sane system the read of the ioapic will | |
2640 | * flush writes (and acks) going to the ioapic from | |
2641 | * this cpu. | |
2642 | * - We get to see if the ACK has actually been delivered. | |
2643 | * | |
2644 | * Based on failed experiments of reprogramming the | |
2645 | * ioapic entry from outside of irq context starting | |
2646 | * with masking the ioapic entry and then polling until | |
2647 | * Remote IRR was clear before reprogramming the | |
2648 | * ioapic I don't trust the Remote IRR bit to be | |
2649 | * completey accurate. | |
2650 | * | |
2651 | * However there appears to be no other way to plug | |
2652 | * this race, so if the Remote IRR bit is not | |
2653 | * accurate and is causing problems then it is a hardware bug | |
2654 | * and you can go talk to the chipset vendor about it. | |
2655 | */ | |
3145e941 YL |
2656 | cfg = desc->chip_data; |
2657 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2658 | move_masked_irq(irq); |
3145e941 | 2659 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2660 | } |
1d025192 | 2661 | |
3eb2cce8 | 2662 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2663 | if (!(v & (1 << (i & 0x1f)))) { |
2664 | atomic_inc(&irq_mis_count); | |
2665 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2666 | __mask_and_edge_IO_APIC_irq(cfg); |
2667 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2668 | spin_unlock(&ioapic_lock); |
2669 | } | |
047c8fdb | 2670 | #endif |
3eb2cce8 | 2671 | } |
1d025192 | 2672 | |
f5b9ed7a | 2673 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2674 | .name = "IO-APIC", |
2675 | .startup = startup_ioapic_irq, | |
2676 | .mask = mask_IO_APIC_irq, | |
2677 | .unmask = unmask_IO_APIC_irq, | |
2678 | .ack = ack_apic_edge, | |
2679 | .eoi = ack_apic_level, | |
54d5d424 | 2680 | #ifdef CONFIG_SMP |
d6c88a50 | 2681 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2682 | #endif |
ace80ab7 | 2683 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2684 | }; |
2685 | ||
54168ed7 IM |
2686 | #ifdef CONFIG_INTR_REMAP |
2687 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
d6c88a50 TG |
2688 | .name = "IR-IO-APIC", |
2689 | .startup = startup_ioapic_irq, | |
2690 | .mask = mask_IO_APIC_irq, | |
2691 | .unmask = unmask_IO_APIC_irq, | |
2692 | .ack = ack_x2apic_edge, | |
2693 | .eoi = ack_x2apic_level, | |
54168ed7 | 2694 | #ifdef CONFIG_SMP |
d6c88a50 | 2695 | .set_affinity = set_ir_ioapic_affinity_irq, |
54168ed7 IM |
2696 | #endif |
2697 | .retrigger = ioapic_retrigger_irq, | |
2698 | }; | |
2699 | #endif | |
1da177e4 LT |
2700 | |
2701 | static inline void init_IO_APIC_traps(void) | |
2702 | { | |
2703 | int irq; | |
08678b08 | 2704 | struct irq_desc *desc; |
da51a821 | 2705 | struct irq_cfg *cfg; |
1da177e4 LT |
2706 | |
2707 | /* | |
2708 | * NOTE! The local APIC isn't very good at handling | |
2709 | * multiple interrupts at the same interrupt level. | |
2710 | * As the interrupt level is determined by taking the | |
2711 | * vector number and shifting that right by 4, we | |
2712 | * want to spread these out a bit so that they don't | |
2713 | * all fall in the same interrupt level. | |
2714 | * | |
2715 | * Also, we've got to be careful not to trash gate | |
2716 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2717 | */ | |
0b8f1efa YL |
2718 | for_each_irq_desc(irq, desc) { |
2719 | if (!desc) | |
2720 | continue; | |
2721 | ||
2722 | cfg = desc->chip_data; | |
2723 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2724 | /* |
2725 | * Hmm.. We don't have an entry for this, | |
2726 | * so default to an old-fashioned 8259 | |
2727 | * interrupt if we can.. | |
2728 | */ | |
99d093d1 | 2729 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2730 | make_8259A_irq(irq); |
0b8f1efa | 2731 | else |
1da177e4 | 2732 | /* Strange. Oh, well.. */ |
08678b08 | 2733 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2734 | } |
2735 | } | |
2736 | } | |
2737 | ||
f5b9ed7a IM |
2738 | /* |
2739 | * The local APIC irq-chip implementation: | |
2740 | */ | |
1da177e4 | 2741 | |
36062448 | 2742 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2743 | { |
2744 | unsigned long v; | |
2745 | ||
2746 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2747 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2748 | } |
2749 | ||
36062448 | 2750 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2751 | { |
f5b9ed7a | 2752 | unsigned long v; |
1da177e4 | 2753 | |
f5b9ed7a | 2754 | v = apic_read(APIC_LVT0); |
593f4a78 | 2755 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2756 | } |
1da177e4 | 2757 | |
3145e941 | 2758 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2759 | { |
2760 | ack_APIC_irq(); | |
2761 | } | |
2762 | ||
f5b9ed7a | 2763 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2764 | .name = "local-APIC", |
f5b9ed7a IM |
2765 | .mask = mask_lapic_irq, |
2766 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2767 | .ack = ack_lapic_irq, |
1da177e4 LT |
2768 | }; |
2769 | ||
3145e941 | 2770 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2771 | { |
08678b08 | 2772 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2773 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2774 | "edge"); | |
c88ac1df MR |
2775 | } |
2776 | ||
e9427101 | 2777 | static void __init setup_nmi(void) |
1da177e4 LT |
2778 | { |
2779 | /* | |
36062448 | 2780 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2781 | * We put the 8259A master into AEOI mode and |
2782 | * unmask on all local APICs LVT0 as NMI. | |
2783 | * | |
2784 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2785 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2786 | * the NMI handler or the timer interrupt. | |
36062448 | 2787 | */ |
1da177e4 LT |
2788 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2789 | ||
e9427101 | 2790 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2791 | |
2792 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2793 | } | |
2794 | ||
2795 | /* | |
2796 | * This looks a bit hackish but it's about the only one way of sending | |
2797 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2798 | * not support the ExtINT mode, unfortunately. We need to send these | |
2799 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2800 | * 8259A interrupt line asserted until INTA. --macro | |
2801 | */ | |
28acf285 | 2802 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2803 | { |
fcfd636a | 2804 | int apic, pin, i; |
1da177e4 LT |
2805 | struct IO_APIC_route_entry entry0, entry1; |
2806 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2807 | |
fcfd636a | 2808 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2809 | if (pin == -1) { |
2810 | WARN_ON_ONCE(1); | |
2811 | return; | |
2812 | } | |
fcfd636a | 2813 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2814 | if (apic == -1) { |
2815 | WARN_ON_ONCE(1); | |
1da177e4 | 2816 | return; |
956fb531 | 2817 | } |
1da177e4 | 2818 | |
cf4c6a2f | 2819 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2820 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2821 | |
2822 | memset(&entry1, 0, sizeof(entry1)); | |
2823 | ||
2824 | entry1.dest_mode = 0; /* physical delivery */ | |
2825 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2826 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2827 | entry1.delivery_mode = dest_ExtINT; |
2828 | entry1.polarity = entry0.polarity; | |
2829 | entry1.trigger = 0; | |
2830 | entry1.vector = 0; | |
2831 | ||
cf4c6a2f | 2832 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2833 | |
2834 | save_control = CMOS_READ(RTC_CONTROL); | |
2835 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2836 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2837 | RTC_FREQ_SELECT); | |
2838 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2839 | ||
2840 | i = 100; | |
2841 | while (i-- > 0) { | |
2842 | mdelay(10); | |
2843 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2844 | i -= 10; | |
2845 | } | |
2846 | ||
2847 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2848 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2849 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2850 | |
cf4c6a2f | 2851 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2852 | } |
2853 | ||
efa2559f | 2854 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2855 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2856 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2857 | { |
2858 | disable_timer_pin_1 = 1; | |
2859 | return 0; | |
2860 | } | |
54168ed7 | 2861 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2862 | |
2863 | int timer_through_8259 __initdata; | |
2864 | ||
1da177e4 LT |
2865 | /* |
2866 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2867 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2868 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2869 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2870 | * |
2871 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2872 | */ |
8542b200 | 2873 | static inline void __init check_timer(void) |
1da177e4 | 2874 | { |
3145e941 YL |
2875 | struct irq_desc *desc = irq_to_desc(0); |
2876 | struct irq_cfg *cfg = desc->chip_data; | |
2877 | int cpu = boot_cpu_id; | |
fcfd636a | 2878 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2879 | unsigned long flags; |
047c8fdb YL |
2880 | unsigned int ver; |
2881 | int no_pin1 = 0; | |
4aae0702 IM |
2882 | |
2883 | local_irq_save(flags); | |
d4d25dec | 2884 | |
d6c88a50 TG |
2885 | ver = apic_read(APIC_LVR); |
2886 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2887 | |
1da177e4 LT |
2888 | /* |
2889 | * get/set the timer IRQ vector: | |
2890 | */ | |
2891 | disable_8259A_irq(0); | |
3145e941 | 2892 | assign_irq_vector(0, cfg, TARGET_CPUS); |
1da177e4 LT |
2893 | |
2894 | /* | |
d11d5794 MR |
2895 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2896 | * wire has to be disabled in the local APIC. Also | |
2897 | * timer interrupts need to be acknowledged manually in | |
2898 | * the 8259A for the i82489DX when using the NMI | |
2899 | * watchdog as that APIC treats NMIs as level-triggered. | |
2900 | * The AEOI mode will finish them in the 8259A | |
2901 | * automatically. | |
1da177e4 | 2902 | */ |
593f4a78 | 2903 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2904 | init_8259A(1); |
54168ed7 | 2905 | #ifdef CONFIG_X86_32 |
d11d5794 | 2906 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2907 | #endif |
1da177e4 | 2908 | |
fcfd636a EB |
2909 | pin1 = find_isa_irq_pin(0, mp_INT); |
2910 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2911 | pin2 = ioapic_i8259.pin; | |
2912 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2913 | |
49a66a0b MR |
2914 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2915 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2916 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2917 | |
691874fa MR |
2918 | /* |
2919 | * Some BIOS writers are clueless and report the ExtINTA | |
2920 | * I/O APIC input from the cascaded 8259A as the timer | |
2921 | * interrupt input. So just in case, if only one pin | |
2922 | * was found above, try it both directly and through the | |
2923 | * 8259A. | |
2924 | */ | |
2925 | if (pin1 == -1) { | |
54168ed7 IM |
2926 | #ifdef CONFIG_INTR_REMAP |
2927 | if (intr_remapping_enabled) | |
2928 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2929 | #endif | |
691874fa MR |
2930 | pin1 = pin2; |
2931 | apic1 = apic2; | |
2932 | no_pin1 = 1; | |
2933 | } else if (pin2 == -1) { | |
2934 | pin2 = pin1; | |
2935 | apic2 = apic1; | |
2936 | } | |
2937 | ||
1da177e4 LT |
2938 | if (pin1 != -1) { |
2939 | /* | |
2940 | * Ok, does IRQ0 through the IOAPIC work? | |
2941 | */ | |
691874fa | 2942 | if (no_pin1) { |
3145e941 | 2943 | add_pin_to_irq_cpu(cfg, cpu, apic1, pin1); |
497c9a19 | 2944 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2945 | } |
3145e941 | 2946 | unmask_IO_APIC_irq_desc(desc); |
1da177e4 LT |
2947 | if (timer_irq_works()) { |
2948 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2949 | setup_nmi(); |
2950 | enable_8259A_irq(0); | |
1da177e4 | 2951 | } |
66759a01 CE |
2952 | if (disable_timer_pin_1 > 0) |
2953 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2954 | goto out; |
1da177e4 | 2955 | } |
54168ed7 IM |
2956 | #ifdef CONFIG_INTR_REMAP |
2957 | if (intr_remapping_enabled) | |
2958 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2959 | #endif | |
fcfd636a | 2960 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2961 | if (!no_pin1) |
49a66a0b MR |
2962 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2963 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2964 | |
49a66a0b MR |
2965 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2966 | "(IRQ0) through the 8259A ...\n"); | |
2967 | apic_printk(APIC_QUIET, KERN_INFO | |
2968 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2969 | /* |
2970 | * legacy devices should be connected to IO APIC #0 | |
2971 | */ | |
3145e941 | 2972 | replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2); |
497c9a19 | 2973 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
3145e941 | 2974 | unmask_IO_APIC_irq_desc(desc); |
ecd29476 | 2975 | enable_8259A_irq(0); |
1da177e4 | 2976 | if (timer_irq_works()) { |
49a66a0b | 2977 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2978 | timer_through_8259 = 1; |
1da177e4 | 2979 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2980 | disable_8259A_irq(0); |
1da177e4 | 2981 | setup_nmi(); |
60134ebe | 2982 | enable_8259A_irq(0); |
1da177e4 | 2983 | } |
4aae0702 | 2984 | goto out; |
1da177e4 LT |
2985 | } |
2986 | /* | |
2987 | * Cleanup, just in case ... | |
2988 | */ | |
ecd29476 | 2989 | disable_8259A_irq(0); |
fcfd636a | 2990 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2991 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2992 | } |
1da177e4 LT |
2993 | |
2994 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2995 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2996 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2997 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2998 | } |
54168ed7 | 2999 | #ifdef CONFIG_X86_32 |
d11d5794 | 3000 | timer_ack = 0; |
54168ed7 | 3001 | #endif |
1da177e4 | 3002 | |
49a66a0b MR |
3003 | apic_printk(APIC_QUIET, KERN_INFO |
3004 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 3005 | |
3145e941 | 3006 | lapic_register_intr(0, desc); |
497c9a19 | 3007 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
3008 | enable_8259A_irq(0); |
3009 | ||
3010 | if (timer_irq_works()) { | |
49a66a0b | 3011 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3012 | goto out; |
1da177e4 | 3013 | } |
e67465f1 | 3014 | disable_8259A_irq(0); |
497c9a19 | 3015 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3016 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3017 | |
49a66a0b MR |
3018 | apic_printk(APIC_QUIET, KERN_INFO |
3019 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3020 | |
1da177e4 LT |
3021 | init_8259A(0); |
3022 | make_8259A_irq(0); | |
593f4a78 | 3023 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3024 | |
3025 | unlock_ExtINT_logic(); | |
3026 | ||
3027 | if (timer_irq_works()) { | |
49a66a0b | 3028 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3029 | goto out; |
1da177e4 | 3030 | } |
49a66a0b | 3031 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3032 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3033 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3034 | out: |
3035 | local_irq_restore(flags); | |
1da177e4 LT |
3036 | } |
3037 | ||
3038 | /* | |
af174783 MR |
3039 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3040 | * to devices. However there may be an I/O APIC pin available for | |
3041 | * this interrupt regardless. The pin may be left unconnected, but | |
3042 | * typically it will be reused as an ExtINT cascade interrupt for | |
3043 | * the master 8259A. In the MPS case such a pin will normally be | |
3044 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3045 | * there is no provision for ExtINT interrupts, and in the absence | |
3046 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3047 | * interrupt, that is edge-triggered and unmasked by default. We | |
3048 | * used to do this, but it caused problems on some systems because | |
3049 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3050 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3051 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3052 | * the I/O APIC in all cases now. No actual device should request | |
3053 | * it anyway. --macro | |
1da177e4 LT |
3054 | */ |
3055 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3056 | ||
3057 | void __init setup_IO_APIC(void) | |
3058 | { | |
54168ed7 IM |
3059 | |
3060 | #ifdef CONFIG_X86_32 | |
1da177e4 | 3061 | enable_IO_APIC(); |
54168ed7 IM |
3062 | #else |
3063 | /* | |
3064 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3065 | */ | |
3066 | #endif | |
1da177e4 | 3067 | |
af174783 | 3068 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3069 | |
54168ed7 | 3070 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3071 | /* |
54168ed7 IM |
3072 | * Set up IO-APIC IRQ routing. |
3073 | */ | |
3074 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3075 | if (!acpi_ioapic) |
3076 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3077 | #endif |
1da177e4 LT |
3078 | sync_Arb_IDs(); |
3079 | setup_IO_APIC_irqs(); | |
3080 | init_IO_APIC_traps(); | |
1e4c85f9 | 3081 | check_timer(); |
1da177e4 LT |
3082 | } |
3083 | ||
3084 | /* | |
54168ed7 IM |
3085 | * Called after all the initialization is done. If we didnt find any |
3086 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3087 | */ |
36062448 | 3088 | |
1da177e4 LT |
3089 | static int __init io_apic_bug_finalize(void) |
3090 | { | |
d6c88a50 TG |
3091 | if (sis_apic_bug == -1) |
3092 | sis_apic_bug = 0; | |
3093 | return 0; | |
1da177e4 LT |
3094 | } |
3095 | ||
3096 | late_initcall(io_apic_bug_finalize); | |
3097 | ||
3098 | struct sysfs_ioapic_data { | |
3099 | struct sys_device dev; | |
3100 | struct IO_APIC_route_entry entry[0]; | |
3101 | }; | |
54168ed7 | 3102 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3103 | |
438510f6 | 3104 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3105 | { |
3106 | struct IO_APIC_route_entry *entry; | |
3107 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3108 | int i; |
36062448 | 3109 | |
1da177e4 LT |
3110 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3111 | entry = data->entry; | |
54168ed7 IM |
3112 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3113 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3114 | |
3115 | return 0; | |
3116 | } | |
3117 | ||
3118 | static int ioapic_resume(struct sys_device *dev) | |
3119 | { | |
3120 | struct IO_APIC_route_entry *entry; | |
3121 | struct sysfs_ioapic_data *data; | |
3122 | unsigned long flags; | |
3123 | union IO_APIC_reg_00 reg_00; | |
3124 | int i; | |
36062448 | 3125 | |
1da177e4 LT |
3126 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3127 | entry = data->entry; | |
3128 | ||
3129 | spin_lock_irqsave(&ioapic_lock, flags); | |
3130 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
3131 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
3132 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
3133 | io_apic_write(dev->id, 0, reg_00.raw); |
3134 | } | |
1da177e4 | 3135 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3136 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3137 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3138 | |
3139 | return 0; | |
3140 | } | |
3141 | ||
3142 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3143 | .name = "ioapic", |
1da177e4 LT |
3144 | .suspend = ioapic_suspend, |
3145 | .resume = ioapic_resume, | |
3146 | }; | |
3147 | ||
3148 | static int __init ioapic_init_sysfs(void) | |
3149 | { | |
54168ed7 IM |
3150 | struct sys_device * dev; |
3151 | int i, size, error; | |
1da177e4 LT |
3152 | |
3153 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3154 | if (error) | |
3155 | return error; | |
3156 | ||
54168ed7 | 3157 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3158 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3159 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3160 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3161 | if (!mp_ioapic_data[i]) { |
3162 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3163 | continue; | |
3164 | } | |
1da177e4 | 3165 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3166 | dev->id = i; |
1da177e4 LT |
3167 | dev->cls = &ioapic_sysdev_class; |
3168 | error = sysdev_register(dev); | |
3169 | if (error) { | |
3170 | kfree(mp_ioapic_data[i]); | |
3171 | mp_ioapic_data[i] = NULL; | |
3172 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3173 | continue; | |
3174 | } | |
3175 | } | |
3176 | ||
3177 | return 0; | |
3178 | } | |
3179 | ||
3180 | device_initcall(ioapic_init_sysfs); | |
3181 | ||
3fc471ed | 3182 | /* |
95d77884 | 3183 | * Dynamic irq allocate and deallocation |
3fc471ed | 3184 | */ |
199751d7 | 3185 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3186 | { |
ace80ab7 | 3187 | /* Allocate an unused irq */ |
54168ed7 IM |
3188 | unsigned int irq; |
3189 | unsigned int new; | |
3fc471ed | 3190 | unsigned long flags; |
0b8f1efa YL |
3191 | struct irq_cfg *cfg_new = NULL; |
3192 | int cpu = boot_cpu_id; | |
3193 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
3194 | |
3195 | irq = 0; | |
ace80ab7 | 3196 | spin_lock_irqsave(&vector_lock, flags); |
be5d5350 | 3197 | for (new = irq_want; new < NR_IRQS; new++) { |
ace80ab7 EB |
3198 | if (platform_legacy_irq(new)) |
3199 | continue; | |
0b8f1efa YL |
3200 | |
3201 | desc_new = irq_to_desc_alloc_cpu(new, cpu); | |
3202 | if (!desc_new) { | |
3203 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
3204 | continue; | |
3205 | } | |
3206 | cfg_new = desc_new->chip_data; | |
3207 | ||
3208 | if (cfg_new->vector != 0) | |
ace80ab7 | 3209 | continue; |
3145e941 | 3210 | if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0) |
ace80ab7 EB |
3211 | irq = new; |
3212 | break; | |
3213 | } | |
3214 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3215 | |
199751d7 | 3216 | if (irq > 0) { |
3fc471ed | 3217 | dynamic_irq_init(irq); |
0b8f1efa YL |
3218 | /* restore it, in case dynamic_irq_init clear it */ |
3219 | if (desc_new) | |
3220 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3221 | } |
3222 | return irq; | |
3223 | } | |
3224 | ||
be5d5350 | 3225 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
199751d7 YL |
3226 | int create_irq(void) |
3227 | { | |
be5d5350 | 3228 | unsigned int irq_want; |
54168ed7 IM |
3229 | int irq; |
3230 | ||
be5d5350 YL |
3231 | irq_want = nr_irqs_gsi; |
3232 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3233 | |
3234 | if (irq == 0) | |
3235 | irq = -1; | |
3236 | ||
3237 | return irq; | |
199751d7 YL |
3238 | } |
3239 | ||
3fc471ed EB |
3240 | void destroy_irq(unsigned int irq) |
3241 | { | |
3242 | unsigned long flags; | |
0b8f1efa YL |
3243 | struct irq_cfg *cfg; |
3244 | struct irq_desc *desc; | |
3fc471ed | 3245 | |
0b8f1efa YL |
3246 | /* store it, in case dynamic_irq_cleanup clear it */ |
3247 | desc = irq_to_desc(irq); | |
3248 | cfg = desc->chip_data; | |
3fc471ed | 3249 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3250 | /* connect back irq_cfg */ |
3251 | if (desc) | |
3252 | desc->chip_data = cfg; | |
3fc471ed | 3253 | |
54168ed7 IM |
3254 | #ifdef CONFIG_INTR_REMAP |
3255 | free_irte(irq); | |
3256 | #endif | |
3fc471ed | 3257 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3258 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3259 | spin_unlock_irqrestore(&vector_lock, flags); |
3260 | } | |
3fc471ed | 3261 | |
2d3fcc1c | 3262 | /* |
27b46d76 | 3263 | * MSI message composition |
2d3fcc1c EB |
3264 | */ |
3265 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3266 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3267 | { |
497c9a19 YL |
3268 | struct irq_cfg *cfg; |
3269 | int err; | |
2d3fcc1c EB |
3270 | unsigned dest; |
3271 | ||
3145e941 | 3272 | cfg = irq_cfg(irq); |
22f65d31 | 3273 | err = assign_irq_vector(irq, cfg, TARGET_CPUS); |
497c9a19 YL |
3274 | if (err) |
3275 | return err; | |
2d3fcc1c | 3276 | |
22f65d31 | 3277 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
497c9a19 | 3278 | |
54168ed7 IM |
3279 | #ifdef CONFIG_INTR_REMAP |
3280 | if (irq_remapped(irq)) { | |
3281 | struct irte irte; | |
3282 | int ir_index; | |
3283 | u16 sub_handle; | |
3284 | ||
3285 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3286 | BUG_ON(ir_index == -1); | |
3287 | ||
3288 | memset (&irte, 0, sizeof(irte)); | |
3289 | ||
3290 | irte.present = 1; | |
3291 | irte.dst_mode = INT_DEST_MODE; | |
3292 | irte.trigger_mode = 0; /* edge */ | |
3293 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
3294 | irte.vector = cfg->vector; | |
3295 | irte.dest_id = IRTE_DEST(dest); | |
3296 | ||
3297 | modify_irte(irq, &irte); | |
3298 | ||
3299 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3300 | msg->data = sub_handle; | |
3301 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3302 | MSI_ADDR_IR_SHV | | |
3303 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3304 | MSI_ADDR_IR_INDEX2(ir_index); | |
3305 | } else | |
3306 | #endif | |
3307 | { | |
3308 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3309 | msg->address_lo = | |
3310 | MSI_ADDR_BASE_LO | | |
3311 | ((INT_DEST_MODE == 0) ? | |
3312 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3313 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3314 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3315 | MSI_ADDR_REDIRECTION_CPU: | |
3316 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3317 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3318 | |
54168ed7 IM |
3319 | msg->data = |
3320 | MSI_DATA_TRIGGER_EDGE | | |
3321 | MSI_DATA_LEVEL_ASSERT | | |
3322 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3323 | MSI_DATA_DELIVERY_FIXED: | |
3324 | MSI_DATA_DELIVERY_LOWPRI) | | |
3325 | MSI_DATA_VECTOR(cfg->vector); | |
3326 | } | |
497c9a19 | 3327 | return err; |
2d3fcc1c EB |
3328 | } |
3329 | ||
3b7d1921 | 3330 | #ifdef CONFIG_SMP |
0de26520 | 3331 | static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3332 | { |
3145e941 | 3333 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3334 | struct irq_cfg *cfg; |
3b7d1921 EB |
3335 | struct msi_msg msg; |
3336 | unsigned int dest; | |
3b7d1921 | 3337 | |
22f65d31 MT |
3338 | dest = set_desc_affinity(desc, mask); |
3339 | if (dest == BAD_APICID) | |
497c9a19 | 3340 | return; |
2d3fcc1c | 3341 | |
3145e941 | 3342 | cfg = desc->chip_data; |
3b7d1921 | 3343 | |
3145e941 | 3344 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3345 | |
3346 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3347 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3348 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3349 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3350 | ||
3145e941 | 3351 | write_msi_msg_desc(desc, &msg); |
2d3fcc1c | 3352 | } |
54168ed7 IM |
3353 | #ifdef CONFIG_INTR_REMAP |
3354 | /* | |
3355 | * Migrate the MSI irq to another cpumask. This migration is | |
3356 | * done in the process context using interrupt-remapping hardware. | |
3357 | */ | |
e7986739 MT |
3358 | static void |
3359 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) | |
54168ed7 | 3360 | { |
3145e941 | 3361 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3362 | struct irq_cfg *cfg; |
3363 | unsigned int dest; | |
54168ed7 | 3364 | struct irte irte; |
54168ed7 | 3365 | |
54168ed7 IM |
3366 | if (get_irte(irq, &irte)) |
3367 | return; | |
3368 | ||
22f65d31 MT |
3369 | dest = set_desc_affinity(desc, mask); |
3370 | if (dest == BAD_APICID) | |
54168ed7 IM |
3371 | return; |
3372 | ||
54168ed7 IM |
3373 | irte.vector = cfg->vector; |
3374 | irte.dest_id = IRTE_DEST(dest); | |
3375 | ||
3376 | /* | |
3377 | * atomically update the IRTE with the new destination and vector. | |
3378 | */ | |
3379 | modify_irte(irq, &irte); | |
3380 | ||
3381 | /* | |
3382 | * After this point, all the interrupts will start arriving | |
3383 | * at the new destination. So, time to cleanup the previous | |
3384 | * vector allocation. | |
3385 | */ | |
22f65d31 MT |
3386 | if (cfg->move_in_progress) |
3387 | send_cleanup_vector(cfg); | |
54168ed7 | 3388 | } |
3145e941 | 3389 | |
54168ed7 | 3390 | #endif |
3b7d1921 | 3391 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3392 | |
3b7d1921 EB |
3393 | /* |
3394 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3395 | * which implement the MSI or MSI-X Capability Structure. | |
3396 | */ | |
3397 | static struct irq_chip msi_chip = { | |
3398 | .name = "PCI-MSI", | |
3399 | .unmask = unmask_msi_irq, | |
3400 | .mask = mask_msi_irq, | |
1d025192 | 3401 | .ack = ack_apic_edge, |
3b7d1921 EB |
3402 | #ifdef CONFIG_SMP |
3403 | .set_affinity = set_msi_irq_affinity, | |
3404 | #endif | |
3405 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3406 | }; |
3407 | ||
54168ed7 IM |
3408 | #ifdef CONFIG_INTR_REMAP |
3409 | static struct irq_chip msi_ir_chip = { | |
3410 | .name = "IR-PCI-MSI", | |
3411 | .unmask = unmask_msi_irq, | |
3412 | .mask = mask_msi_irq, | |
3413 | .ack = ack_x2apic_edge, | |
3414 | #ifdef CONFIG_SMP | |
3415 | .set_affinity = ir_set_msi_irq_affinity, | |
3416 | #endif | |
3417 | .retrigger = ioapic_retrigger_irq, | |
3418 | }; | |
3419 | ||
3420 | /* | |
3421 | * Map the PCI dev to the corresponding remapping hardware unit | |
3422 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3423 | * in it. | |
3424 | */ | |
3425 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3426 | { | |
3427 | struct intel_iommu *iommu; | |
3428 | int index; | |
3429 | ||
3430 | iommu = map_dev_to_ir(dev); | |
3431 | if (!iommu) { | |
3432 | printk(KERN_ERR | |
3433 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3434 | return -ENOENT; | |
3435 | } | |
3436 | ||
3437 | index = alloc_irte(iommu, irq, nvec); | |
3438 | if (index < 0) { | |
3439 | printk(KERN_ERR | |
3440 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3441 | pci_name(dev)); |
54168ed7 IM |
3442 | return -ENOSPC; |
3443 | } | |
3444 | return index; | |
3445 | } | |
3446 | #endif | |
1d025192 | 3447 | |
3145e941 | 3448 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3449 | { |
3450 | int ret; | |
3451 | struct msi_msg msg; | |
3452 | ||
3453 | ret = msi_compose_msg(dev, irq, &msg); | |
3454 | if (ret < 0) | |
3455 | return ret; | |
3456 | ||
3145e941 | 3457 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3458 | write_msi_msg(irq, &msg); |
3459 | ||
54168ed7 IM |
3460 | #ifdef CONFIG_INTR_REMAP |
3461 | if (irq_remapped(irq)) { | |
3462 | struct irq_desc *desc = irq_to_desc(irq); | |
3463 | /* | |
3464 | * irq migration in process context | |
3465 | */ | |
3466 | desc->status |= IRQ_MOVE_PCNTXT; | |
3467 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3468 | } else | |
3469 | #endif | |
3470 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 | 3471 | |
c81bba49 YL |
3472 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3473 | ||
1d025192 YL |
3474 | return 0; |
3475 | } | |
3476 | ||
0b8f1efa | 3477 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc) |
3b7d1921 | 3478 | { |
54168ed7 IM |
3479 | unsigned int irq; |
3480 | int ret; | |
199751d7 YL |
3481 | unsigned int irq_want; |
3482 | ||
be5d5350 | 3483 | irq_want = nr_irqs_gsi; |
199751d7 | 3484 | irq = create_irq_nr(irq_want); |
199751d7 YL |
3485 | if (irq == 0) |
3486 | return -1; | |
f7feaca7 | 3487 | |
54168ed7 IM |
3488 | #ifdef CONFIG_INTR_REMAP |
3489 | if (!intr_remapping_enabled) | |
3490 | goto no_ir; | |
3491 | ||
3492 | ret = msi_alloc_irte(dev, irq, 1); | |
3493 | if (ret < 0) | |
3494 | goto error; | |
3495 | no_ir: | |
3496 | #endif | |
0b8f1efa | 3497 | ret = setup_msi_irq(dev, msidesc, irq); |
f7feaca7 EB |
3498 | if (ret < 0) { |
3499 | destroy_irq(irq); | |
3b7d1921 | 3500 | return ret; |
54168ed7 | 3501 | } |
7fe3730d | 3502 | return 0; |
54168ed7 IM |
3503 | |
3504 | #ifdef CONFIG_INTR_REMAP | |
3505 | error: | |
3506 | destroy_irq(irq); | |
3507 | return ret; | |
3508 | #endif | |
3b7d1921 EB |
3509 | } |
3510 | ||
047c8fdb YL |
3511 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3512 | { | |
54168ed7 IM |
3513 | unsigned int irq; |
3514 | int ret, sub_handle; | |
0b8f1efa | 3515 | struct msi_desc *msidesc; |
54168ed7 IM |
3516 | unsigned int irq_want; |
3517 | ||
3518 | #ifdef CONFIG_INTR_REMAP | |
3519 | struct intel_iommu *iommu = 0; | |
3520 | int index = 0; | |
3521 | #endif | |
3522 | ||
be5d5350 | 3523 | irq_want = nr_irqs_gsi; |
54168ed7 | 3524 | sub_handle = 0; |
0b8f1efa YL |
3525 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3526 | irq = create_irq_nr(irq_want); | |
be5d5350 | 3527 | irq_want++; |
54168ed7 IM |
3528 | if (irq == 0) |
3529 | return -1; | |
3530 | #ifdef CONFIG_INTR_REMAP | |
3531 | if (!intr_remapping_enabled) | |
3532 | goto no_ir; | |
3533 | ||
3534 | if (!sub_handle) { | |
3535 | /* | |
3536 | * allocate the consecutive block of IRTE's | |
3537 | * for 'nvec' | |
3538 | */ | |
3539 | index = msi_alloc_irte(dev, irq, nvec); | |
3540 | if (index < 0) { | |
3541 | ret = index; | |
3542 | goto error; | |
3543 | } | |
3544 | } else { | |
3545 | iommu = map_dev_to_ir(dev); | |
3546 | if (!iommu) { | |
3547 | ret = -ENOENT; | |
3548 | goto error; | |
3549 | } | |
3550 | /* | |
3551 | * setup the mapping between the irq and the IRTE | |
3552 | * base index, the sub_handle pointing to the | |
3553 | * appropriate interrupt remap table entry. | |
3554 | */ | |
3555 | set_irte_irq(irq, iommu, index, sub_handle); | |
3556 | } | |
3557 | no_ir: | |
3558 | #endif | |
0b8f1efa | 3559 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3560 | if (ret < 0) |
3561 | goto error; | |
3562 | sub_handle++; | |
3563 | } | |
3564 | return 0; | |
047c8fdb YL |
3565 | |
3566 | error: | |
54168ed7 IM |
3567 | destroy_irq(irq); |
3568 | return ret; | |
047c8fdb YL |
3569 | } |
3570 | ||
3b7d1921 EB |
3571 | void arch_teardown_msi_irq(unsigned int irq) |
3572 | { | |
f7feaca7 | 3573 | destroy_irq(irq); |
3b7d1921 EB |
3574 | } |
3575 | ||
54168ed7 IM |
3576 | #ifdef CONFIG_DMAR |
3577 | #ifdef CONFIG_SMP | |
22f65d31 | 3578 | static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3579 | { |
3145e941 | 3580 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3581 | struct irq_cfg *cfg; |
3582 | struct msi_msg msg; | |
3583 | unsigned int dest; | |
54168ed7 | 3584 | |
22f65d31 MT |
3585 | dest = set_desc_affinity(desc, mask); |
3586 | if (dest == BAD_APICID) | |
54168ed7 IM |
3587 | return; |
3588 | ||
3145e941 | 3589 | cfg = desc->chip_data; |
54168ed7 IM |
3590 | |
3591 | dmar_msi_read(irq, &msg); | |
3592 | ||
3593 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3594 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3595 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3596 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3597 | ||
3598 | dmar_msi_write(irq, &msg); | |
54168ed7 | 3599 | } |
3145e941 | 3600 | |
54168ed7 IM |
3601 | #endif /* CONFIG_SMP */ |
3602 | ||
3603 | struct irq_chip dmar_msi_type = { | |
3604 | .name = "DMAR_MSI", | |
3605 | .unmask = dmar_msi_unmask, | |
3606 | .mask = dmar_msi_mask, | |
3607 | .ack = ack_apic_edge, | |
3608 | #ifdef CONFIG_SMP | |
3609 | .set_affinity = dmar_msi_set_affinity, | |
3610 | #endif | |
3611 | .retrigger = ioapic_retrigger_irq, | |
3612 | }; | |
3613 | ||
3614 | int arch_setup_dmar_msi(unsigned int irq) | |
3615 | { | |
3616 | int ret; | |
3617 | struct msi_msg msg; | |
2d3fcc1c | 3618 | |
54168ed7 IM |
3619 | ret = msi_compose_msg(NULL, irq, &msg); |
3620 | if (ret < 0) | |
3621 | return ret; | |
3622 | dmar_msi_write(irq, &msg); | |
3623 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3624 | "edge"); | |
3625 | return 0; | |
3626 | } | |
3627 | #endif | |
3628 | ||
58ac1e76 | 3629 | #ifdef CONFIG_HPET_TIMER |
3630 | ||
3631 | #ifdef CONFIG_SMP | |
22f65d31 | 3632 | static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3633 | { |
3145e941 | 3634 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3635 | struct irq_cfg *cfg; |
58ac1e76 | 3636 | struct msi_msg msg; |
3637 | unsigned int dest; | |
58ac1e76 | 3638 | |
22f65d31 MT |
3639 | dest = set_desc_affinity(desc, mask); |
3640 | if (dest == BAD_APICID) | |
58ac1e76 | 3641 | return; |
3642 | ||
3145e941 | 3643 | cfg = desc->chip_data; |
58ac1e76 | 3644 | |
3645 | hpet_msi_read(irq, &msg); | |
3646 | ||
3647 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3648 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3649 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3650 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3651 | ||
3652 | hpet_msi_write(irq, &msg); | |
58ac1e76 | 3653 | } |
3145e941 | 3654 | |
58ac1e76 | 3655 | #endif /* CONFIG_SMP */ |
3656 | ||
3657 | struct irq_chip hpet_msi_type = { | |
3658 | .name = "HPET_MSI", | |
3659 | .unmask = hpet_msi_unmask, | |
3660 | .mask = hpet_msi_mask, | |
3661 | .ack = ack_apic_edge, | |
3662 | #ifdef CONFIG_SMP | |
3663 | .set_affinity = hpet_msi_set_affinity, | |
3664 | #endif | |
3665 | .retrigger = ioapic_retrigger_irq, | |
3666 | }; | |
3667 | ||
3668 | int arch_setup_hpet_msi(unsigned int irq) | |
3669 | { | |
3670 | int ret; | |
3671 | struct msi_msg msg; | |
3672 | ||
3673 | ret = msi_compose_msg(NULL, irq, &msg); | |
3674 | if (ret < 0) | |
3675 | return ret; | |
3676 | ||
3677 | hpet_msi_write(irq, &msg); | |
3678 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3679 | "edge"); | |
c81bba49 | 3680 | |
58ac1e76 | 3681 | return 0; |
3682 | } | |
3683 | #endif | |
3684 | ||
54168ed7 | 3685 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3686 | /* |
3687 | * Hypertransport interrupt support | |
3688 | */ | |
3689 | #ifdef CONFIG_HT_IRQ | |
3690 | ||
3691 | #ifdef CONFIG_SMP | |
3692 | ||
497c9a19 | 3693 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3694 | { |
ec68307c EB |
3695 | struct ht_irq_msg msg; |
3696 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3697 | |
497c9a19 | 3698 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3699 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3700 | |
497c9a19 | 3701 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3702 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3703 | |
ec68307c | 3704 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3705 | } |
3706 | ||
22f65d31 | 3707 | static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3708 | { |
3145e941 | 3709 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3710 | struct irq_cfg *cfg; |
8b955b0d | 3711 | unsigned int dest; |
8b955b0d | 3712 | |
22f65d31 MT |
3713 | dest = set_desc_affinity(desc, mask); |
3714 | if (dest == BAD_APICID) | |
497c9a19 | 3715 | return; |
8b955b0d | 3716 | |
3145e941 | 3717 | cfg = desc->chip_data; |
8b955b0d | 3718 | |
497c9a19 | 3719 | target_ht_irq(irq, dest, cfg->vector); |
8b955b0d | 3720 | } |
3145e941 | 3721 | |
8b955b0d EB |
3722 | #endif |
3723 | ||
c37e108d | 3724 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3725 | .name = "PCI-HT", |
3726 | .mask = mask_ht_irq, | |
3727 | .unmask = unmask_ht_irq, | |
1d025192 | 3728 | .ack = ack_apic_edge, |
8b955b0d EB |
3729 | #ifdef CONFIG_SMP |
3730 | .set_affinity = set_ht_irq_affinity, | |
3731 | #endif | |
3732 | .retrigger = ioapic_retrigger_irq, | |
3733 | }; | |
3734 | ||
3735 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3736 | { | |
497c9a19 YL |
3737 | struct irq_cfg *cfg; |
3738 | int err; | |
8b955b0d | 3739 | |
3145e941 | 3740 | cfg = irq_cfg(irq); |
e7986739 | 3741 | err = assign_irq_vector(irq, cfg, TARGET_CPUS); |
54168ed7 | 3742 | if (!err) { |
ec68307c | 3743 | struct ht_irq_msg msg; |
8b955b0d | 3744 | unsigned dest; |
8b955b0d | 3745 | |
22f65d31 | 3746 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
8b955b0d | 3747 | |
ec68307c | 3748 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3749 | |
ec68307c EB |
3750 | msg.address_lo = |
3751 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3752 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3753 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3754 | ((INT_DEST_MODE == 0) ? |
3755 | HT_IRQ_LOW_DM_PHYSICAL : | |
3756 | HT_IRQ_LOW_DM_LOGICAL) | | |
3757 | HT_IRQ_LOW_RQEOI_EDGE | | |
3758 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3759 | HT_IRQ_LOW_MT_FIXED : | |
3760 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3761 | HT_IRQ_LOW_IRQ_MASKED; | |
3762 | ||
ec68307c | 3763 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3764 | |
a460e745 IM |
3765 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3766 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3767 | |
3768 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3769 | } |
497c9a19 | 3770 | return err; |
8b955b0d EB |
3771 | } |
3772 | #endif /* CONFIG_HT_IRQ */ | |
3773 | ||
4173a0e7 DN |
3774 | #ifdef CONFIG_X86_64 |
3775 | /* | |
3776 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3777 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3778 | */ | |
3779 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3780 | unsigned long mmr_offset) | |
3781 | { | |
22f65d31 | 3782 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3783 | struct irq_cfg *cfg; |
3784 | int mmr_pnode; | |
3785 | unsigned long mmr_value; | |
3786 | struct uv_IO_APIC_route_entry *entry; | |
3787 | unsigned long flags; | |
3788 | int err; | |
3789 | ||
3145e941 YL |
3790 | cfg = irq_cfg(irq); |
3791 | ||
e7986739 | 3792 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3793 | if (err != 0) |
3794 | return err; | |
3795 | ||
3796 | spin_lock_irqsave(&vector_lock, flags); | |
3797 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3798 | irq_name); | |
3799 | spin_unlock_irqrestore(&vector_lock, flags); | |
3800 | ||
4173a0e7 DN |
3801 | mmr_value = 0; |
3802 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3803 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3804 | ||
3805 | entry->vector = cfg->vector; | |
3806 | entry->delivery_mode = INT_DELIVERY_MODE; | |
3807 | entry->dest_mode = INT_DEST_MODE; | |
3808 | entry->polarity = 0; | |
3809 | entry->trigger = 0; | |
3810 | entry->mask = 0; | |
e7986739 | 3811 | entry->dest = cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3812 | |
3813 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3814 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3815 | ||
3816 | return irq; | |
3817 | } | |
3818 | ||
3819 | /* | |
3820 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3821 | * longer allowed to be sent. | |
3822 | */ | |
3823 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3824 | { | |
3825 | unsigned long mmr_value; | |
3826 | struct uv_IO_APIC_route_entry *entry; | |
3827 | int mmr_pnode; | |
3828 | ||
3829 | mmr_value = 0; | |
3830 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3831 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3832 | ||
3833 | entry->mask = 1; | |
3834 | ||
3835 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3836 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3837 | } | |
3838 | #endif /* CONFIG_X86_64 */ | |
3839 | ||
9d6a4d08 YL |
3840 | int __init io_apic_get_redir_entries (int ioapic) |
3841 | { | |
3842 | union IO_APIC_reg_01 reg_01; | |
3843 | unsigned long flags; | |
3844 | ||
3845 | spin_lock_irqsave(&ioapic_lock, flags); | |
3846 | reg_01.raw = io_apic_read(ioapic, 1); | |
3847 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3848 | ||
3849 | return reg_01.bits.entries; | |
3850 | } | |
3851 | ||
be5d5350 | 3852 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3853 | { |
be5d5350 YL |
3854 | int idx; |
3855 | int nr = 0; | |
3856 | ||
3857 | for (idx = 0; idx < nr_ioapics; idx++) | |
3858 | nr += io_apic_get_redir_entries(idx) + 1; | |
3859 | ||
3860 | if (nr > nr_irqs_gsi) | |
3861 | nr_irqs_gsi = nr; | |
9d6a4d08 YL |
3862 | } |
3863 | ||
1da177e4 | 3864 | /* -------------------------------------------------------------------------- |
54168ed7 | 3865 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3866 | -------------------------------------------------------------------------- */ |
3867 | ||
888ba6c6 | 3868 | #ifdef CONFIG_ACPI |
1da177e4 | 3869 | |
54168ed7 | 3870 | #ifdef CONFIG_X86_32 |
36062448 | 3871 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3872 | { |
3873 | union IO_APIC_reg_00 reg_00; | |
3874 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3875 | physid_mask_t tmp; | |
3876 | unsigned long flags; | |
3877 | int i = 0; | |
3878 | ||
3879 | /* | |
36062448 PC |
3880 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3881 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3882 | * supports up to 16 on one shared APIC bus. |
36062448 | 3883 | * |
1da177e4 LT |
3884 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3885 | * advantage of new APIC bus architecture. | |
3886 | */ | |
3887 | ||
3888 | if (physids_empty(apic_id_map)) | |
3889 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3890 | ||
3891 | spin_lock_irqsave(&ioapic_lock, flags); | |
3892 | reg_00.raw = io_apic_read(ioapic, 0); | |
3893 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3894 | ||
3895 | if (apic_id >= get_physical_broadcast()) { | |
3896 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3897 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3898 | apic_id = reg_00.bits.ID; | |
3899 | } | |
3900 | ||
3901 | /* | |
36062448 | 3902 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3903 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3904 | */ | |
3905 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3906 | ||
3907 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3908 | if (!check_apicid_used(apic_id_map, i)) | |
3909 | break; | |
3910 | } | |
3911 | ||
3912 | if (i == get_physical_broadcast()) | |
3913 | panic("Max apic_id exceeded!\n"); | |
3914 | ||
3915 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3916 | "trying %d\n", ioapic, apic_id, i); | |
3917 | ||
3918 | apic_id = i; | |
36062448 | 3919 | } |
1da177e4 LT |
3920 | |
3921 | tmp = apicid_to_cpu_present(apic_id); | |
3922 | physids_or(apic_id_map, apic_id_map, tmp); | |
3923 | ||
3924 | if (reg_00.bits.ID != apic_id) { | |
3925 | reg_00.bits.ID = apic_id; | |
3926 | ||
3927 | spin_lock_irqsave(&ioapic_lock, flags); | |
3928 | io_apic_write(ioapic, 0, reg_00.raw); | |
3929 | reg_00.raw = io_apic_read(ioapic, 0); | |
3930 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3931 | ||
3932 | /* Sanity check */ | |
6070f9ec AD |
3933 | if (reg_00.bits.ID != apic_id) { |
3934 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3935 | return -1; | |
3936 | } | |
1da177e4 LT |
3937 | } |
3938 | ||
3939 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3940 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3941 | ||
3942 | return apic_id; | |
3943 | } | |
3944 | ||
36062448 | 3945 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3946 | { |
3947 | union IO_APIC_reg_01 reg_01; | |
3948 | unsigned long flags; | |
3949 | ||
3950 | spin_lock_irqsave(&ioapic_lock, flags); | |
3951 | reg_01.raw = io_apic_read(ioapic, 1); | |
3952 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3953 | ||
3954 | return reg_01.bits.version; | |
3955 | } | |
54168ed7 | 3956 | #endif |
1da177e4 | 3957 | |
54168ed7 | 3958 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3959 | { |
0b8f1efa YL |
3960 | struct irq_desc *desc; |
3961 | struct irq_cfg *cfg; | |
3962 | int cpu = boot_cpu_id; | |
3963 | ||
1da177e4 | 3964 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3965 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3966 | ioapic); |
3967 | return -EINVAL; | |
3968 | } | |
3969 | ||
0b8f1efa YL |
3970 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
3971 | if (!desc) { | |
3972 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3973 | return 0; | |
3974 | } | |
3975 | ||
1da177e4 LT |
3976 | /* |
3977 | * IRQs < 16 are already in the irq_2_pin[] map | |
3978 | */ | |
99d093d1 | 3979 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3980 | cfg = desc->chip_data; |
3145e941 | 3981 | add_pin_to_irq_cpu(cfg, cpu, ioapic, pin); |
0b8f1efa | 3982 | } |
1da177e4 | 3983 | |
3145e941 | 3984 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3985 | |
3986 | return 0; | |
3987 | } | |
3988 | ||
54168ed7 | 3989 | |
61fd47e0 SL |
3990 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3991 | { | |
3992 | int i; | |
3993 | ||
3994 | if (skip_ioapic_setup) | |
3995 | return -1; | |
3996 | ||
3997 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
3998 | if (mp_irqs[i].mp_irqtype == mp_INT && |
3999 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
4000 | break; |
4001 | if (i >= mp_irq_entries) | |
4002 | return -1; | |
4003 | ||
4004 | *trigger = irq_trigger(i); | |
4005 | *polarity = irq_polarity(i); | |
4006 | return 0; | |
4007 | } | |
4008 | ||
888ba6c6 | 4009 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4010 | |
497c9a19 YL |
4011 | /* |
4012 | * This function currently is only a helper for the i386 smp boot process where | |
4013 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
4014 | * so mask in all cases should simply be TARGET_CPUS | |
4015 | */ | |
4016 | #ifdef CONFIG_SMP | |
4017 | void __init setup_ioapic_dest(void) | |
4018 | { | |
4019 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4020 | struct irq_desc *desc; |
497c9a19 | 4021 | struct irq_cfg *cfg; |
22f65d31 | 4022 | const struct cpumask *mask; |
497c9a19 YL |
4023 | |
4024 | if (skip_ioapic_setup == 1) | |
4025 | return; | |
4026 | ||
4027 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4028 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4029 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4030 | if (irq_entry == -1) | |
4031 | continue; | |
4032 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4033 | ||
4034 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4035 | * when you have too many devices, because at that time only boot | |
4036 | * cpu is online. | |
4037 | */ | |
0b8f1efa YL |
4038 | desc = irq_to_desc(irq); |
4039 | cfg = desc->chip_data; | |
6c2e9403 | 4040 | if (!cfg->vector) { |
3145e941 | 4041 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4042 | irq_trigger(irq_entry), |
4043 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4044 | continue; |
4045 | ||
4046 | } | |
4047 | ||
4048 | /* | |
4049 | * Honour affinities which have been set in early boot | |
4050 | */ | |
6c2e9403 TG |
4051 | if (desc->status & |
4052 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
e7986739 | 4053 | mask = &desc->affinity; |
6c2e9403 TG |
4054 | else |
4055 | mask = TARGET_CPUS; | |
4056 | ||
54168ed7 | 4057 | #ifdef CONFIG_INTR_REMAP |
6c2e9403 | 4058 | if (intr_remapping_enabled) |
e7986739 | 4059 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4060 | else |
6c2e9403 | 4061 | #endif |
e7986739 | 4062 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4063 | } |
4064 | ||
4065 | } | |
4066 | } | |
4067 | #endif | |
4068 | ||
54168ed7 IM |
4069 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4070 | ||
4071 | static struct resource *ioapic_resources; | |
4072 | ||
4073 | static struct resource * __init ioapic_setup_resources(void) | |
4074 | { | |
4075 | unsigned long n; | |
4076 | struct resource *res; | |
4077 | char *mem; | |
4078 | int i; | |
4079 | ||
4080 | if (nr_ioapics <= 0) | |
4081 | return NULL; | |
4082 | ||
4083 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4084 | n *= nr_ioapics; | |
4085 | ||
4086 | mem = alloc_bootmem(n); | |
4087 | res = (void *)mem; | |
4088 | ||
4089 | if (mem != NULL) { | |
4090 | mem += sizeof(struct resource) * nr_ioapics; | |
4091 | ||
4092 | for (i = 0; i < nr_ioapics; i++) { | |
4093 | res[i].name = mem; | |
4094 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4095 | sprintf(mem, "IOAPIC %u", i); | |
4096 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4097 | } | |
4098 | } | |
4099 | ||
4100 | ioapic_resources = res; | |
4101 | ||
4102 | return res; | |
4103 | } | |
54168ed7 | 4104 | |
f3294a33 YL |
4105 | void __init ioapic_init_mappings(void) |
4106 | { | |
4107 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4108 | struct resource *ioapic_res; |
d6c88a50 | 4109 | int i; |
f3294a33 | 4110 | |
54168ed7 | 4111 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4112 | for (i = 0; i < nr_ioapics; i++) { |
4113 | if (smp_found_config) { | |
4114 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
54168ed7 | 4115 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4116 | if (!ioapic_phys) { |
4117 | printk(KERN_ERR | |
4118 | "WARNING: bogus zero IO-APIC " | |
4119 | "address found in MPTABLE, " | |
4120 | "disabling IO/APIC support!\n"); | |
4121 | smp_found_config = 0; | |
4122 | skip_ioapic_setup = 1; | |
4123 | goto fake_ioapic_page; | |
4124 | } | |
54168ed7 | 4125 | #endif |
f3294a33 | 4126 | } else { |
54168ed7 | 4127 | #ifdef CONFIG_X86_32 |
f3294a33 | 4128 | fake_ioapic_page: |
54168ed7 | 4129 | #endif |
f3294a33 | 4130 | ioapic_phys = (unsigned long) |
54168ed7 | 4131 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4132 | ioapic_phys = __pa(ioapic_phys); |
4133 | } | |
4134 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4135 | apic_printk(APIC_VERBOSE, |
4136 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4137 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4138 | idx++; |
54168ed7 | 4139 | |
54168ed7 IM |
4140 | if (ioapic_res != NULL) { |
4141 | ioapic_res->start = ioapic_phys; | |
4142 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4143 | ioapic_res++; | |
4144 | } | |
f3294a33 YL |
4145 | } |
4146 | } | |
4147 | ||
54168ed7 IM |
4148 | static int __init ioapic_insert_resources(void) |
4149 | { | |
4150 | int i; | |
4151 | struct resource *r = ioapic_resources; | |
4152 | ||
4153 | if (!r) { | |
4154 | printk(KERN_ERR | |
4155 | "IO APIC resources could be not be allocated.\n"); | |
4156 | return -1; | |
4157 | } | |
4158 | ||
4159 | for (i = 0; i < nr_ioapics; i++) { | |
4160 | insert_resource(&iomem_resource, r); | |
4161 | r++; | |
4162 | } | |
4163 | ||
4164 | return 0; | |
4165 | } | |
4166 | ||
4167 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4168 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4169 | late_initcall(ioapic_insert_resources); |