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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
49 | #include <asm/desc.h> | |
d4057bdb YL |
50 | #include <asm/proto.h> |
51 | #include <asm/acpi.h> | |
52 | #include <asm/dma.h> | |
1da177e4 | 53 | #include <asm/timer.h> |
306e440d | 54 | #include <asm/i8259.h> |
3e4ff115 | 55 | #include <asm/nmi.h> |
2d3fcc1c | 56 | #include <asm/msidef.h> |
8b955b0d | 57 | #include <asm/hypertransport.h> |
a4dbc34d | 58 | #include <asm/setup.h> |
d4057bdb | 59 | #include <asm/irq_remapping.h> |
58ac1e76 | 60 | #include <asm/hpet.h> |
4173a0e7 DN |
61 | #include <asm/uv/uv_hub.h> |
62 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 63 | |
497c9a19 | 64 | #include <mach_ipi.h> |
1da177e4 | 65 | #include <mach_apic.h> |
874c4fe3 | 66 | #include <mach_apicdef.h> |
1da177e4 | 67 | |
32f71aff MR |
68 | #define __apicdebuginit(type) static type __init |
69 | ||
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
ec2cd0a2 | 85 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
584f734d | 88 | /* MP IRQ source entries */ |
2fddb6e2 | 89 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
90 | |
91 | /* # of MP IRQ source entries */ | |
92 | int mp_irq_entries; | |
93 | ||
8732fc4b AS |
94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
96 | #endif | |
97 | ||
98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
99 | ||
efa2559f YL |
100 | int skip_ioapic_setup; |
101 | ||
54168ed7 | 102 | static int __init parse_noapic(char *str) |
efa2559f YL |
103 | { |
104 | /* disable IO-APIC */ | |
105 | disable_ioapic_setup(); | |
106 | return 0; | |
107 | } | |
108 | early_param("noapic", parse_noapic); | |
66759a01 | 109 | |
da51a821 | 110 | struct irq_cfg; |
0f978f45 | 111 | struct irq_pin_list; |
a1420f39 | 112 | struct irq_cfg { |
da51a821 | 113 | unsigned int irq; |
0f978f45 | 114 | struct irq_pin_list *irq_2_pin; |
497c9a19 YL |
115 | cpumask_t domain; |
116 | cpumask_t old_domain; | |
117 | unsigned move_cleanup_count; | |
a1420f39 | 118 | u8 vector; |
497c9a19 | 119 | u8 move_in_progress : 1; |
a1420f39 YL |
120 | }; |
121 | ||
a1420f39 YL |
122 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
123 | static struct irq_cfg irq_cfg_legacy[] __initdata = { | |
497c9a19 YL |
124 | [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, |
125 | [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
126 | [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
127 | [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
128 | [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
129 | [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
130 | [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
131 | [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
132 | [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
133 | [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
134 | [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
135 | [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
136 | [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
137 | [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
138 | [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
139 | [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
140 | }; |
141 | ||
da51a821 | 142 | static struct irq_cfg irq_cfg_init = { .irq = -1U, }; |
da51a821 YL |
143 | |
144 | static void init_one_irq_cfg(struct irq_cfg *cfg) | |
145 | { | |
146 | memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg)); | |
147 | } | |
148 | ||
149 | static struct irq_cfg *irq_cfgx; | |
e89eb438 | 150 | |
a1420f39 YL |
151 | static void __init init_work(void *data) |
152 | { | |
da51a821 YL |
153 | struct dyn_array *da = data; |
154 | struct irq_cfg *cfg; | |
155 | int legacy_count; | |
156 | int i; | |
157 | ||
158 | cfg = *da->name; | |
a1420f39 | 159 | |
da51a821 | 160 | memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy)); |
a1420f39 | 161 | |
676f4a92 | 162 | legacy_count = ARRAY_SIZE(irq_cfg_legacy); |
da51a821 YL |
163 | for (i = legacy_count; i < *da->nr; i++) |
164 | init_one_irq_cfg(&cfg[i]); | |
a1420f39 | 165 | } |
8f09cd20 YL |
166 | |
167 | #define for_each_irq_cfg(irq, cfg) \ | |
168 | for (irq = 0, cfg = &irq_cfgx[irq]; irq < nr_irqs; irq++, cfg = &irq_cfgx[irq]) | |
169 | ||
170 | DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irqs, PAGE_SIZE, init_work); | |
a1420f39 | 171 | |
8f09cd20 YL |
172 | struct irq_cfg *irq_cfg(unsigned int irq) |
173 | { | |
2cc21ef8 TG |
174 | if (irq < nr_irqs) |
175 | return &irq_cfgx[irq]; | |
8f09cd20 | 176 | |
2cc21ef8 | 177 | return NULL; |
8f09cd20 YL |
178 | } |
179 | struct irq_cfg *irq_cfg_alloc(unsigned int irq) | |
180 | { | |
2cc21ef8 | 181 | return irq_cfg(irq); |
8f09cd20 YL |
182 | } |
183 | ||
1da177e4 LT |
184 | /* |
185 | * This is performance-critical, we want to do it O(1) | |
186 | * | |
187 | * the indexing order of this array favors 1:1 mappings | |
188 | * between pins and IRQs. | |
189 | */ | |
190 | ||
0f978f45 YL |
191 | struct irq_pin_list { |
192 | int apic, pin; | |
193 | struct irq_pin_list *next; | |
194 | }; | |
195 | ||
196 | static struct irq_pin_list *irq_2_pin_head; | |
197 | /* fill one page ? */ | |
198 | static int nr_irq_2_pin = 0x100; | |
199 | static struct irq_pin_list *irq_2_pin_ptr; | |
200 | static void __init irq_2_pin_init_work(void *data) | |
201 | { | |
202 | struct dyn_array *da = data; | |
203 | struct irq_pin_list *pin; | |
204 | int i; | |
205 | ||
206 | pin = *da->name; | |
207 | ||
208 | for (i = 1; i < *da->nr; i++) | |
209 | pin[i-1].next = &pin[i]; | |
210 | ||
211 | irq_2_pin_ptr = &pin[0]; | |
212 | } | |
213 | DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work); | |
214 | ||
215 | static struct irq_pin_list *get_one_free_irq_2_pin(void) | |
216 | { | |
217 | struct irq_pin_list *pin; | |
218 | int i; | |
219 | ||
220 | pin = irq_2_pin_ptr; | |
221 | ||
222 | if (pin) { | |
223 | irq_2_pin_ptr = pin->next; | |
224 | pin->next = NULL; | |
225 | return pin; | |
226 | } | |
227 | ||
228 | /* | |
229 | * we run out of pre-allocate ones, allocate more | |
230 | */ | |
231 | printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin); | |
232 | ||
233 | if (after_bootmem) | |
234 | pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin, | |
235 | GFP_ATOMIC); | |
236 | else | |
237 | pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) * | |
238 | nr_irq_2_pin, PAGE_SIZE, 0); | |
239 | ||
240 | if (!pin) | |
241 | panic("can not get more irq_2_pin\n"); | |
301e6190 | 242 | |
0f978f45 YL |
243 | for (i = 1; i < nr_irq_2_pin; i++) |
244 | pin[i-1].next = &pin[i]; | |
245 | ||
246 | irq_2_pin_ptr = pin->next; | |
247 | pin->next = NULL; | |
248 | ||
249 | return pin; | |
250 | } | |
1da177e4 | 251 | |
130fe05d LT |
252 | struct io_apic { |
253 | unsigned int index; | |
254 | unsigned int unused[3]; | |
255 | unsigned int data; | |
256 | }; | |
257 | ||
258 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
259 | { | |
260 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 261 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
262 | } |
263 | ||
264 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
265 | { | |
266 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
267 | writel(reg, &io_apic->index); | |
268 | return readl(&io_apic->data); | |
269 | } | |
270 | ||
271 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
272 | { | |
273 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
274 | writel(reg, &io_apic->index); | |
275 | writel(value, &io_apic->data); | |
276 | } | |
277 | ||
278 | /* | |
279 | * Re-write a value: to be used for read-modify-write | |
280 | * cycles where the read already set up the index register. | |
281 | * | |
282 | * Older SiS APIC requires we rewrite the index register | |
283 | */ | |
284 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
285 | { | |
54168ed7 IM |
286 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
287 | if (sis_apic_bug) | |
288 | writel(reg, &io_apic->index); | |
130fe05d LT |
289 | writel(value, &io_apic->data); |
290 | } | |
291 | ||
047c8fdb YL |
292 | static bool io_apic_level_ack_pending(unsigned int irq) |
293 | { | |
294 | struct irq_pin_list *entry; | |
295 | unsigned long flags; | |
296 | struct irq_cfg *cfg = irq_cfg(irq); | |
297 | ||
298 | spin_lock_irqsave(&ioapic_lock, flags); | |
299 | entry = cfg->irq_2_pin; | |
300 | for (;;) { | |
301 | unsigned int reg; | |
302 | int pin; | |
303 | ||
304 | if (!entry) | |
305 | break; | |
306 | pin = entry->pin; | |
307 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
308 | /* Is the remote IRR bit set? */ | |
309 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
310 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
311 | return true; | |
312 | } | |
313 | if (!entry->next) | |
314 | break; | |
315 | entry = entry->next; | |
316 | } | |
317 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
318 | ||
319 | return false; | |
320 | } | |
047c8fdb | 321 | |
cf4c6a2f AK |
322 | union entry_union { |
323 | struct { u32 w1, w2; }; | |
324 | struct IO_APIC_route_entry entry; | |
325 | }; | |
326 | ||
327 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
328 | { | |
329 | union entry_union eu; | |
330 | unsigned long flags; | |
331 | spin_lock_irqsave(&ioapic_lock, flags); | |
332 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
333 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
334 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
335 | return eu.entry; | |
336 | } | |
337 | ||
f9dadfa7 LT |
338 | /* |
339 | * When we write a new IO APIC routing entry, we need to write the high | |
340 | * word first! If the mask bit in the low word is clear, we will enable | |
341 | * the interrupt, and we need to make sure the entry is fully populated | |
342 | * before that happens. | |
343 | */ | |
d15512f4 AK |
344 | static void |
345 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 346 | { |
cf4c6a2f AK |
347 | union entry_union eu; |
348 | eu.entry = e; | |
f9dadfa7 LT |
349 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
350 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
351 | } |
352 | ||
353 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
354 | { | |
355 | unsigned long flags; | |
356 | spin_lock_irqsave(&ioapic_lock, flags); | |
357 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
358 | spin_unlock_irqrestore(&ioapic_lock, flags); |
359 | } | |
360 | ||
361 | /* | |
362 | * When we mask an IO APIC routing entry, we need to write the low | |
363 | * word first, in order to set the mask bit before we change the | |
364 | * high bits! | |
365 | */ | |
366 | static void ioapic_mask_entry(int apic, int pin) | |
367 | { | |
368 | unsigned long flags; | |
369 | union entry_union eu = { .entry.mask = 1 }; | |
370 | ||
cf4c6a2f AK |
371 | spin_lock_irqsave(&ioapic_lock, flags); |
372 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
373 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
374 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
375 | } | |
376 | ||
497c9a19 YL |
377 | #ifdef CONFIG_SMP |
378 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) | |
379 | { | |
380 | int apic, pin; | |
381 | struct irq_cfg *cfg; | |
382 | struct irq_pin_list *entry; | |
383 | ||
384 | cfg = irq_cfg(irq); | |
385 | entry = cfg->irq_2_pin; | |
386 | for (;;) { | |
387 | unsigned int reg; | |
388 | ||
389 | if (!entry) | |
390 | break; | |
391 | ||
392 | apic = entry->apic; | |
393 | pin = entry->pin; | |
54168ed7 IM |
394 | #ifdef CONFIG_INTR_REMAP |
395 | /* | |
396 | * With interrupt-remapping, destination information comes | |
397 | * from interrupt-remapping table entry. | |
398 | */ | |
399 | if (!irq_remapped(irq)) | |
400 | io_apic_write(apic, 0x11 + pin*2, dest); | |
401 | #else | |
497c9a19 | 402 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 403 | #endif |
497c9a19 YL |
404 | reg = io_apic_read(apic, 0x10 + pin*2); |
405 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
406 | reg |= vector; | |
54168ed7 | 407 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
408 | if (!entry->next) |
409 | break; | |
410 | entry = entry->next; | |
411 | } | |
412 | } | |
efa2559f YL |
413 | |
414 | static int assign_irq_vector(int irq, cpumask_t mask); | |
415 | ||
497c9a19 YL |
416 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
417 | { | |
418 | struct irq_cfg *cfg; | |
419 | unsigned long flags; | |
420 | unsigned int dest; | |
421 | cpumask_t tmp; | |
54168ed7 | 422 | struct irq_desc *desc; |
497c9a19 | 423 | |
497c9a19 YL |
424 | cpus_and(tmp, mask, cpu_online_map); |
425 | if (cpus_empty(tmp)) | |
426 | return; | |
427 | ||
047c8fdb | 428 | cfg = irq_cfg(irq); |
497c9a19 YL |
429 | if (assign_irq_vector(irq, mask)) |
430 | return; | |
431 | ||
432 | cpus_and(tmp, cfg->domain, mask); | |
497c9a19 YL |
433 | dest = cpu_mask_to_apicid(tmp); |
434 | /* | |
435 | * Only the high 8 bits are valid. | |
436 | */ | |
437 | dest = SET_APIC_LOGICAL_ID(dest); | |
438 | ||
54168ed7 | 439 | desc = irq_to_desc(irq); |
497c9a19 YL |
440 | spin_lock_irqsave(&ioapic_lock, flags); |
441 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
54168ed7 | 442 | desc->affinity = mask; |
497c9a19 YL |
443 | spin_unlock_irqrestore(&ioapic_lock, flags); |
444 | } | |
497c9a19 YL |
445 | #endif /* CONFIG_SMP */ |
446 | ||
1da177e4 LT |
447 | /* |
448 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
449 | * shared ISA-space IRQs, so we have to support them. We are super | |
450 | * fast in the common case, and fast for shared ISA-space IRQs. | |
451 | */ | |
452 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
453 | { | |
0f978f45 YL |
454 | struct irq_cfg *cfg; |
455 | struct irq_pin_list *entry; | |
456 | ||
457 | /* first time to refer irq_cfg, so with new */ | |
458 | cfg = irq_cfg_alloc(irq); | |
459 | entry = cfg->irq_2_pin; | |
460 | if (!entry) { | |
461 | entry = get_one_free_irq_2_pin(); | |
462 | cfg->irq_2_pin = entry; | |
463 | entry->apic = apic; | |
464 | entry->pin = pin; | |
0f978f45 YL |
465 | return; |
466 | } | |
1da177e4 | 467 | |
0f978f45 YL |
468 | while (entry->next) { |
469 | /* not again, please */ | |
470 | if (entry->apic == apic && entry->pin == pin) | |
471 | return; | |
1da177e4 | 472 | |
0f978f45 | 473 | entry = entry->next; |
1da177e4 | 474 | } |
0f978f45 YL |
475 | |
476 | entry->next = get_one_free_irq_2_pin(); | |
477 | entry = entry->next; | |
1da177e4 LT |
478 | entry->apic = apic; |
479 | entry->pin = pin; | |
480 | } | |
481 | ||
482 | /* | |
483 | * Reroute an IRQ to a different pin. | |
484 | */ | |
485 | static void __init replace_pin_at_irq(unsigned int irq, | |
486 | int oldapic, int oldpin, | |
487 | int newapic, int newpin) | |
488 | { | |
0f978f45 YL |
489 | struct irq_cfg *cfg = irq_cfg(irq); |
490 | struct irq_pin_list *entry = cfg->irq_2_pin; | |
491 | int replaced = 0; | |
1da177e4 | 492 | |
0f978f45 | 493 | while (entry) { |
1da177e4 LT |
494 | if (entry->apic == oldapic && entry->pin == oldpin) { |
495 | entry->apic = newapic; | |
496 | entry->pin = newpin; | |
0f978f45 YL |
497 | replaced = 1; |
498 | /* every one is different, right? */ | |
1da177e4 | 499 | break; |
0f978f45 YL |
500 | } |
501 | entry = entry->next; | |
1da177e4 | 502 | } |
0f978f45 YL |
503 | |
504 | /* why? call replace before add? */ | |
505 | if (!replaced) | |
506 | add_pin_to_irq(irq, newapic, newpin); | |
1da177e4 LT |
507 | } |
508 | ||
87783be4 CG |
509 | static inline void io_apic_modify_irq(unsigned int irq, |
510 | int mask_and, int mask_or, | |
511 | void (*final)(struct irq_pin_list *entry)) | |
512 | { | |
513 | int pin; | |
514 | struct irq_cfg *cfg; | |
515 | struct irq_pin_list *entry; | |
047c8fdb | 516 | |
87783be4 CG |
517 | cfg = irq_cfg(irq); |
518 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { | |
519 | unsigned int reg; | |
520 | pin = entry->pin; | |
521 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
522 | reg &= mask_and; | |
523 | reg |= mask_or; | |
524 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
525 | if (final) | |
526 | final(entry); | |
527 | } | |
528 | } | |
047c8fdb | 529 | |
87783be4 CG |
530 | static void __unmask_IO_APIC_irq(unsigned int irq) |
531 | { | |
532 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, 0, NULL); | |
533 | } | |
047c8fdb | 534 | |
4e738e2f | 535 | #ifdef CONFIG_X86_64 |
87783be4 | 536 | void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 537 | { |
87783be4 CG |
538 | /* |
539 | * Synchronize the IO-APIC and the CPU by doing | |
540 | * a dummy read from the IO-APIC | |
541 | */ | |
542 | struct io_apic __iomem *io_apic; | |
543 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 544 | readl(&io_apic->data); |
1da177e4 LT |
545 | } |
546 | ||
87783be4 CG |
547 | static void __mask_IO_APIC_irq(unsigned int irq) |
548 | { | |
549 | io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); | |
550 | } | |
551 | #else /* CONFIG_X86_32 */ | |
552 | static void __mask_IO_APIC_irq(unsigned int irq) | |
553 | { | |
554 | io_apic_modify_irq(irq, ~0, IO_APIC_REDIR_MASKED, NULL); | |
555 | } | |
1da177e4 | 556 | |
87783be4 CG |
557 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
558 | { | |
559 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_LEVEL_TRIGGER, | |
560 | IO_APIC_REDIR_MASKED, NULL); | |
561 | } | |
1da177e4 | 562 | |
87783be4 CG |
563 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
564 | { | |
565 | io_apic_modify_irq(irq, ~IO_APIC_REDIR_MASKED, | |
566 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | |
567 | } | |
568 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 569 | |
54168ed7 | 570 | static void mask_IO_APIC_irq (unsigned int irq) |
1da177e4 LT |
571 | { |
572 | unsigned long flags; | |
573 | ||
574 | spin_lock_irqsave(&ioapic_lock, flags); | |
575 | __mask_IO_APIC_irq(irq); | |
576 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
577 | } | |
578 | ||
54168ed7 | 579 | static void unmask_IO_APIC_irq (unsigned int irq) |
1da177e4 LT |
580 | { |
581 | unsigned long flags; | |
582 | ||
583 | spin_lock_irqsave(&ioapic_lock, flags); | |
584 | __unmask_IO_APIC_irq(irq); | |
585 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
586 | } | |
587 | ||
588 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
589 | { | |
590 | struct IO_APIC_route_entry entry; | |
36062448 | 591 | |
1da177e4 | 592 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 593 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
594 | if (entry.delivery_mode == dest_SMI) |
595 | return; | |
1da177e4 LT |
596 | /* |
597 | * Disable it in the IO-APIC irq-routing table: | |
598 | */ | |
f9dadfa7 | 599 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
600 | } |
601 | ||
54168ed7 | 602 | static void clear_IO_APIC (void) |
1da177e4 LT |
603 | { |
604 | int apic, pin; | |
605 | ||
606 | for (apic = 0; apic < nr_ioapics; apic++) | |
607 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
608 | clear_IO_APIC_pin(apic, pin); | |
609 | } | |
610 | ||
54168ed7 | 611 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 612 | void send_IPI_self(int vector) |
1da177e4 LT |
613 | { |
614 | unsigned int cfg; | |
615 | ||
616 | /* | |
617 | * Wait for idle. | |
618 | */ | |
619 | apic_wait_icr_idle(); | |
620 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
621 | /* | |
622 | * Send the IPI. The write to APIC_ICR fires this off. | |
623 | */ | |
593f4a78 | 624 | apic_write(APIC_ICR, cfg); |
1da177e4 | 625 | } |
54168ed7 | 626 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 627 | |
54168ed7 | 628 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
629 | /* |
630 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
631 | * specific CPU-side IRQs. | |
632 | */ | |
633 | ||
634 | #define MAX_PIRQS 8 | |
635 | static int pirq_entries [MAX_PIRQS]; | |
636 | static int pirqs_enabled; | |
1da177e4 | 637 | |
1da177e4 LT |
638 | static int __init ioapic_pirq_setup(char *str) |
639 | { | |
640 | int i, max; | |
641 | int ints[MAX_PIRQS+1]; | |
642 | ||
643 | get_options(str, ARRAY_SIZE(ints), ints); | |
644 | ||
645 | for (i = 0; i < MAX_PIRQS; i++) | |
646 | pirq_entries[i] = -1; | |
647 | ||
648 | pirqs_enabled = 1; | |
649 | apic_printk(APIC_VERBOSE, KERN_INFO | |
650 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
651 | max = MAX_PIRQS; | |
652 | if (ints[0] < MAX_PIRQS) | |
653 | max = ints[0]; | |
654 | ||
655 | for (i = 0; i < max; i++) { | |
656 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
657 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
658 | /* | |
659 | * PIRQs are mapped upside down, usually. | |
660 | */ | |
661 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
662 | } | |
663 | return 1; | |
664 | } | |
665 | ||
666 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
667 | #endif /* CONFIG_X86_32 */ |
668 | ||
669 | #ifdef CONFIG_INTR_REMAP | |
670 | /* I/O APIC RTE contents at the OS boot up */ | |
671 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
672 | ||
673 | /* | |
674 | * Saves and masks all the unmasked IO-APIC RTE's | |
675 | */ | |
676 | int save_mask_IO_APIC_setup(void) | |
677 | { | |
678 | union IO_APIC_reg_01 reg_01; | |
679 | unsigned long flags; | |
680 | int apic, pin; | |
681 | ||
682 | /* | |
683 | * The number of IO-APIC IRQ registers (== #pins): | |
684 | */ | |
685 | for (apic = 0; apic < nr_ioapics; apic++) { | |
686 | spin_lock_irqsave(&ioapic_lock, flags); | |
687 | reg_01.raw = io_apic_read(apic, 1); | |
688 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
689 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
690 | } | |
691 | ||
692 | for (apic = 0; apic < nr_ioapics; apic++) { | |
693 | early_ioapic_entries[apic] = | |
694 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
695 | nr_ioapic_registers[apic], GFP_KERNEL); | |
696 | if (!early_ioapic_entries[apic]) | |
5ffa4eb2 | 697 | goto nomem; |
54168ed7 IM |
698 | } |
699 | ||
700 | for (apic = 0; apic < nr_ioapics; apic++) | |
701 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
702 | struct IO_APIC_route_entry entry; | |
703 | ||
704 | entry = early_ioapic_entries[apic][pin] = | |
705 | ioapic_read_entry(apic, pin); | |
706 | if (!entry.mask) { | |
707 | entry.mask = 1; | |
708 | ioapic_write_entry(apic, pin, entry); | |
709 | } | |
710 | } | |
5ffa4eb2 | 711 | |
54168ed7 | 712 | return 0; |
5ffa4eb2 CG |
713 | |
714 | nomem: | |
c1370b49 CG |
715 | while (apic >= 0) |
716 | kfree(early_ioapic_entries[apic--]); | |
5ffa4eb2 CG |
717 | memset(early_ioapic_entries, 0, |
718 | ARRAY_SIZE(early_ioapic_entries)); | |
719 | ||
720 | return -ENOMEM; | |
54168ed7 IM |
721 | } |
722 | ||
723 | void restore_IO_APIC_setup(void) | |
724 | { | |
725 | int apic, pin; | |
726 | ||
5ffa4eb2 CG |
727 | for (apic = 0; apic < nr_ioapics; apic++) { |
728 | if (!early_ioapic_entries[apic]) | |
729 | break; | |
54168ed7 IM |
730 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
731 | ioapic_write_entry(apic, pin, | |
732 | early_ioapic_entries[apic][pin]); | |
5ffa4eb2 CG |
733 | kfree(early_ioapic_entries[apic]); |
734 | early_ioapic_entries[apic] = NULL; | |
735 | } | |
54168ed7 IM |
736 | } |
737 | ||
738 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
739 | { | |
740 | /* | |
741 | * for now plain restore of previous settings. | |
742 | * TBD: In the case of OS enabling interrupt-remapping, | |
743 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
744 | * table entries. for now, do a plain restore, and wait for | |
745 | * the setup_IO_APIC_irqs() to do proper initialization. | |
746 | */ | |
747 | restore_IO_APIC_setup(); | |
748 | } | |
749 | #endif | |
1da177e4 LT |
750 | |
751 | /* | |
752 | * Find the IRQ entry number of a certain pin. | |
753 | */ | |
754 | static int find_irq_entry(int apic, int pin, int type) | |
755 | { | |
756 | int i; | |
757 | ||
758 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
759 | if (mp_irqs[i].mp_irqtype == type && |
760 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
761 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
762 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
763 | return i; |
764 | ||
765 | return -1; | |
766 | } | |
767 | ||
768 | /* | |
769 | * Find the pin to which IRQ[irq] (ISA) is connected | |
770 | */ | |
fcfd636a | 771 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
772 | { |
773 | int i; | |
774 | ||
775 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 776 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 777 | |
d27e2b8e | 778 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
779 | (mp_irqs[i].mp_irqtype == type) && |
780 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 781 | |
2fddb6e2 | 782 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
783 | } |
784 | return -1; | |
785 | } | |
786 | ||
fcfd636a EB |
787 | static int __init find_isa_irq_apic(int irq, int type) |
788 | { | |
789 | int i; | |
790 | ||
791 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 792 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 793 | |
73b2961b | 794 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
795 | (mp_irqs[i].mp_irqtype == type) && |
796 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
797 | break; |
798 | } | |
799 | if (i < mp_irq_entries) { | |
800 | int apic; | |
54168ed7 | 801 | for(apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 802 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
803 | return apic; |
804 | } | |
805 | } | |
806 | ||
807 | return -1; | |
808 | } | |
809 | ||
1da177e4 LT |
810 | /* |
811 | * Find a specific PCI IRQ entry. | |
812 | * Not an __init, possibly needed by modules | |
813 | */ | |
814 | static int pin_2_irq(int idx, int apic, int pin); | |
815 | ||
816 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
817 | { | |
818 | int apic, i, best_guess = -1; | |
819 | ||
54168ed7 IM |
820 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
821 | bus, slot, pin); | |
ce6444d3 | 822 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 823 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
824 | return -1; |
825 | } | |
826 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 827 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
828 | |
829 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
830 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
831 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
832 | break; |
833 | ||
47cab822 | 834 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 835 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 836 | (bus == lbus) && |
2fddb6e2 | 837 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
54168ed7 | 838 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
1da177e4 LT |
839 | |
840 | if (!(apic || IO_APIC_IRQ(irq))) | |
841 | continue; | |
842 | ||
2fddb6e2 | 843 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
844 | return irq; |
845 | /* | |
846 | * Use the first all-but-pin matching entry as a | |
847 | * best-guess fuzzy result for broken mptables. | |
848 | */ | |
849 | if (best_guess < 0) | |
850 | best_guess = irq; | |
851 | } | |
852 | } | |
853 | return best_guess; | |
854 | } | |
54168ed7 | 855 | |
129f6946 | 856 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 857 | |
c0a282c2 | 858 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
859 | /* |
860 | * EISA Edge/Level control register, ELCR | |
861 | */ | |
862 | static int EISA_ELCR(unsigned int irq) | |
863 | { | |
864 | if (irq < 16) { | |
865 | unsigned int port = 0x4d0 + (irq >> 3); | |
866 | return (inb(port) >> (irq & 7)) & 1; | |
867 | } | |
868 | apic_printk(APIC_VERBOSE, KERN_INFO | |
869 | "Broken MPtable reports ISA irq %d\n", irq); | |
870 | return 0; | |
871 | } | |
54168ed7 | 872 | |
c0a282c2 | 873 | #endif |
1da177e4 | 874 | |
6728801d AS |
875 | /* ISA interrupts are always polarity zero edge triggered, |
876 | * when listed as conforming in the MP table. */ | |
877 | ||
878 | #define default_ISA_trigger(idx) (0) | |
879 | #define default_ISA_polarity(idx) (0) | |
880 | ||
1da177e4 LT |
881 | /* EISA interrupts are always polarity zero and can be edge or level |
882 | * trigger depending on the ELCR value. If an interrupt is listed as | |
883 | * EISA conforming in the MP table, that means its trigger type must | |
884 | * be read in from the ELCR */ | |
885 | ||
2fddb6e2 | 886 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 887 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
888 | |
889 | /* PCI interrupts are always polarity one level triggered, | |
890 | * when listed as conforming in the MP table. */ | |
891 | ||
892 | #define default_PCI_trigger(idx) (1) | |
893 | #define default_PCI_polarity(idx) (1) | |
894 | ||
895 | /* MCA interrupts are always polarity zero level triggered, | |
896 | * when listed as conforming in the MP table. */ | |
897 | ||
898 | #define default_MCA_trigger(idx) (1) | |
6728801d | 899 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 900 | |
61fd47e0 | 901 | static int MPBIOS_polarity(int idx) |
1da177e4 | 902 | { |
2fddb6e2 | 903 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
904 | int polarity; |
905 | ||
906 | /* | |
907 | * Determine IRQ line polarity (high active or low active): | |
908 | */ | |
54168ed7 | 909 | switch (mp_irqs[idx].mp_irqflag & 3) |
36062448 | 910 | { |
54168ed7 IM |
911 | case 0: /* conforms, ie. bus-type dependent polarity */ |
912 | if (test_bit(bus, mp_bus_not_pci)) | |
913 | polarity = default_ISA_polarity(idx); | |
914 | else | |
915 | polarity = default_PCI_polarity(idx); | |
916 | break; | |
917 | case 1: /* high active */ | |
918 | { | |
919 | polarity = 0; | |
920 | break; | |
921 | } | |
922 | case 2: /* reserved */ | |
923 | { | |
924 | printk(KERN_WARNING "broken BIOS!!\n"); | |
925 | polarity = 1; | |
926 | break; | |
927 | } | |
928 | case 3: /* low active */ | |
929 | { | |
930 | polarity = 1; | |
931 | break; | |
932 | } | |
933 | default: /* invalid */ | |
934 | { | |
935 | printk(KERN_WARNING "broken BIOS!!\n"); | |
936 | polarity = 1; | |
937 | break; | |
938 | } | |
1da177e4 LT |
939 | } |
940 | return polarity; | |
941 | } | |
942 | ||
943 | static int MPBIOS_trigger(int idx) | |
944 | { | |
2fddb6e2 | 945 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
946 | int trigger; |
947 | ||
948 | /* | |
949 | * Determine IRQ trigger mode (edge or level sensitive): | |
950 | */ | |
54168ed7 | 951 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 | 952 | { |
54168ed7 IM |
953 | case 0: /* conforms, ie. bus-type dependent */ |
954 | if (test_bit(bus, mp_bus_not_pci)) | |
955 | trigger = default_ISA_trigger(idx); | |
956 | else | |
957 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 958 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
959 | switch (mp_bus_id_to_type[bus]) { |
960 | case MP_BUS_ISA: /* ISA pin */ | |
961 | { | |
962 | /* set before the switch */ | |
963 | break; | |
964 | } | |
965 | case MP_BUS_EISA: /* EISA pin */ | |
966 | { | |
967 | trigger = default_EISA_trigger(idx); | |
968 | break; | |
969 | } | |
970 | case MP_BUS_PCI: /* PCI pin */ | |
971 | { | |
972 | /* set before the switch */ | |
973 | break; | |
974 | } | |
975 | case MP_BUS_MCA: /* MCA pin */ | |
976 | { | |
977 | trigger = default_MCA_trigger(idx); | |
978 | break; | |
979 | } | |
980 | default: | |
981 | { | |
982 | printk(KERN_WARNING "broken BIOS!!\n"); | |
983 | trigger = 1; | |
984 | break; | |
985 | } | |
986 | } | |
987 | #endif | |
1da177e4 | 988 | break; |
54168ed7 | 989 | case 1: /* edge */ |
1da177e4 | 990 | { |
54168ed7 | 991 | trigger = 0; |
1da177e4 LT |
992 | break; |
993 | } | |
54168ed7 | 994 | case 2: /* reserved */ |
1da177e4 | 995 | { |
54168ed7 IM |
996 | printk(KERN_WARNING "broken BIOS!!\n"); |
997 | trigger = 1; | |
1da177e4 LT |
998 | break; |
999 | } | |
54168ed7 | 1000 | case 3: /* level */ |
1da177e4 | 1001 | { |
54168ed7 | 1002 | trigger = 1; |
1da177e4 LT |
1003 | break; |
1004 | } | |
54168ed7 | 1005 | default: /* invalid */ |
1da177e4 LT |
1006 | { |
1007 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1008 | trigger = 0; |
1da177e4 LT |
1009 | break; |
1010 | } | |
1011 | } | |
1012 | return trigger; | |
1013 | } | |
1014 | ||
1015 | static inline int irq_polarity(int idx) | |
1016 | { | |
1017 | return MPBIOS_polarity(idx); | |
1018 | } | |
1019 | ||
1020 | static inline int irq_trigger(int idx) | |
1021 | { | |
1022 | return MPBIOS_trigger(idx); | |
1023 | } | |
1024 | ||
efa2559f | 1025 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1026 | static int pin_2_irq(int idx, int apic, int pin) |
1027 | { | |
1028 | int irq, i; | |
2fddb6e2 | 1029 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1030 | |
1031 | /* | |
1032 | * Debugging check, we are in big trouble if this message pops up! | |
1033 | */ | |
2fddb6e2 | 1034 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1035 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1036 | ||
54168ed7 | 1037 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 1038 | irq = mp_irqs[idx].mp_srcbusirq; |
54168ed7 | 1039 | } else { |
643befed AS |
1040 | /* |
1041 | * PCI IRQs are mapped in order | |
1042 | */ | |
1043 | i = irq = 0; | |
1044 | while (i < apic) | |
1045 | irq += nr_ioapic_registers[i++]; | |
1046 | irq += pin; | |
54168ed7 IM |
1047 | /* |
1048 | * For MPS mode, so far only needed by ES7000 platform | |
1049 | */ | |
1050 | if (ioapic_renumber_irq) | |
1051 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1052 | } |
1053 | ||
54168ed7 | 1054 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1055 | /* |
1056 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1057 | */ | |
1058 | if ((pin >= 16) && (pin <= 23)) { | |
1059 | if (pirq_entries[pin-16] != -1) { | |
1060 | if (!pirq_entries[pin-16]) { | |
1061 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1062 | "disabling PIRQ%d\n", pin-16); | |
1063 | } else { | |
1064 | irq = pirq_entries[pin-16]; | |
1065 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1066 | "using PIRQ%d -> IRQ %d\n", | |
1067 | pin-16, irq); | |
1068 | } | |
1069 | } | |
1070 | } | |
54168ed7 IM |
1071 | #endif |
1072 | ||
1da177e4 LT |
1073 | return irq; |
1074 | } | |
1075 | ||
497c9a19 YL |
1076 | void lock_vector_lock(void) |
1077 | { | |
1078 | /* Used to the online set of cpus does not change | |
1079 | * during assign_irq_vector. | |
1080 | */ | |
1081 | spin_lock(&vector_lock); | |
1082 | } | |
1da177e4 | 1083 | |
497c9a19 | 1084 | void unlock_vector_lock(void) |
1da177e4 | 1085 | { |
497c9a19 YL |
1086 | spin_unlock(&vector_lock); |
1087 | } | |
1da177e4 | 1088 | |
497c9a19 YL |
1089 | static int __assign_irq_vector(int irq, cpumask_t mask) |
1090 | { | |
047c8fdb YL |
1091 | /* |
1092 | * NOTE! The local APIC isn't very good at handling | |
1093 | * multiple interrupts at the same interrupt level. | |
1094 | * As the interrupt level is determined by taking the | |
1095 | * vector number and shifting that right by 4, we | |
1096 | * want to spread these out a bit so that they don't | |
1097 | * all fall in the same interrupt level. | |
1098 | * | |
1099 | * Also, we've got to be careful not to trash gate | |
1100 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1101 | */ | |
54168ed7 IM |
1102 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1103 | unsigned int old_vector; | |
1104 | int cpu; | |
1105 | struct irq_cfg *cfg; | |
ace80ab7 | 1106 | |
54168ed7 | 1107 | cfg = irq_cfg(irq); |
8339f000 | 1108 | |
54168ed7 IM |
1109 | /* Only try and allocate irqs on cpus that are present */ |
1110 | cpus_and(mask, mask, cpu_online_map); | |
ace80ab7 | 1111 | |
54168ed7 IM |
1112 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1113 | return -EBUSY; | |
0a1ad60d | 1114 | |
54168ed7 IM |
1115 | old_vector = cfg->vector; |
1116 | if (old_vector) { | |
1117 | cpumask_t tmp; | |
1118 | cpus_and(tmp, cfg->domain, mask); | |
1119 | if (!cpus_empty(tmp)) | |
1120 | return 0; | |
1121 | } | |
497c9a19 | 1122 | |
54168ed7 IM |
1123 | for_each_cpu_mask_nr(cpu, mask) { |
1124 | cpumask_t domain, new_mask; | |
1125 | int new_cpu; | |
1126 | int vector, offset; | |
497c9a19 | 1127 | |
54168ed7 IM |
1128 | domain = vector_allocation_domain(cpu); |
1129 | cpus_and(new_mask, domain, cpu_online_map); | |
497c9a19 | 1130 | |
54168ed7 IM |
1131 | vector = current_vector; |
1132 | offset = current_offset; | |
497c9a19 | 1133 | next: |
54168ed7 IM |
1134 | vector += 8; |
1135 | if (vector >= first_system_vector) { | |
1136 | /* If we run out of vectors on large boxen, must share them. */ | |
1137 | offset = (offset + 1) % 8; | |
1138 | vector = FIRST_DEVICE_VECTOR + offset; | |
1139 | } | |
1140 | if (unlikely(current_vector == vector)) | |
1141 | continue; | |
047c8fdb | 1142 | #ifdef CONFIG_X86_64 |
54168ed7 IM |
1143 | if (vector == IA32_SYSCALL_VECTOR) |
1144 | goto next; | |
047c8fdb | 1145 | #else |
54168ed7 IM |
1146 | if (vector == SYSCALL_VECTOR) |
1147 | goto next; | |
047c8fdb | 1148 | #endif |
54168ed7 IM |
1149 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1150 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) | |
1151 | goto next; | |
1152 | /* Found one! */ | |
1153 | current_vector = vector; | |
1154 | current_offset = offset; | |
1155 | if (old_vector) { | |
1156 | cfg->move_in_progress = 1; | |
1157 | cfg->old_domain = cfg->domain; | |
7a959cff | 1158 | } |
54168ed7 IM |
1159 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1160 | per_cpu(vector_irq, new_cpu)[vector] = irq; | |
1161 | cfg->vector = vector; | |
1162 | cfg->domain = domain; | |
1163 | return 0; | |
1164 | } | |
1165 | return -ENOSPC; | |
497c9a19 YL |
1166 | } |
1167 | ||
1168 | static int assign_irq_vector(int irq, cpumask_t mask) | |
1169 | { | |
1170 | int err; | |
ace80ab7 | 1171 | unsigned long flags; |
ace80ab7 EB |
1172 | |
1173 | spin_lock_irqsave(&vector_lock, flags); | |
497c9a19 | 1174 | err = __assign_irq_vector(irq, mask); |
26a3c49c | 1175 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1176 | return err; |
1177 | } | |
1178 | ||
1179 | static void __clear_irq_vector(int irq) | |
1180 | { | |
1181 | struct irq_cfg *cfg; | |
1182 | cpumask_t mask; | |
1183 | int cpu, vector; | |
1184 | ||
1185 | cfg = irq_cfg(irq); | |
1186 | BUG_ON(!cfg->vector); | |
1187 | ||
1188 | vector = cfg->vector; | |
1189 | cpus_and(mask, cfg->domain, cpu_online_map); | |
1190 | for_each_cpu_mask_nr(cpu, mask) | |
1191 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1192 | ||
1193 | cfg->vector = 0; | |
1194 | cpus_clear(cfg->domain); | |
1195 | } | |
1196 | ||
1197 | void __setup_vector_irq(int cpu) | |
1198 | { | |
1199 | /* Initialize vector_irq on a new cpu */ | |
1200 | /* This function must be called with vector_lock held */ | |
1201 | int irq, vector; | |
1202 | struct irq_cfg *cfg; | |
1203 | ||
1204 | /* Mark the inuse vectors */ | |
8f09cd20 | 1205 | for_each_irq_cfg(irq, cfg) { |
497c9a19 YL |
1206 | if (!cpu_isset(cpu, cfg->domain)) |
1207 | continue; | |
1208 | vector = cfg->vector; | |
497c9a19 YL |
1209 | per_cpu(vector_irq, cpu)[vector] = irq; |
1210 | } | |
1211 | /* Mark the free vectors */ | |
1212 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1213 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1214 | if (irq < 0) | |
1215 | continue; | |
1216 | ||
1217 | cfg = irq_cfg(irq); | |
1218 | if (!cpu_isset(cpu, cfg->domain)) | |
1219 | per_cpu(vector_irq, cpu)[vector] = -1; | |
54168ed7 | 1220 | } |
1da177e4 | 1221 | } |
3fde6900 | 1222 | |
f5b9ed7a | 1223 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1224 | #ifdef CONFIG_INTR_REMAP |
1225 | static struct irq_chip ir_ioapic_chip; | |
1226 | #endif | |
1da177e4 | 1227 | |
54168ed7 IM |
1228 | #define IOAPIC_AUTO -1 |
1229 | #define IOAPIC_EDGE 0 | |
1230 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1231 | |
047c8fdb | 1232 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1233 | static inline int IO_APIC_irq_trigger(int irq) |
1234 | { | |
54168ed7 | 1235 | int apic, idx, pin; |
1d025192 | 1236 | |
54168ed7 IM |
1237 | for (apic = 0; apic < nr_ioapics; apic++) { |
1238 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1239 | idx = find_irq_entry(apic, pin, mp_INT); | |
1240 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1241 | return irq_trigger(idx); | |
1242 | } | |
1243 | } | |
1244 | /* | |
1245 | * nonexistent IRQs are edge default | |
1246 | */ | |
1247 | return 0; | |
1d025192 | 1248 | } |
047c8fdb YL |
1249 | #else |
1250 | static inline int IO_APIC_irq_trigger(int irq) | |
1251 | { | |
54168ed7 | 1252 | return 1; |
047c8fdb YL |
1253 | } |
1254 | #endif | |
1d025192 | 1255 | |
497c9a19 | 1256 | static void ioapic_register_intr(int irq, unsigned long trigger) |
1da177e4 | 1257 | { |
08678b08 YL |
1258 | struct irq_desc *desc; |
1259 | ||
ee32c973 | 1260 | desc = irq_to_desc(irq); |
199751d7 | 1261 | |
6ebcc00e | 1262 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1263 | trigger == IOAPIC_LEVEL) |
08678b08 | 1264 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1265 | else |
1266 | desc->status &= ~IRQ_LEVEL; | |
1267 | ||
54168ed7 IM |
1268 | #ifdef CONFIG_INTR_REMAP |
1269 | if (irq_remapped(irq)) { | |
1270 | desc->status |= IRQ_MOVE_PCNTXT; | |
1271 | if (trigger) | |
1272 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1273 | handle_fasteoi_irq, | |
1274 | "fasteoi"); | |
1275 | else | |
1276 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1277 | handle_edge_irq, "edge"); | |
1278 | return; | |
1279 | } | |
1280 | #endif | |
047c8fdb YL |
1281 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1282 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1283 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1284 | handle_fasteoi_irq, |
1285 | "fasteoi"); | |
047c8fdb | 1286 | else |
a460e745 | 1287 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1288 | handle_edge_irq, "edge"); |
1da177e4 LT |
1289 | } |
1290 | ||
497c9a19 YL |
1291 | static int setup_ioapic_entry(int apic, int irq, |
1292 | struct IO_APIC_route_entry *entry, | |
1293 | unsigned int destination, int trigger, | |
1294 | int polarity, int vector) | |
1da177e4 | 1295 | { |
497c9a19 YL |
1296 | /* |
1297 | * add it to the IO-APIC irq-routing table: | |
1298 | */ | |
1299 | memset(entry,0,sizeof(*entry)); | |
1300 | ||
54168ed7 IM |
1301 | #ifdef CONFIG_INTR_REMAP |
1302 | if (intr_remapping_enabled) { | |
1303 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1304 | struct irte irte; | |
1305 | struct IR_IO_APIC_route_entry *ir_entry = | |
1306 | (struct IR_IO_APIC_route_entry *) entry; | |
1307 | int index; | |
1308 | ||
1309 | if (!iommu) | |
1310 | panic("No mapping iommu for ioapic %d\n", apic); | |
1311 | ||
1312 | index = alloc_irte(iommu, irq, 1); | |
1313 | if (index < 0) | |
1314 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1315 | ||
1316 | memset(&irte, 0, sizeof(irte)); | |
1317 | ||
1318 | irte.present = 1; | |
1319 | irte.dst_mode = INT_DEST_MODE; | |
1320 | irte.trigger_mode = trigger; | |
1321 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1322 | irte.vector = vector; | |
1323 | irte.dest_id = IRTE_DEST(destination); | |
1324 | ||
1325 | modify_irte(irq, &irte); | |
1326 | ||
1327 | ir_entry->index2 = (index >> 15) & 0x1; | |
1328 | ir_entry->zero = 0; | |
1329 | ir_entry->format = 1; | |
1330 | ir_entry->index = (index & 0x7fff); | |
1331 | } else | |
1332 | #endif | |
1333 | { | |
1334 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1335 | entry->dest_mode = INT_DEST_MODE; | |
1336 | entry->dest = destination; | |
1337 | } | |
497c9a19 | 1338 | |
54168ed7 | 1339 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1340 | entry->trigger = trigger; |
1341 | entry->polarity = polarity; | |
1342 | entry->vector = vector; | |
1343 | ||
1344 | /* Mask level triggered irqs. | |
1345 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1346 | */ | |
1347 | if (trigger) | |
1348 | entry->mask = 1; | |
497c9a19 YL |
1349 | return 0; |
1350 | } | |
1351 | ||
1352 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, | |
54168ed7 | 1353 | int trigger, int polarity) |
497c9a19 YL |
1354 | { |
1355 | struct irq_cfg *cfg; | |
1da177e4 | 1356 | struct IO_APIC_route_entry entry; |
497c9a19 YL |
1357 | cpumask_t mask; |
1358 | ||
1359 | if (!IO_APIC_IRQ(irq)) | |
1360 | return; | |
1361 | ||
1362 | cfg = irq_cfg(irq); | |
1363 | ||
1364 | mask = TARGET_CPUS; | |
1365 | if (assign_irq_vector(irq, mask)) | |
1366 | return; | |
1367 | ||
1368 | cpus_and(mask, cfg->domain, mask); | |
1369 | ||
1370 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1371 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1372 | "IRQ %d Mode:%i Active:%i)\n", | |
1373 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1374 | irq, trigger, polarity); | |
1375 | ||
1376 | ||
1377 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
1378 | cpu_mask_to_apicid(mask), trigger, polarity, | |
1379 | cfg->vector)) { | |
1380 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
1381 | mp_ioapics[apic].mp_apicid, pin); | |
1382 | __clear_irq_vector(irq); | |
1383 | return; | |
1384 | } | |
1385 | ||
1386 | ioapic_register_intr(irq, trigger); | |
1387 | if (irq < 16) | |
1388 | disable_8259A_irq(irq); | |
1389 | ||
1390 | ioapic_write_entry(apic, pin, entry); | |
1391 | } | |
1392 | ||
1393 | static void __init setup_IO_APIC_irqs(void) | |
1394 | { | |
3c2cbd24 CG |
1395 | int apic, pin, idx, irq; |
1396 | int notcon = 0; | |
1da177e4 LT |
1397 | |
1398 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1399 | ||
1400 | for (apic = 0; apic < nr_ioapics; apic++) { | |
3c2cbd24 | 1401 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
20d225b9 | 1402 | |
3c2cbd24 CG |
1403 | idx = find_irq_entry(apic, pin, mp_INT); |
1404 | if (idx == -1) { | |
2a554fb1 | 1405 | if (!notcon) { |
3c2cbd24 | 1406 | notcon = 1; |
2a554fb1 CG |
1407 | apic_printk(APIC_VERBOSE, |
1408 | KERN_DEBUG " %d-%d", | |
1409 | mp_ioapics[apic].mp_apicid, | |
1410 | pin); | |
1411 | } else | |
1412 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1413 | mp_ioapics[apic].mp_apicid, | |
1414 | pin); | |
3c2cbd24 CG |
1415 | continue; |
1416 | } | |
56ffa1a0 CG |
1417 | if (notcon) { |
1418 | apic_printk(APIC_VERBOSE, | |
1419 | " (apicid-pin) not connected\n"); | |
1420 | notcon = 0; | |
1421 | } | |
3c2cbd24 CG |
1422 | |
1423 | irq = pin_2_irq(idx, apic, pin); | |
54168ed7 | 1424 | #ifdef CONFIG_X86_32 |
3c2cbd24 CG |
1425 | if (multi_timer_check(apic, irq)) |
1426 | continue; | |
54168ed7 | 1427 | #endif |
3c2cbd24 | 1428 | add_pin_to_irq(irq, apic, pin); |
36062448 | 1429 | |
3c2cbd24 CG |
1430 | setup_IO_APIC_irq(apic, pin, irq, |
1431 | irq_trigger(idx), irq_polarity(idx)); | |
1432 | } | |
1da177e4 LT |
1433 | } |
1434 | ||
3c2cbd24 CG |
1435 | if (notcon) |
1436 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1437 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1438 | } |
1439 | ||
1440 | /* | |
f7633ce5 | 1441 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1442 | */ |
f7633ce5 MR |
1443 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1444 | int vector) | |
1da177e4 LT |
1445 | { |
1446 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1447 | |
54168ed7 IM |
1448 | #ifdef CONFIG_INTR_REMAP |
1449 | if (intr_remapping_enabled) | |
1450 | return; | |
1451 | #endif | |
1452 | ||
36062448 | 1453 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1454 | |
1455 | /* | |
1456 | * We use logical delivery to get the timer IRQ | |
1457 | * to the first CPU. | |
1458 | */ | |
1459 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1460 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1461 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1462 | entry.delivery_mode = INT_DELIVERY_MODE; |
1463 | entry.polarity = 0; | |
1464 | entry.trigger = 0; | |
1465 | entry.vector = vector; | |
1466 | ||
1467 | /* | |
1468 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1469 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1470 | */ |
54168ed7 | 1471 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1472 | |
1473 | /* | |
1474 | * Add it to the IO-APIC irq-routing table: | |
1475 | */ | |
cf4c6a2f | 1476 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1477 | } |
1478 | ||
32f71aff MR |
1479 | |
1480 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1481 | { |
1482 | int apic, i; | |
1483 | union IO_APIC_reg_00 reg_00; | |
1484 | union IO_APIC_reg_01 reg_01; | |
1485 | union IO_APIC_reg_02 reg_02; | |
1486 | union IO_APIC_reg_03 reg_03; | |
1487 | unsigned long flags; | |
0f978f45 | 1488 | struct irq_cfg *cfg; |
8f09cd20 | 1489 | unsigned int irq; |
1da177e4 LT |
1490 | |
1491 | if (apic_verbosity == APIC_QUIET) | |
1492 | return; | |
1493 | ||
36062448 | 1494 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1495 | for (i = 0; i < nr_ioapics; i++) |
1496 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1497 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1498 | |
1499 | /* | |
1500 | * We are a bit conservative about what we expect. We have to | |
1501 | * know about every hardware change ASAP. | |
1502 | */ | |
1503 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1504 | ||
1505 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1506 | ||
1507 | spin_lock_irqsave(&ioapic_lock, flags); | |
1508 | reg_00.raw = io_apic_read(apic, 0); | |
1509 | reg_01.raw = io_apic_read(apic, 1); | |
1510 | if (reg_01.bits.version >= 0x10) | |
1511 | reg_02.raw = io_apic_read(apic, 2); | |
54168ed7 IM |
1512 | if (reg_01.bits.version >= 0x20) |
1513 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1514 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1515 | ||
54168ed7 | 1516 | printk("\n"); |
ec2cd0a2 | 1517 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1518 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1519 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1520 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1521 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1522 | |
54168ed7 | 1523 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1524 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1525 | |
1526 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1527 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1528 | |
1529 | /* | |
1530 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1531 | * but the value of reg_02 is read as the previous read register | |
1532 | * value, so ignore it if reg_02 == reg_01. | |
1533 | */ | |
1534 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1535 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1536 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1537 | } |
1538 | ||
1539 | /* | |
1540 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1541 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1542 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1543 | */ | |
1544 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1545 | reg_03.raw != reg_01.raw) { | |
1546 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1547 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1548 | } |
1549 | ||
1550 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1551 | ||
d83e94ac YL |
1552 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1553 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1554 | |
1555 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1556 | struct IO_APIC_route_entry entry; | |
1557 | ||
cf4c6a2f | 1558 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1559 | |
54168ed7 IM |
1560 | printk(KERN_DEBUG " %02x %03X ", |
1561 | i, | |
1562 | entry.dest | |
1563 | ); | |
1da177e4 LT |
1564 | |
1565 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1566 | entry.mask, | |
1567 | entry.trigger, | |
1568 | entry.irr, | |
1569 | entry.polarity, | |
1570 | entry.delivery_status, | |
1571 | entry.dest_mode, | |
1572 | entry.delivery_mode, | |
1573 | entry.vector | |
1574 | ); | |
1575 | } | |
1576 | } | |
1da177e4 | 1577 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
8f09cd20 | 1578 | for_each_irq_cfg(irq, cfg) { |
0f978f45 YL |
1579 | struct irq_pin_list *entry = cfg->irq_2_pin; |
1580 | if (!entry) | |
1da177e4 | 1581 | continue; |
8f09cd20 | 1582 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1583 | for (;;) { |
1584 | printk("-> %d:%d", entry->apic, entry->pin); | |
1585 | if (!entry->next) | |
1586 | break; | |
0f978f45 | 1587 | entry = entry->next; |
1da177e4 LT |
1588 | } |
1589 | printk("\n"); | |
1590 | } | |
1591 | ||
1592 | printk(KERN_INFO ".................................... done.\n"); | |
1593 | ||
1594 | return; | |
1595 | } | |
1596 | ||
32f71aff | 1597 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1598 | { |
1599 | unsigned int v; | |
1600 | int i, j; | |
1601 | ||
1602 | if (apic_verbosity == APIC_QUIET) | |
1603 | return; | |
1604 | ||
1605 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1606 | for (i = 0; i < 8; i++) { | |
1607 | v = apic_read(base + i*0x10); | |
1608 | for (j = 0; j < 32; j++) { | |
1609 | if (v & (1<<j)) | |
1610 | printk("1"); | |
1611 | else | |
1612 | printk("0"); | |
1613 | } | |
1614 | printk("\n"); | |
1615 | } | |
1616 | } | |
1617 | ||
32f71aff | 1618 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1619 | { |
1620 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1621 | u64 icr; |
1da177e4 LT |
1622 | |
1623 | if (apic_verbosity == APIC_QUIET) | |
1624 | return; | |
1625 | ||
1626 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1627 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1628 | v = apic_read(APIC_ID); |
54168ed7 | 1629 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1630 | v = apic_read(APIC_LVR); |
1631 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1632 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1633 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1634 | |
1635 | v = apic_read(APIC_TASKPRI); | |
1636 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1637 | ||
54168ed7 | 1638 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1639 | if (!APIC_XAPIC(ver)) { |
1640 | v = apic_read(APIC_ARBPRI); | |
1641 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1642 | v & APIC_ARBPRI_MASK); | |
1643 | } | |
1da177e4 LT |
1644 | v = apic_read(APIC_PROCPRI); |
1645 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1646 | } | |
1647 | ||
a11b5abe YL |
1648 | /* |
1649 | * Remote read supported only in the 82489DX and local APIC for | |
1650 | * Pentium processors. | |
1651 | */ | |
1652 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1653 | v = apic_read(APIC_RRR); | |
1654 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1655 | } | |
1656 | ||
1da177e4 LT |
1657 | v = apic_read(APIC_LDR); |
1658 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1659 | if (!x2apic_enabled()) { |
1660 | v = apic_read(APIC_DFR); | |
1661 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1662 | } | |
1da177e4 LT |
1663 | v = apic_read(APIC_SPIV); |
1664 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1665 | ||
1666 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1667 | print_APIC_bitfield(APIC_ISR); | |
1668 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1669 | print_APIC_bitfield(APIC_TMR); | |
1670 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1671 | print_APIC_bitfield(APIC_IRR); | |
1672 | ||
54168ed7 IM |
1673 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1674 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1675 | apic_write(APIC_ESR, 0); |
54168ed7 | 1676 | |
1da177e4 LT |
1677 | v = apic_read(APIC_ESR); |
1678 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1679 | } | |
1680 | ||
7ab6af7a | 1681 | icr = apic_icr_read(); |
0c425cec IM |
1682 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1683 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1684 | |
1685 | v = apic_read(APIC_LVTT); | |
1686 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1687 | ||
1688 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1689 | v = apic_read(APIC_LVTPC); | |
1690 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1691 | } | |
1692 | v = apic_read(APIC_LVT0); | |
1693 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1694 | v = apic_read(APIC_LVT1); | |
1695 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1696 | ||
1697 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1698 | v = apic_read(APIC_LVTERR); | |
1699 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1700 | } | |
1701 | ||
1702 | v = apic_read(APIC_TMICT); | |
1703 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1704 | v = apic_read(APIC_TMCCT); | |
1705 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1706 | v = apic_read(APIC_TDCR); | |
1707 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1708 | printk("\n"); | |
1709 | } | |
1710 | ||
32f71aff | 1711 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1712 | { |
ffd5aae7 YL |
1713 | int cpu; |
1714 | ||
1715 | preempt_disable(); | |
1716 | for_each_online_cpu(cpu) | |
1717 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1718 | preempt_enable(); | |
1da177e4 LT |
1719 | } |
1720 | ||
32f71aff | 1721 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1722 | { |
1da177e4 LT |
1723 | unsigned int v; |
1724 | unsigned long flags; | |
1725 | ||
1726 | if (apic_verbosity == APIC_QUIET) | |
1727 | return; | |
1728 | ||
1729 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1730 | ||
1731 | spin_lock_irqsave(&i8259A_lock, flags); | |
1732 | ||
1733 | v = inb(0xa1) << 8 | inb(0x21); | |
1734 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1735 | ||
1736 | v = inb(0xa0) << 8 | inb(0x20); | |
1737 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1738 | ||
54168ed7 IM |
1739 | outb(0x0b,0xa0); |
1740 | outb(0x0b,0x20); | |
1da177e4 | 1741 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1742 | outb(0x0a,0xa0); |
1743 | outb(0x0a,0x20); | |
1da177e4 LT |
1744 | |
1745 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1746 | ||
1747 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1748 | ||
1749 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1750 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1751 | } | |
1752 | ||
32f71aff MR |
1753 | __apicdebuginit(int) print_all_ICs(void) |
1754 | { | |
1755 | print_PIC(); | |
1756 | print_all_local_APICs(); | |
1757 | print_IO_APIC(); | |
1758 | ||
1759 | return 0; | |
1760 | } | |
1761 | ||
1762 | fs_initcall(print_all_ICs); | |
1763 | ||
1da177e4 | 1764 | |
efa2559f YL |
1765 | /* Where if anywhere is the i8259 connect in external int mode */ |
1766 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1767 | ||
54168ed7 | 1768 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1769 | { |
1770 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1771 | int i8259_apic, i8259_pin; |
54168ed7 | 1772 | int apic; |
1da177e4 LT |
1773 | unsigned long flags; |
1774 | ||
54168ed7 IM |
1775 | #ifdef CONFIG_X86_32 |
1776 | int i; | |
1da177e4 LT |
1777 | if (!pirqs_enabled) |
1778 | for (i = 0; i < MAX_PIRQS; i++) | |
1779 | pirq_entries[i] = -1; | |
54168ed7 | 1780 | #endif |
1da177e4 LT |
1781 | |
1782 | /* | |
1783 | * The number of IO-APIC IRQ registers (== #pins): | |
1784 | */ | |
fcfd636a | 1785 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1786 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1787 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1788 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1789 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1790 | } | |
54168ed7 | 1791 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1792 | int pin; |
1793 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1794 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1795 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1796 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1797 | |
fcfd636a EB |
1798 | /* If the interrupt line is enabled and in ExtInt mode |
1799 | * I have found the pin where the i8259 is connected. | |
1800 | */ | |
1801 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1802 | ioapic_i8259.apic = apic; | |
1803 | ioapic_i8259.pin = pin; | |
1804 | goto found_i8259; | |
1805 | } | |
1806 | } | |
1807 | } | |
1808 | found_i8259: | |
1809 | /* Look to see what if the MP table has reported the ExtINT */ | |
1810 | /* If we could not find the appropriate pin by looking at the ioapic | |
1811 | * the i8259 probably is not connected the ioapic but give the | |
1812 | * mptable a chance anyway. | |
1813 | */ | |
1814 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1815 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1816 | /* Trust the MP table if nothing is setup in the hardware */ | |
1817 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1818 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1819 | ioapic_i8259.pin = i8259_pin; | |
1820 | ioapic_i8259.apic = i8259_apic; | |
1821 | } | |
1822 | /* Complain if the MP table and the hardware disagree */ | |
1823 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1824 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1825 | { | |
1826 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1827 | } |
1828 | ||
1829 | /* | |
1830 | * Do not trust the IO-APIC being empty at bootup | |
1831 | */ | |
1832 | clear_IO_APIC(); | |
1833 | } | |
1834 | ||
1835 | /* | |
1836 | * Not an __init, needed by the reboot code | |
1837 | */ | |
1838 | void disable_IO_APIC(void) | |
1839 | { | |
1840 | /* | |
1841 | * Clear the IO-APIC before rebooting: | |
1842 | */ | |
1843 | clear_IO_APIC(); | |
1844 | ||
650927ef | 1845 | /* |
0b968d23 | 1846 | * If the i8259 is routed through an IOAPIC |
650927ef | 1847 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1848 | * so legacy interrupts can be delivered. |
650927ef | 1849 | */ |
fcfd636a | 1850 | if (ioapic_i8259.pin != -1) { |
650927ef | 1851 | struct IO_APIC_route_entry entry; |
650927ef EB |
1852 | |
1853 | memset(&entry, 0, sizeof(entry)); | |
1854 | entry.mask = 0; /* Enabled */ | |
1855 | entry.trigger = 0; /* Edge */ | |
1856 | entry.irr = 0; | |
1857 | entry.polarity = 0; /* High */ | |
1858 | entry.delivery_status = 0; | |
1859 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1860 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1861 | entry.vector = 0; |
54168ed7 | 1862 | entry.dest = read_apic_id(); |
650927ef EB |
1863 | |
1864 | /* | |
1865 | * Add it to the IO-APIC irq-routing table: | |
1866 | */ | |
cf4c6a2f | 1867 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1868 | } |
54168ed7 | 1869 | |
fcfd636a | 1870 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1871 | } |
1872 | ||
54168ed7 | 1873 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1874 | /* |
1875 | * function to set the IO-APIC physical IDs based on the | |
1876 | * values stored in the MPC table. | |
1877 | * | |
1878 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1879 | */ | |
1880 | ||
1da177e4 LT |
1881 | static void __init setup_ioapic_ids_from_mpc(void) |
1882 | { | |
1883 | union IO_APIC_reg_00 reg_00; | |
1884 | physid_mask_t phys_id_present_map; | |
1885 | int apic; | |
1886 | int i; | |
1887 | unsigned char old_id; | |
1888 | unsigned long flags; | |
1889 | ||
a4dbc34d | 1890 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 1891 | return; |
d49c4288 | 1892 | |
ca05fea6 NP |
1893 | /* |
1894 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1895 | * no meaning without the serial APIC bus. | |
1896 | */ | |
7c5c1e42 SL |
1897 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1898 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1899 | return; |
1da177e4 LT |
1900 | /* |
1901 | * This is broken; anything with a real cpu count has to | |
1902 | * circumvent this idiocy regardless. | |
1903 | */ | |
1904 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1905 | ||
1906 | /* | |
1907 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1908 | */ | |
1909 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1910 | ||
1911 | /* Read the register 0 value */ | |
1912 | spin_lock_irqsave(&ioapic_lock, flags); | |
1913 | reg_00.raw = io_apic_read(apic, 0); | |
1914 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1915 | |
ec2cd0a2 | 1916 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1917 | |
ec2cd0a2 | 1918 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1919 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1920 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1921 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1922 | reg_00.bits.ID); | |
ec2cd0a2 | 1923 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1924 | } |
1925 | ||
1da177e4 LT |
1926 | /* |
1927 | * Sanity check, is the ID really free? Every APIC in a | |
1928 | * system must have a unique ID or we get lots of nice | |
1929 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1930 | */ | |
1931 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1932 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 1933 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 1934 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1935 | for (i = 0; i < get_physical_broadcast(); i++) |
1936 | if (!physid_isset(i, phys_id_present_map)) | |
1937 | break; | |
1938 | if (i >= get_physical_broadcast()) | |
1939 | panic("Max APIC ID exceeded!\n"); | |
1940 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1941 | i); | |
1942 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 1943 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
1944 | } else { |
1945 | physid_mask_t tmp; | |
ec2cd0a2 | 1946 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1947 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1948 | "phys_id_present_map\n", | |
ec2cd0a2 | 1949 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1950 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1951 | } | |
1952 | ||
1953 | ||
1954 | /* | |
1955 | * We need to adjust the IRQ routing table | |
1956 | * if the ID changed. | |
1957 | */ | |
ec2cd0a2 | 1958 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 1959 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
1960 | if (mp_irqs[i].mp_dstapic == old_id) |
1961 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 1962 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1963 | |
1964 | /* | |
1965 | * Read the right value from the MPC table and | |
1966 | * write it into the ID register. | |
36062448 | 1967 | */ |
1da177e4 LT |
1968 | apic_printk(APIC_VERBOSE, KERN_INFO |
1969 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 1970 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 1971 | |
ec2cd0a2 | 1972 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1973 | spin_lock_irqsave(&ioapic_lock, flags); |
a2d332fa YL |
1974 | io_apic_write(apic, 0, reg_00.raw); |
1975 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1da177e4 LT |
1976 | |
1977 | /* | |
1978 | * Sanity check | |
1979 | */ | |
1980 | spin_lock_irqsave(&ioapic_lock, flags); | |
1981 | reg_00.raw = io_apic_read(apic, 0); | |
1982 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 1983 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
1984 | printk("could not set ID!\n"); |
1985 | else | |
1986 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1987 | } | |
1988 | } | |
54168ed7 | 1989 | #endif |
1da177e4 | 1990 | |
7ce0bcfd | 1991 | int no_timer_check __initdata; |
8542b200 ZA |
1992 | |
1993 | static int __init notimercheck(char *s) | |
1994 | { | |
1995 | no_timer_check = 1; | |
1996 | return 1; | |
1997 | } | |
1998 | __setup("no_timer_check", notimercheck); | |
1999 | ||
1da177e4 LT |
2000 | /* |
2001 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2002 | * about the timer IRQ. We do the following to work around the situation: | |
2003 | * | |
2004 | * - timer IRQ defaults to IO-APIC IRQ | |
2005 | * - if this function detects that timer IRQs are defunct, then we fall | |
2006 | * back to ISA timer IRQs | |
2007 | */ | |
f0a7a5c9 | 2008 | static int __init timer_irq_works(void) |
1da177e4 LT |
2009 | { |
2010 | unsigned long t1 = jiffies; | |
4aae0702 | 2011 | unsigned long flags; |
1da177e4 | 2012 | |
8542b200 ZA |
2013 | if (no_timer_check) |
2014 | return 1; | |
2015 | ||
4aae0702 | 2016 | local_save_flags(flags); |
1da177e4 LT |
2017 | local_irq_enable(); |
2018 | /* Let ten ticks pass... */ | |
2019 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2020 | local_irq_restore(flags); |
1da177e4 LT |
2021 | |
2022 | /* | |
2023 | * Expect a few ticks at least, to be sure some possible | |
2024 | * glue logic does not lock up after one or two first | |
2025 | * ticks in a non-ExtINT mode. Also the local APIC | |
2026 | * might have cached one ExtINT interrupt. Finally, at | |
2027 | * least one tick may be lost due to delays. | |
2028 | */ | |
54168ed7 IM |
2029 | |
2030 | /* jiffies wrap? */ | |
1d16b53e | 2031 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2032 | return 1; |
1da177e4 LT |
2033 | return 0; |
2034 | } | |
2035 | ||
2036 | /* | |
2037 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2038 | * number of pending IRQ events unhandled. These cases are very rare, | |
2039 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2040 | * better to do it this way as thus we do not have to be aware of | |
2041 | * 'pending' interrupts in the IRQ path, except at this point. | |
2042 | */ | |
2043 | /* | |
2044 | * Edge triggered needs to resend any interrupt | |
2045 | * that was delayed but this is now handled in the device | |
2046 | * independent code. | |
2047 | */ | |
2048 | ||
2049 | /* | |
2050 | * Starting up a edge-triggered IO-APIC interrupt is | |
2051 | * nasty - we need to make sure that we get the edge. | |
2052 | * If it is already asserted for some reason, we need | |
2053 | * return 1 to indicate that is was pending. | |
2054 | * | |
2055 | * This is not complete - we should be able to fake | |
2056 | * an edge even if it isn't on the 8259A... | |
2057 | */ | |
54168ed7 | 2058 | |
f5b9ed7a | 2059 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2060 | { |
2061 | int was_pending = 0; | |
2062 | unsigned long flags; | |
2063 | ||
2064 | spin_lock_irqsave(&ioapic_lock, flags); | |
2065 | if (irq < 16) { | |
2066 | disable_8259A_irq(irq); | |
2067 | if (i8259A_irq_pending(irq)) | |
2068 | was_pending = 1; | |
2069 | } | |
2070 | __unmask_IO_APIC_irq(irq); | |
2071 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2072 | ||
2073 | return was_pending; | |
2074 | } | |
2075 | ||
54168ed7 | 2076 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2077 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2078 | { |
54168ed7 IM |
2079 | |
2080 | struct irq_cfg *cfg = irq_cfg(irq); | |
2081 | unsigned long flags; | |
2082 | ||
2083 | spin_lock_irqsave(&vector_lock, flags); | |
2084 | send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector); | |
2085 | spin_unlock_irqrestore(&vector_lock, flags); | |
c0ad90a3 IM |
2086 | |
2087 | return 1; | |
2088 | } | |
54168ed7 IM |
2089 | #else |
2090 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2091 | { |
54168ed7 | 2092 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2093 | |
54168ed7 IM |
2094 | return 1; |
2095 | } | |
2096 | #endif | |
497c9a19 | 2097 | |
54168ed7 IM |
2098 | /* |
2099 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2100 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2101 | * handled with the level-triggered descriptor, but that one has slightly | |
2102 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2103 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2104 | * races. | |
2105 | */ | |
497c9a19 | 2106 | |
54168ed7 | 2107 | #ifdef CONFIG_SMP |
497c9a19 | 2108 | |
54168ed7 IM |
2109 | #ifdef CONFIG_INTR_REMAP |
2110 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2111 | |
54168ed7 | 2112 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2113 | |
54168ed7 IM |
2114 | /* |
2115 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2116 | * | |
2117 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2118 | * and cpu destination) of IRTE and flush the hardware cache. | |
2119 | * | |
2120 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2121 | * vector information, along with modifying IRTE with vector and destination. | |
2122 | * So irq migration for level triggered is little bit more complex compared to | |
2123 | * edge triggered migration. But the good news is, we use the same algorithm | |
2124 | * for level triggered migration as we have today, only difference being, | |
2125 | * we now initiate the irq migration from process context instead of the | |
2126 | * interrupt context. | |
2127 | * | |
2128 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2129 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2130 | * as simple as edge triggered migration and we can do the irq migration | |
2131 | * with a simple atomic update to IO-APIC RTE. | |
2132 | */ | |
2133 | static void migrate_ioapic_irq(int irq, cpumask_t mask) | |
497c9a19 | 2134 | { |
54168ed7 IM |
2135 | struct irq_cfg *cfg; |
2136 | struct irq_desc *desc; | |
2137 | cpumask_t tmp, cleanup_mask; | |
2138 | struct irte irte; | |
2139 | int modify_ioapic_rte; | |
2140 | unsigned int dest; | |
2141 | unsigned long flags; | |
497c9a19 | 2142 | |
54168ed7 IM |
2143 | cpus_and(tmp, mask, cpu_online_map); |
2144 | if (cpus_empty(tmp)) | |
497c9a19 YL |
2145 | return; |
2146 | ||
54168ed7 IM |
2147 | if (get_irte(irq, &irte)) |
2148 | return; | |
497c9a19 | 2149 | |
54168ed7 IM |
2150 | if (assign_irq_vector(irq, mask)) |
2151 | return; | |
2152 | ||
2153 | cfg = irq_cfg(irq); | |
2154 | cpus_and(tmp, cfg->domain, mask); | |
2155 | dest = cpu_mask_to_apicid(tmp); | |
2156 | ||
2157 | desc = irq_to_desc(irq); | |
2158 | modify_ioapic_rte = desc->status & IRQ_LEVEL; | |
2159 | if (modify_ioapic_rte) { | |
2160 | spin_lock_irqsave(&ioapic_lock, flags); | |
2161 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
2162 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2163 | } | |
2164 | ||
2165 | irte.vector = cfg->vector; | |
2166 | irte.dest_id = IRTE_DEST(dest); | |
2167 | ||
2168 | /* | |
2169 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2170 | */ | |
2171 | modify_irte(irq, &irte); | |
2172 | ||
2173 | if (cfg->move_in_progress) { | |
2174 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2175 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2176 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2177 | cfg->move_in_progress = 0; | |
2178 | } | |
2179 | ||
2180 | desc->affinity = mask; | |
2181 | } | |
2182 | ||
2183 | static int migrate_irq_remapped_level(int irq) | |
2184 | { | |
2185 | int ret = -1; | |
2186 | struct irq_desc *desc = irq_to_desc(irq); | |
2187 | ||
2188 | mask_IO_APIC_irq(irq); | |
2189 | ||
2190 | if (io_apic_level_ack_pending(irq)) { | |
2191 | /* | |
2192 | * Interrupt in progress. Migrating irq now will change the | |
2193 | * vector information in the IO-APIC RTE and that will confuse | |
2194 | * the EOI broadcast performed by cpu. | |
2195 | * So, delay the irq migration to the next instance. | |
2196 | */ | |
2197 | schedule_delayed_work(&ir_migration_work, 1); | |
2198 | goto unmask; | |
2199 | } | |
2200 | ||
2201 | /* everthing is clear. we have right of way */ | |
2202 | migrate_ioapic_irq(irq, desc->pending_mask); | |
2203 | ||
2204 | ret = 0; | |
2205 | desc->status &= ~IRQ_MOVE_PENDING; | |
2206 | cpus_clear(desc->pending_mask); | |
2207 | ||
2208 | unmask: | |
2209 | unmask_IO_APIC_irq(irq); | |
2210 | return ret; | |
2211 | } | |
2212 | ||
2213 | static void ir_irq_migration(struct work_struct *work) | |
2214 | { | |
2215 | unsigned int irq; | |
2216 | struct irq_desc *desc; | |
2217 | ||
2218 | for_each_irq_desc(irq, desc) { | |
2219 | if (desc->status & IRQ_MOVE_PENDING) { | |
2220 | unsigned long flags; | |
2221 | ||
2222 | spin_lock_irqsave(&desc->lock, flags); | |
2223 | if (!desc->chip->set_affinity || | |
2224 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2225 | desc->status &= ~IRQ_MOVE_PENDING; | |
2226 | spin_unlock_irqrestore(&desc->lock, flags); | |
2227 | continue; | |
2228 | } | |
2229 | ||
2230 | desc->chip->set_affinity(irq, desc->pending_mask); | |
2231 | spin_unlock_irqrestore(&desc->lock, flags); | |
2232 | } | |
2233 | } | |
2234 | } | |
2235 | ||
2236 | /* | |
2237 | * Migrates the IRQ destination in the process context. | |
2238 | */ | |
2239 | static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
2240 | { | |
2241 | struct irq_desc *desc = irq_to_desc(irq); | |
2242 | ||
2243 | if (desc->status & IRQ_LEVEL) { | |
2244 | desc->status |= IRQ_MOVE_PENDING; | |
2245 | desc->pending_mask = mask; | |
2246 | migrate_irq_remapped_level(irq); | |
2247 | return; | |
2248 | } | |
2249 | ||
2250 | migrate_ioapic_irq(irq, mask); | |
2251 | } | |
2252 | #endif | |
2253 | ||
2254 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2255 | { | |
2256 | unsigned vector, me; | |
2257 | ack_APIC_irq(); | |
2258 | #ifdef CONFIG_X86_64 | |
2259 | exit_idle(); | |
2260 | #endif | |
2261 | irq_enter(); | |
2262 | ||
2263 | me = smp_processor_id(); | |
2264 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2265 | unsigned int irq; | |
2266 | struct irq_desc *desc; | |
2267 | struct irq_cfg *cfg; | |
2268 | irq = __get_cpu_var(vector_irq)[vector]; | |
2269 | ||
2270 | desc = irq_to_desc(irq); | |
2271 | if (!desc) | |
2272 | continue; | |
2273 | ||
2274 | cfg = irq_cfg(irq); | |
2275 | spin_lock(&desc->lock); | |
2276 | if (!cfg->move_cleanup_count) | |
2277 | goto unlock; | |
2278 | ||
2279 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
2280 | goto unlock; | |
2281 | ||
2282 | __get_cpu_var(vector_irq)[vector] = -1; | |
2283 | cfg->move_cleanup_count--; | |
2284 | unlock: | |
2285 | spin_unlock(&desc->lock); | |
2286 | } | |
2287 | ||
2288 | irq_exit(); | |
2289 | } | |
2290 | ||
2291 | static void irq_complete_move(unsigned int irq) | |
2292 | { | |
2293 | struct irq_cfg *cfg = irq_cfg(irq); | |
2294 | unsigned vector, me; | |
2295 | ||
2296 | if (likely(!cfg->move_in_progress)) | |
2297 | return; | |
2298 | ||
2299 | vector = ~get_irq_regs()->orig_ax; | |
2300 | me = smp_processor_id(); | |
2301 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { | |
2302 | cpumask_t cleanup_mask; | |
2303 | ||
2304 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2305 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2306 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
497c9a19 YL |
2307 | cfg->move_in_progress = 0; |
2308 | } | |
2309 | } | |
2310 | #else | |
2311 | static inline void irq_complete_move(unsigned int irq) {} | |
2312 | #endif | |
54168ed7 IM |
2313 | #ifdef CONFIG_INTR_REMAP |
2314 | static void ack_x2apic_level(unsigned int irq) | |
2315 | { | |
2316 | ack_x2APIC_irq(); | |
2317 | } | |
2318 | ||
2319 | static void ack_x2apic_edge(unsigned int irq) | |
2320 | { | |
2321 | ack_x2APIC_irq(); | |
2322 | } | |
2323 | #endif | |
497c9a19 | 2324 | |
1d025192 YL |
2325 | static void ack_apic_edge(unsigned int irq) |
2326 | { | |
2327 | irq_complete_move(irq); | |
2328 | move_native_irq(irq); | |
2329 | ack_APIC_irq(); | |
2330 | } | |
2331 | ||
3eb2cce8 YL |
2332 | #ifdef CONFIG_X86_32 |
2333 | atomic_t irq_mis_count; | |
2334 | #endif | |
2335 | ||
047c8fdb YL |
2336 | static void ack_apic_level(unsigned int irq) |
2337 | { | |
3eb2cce8 YL |
2338 | #ifdef CONFIG_X86_32 |
2339 | unsigned long v; | |
2340 | int i; | |
2341 | #endif | |
54168ed7 | 2342 | int do_unmask_irq = 0; |
047c8fdb | 2343 | |
54168ed7 | 2344 | irq_complete_move(irq); |
047c8fdb | 2345 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 IM |
2346 | /* If we are moving the irq we need to mask it */ |
2347 | if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) { | |
2348 | do_unmask_irq = 1; | |
2349 | mask_IO_APIC_irq(irq); | |
2350 | } | |
047c8fdb YL |
2351 | #endif |
2352 | ||
3eb2cce8 YL |
2353 | #ifdef CONFIG_X86_32 |
2354 | /* | |
2355 | * It appears there is an erratum which affects at least version 0x11 | |
2356 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2357 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2358 | * erroneously delivered as edge-triggered one but the respective IRR | |
2359 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2360 | * message but it will never arrive and further interrupts are blocked | |
2361 | * from the source. The exact reason is so far unknown, but the | |
2362 | * phenomenon was observed when two consecutive interrupt requests | |
2363 | * from a given source get delivered to the same CPU and the source is | |
2364 | * temporarily disabled in between. | |
2365 | * | |
2366 | * A workaround is to simulate an EOI message manually. We achieve it | |
2367 | * by setting the trigger mode to edge and then to level when the edge | |
2368 | * trigger mode gets detected in the TMR of a local APIC for a | |
2369 | * level-triggered interrupt. We mask the source for the time of the | |
2370 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2371 | * The idea is from Manfred Spraul. --macro | |
2372 | */ | |
2373 | i = irq_cfg(irq)->vector; | |
2374 | ||
2375 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2376 | #endif | |
2377 | ||
54168ed7 IM |
2378 | /* |
2379 | * We must acknowledge the irq before we move it or the acknowledge will | |
2380 | * not propagate properly. | |
2381 | */ | |
2382 | ack_APIC_irq(); | |
2383 | ||
2384 | /* Now we can move and renable the irq */ | |
2385 | if (unlikely(do_unmask_irq)) { | |
2386 | /* Only migrate the irq if the ack has been received. | |
2387 | * | |
2388 | * On rare occasions the broadcast level triggered ack gets | |
2389 | * delayed going to ioapics, and if we reprogram the | |
2390 | * vector while Remote IRR is still set the irq will never | |
2391 | * fire again. | |
2392 | * | |
2393 | * To prevent this scenario we read the Remote IRR bit | |
2394 | * of the ioapic. This has two effects. | |
2395 | * - On any sane system the read of the ioapic will | |
2396 | * flush writes (and acks) going to the ioapic from | |
2397 | * this cpu. | |
2398 | * - We get to see if the ACK has actually been delivered. | |
2399 | * | |
2400 | * Based on failed experiments of reprogramming the | |
2401 | * ioapic entry from outside of irq context starting | |
2402 | * with masking the ioapic entry and then polling until | |
2403 | * Remote IRR was clear before reprogramming the | |
2404 | * ioapic I don't trust the Remote IRR bit to be | |
2405 | * completey accurate. | |
2406 | * | |
2407 | * However there appears to be no other way to plug | |
2408 | * this race, so if the Remote IRR bit is not | |
2409 | * accurate and is causing problems then it is a hardware bug | |
2410 | * and you can go talk to the chipset vendor about it. | |
2411 | */ | |
2412 | if (!io_apic_level_ack_pending(irq)) | |
2413 | move_masked_irq(irq); | |
2414 | unmask_IO_APIC_irq(irq); | |
2415 | } | |
1d025192 | 2416 | |
3eb2cce8 | 2417 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2418 | if (!(v & (1 << (i & 0x1f)))) { |
2419 | atomic_inc(&irq_mis_count); | |
2420 | spin_lock(&ioapic_lock); | |
2421 | __mask_and_edge_IO_APIC_irq(irq); | |
2422 | __unmask_and_level_IO_APIC_irq(irq); | |
2423 | spin_unlock(&ioapic_lock); | |
2424 | } | |
047c8fdb | 2425 | #endif |
3eb2cce8 | 2426 | } |
1d025192 | 2427 | |
f5b9ed7a IM |
2428 | static struct irq_chip ioapic_chip __read_mostly = { |
2429 | .name = "IO-APIC", | |
ace80ab7 EB |
2430 | .startup = startup_ioapic_irq, |
2431 | .mask = mask_IO_APIC_irq, | |
2432 | .unmask = unmask_IO_APIC_irq, | |
1d025192 YL |
2433 | .ack = ack_apic_edge, |
2434 | .eoi = ack_apic_level, | |
54d5d424 | 2435 | #ifdef CONFIG_SMP |
ace80ab7 | 2436 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2437 | #endif |
ace80ab7 | 2438 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2439 | }; |
2440 | ||
54168ed7 IM |
2441 | #ifdef CONFIG_INTR_REMAP |
2442 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
2443 | .name = "IR-IO-APIC", | |
2444 | .startup = startup_ioapic_irq, | |
2445 | .mask = mask_IO_APIC_irq, | |
2446 | .unmask = unmask_IO_APIC_irq, | |
2447 | .ack = ack_x2apic_edge, | |
2448 | .eoi = ack_x2apic_level, | |
2449 | #ifdef CONFIG_SMP | |
2450 | .set_affinity = set_ir_ioapic_affinity_irq, | |
2451 | #endif | |
2452 | .retrigger = ioapic_retrigger_irq, | |
2453 | }; | |
2454 | #endif | |
1da177e4 LT |
2455 | |
2456 | static inline void init_IO_APIC_traps(void) | |
2457 | { | |
2458 | int irq; | |
08678b08 | 2459 | struct irq_desc *desc; |
da51a821 | 2460 | struct irq_cfg *cfg; |
1da177e4 LT |
2461 | |
2462 | /* | |
2463 | * NOTE! The local APIC isn't very good at handling | |
2464 | * multiple interrupts at the same interrupt level. | |
2465 | * As the interrupt level is determined by taking the | |
2466 | * vector number and shifting that right by 4, we | |
2467 | * want to spread these out a bit so that they don't | |
2468 | * all fall in the same interrupt level. | |
2469 | * | |
2470 | * Also, we've got to be careful not to trash gate | |
2471 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2472 | */ | |
8f09cd20 | 2473 | for_each_irq_cfg(irq, cfg) { |
da51a821 | 2474 | if (IO_APIC_IRQ(irq) && !cfg->vector) { |
1da177e4 LT |
2475 | /* |
2476 | * Hmm.. We don't have an entry for this, | |
2477 | * so default to an old-fashioned 8259 | |
2478 | * interrupt if we can.. | |
2479 | */ | |
2480 | if (irq < 16) | |
2481 | make_8259A_irq(irq); | |
08678b08 YL |
2482 | else { |
2483 | desc = irq_to_desc(irq); | |
1da177e4 | 2484 | /* Strange. Oh, well.. */ |
08678b08 YL |
2485 | desc->chip = &no_irq_chip; |
2486 | } | |
1da177e4 LT |
2487 | } |
2488 | } | |
2489 | } | |
2490 | ||
f5b9ed7a IM |
2491 | /* |
2492 | * The local APIC irq-chip implementation: | |
2493 | */ | |
1da177e4 | 2494 | |
36062448 | 2495 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2496 | { |
2497 | unsigned long v; | |
2498 | ||
2499 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2500 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2501 | } |
2502 | ||
36062448 | 2503 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2504 | { |
f5b9ed7a | 2505 | unsigned long v; |
1da177e4 | 2506 | |
f5b9ed7a | 2507 | v = apic_read(APIC_LVT0); |
593f4a78 | 2508 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2509 | } |
1da177e4 | 2510 | |
54168ed7 | 2511 | static void ack_lapic_irq (unsigned int irq) |
1d025192 YL |
2512 | { |
2513 | ack_APIC_irq(); | |
2514 | } | |
2515 | ||
f5b9ed7a | 2516 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2517 | .name = "local-APIC", |
f5b9ed7a IM |
2518 | .mask = mask_lapic_irq, |
2519 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2520 | .ack = ack_lapic_irq, |
1da177e4 LT |
2521 | }; |
2522 | ||
497c9a19 | 2523 | static void lapic_register_intr(int irq) |
c88ac1df | 2524 | { |
08678b08 YL |
2525 | struct irq_desc *desc; |
2526 | ||
2527 | desc = irq_to_desc(irq); | |
2528 | desc->status &= ~IRQ_LEVEL; | |
c88ac1df MR |
2529 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2530 | "edge"); | |
c88ac1df MR |
2531 | } |
2532 | ||
e9427101 | 2533 | static void __init setup_nmi(void) |
1da177e4 LT |
2534 | { |
2535 | /* | |
36062448 | 2536 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2537 | * We put the 8259A master into AEOI mode and |
2538 | * unmask on all local APICs LVT0 as NMI. | |
2539 | * | |
2540 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2541 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2542 | * the NMI handler or the timer interrupt. | |
36062448 | 2543 | */ |
1da177e4 LT |
2544 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2545 | ||
e9427101 | 2546 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2547 | |
2548 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2549 | } | |
2550 | ||
2551 | /* | |
2552 | * This looks a bit hackish but it's about the only one way of sending | |
2553 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2554 | * not support the ExtINT mode, unfortunately. We need to send these | |
2555 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2556 | * 8259A interrupt line asserted until INTA. --macro | |
2557 | */ | |
28acf285 | 2558 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2559 | { |
fcfd636a | 2560 | int apic, pin, i; |
1da177e4 LT |
2561 | struct IO_APIC_route_entry entry0, entry1; |
2562 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2563 | |
fcfd636a | 2564 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2565 | if (pin == -1) { |
2566 | WARN_ON_ONCE(1); | |
2567 | return; | |
2568 | } | |
fcfd636a | 2569 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2570 | if (apic == -1) { |
2571 | WARN_ON_ONCE(1); | |
1da177e4 | 2572 | return; |
956fb531 | 2573 | } |
1da177e4 | 2574 | |
cf4c6a2f | 2575 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2576 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2577 | |
2578 | memset(&entry1, 0, sizeof(entry1)); | |
2579 | ||
2580 | entry1.dest_mode = 0; /* physical delivery */ | |
2581 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2582 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2583 | entry1.delivery_mode = dest_ExtINT; |
2584 | entry1.polarity = entry0.polarity; | |
2585 | entry1.trigger = 0; | |
2586 | entry1.vector = 0; | |
2587 | ||
cf4c6a2f | 2588 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2589 | |
2590 | save_control = CMOS_READ(RTC_CONTROL); | |
2591 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2592 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2593 | RTC_FREQ_SELECT); | |
2594 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2595 | ||
2596 | i = 100; | |
2597 | while (i-- > 0) { | |
2598 | mdelay(10); | |
2599 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2600 | i -= 10; | |
2601 | } | |
2602 | ||
2603 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2604 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2605 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2606 | |
cf4c6a2f | 2607 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2608 | } |
2609 | ||
efa2559f | 2610 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2611 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2612 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2613 | { |
2614 | disable_timer_pin_1 = 1; | |
2615 | return 0; | |
2616 | } | |
54168ed7 | 2617 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2618 | |
2619 | int timer_through_8259 __initdata; | |
2620 | ||
1da177e4 LT |
2621 | /* |
2622 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2623 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2624 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2625 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2626 | * |
2627 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2628 | */ |
8542b200 | 2629 | static inline void __init check_timer(void) |
1da177e4 | 2630 | { |
497c9a19 | 2631 | struct irq_cfg *cfg = irq_cfg(0); |
fcfd636a | 2632 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2633 | unsigned long flags; |
047c8fdb YL |
2634 | unsigned int ver; |
2635 | int no_pin1 = 0; | |
4aae0702 IM |
2636 | |
2637 | local_irq_save(flags); | |
d4d25dec | 2638 | |
54168ed7 IM |
2639 | ver = apic_read(APIC_LVR); |
2640 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2641 | |
1da177e4 LT |
2642 | /* |
2643 | * get/set the timer IRQ vector: | |
2644 | */ | |
2645 | disable_8259A_irq(0); | |
497c9a19 | 2646 | assign_irq_vector(0, TARGET_CPUS); |
1da177e4 LT |
2647 | |
2648 | /* | |
d11d5794 MR |
2649 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2650 | * wire has to be disabled in the local APIC. Also | |
2651 | * timer interrupts need to be acknowledged manually in | |
2652 | * the 8259A for the i82489DX when using the NMI | |
2653 | * watchdog as that APIC treats NMIs as level-triggered. | |
2654 | * The AEOI mode will finish them in the 8259A | |
2655 | * automatically. | |
1da177e4 | 2656 | */ |
593f4a78 | 2657 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2658 | init_8259A(1); |
54168ed7 | 2659 | #ifdef CONFIG_X86_32 |
d11d5794 | 2660 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2661 | #endif |
1da177e4 | 2662 | |
fcfd636a EB |
2663 | pin1 = find_isa_irq_pin(0, mp_INT); |
2664 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2665 | pin2 = ioapic_i8259.pin; | |
2666 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2667 | |
49a66a0b MR |
2668 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2669 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2670 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2671 | |
691874fa MR |
2672 | /* |
2673 | * Some BIOS writers are clueless and report the ExtINTA | |
2674 | * I/O APIC input from the cascaded 8259A as the timer | |
2675 | * interrupt input. So just in case, if only one pin | |
2676 | * was found above, try it both directly and through the | |
2677 | * 8259A. | |
2678 | */ | |
2679 | if (pin1 == -1) { | |
54168ed7 IM |
2680 | #ifdef CONFIG_INTR_REMAP |
2681 | if (intr_remapping_enabled) | |
2682 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2683 | #endif | |
691874fa MR |
2684 | pin1 = pin2; |
2685 | apic1 = apic2; | |
2686 | no_pin1 = 1; | |
2687 | } else if (pin2 == -1) { | |
2688 | pin2 = pin1; | |
2689 | apic2 = apic1; | |
2690 | } | |
2691 | ||
1da177e4 LT |
2692 | if (pin1 != -1) { |
2693 | /* | |
2694 | * Ok, does IRQ0 through the IOAPIC work? | |
2695 | */ | |
691874fa MR |
2696 | if (no_pin1) { |
2697 | add_pin_to_irq(0, apic1, pin1); | |
497c9a19 | 2698 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2699 | } |
1da177e4 LT |
2700 | unmask_IO_APIC_irq(0); |
2701 | if (timer_irq_works()) { | |
2702 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2703 | setup_nmi(); |
2704 | enable_8259A_irq(0); | |
1da177e4 | 2705 | } |
66759a01 CE |
2706 | if (disable_timer_pin_1 > 0) |
2707 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2708 | goto out; |
1da177e4 | 2709 | } |
54168ed7 IM |
2710 | #ifdef CONFIG_INTR_REMAP |
2711 | if (intr_remapping_enabled) | |
2712 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2713 | #endif | |
fcfd636a | 2714 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2715 | if (!no_pin1) |
49a66a0b MR |
2716 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2717 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2718 | |
49a66a0b MR |
2719 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2720 | "(IRQ0) through the 8259A ...\n"); | |
2721 | apic_printk(APIC_QUIET, KERN_INFO | |
2722 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2723 | /* |
2724 | * legacy devices should be connected to IO APIC #0 | |
2725 | */ | |
691874fa | 2726 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
497c9a19 | 2727 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
24742ece | 2728 | unmask_IO_APIC_irq(0); |
ecd29476 | 2729 | enable_8259A_irq(0); |
1da177e4 | 2730 | if (timer_irq_works()) { |
49a66a0b | 2731 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2732 | timer_through_8259 = 1; |
1da177e4 | 2733 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2734 | disable_8259A_irq(0); |
1da177e4 | 2735 | setup_nmi(); |
60134ebe | 2736 | enable_8259A_irq(0); |
1da177e4 | 2737 | } |
4aae0702 | 2738 | goto out; |
1da177e4 LT |
2739 | } |
2740 | /* | |
2741 | * Cleanup, just in case ... | |
2742 | */ | |
ecd29476 | 2743 | disable_8259A_irq(0); |
fcfd636a | 2744 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2745 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2746 | } |
1da177e4 LT |
2747 | |
2748 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2749 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2750 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2751 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2752 | } |
54168ed7 | 2753 | #ifdef CONFIG_X86_32 |
d11d5794 | 2754 | timer_ack = 0; |
54168ed7 | 2755 | #endif |
1da177e4 | 2756 | |
49a66a0b MR |
2757 | apic_printk(APIC_QUIET, KERN_INFO |
2758 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2759 | |
497c9a19 YL |
2760 | lapic_register_intr(0); |
2761 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ | |
1da177e4 LT |
2762 | enable_8259A_irq(0); |
2763 | ||
2764 | if (timer_irq_works()) { | |
49a66a0b | 2765 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2766 | goto out; |
1da177e4 | 2767 | } |
e67465f1 | 2768 | disable_8259A_irq(0); |
497c9a19 | 2769 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2770 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2771 | |
49a66a0b MR |
2772 | apic_printk(APIC_QUIET, KERN_INFO |
2773 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2774 | |
1da177e4 LT |
2775 | init_8259A(0); |
2776 | make_8259A_irq(0); | |
593f4a78 | 2777 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2778 | |
2779 | unlock_ExtINT_logic(); | |
2780 | ||
2781 | if (timer_irq_works()) { | |
49a66a0b | 2782 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2783 | goto out; |
1da177e4 | 2784 | } |
49a66a0b | 2785 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2786 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2787 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2788 | out: |
2789 | local_irq_restore(flags); | |
1da177e4 LT |
2790 | } |
2791 | ||
2792 | /* | |
af174783 MR |
2793 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2794 | * to devices. However there may be an I/O APIC pin available for | |
2795 | * this interrupt regardless. The pin may be left unconnected, but | |
2796 | * typically it will be reused as an ExtINT cascade interrupt for | |
2797 | * the master 8259A. In the MPS case such a pin will normally be | |
2798 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2799 | * there is no provision for ExtINT interrupts, and in the absence | |
2800 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2801 | * interrupt, that is edge-triggered and unmasked by default. We | |
2802 | * used to do this, but it caused problems on some systems because | |
2803 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2804 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2805 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2806 | * the I/O APIC in all cases now. No actual device should request | |
2807 | * it anyway. --macro | |
1da177e4 LT |
2808 | */ |
2809 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2810 | ||
2811 | void __init setup_IO_APIC(void) | |
2812 | { | |
54168ed7 IM |
2813 | |
2814 | #ifdef CONFIG_X86_32 | |
1da177e4 | 2815 | enable_IO_APIC(); |
54168ed7 IM |
2816 | #else |
2817 | /* | |
2818 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2819 | */ | |
2820 | #endif | |
1da177e4 | 2821 | |
af174783 | 2822 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 2823 | |
54168ed7 IM |
2824 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
2825 | /* | |
2826 | * Set up IO-APIC IRQ routing. | |
2827 | */ | |
2828 | #ifdef CONFIG_X86_32 | |
2829 | if (!acpi_ioapic) | |
2830 | setup_ioapic_ids_from_mpc(); | |
2831 | #endif | |
1da177e4 LT |
2832 | sync_Arb_IDs(); |
2833 | setup_IO_APIC_irqs(); | |
2834 | init_IO_APIC_traps(); | |
1e4c85f9 | 2835 | check_timer(); |
1da177e4 LT |
2836 | } |
2837 | ||
2838 | /* | |
54168ed7 IM |
2839 | * Called after all the initialization is done. If we didnt find any |
2840 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 2841 | */ |
36062448 | 2842 | |
1da177e4 LT |
2843 | static int __init io_apic_bug_finalize(void) |
2844 | { | |
54168ed7 IM |
2845 | if (sis_apic_bug == -1) |
2846 | sis_apic_bug = 0; | |
2847 | return 0; | |
1da177e4 LT |
2848 | } |
2849 | ||
2850 | late_initcall(io_apic_bug_finalize); | |
2851 | ||
2852 | struct sysfs_ioapic_data { | |
2853 | struct sys_device dev; | |
2854 | struct IO_APIC_route_entry entry[0]; | |
2855 | }; | |
54168ed7 | 2856 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2857 | |
438510f6 | 2858 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2859 | { |
2860 | struct IO_APIC_route_entry *entry; | |
2861 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2862 | int i; |
36062448 | 2863 | |
1da177e4 LT |
2864 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2865 | entry = data->entry; | |
54168ed7 IM |
2866 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
2867 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2868 | |
2869 | return 0; | |
2870 | } | |
2871 | ||
2872 | static int ioapic_resume(struct sys_device *dev) | |
2873 | { | |
2874 | struct IO_APIC_route_entry *entry; | |
2875 | struct sysfs_ioapic_data *data; | |
2876 | unsigned long flags; | |
2877 | union IO_APIC_reg_00 reg_00; | |
2878 | int i; | |
36062448 | 2879 | |
1da177e4 LT |
2880 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2881 | entry = data->entry; | |
2882 | ||
2883 | spin_lock_irqsave(&ioapic_lock, flags); | |
2884 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2885 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2886 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2887 | io_apic_write(dev->id, 0, reg_00.raw); |
2888 | } | |
1da177e4 | 2889 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2890 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2891 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2892 | |
2893 | return 0; | |
2894 | } | |
2895 | ||
2896 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2897 | .name = "ioapic", |
1da177e4 LT |
2898 | .suspend = ioapic_suspend, |
2899 | .resume = ioapic_resume, | |
2900 | }; | |
2901 | ||
2902 | static int __init ioapic_init_sysfs(void) | |
2903 | { | |
54168ed7 IM |
2904 | struct sys_device * dev; |
2905 | int i, size, error; | |
1da177e4 LT |
2906 | |
2907 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2908 | if (error) | |
2909 | return error; | |
2910 | ||
54168ed7 | 2911 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 2912 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 2913 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2914 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2915 | if (!mp_ioapic_data[i]) { |
2916 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2917 | continue; | |
2918 | } | |
1da177e4 | 2919 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2920 | dev->id = i; |
1da177e4 LT |
2921 | dev->cls = &ioapic_sysdev_class; |
2922 | error = sysdev_register(dev); | |
2923 | if (error) { | |
2924 | kfree(mp_ioapic_data[i]); | |
2925 | mp_ioapic_data[i] = NULL; | |
2926 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2927 | continue; | |
2928 | } | |
2929 | } | |
2930 | ||
2931 | return 0; | |
2932 | } | |
2933 | ||
2934 | device_initcall(ioapic_init_sysfs); | |
2935 | ||
3fc471ed | 2936 | /* |
95d77884 | 2937 | * Dynamic irq allocate and deallocation |
3fc471ed | 2938 | */ |
199751d7 | 2939 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 2940 | { |
ace80ab7 | 2941 | /* Allocate an unused irq */ |
54168ed7 IM |
2942 | unsigned int irq; |
2943 | unsigned int new; | |
3fc471ed | 2944 | unsigned long flags; |
da51a821 | 2945 | struct irq_cfg *cfg_new; |
3fc471ed | 2946 | |
199751d7 YL |
2947 | irq_want = nr_irqs - 1; |
2948 | ||
2949 | irq = 0; | |
ace80ab7 | 2950 | spin_lock_irqsave(&vector_lock, flags); |
54168ed7 | 2951 | for (new = irq_want; new > 0; new--) { |
ace80ab7 EB |
2952 | if (platform_legacy_irq(new)) |
2953 | continue; | |
da51a821 YL |
2954 | cfg_new = irq_cfg(new); |
2955 | if (cfg_new && cfg_new->vector != 0) | |
ace80ab7 | 2956 | continue; |
047c8fdb | 2957 | /* check if need to create one */ |
da51a821 YL |
2958 | if (!cfg_new) |
2959 | cfg_new = irq_cfg_alloc(new); | |
497c9a19 | 2960 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
ace80ab7 EB |
2961 | irq = new; |
2962 | break; | |
2963 | } | |
2964 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2965 | |
199751d7 | 2966 | if (irq > 0) { |
3fc471ed EB |
2967 | dynamic_irq_init(irq); |
2968 | } | |
2969 | return irq; | |
2970 | } | |
2971 | ||
199751d7 YL |
2972 | int create_irq(void) |
2973 | { | |
54168ed7 IM |
2974 | int irq; |
2975 | ||
2976 | irq = create_irq_nr(nr_irqs - 1); | |
2977 | ||
2978 | if (irq == 0) | |
2979 | irq = -1; | |
2980 | ||
2981 | return irq; | |
199751d7 YL |
2982 | } |
2983 | ||
3fc471ed EB |
2984 | void destroy_irq(unsigned int irq) |
2985 | { | |
2986 | unsigned long flags; | |
3fc471ed EB |
2987 | |
2988 | dynamic_irq_cleanup(irq); | |
2989 | ||
54168ed7 IM |
2990 | #ifdef CONFIG_INTR_REMAP |
2991 | free_irte(irq); | |
2992 | #endif | |
3fc471ed | 2993 | spin_lock_irqsave(&vector_lock, flags); |
497c9a19 | 2994 | __clear_irq_vector(irq); |
3fc471ed EB |
2995 | spin_unlock_irqrestore(&vector_lock, flags); |
2996 | } | |
3fc471ed | 2997 | |
2d3fcc1c | 2998 | /* |
27b46d76 | 2999 | * MSI message composition |
2d3fcc1c EB |
3000 | */ |
3001 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3002 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3003 | { |
497c9a19 YL |
3004 | struct irq_cfg *cfg; |
3005 | int err; | |
2d3fcc1c | 3006 | unsigned dest; |
497c9a19 | 3007 | cpumask_t tmp; |
2d3fcc1c | 3008 | |
497c9a19 YL |
3009 | tmp = TARGET_CPUS; |
3010 | err = assign_irq_vector(irq, tmp); | |
3011 | if (err) | |
3012 | return err; | |
2d3fcc1c | 3013 | |
497c9a19 YL |
3014 | cfg = irq_cfg(irq); |
3015 | cpus_and(tmp, cfg->domain, tmp); | |
3016 | dest = cpu_mask_to_apicid(tmp); | |
3017 | ||
54168ed7 IM |
3018 | #ifdef CONFIG_INTR_REMAP |
3019 | if (irq_remapped(irq)) { | |
3020 | struct irte irte; | |
3021 | int ir_index; | |
3022 | u16 sub_handle; | |
3023 | ||
3024 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3025 | BUG_ON(ir_index == -1); | |
3026 | ||
3027 | memset (&irte, 0, sizeof(irte)); | |
3028 | ||
3029 | irte.present = 1; | |
3030 | irte.dst_mode = INT_DEST_MODE; | |
3031 | irte.trigger_mode = 0; /* edge */ | |
3032 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
3033 | irte.vector = cfg->vector; | |
3034 | irte.dest_id = IRTE_DEST(dest); | |
3035 | ||
3036 | modify_irte(irq, &irte); | |
3037 | ||
3038 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3039 | msg->data = sub_handle; | |
3040 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3041 | MSI_ADDR_IR_SHV | | |
3042 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3043 | MSI_ADDR_IR_INDEX2(ir_index); | |
3044 | } else | |
3045 | #endif | |
3046 | { | |
3047 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3048 | msg->address_lo = | |
3049 | MSI_ADDR_BASE_LO | | |
3050 | ((INT_DEST_MODE == 0) ? | |
3051 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3052 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3053 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3054 | MSI_ADDR_REDIRECTION_CPU: | |
3055 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3056 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3057 | |
54168ed7 IM |
3058 | msg->data = |
3059 | MSI_DATA_TRIGGER_EDGE | | |
3060 | MSI_DATA_LEVEL_ASSERT | | |
3061 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3062 | MSI_DATA_DELIVERY_FIXED: | |
3063 | MSI_DATA_DELIVERY_LOWPRI) | | |
3064 | MSI_DATA_VECTOR(cfg->vector); | |
3065 | } | |
497c9a19 | 3066 | return err; |
2d3fcc1c EB |
3067 | } |
3068 | ||
3b7d1921 EB |
3069 | #ifdef CONFIG_SMP |
3070 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 3071 | { |
497c9a19 | 3072 | struct irq_cfg *cfg; |
3b7d1921 EB |
3073 | struct msi_msg msg; |
3074 | unsigned int dest; | |
3075 | cpumask_t tmp; | |
54168ed7 | 3076 | struct irq_desc *desc; |
3b7d1921 EB |
3077 | |
3078 | cpus_and(tmp, mask, cpu_online_map); | |
3079 | if (cpus_empty(tmp)) | |
497c9a19 | 3080 | return; |
2d3fcc1c | 3081 | |
497c9a19 | 3082 | if (assign_irq_vector(irq, mask)) |
3b7d1921 | 3083 | return; |
2d3fcc1c | 3084 | |
497c9a19 YL |
3085 | cfg = irq_cfg(irq); |
3086 | cpus_and(tmp, cfg->domain, mask); | |
3087 | dest = cpu_mask_to_apicid(tmp); | |
3b7d1921 EB |
3088 | |
3089 | read_msi_msg(irq, &msg); | |
3090 | ||
3091 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3092 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3093 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3094 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3095 | ||
3096 | write_msi_msg(irq, &msg); | |
54168ed7 IM |
3097 | desc = irq_to_desc(irq); |
3098 | desc->affinity = mask; | |
2d3fcc1c | 3099 | } |
54168ed7 IM |
3100 | |
3101 | #ifdef CONFIG_INTR_REMAP | |
3102 | /* | |
3103 | * Migrate the MSI irq to another cpumask. This migration is | |
3104 | * done in the process context using interrupt-remapping hardware. | |
3105 | */ | |
3106 | static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
3107 | { | |
3108 | struct irq_cfg *cfg; | |
3109 | unsigned int dest; | |
3110 | cpumask_t tmp, cleanup_mask; | |
3111 | struct irte irte; | |
3112 | struct irq_desc *desc; | |
3113 | ||
3114 | cpus_and(tmp, mask, cpu_online_map); | |
3115 | if (cpus_empty(tmp)) | |
3116 | return; | |
3117 | ||
3118 | if (get_irte(irq, &irte)) | |
3119 | return; | |
3120 | ||
3121 | if (assign_irq_vector(irq, mask)) | |
3122 | return; | |
3123 | ||
3124 | cfg = irq_cfg(irq); | |
3125 | cpus_and(tmp, cfg->domain, mask); | |
3126 | dest = cpu_mask_to_apicid(tmp); | |
3127 | ||
3128 | irte.vector = cfg->vector; | |
3129 | irte.dest_id = IRTE_DEST(dest); | |
3130 | ||
3131 | /* | |
3132 | * atomically update the IRTE with the new destination and vector. | |
3133 | */ | |
3134 | modify_irte(irq, &irte); | |
3135 | ||
3136 | /* | |
3137 | * After this point, all the interrupts will start arriving | |
3138 | * at the new destination. So, time to cleanup the previous | |
3139 | * vector allocation. | |
3140 | */ | |
3141 | if (cfg->move_in_progress) { | |
3142 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
3143 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
3144 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
3145 | cfg->move_in_progress = 0; | |
3146 | } | |
3147 | ||
3148 | desc = irq_to_desc(irq); | |
3149 | desc->affinity = mask; | |
3150 | } | |
3151 | #endif | |
3b7d1921 | 3152 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3153 | |
3b7d1921 EB |
3154 | /* |
3155 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3156 | * which implement the MSI or MSI-X Capability Structure. | |
3157 | */ | |
3158 | static struct irq_chip msi_chip = { | |
3159 | .name = "PCI-MSI", | |
3160 | .unmask = unmask_msi_irq, | |
3161 | .mask = mask_msi_irq, | |
1d025192 | 3162 | .ack = ack_apic_edge, |
3b7d1921 EB |
3163 | #ifdef CONFIG_SMP |
3164 | .set_affinity = set_msi_irq_affinity, | |
3165 | #endif | |
3166 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3167 | }; |
3168 | ||
54168ed7 IM |
3169 | #ifdef CONFIG_INTR_REMAP |
3170 | static struct irq_chip msi_ir_chip = { | |
3171 | .name = "IR-PCI-MSI", | |
3172 | .unmask = unmask_msi_irq, | |
3173 | .mask = mask_msi_irq, | |
3174 | .ack = ack_x2apic_edge, | |
3175 | #ifdef CONFIG_SMP | |
3176 | .set_affinity = ir_set_msi_irq_affinity, | |
3177 | #endif | |
3178 | .retrigger = ioapic_retrigger_irq, | |
3179 | }; | |
3180 | ||
3181 | /* | |
3182 | * Map the PCI dev to the corresponding remapping hardware unit | |
3183 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3184 | * in it. | |
3185 | */ | |
3186 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3187 | { | |
3188 | struct intel_iommu *iommu; | |
3189 | int index; | |
3190 | ||
3191 | iommu = map_dev_to_ir(dev); | |
3192 | if (!iommu) { | |
3193 | printk(KERN_ERR | |
3194 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3195 | return -ENOENT; | |
3196 | } | |
3197 | ||
3198 | index = alloc_irte(iommu, irq, nvec); | |
3199 | if (index < 0) { | |
3200 | printk(KERN_ERR | |
3201 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
3202 | pci_name(dev)); | |
3203 | return -ENOSPC; | |
3204 | } | |
3205 | return index; | |
3206 | } | |
3207 | #endif | |
1d025192 YL |
3208 | |
3209 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq) | |
3210 | { | |
3211 | int ret; | |
3212 | struct msi_msg msg; | |
3213 | ||
3214 | ret = msi_compose_msg(dev, irq, &msg); | |
3215 | if (ret < 0) | |
3216 | return ret; | |
3217 | ||
3218 | set_irq_msi(irq, desc); | |
3219 | write_msi_msg(irq, &msg); | |
3220 | ||
54168ed7 IM |
3221 | #ifdef CONFIG_INTR_REMAP |
3222 | if (irq_remapped(irq)) { | |
3223 | struct irq_desc *desc = irq_to_desc(irq); | |
3224 | /* | |
3225 | * irq migration in process context | |
3226 | */ | |
3227 | desc->status |= IRQ_MOVE_PCNTXT; | |
3228 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3229 | } else | |
3230 | #endif | |
3231 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 | 3232 | |
c81bba49 YL |
3233 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3234 | ||
1d025192 YL |
3235 | return 0; |
3236 | } | |
3237 | ||
199751d7 YL |
3238 | static unsigned int build_irq_for_pci_dev(struct pci_dev *dev) |
3239 | { | |
3240 | unsigned int irq; | |
3241 | ||
3242 | irq = dev->bus->number; | |
3243 | irq <<= 8; | |
3244 | irq |= dev->devfn; | |
3245 | irq <<= 12; | |
3246 | ||
3247 | return irq; | |
3248 | } | |
3249 | ||
f7feaca7 | 3250 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 | 3251 | { |
54168ed7 IM |
3252 | unsigned int irq; |
3253 | int ret; | |
199751d7 YL |
3254 | unsigned int irq_want; |
3255 | ||
3256 | irq_want = build_irq_for_pci_dev(dev) + 0x100; | |
3257 | ||
3258 | irq = create_irq_nr(irq_want); | |
199751d7 YL |
3259 | if (irq == 0) |
3260 | return -1; | |
f7feaca7 | 3261 | |
54168ed7 IM |
3262 | #ifdef CONFIG_INTR_REMAP |
3263 | if (!intr_remapping_enabled) | |
3264 | goto no_ir; | |
3265 | ||
3266 | ret = msi_alloc_irte(dev, irq, 1); | |
3267 | if (ret < 0) | |
3268 | goto error; | |
3269 | no_ir: | |
3270 | #endif | |
1d025192 | 3271 | ret = setup_msi_irq(dev, desc, irq); |
f7feaca7 EB |
3272 | if (ret < 0) { |
3273 | destroy_irq(irq); | |
3b7d1921 | 3274 | return ret; |
54168ed7 | 3275 | } |
7fe3730d | 3276 | return 0; |
54168ed7 IM |
3277 | |
3278 | #ifdef CONFIG_INTR_REMAP | |
3279 | error: | |
3280 | destroy_irq(irq); | |
3281 | return ret; | |
3282 | #endif | |
3b7d1921 EB |
3283 | } |
3284 | ||
047c8fdb YL |
3285 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3286 | { | |
54168ed7 IM |
3287 | unsigned int irq; |
3288 | int ret, sub_handle; | |
3289 | struct msi_desc *desc; | |
3290 | unsigned int irq_want; | |
3291 | ||
3292 | #ifdef CONFIG_INTR_REMAP | |
3293 | struct intel_iommu *iommu = 0; | |
3294 | int index = 0; | |
3295 | #endif | |
3296 | ||
3297 | irq_want = build_irq_for_pci_dev(dev) + 0x100; | |
3298 | sub_handle = 0; | |
3299 | list_for_each_entry(desc, &dev->msi_list, list) { | |
3300 | irq = create_irq_nr(irq_want--); | |
3301 | if (irq == 0) | |
3302 | return -1; | |
3303 | #ifdef CONFIG_INTR_REMAP | |
3304 | if (!intr_remapping_enabled) | |
3305 | goto no_ir; | |
3306 | ||
3307 | if (!sub_handle) { | |
3308 | /* | |
3309 | * allocate the consecutive block of IRTE's | |
3310 | * for 'nvec' | |
3311 | */ | |
3312 | index = msi_alloc_irte(dev, irq, nvec); | |
3313 | if (index < 0) { | |
3314 | ret = index; | |
3315 | goto error; | |
3316 | } | |
3317 | } else { | |
3318 | iommu = map_dev_to_ir(dev); | |
3319 | if (!iommu) { | |
3320 | ret = -ENOENT; | |
3321 | goto error; | |
3322 | } | |
3323 | /* | |
3324 | * setup the mapping between the irq and the IRTE | |
3325 | * base index, the sub_handle pointing to the | |
3326 | * appropriate interrupt remap table entry. | |
3327 | */ | |
3328 | set_irte_irq(irq, iommu, index, sub_handle); | |
3329 | } | |
3330 | no_ir: | |
3331 | #endif | |
3332 | ret = setup_msi_irq(dev, desc, irq); | |
3333 | if (ret < 0) | |
3334 | goto error; | |
3335 | sub_handle++; | |
3336 | } | |
3337 | return 0; | |
047c8fdb YL |
3338 | |
3339 | error: | |
54168ed7 IM |
3340 | destroy_irq(irq); |
3341 | return ret; | |
047c8fdb YL |
3342 | } |
3343 | ||
3b7d1921 EB |
3344 | void arch_teardown_msi_irq(unsigned int irq) |
3345 | { | |
f7feaca7 | 3346 | destroy_irq(irq); |
3b7d1921 EB |
3347 | } |
3348 | ||
54168ed7 IM |
3349 | #ifdef CONFIG_DMAR |
3350 | #ifdef CONFIG_SMP | |
3351 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
3352 | { | |
3353 | struct irq_cfg *cfg; | |
3354 | struct msi_msg msg; | |
3355 | unsigned int dest; | |
3356 | cpumask_t tmp; | |
3357 | struct irq_desc *desc; | |
3358 | ||
3359 | cpus_and(tmp, mask, cpu_online_map); | |
3360 | if (cpus_empty(tmp)) | |
3361 | return; | |
3362 | ||
3363 | if (assign_irq_vector(irq, mask)) | |
3364 | return; | |
3365 | ||
3366 | cfg = irq_cfg(irq); | |
3367 | cpus_and(tmp, cfg->domain, mask); | |
3368 | dest = cpu_mask_to_apicid(tmp); | |
3369 | ||
3370 | dmar_msi_read(irq, &msg); | |
3371 | ||
3372 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3373 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3374 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3375 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3376 | ||
3377 | dmar_msi_write(irq, &msg); | |
3378 | desc = irq_to_desc(irq); | |
3379 | desc->affinity = mask; | |
3380 | } | |
3381 | #endif /* CONFIG_SMP */ | |
3382 | ||
3383 | struct irq_chip dmar_msi_type = { | |
3384 | .name = "DMAR_MSI", | |
3385 | .unmask = dmar_msi_unmask, | |
3386 | .mask = dmar_msi_mask, | |
3387 | .ack = ack_apic_edge, | |
3388 | #ifdef CONFIG_SMP | |
3389 | .set_affinity = dmar_msi_set_affinity, | |
3390 | #endif | |
3391 | .retrigger = ioapic_retrigger_irq, | |
3392 | }; | |
3393 | ||
3394 | int arch_setup_dmar_msi(unsigned int irq) | |
3395 | { | |
3396 | int ret; | |
3397 | struct msi_msg msg; | |
2d3fcc1c | 3398 | |
54168ed7 IM |
3399 | ret = msi_compose_msg(NULL, irq, &msg); |
3400 | if (ret < 0) | |
3401 | return ret; | |
3402 | dmar_msi_write(irq, &msg); | |
3403 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3404 | "edge"); | |
3405 | return 0; | |
3406 | } | |
3407 | #endif | |
3408 | ||
58ac1e76 | 3409 | #ifdef CONFIG_HPET_TIMER |
3410 | ||
3411 | #ifdef CONFIG_SMP | |
3412 | static void hpet_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
3413 | { | |
3414 | struct irq_cfg *cfg; | |
3415 | struct irq_desc *desc; | |
3416 | struct msi_msg msg; | |
3417 | unsigned int dest; | |
3418 | cpumask_t tmp; | |
3419 | ||
3420 | cpus_and(tmp, mask, cpu_online_map); | |
3421 | if (cpus_empty(tmp)) | |
3422 | return; | |
3423 | ||
3424 | if (assign_irq_vector(irq, mask)) | |
3425 | return; | |
3426 | ||
3427 | cfg = irq_cfg(irq); | |
3428 | cpus_and(tmp, cfg->domain, mask); | |
3429 | dest = cpu_mask_to_apicid(tmp); | |
3430 | ||
3431 | hpet_msi_read(irq, &msg); | |
3432 | ||
3433 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3434 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3435 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3436 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3437 | ||
3438 | hpet_msi_write(irq, &msg); | |
3439 | desc = irq_to_desc(irq); | |
3440 | desc->affinity = mask; | |
3441 | } | |
3442 | #endif /* CONFIG_SMP */ | |
3443 | ||
3444 | struct irq_chip hpet_msi_type = { | |
3445 | .name = "HPET_MSI", | |
3446 | .unmask = hpet_msi_unmask, | |
3447 | .mask = hpet_msi_mask, | |
3448 | .ack = ack_apic_edge, | |
3449 | #ifdef CONFIG_SMP | |
3450 | .set_affinity = hpet_msi_set_affinity, | |
3451 | #endif | |
3452 | .retrigger = ioapic_retrigger_irq, | |
3453 | }; | |
3454 | ||
3455 | int arch_setup_hpet_msi(unsigned int irq) | |
3456 | { | |
3457 | int ret; | |
3458 | struct msi_msg msg; | |
3459 | ||
3460 | ret = msi_compose_msg(NULL, irq, &msg); | |
3461 | if (ret < 0) | |
3462 | return ret; | |
3463 | ||
3464 | hpet_msi_write(irq, &msg); | |
3465 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3466 | "edge"); | |
c81bba49 | 3467 | |
58ac1e76 | 3468 | return 0; |
3469 | } | |
3470 | #endif | |
3471 | ||
54168ed7 | 3472 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3473 | /* |
3474 | * Hypertransport interrupt support | |
3475 | */ | |
3476 | #ifdef CONFIG_HT_IRQ | |
3477 | ||
3478 | #ifdef CONFIG_SMP | |
3479 | ||
497c9a19 | 3480 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3481 | { |
ec68307c EB |
3482 | struct ht_irq_msg msg; |
3483 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3484 | |
497c9a19 | 3485 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3486 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3487 | |
497c9a19 | 3488 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3489 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3490 | |
ec68307c | 3491 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3492 | } |
3493 | ||
3494 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
3495 | { | |
497c9a19 | 3496 | struct irq_cfg *cfg; |
8b955b0d EB |
3497 | unsigned int dest; |
3498 | cpumask_t tmp; | |
54168ed7 | 3499 | struct irq_desc *desc; |
8b955b0d EB |
3500 | |
3501 | cpus_and(tmp, mask, cpu_online_map); | |
3502 | if (cpus_empty(tmp)) | |
497c9a19 | 3503 | return; |
8b955b0d | 3504 | |
497c9a19 YL |
3505 | if (assign_irq_vector(irq, mask)) |
3506 | return; | |
8b955b0d | 3507 | |
497c9a19 YL |
3508 | cfg = irq_cfg(irq); |
3509 | cpus_and(tmp, cfg->domain, mask); | |
3510 | dest = cpu_mask_to_apicid(tmp); | |
8b955b0d | 3511 | |
497c9a19 | 3512 | target_ht_irq(irq, dest, cfg->vector); |
54168ed7 IM |
3513 | desc = irq_to_desc(irq); |
3514 | desc->affinity = mask; | |
8b955b0d EB |
3515 | } |
3516 | #endif | |
3517 | ||
c37e108d | 3518 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3519 | .name = "PCI-HT", |
3520 | .mask = mask_ht_irq, | |
3521 | .unmask = unmask_ht_irq, | |
1d025192 | 3522 | .ack = ack_apic_edge, |
8b955b0d EB |
3523 | #ifdef CONFIG_SMP |
3524 | .set_affinity = set_ht_irq_affinity, | |
3525 | #endif | |
3526 | .retrigger = ioapic_retrigger_irq, | |
3527 | }; | |
3528 | ||
3529 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3530 | { | |
497c9a19 YL |
3531 | struct irq_cfg *cfg; |
3532 | int err; | |
3533 | cpumask_t tmp; | |
8b955b0d | 3534 | |
497c9a19 YL |
3535 | tmp = TARGET_CPUS; |
3536 | err = assign_irq_vector(irq, tmp); | |
54168ed7 | 3537 | if (!err) { |
ec68307c | 3538 | struct ht_irq_msg msg; |
8b955b0d | 3539 | unsigned dest; |
8b955b0d | 3540 | |
497c9a19 YL |
3541 | cfg = irq_cfg(irq); |
3542 | cpus_and(tmp, cfg->domain, tmp); | |
8b955b0d EB |
3543 | dest = cpu_mask_to_apicid(tmp); |
3544 | ||
ec68307c | 3545 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3546 | |
ec68307c EB |
3547 | msg.address_lo = |
3548 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3549 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3550 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3551 | ((INT_DEST_MODE == 0) ? |
3552 | HT_IRQ_LOW_DM_PHYSICAL : | |
3553 | HT_IRQ_LOW_DM_LOGICAL) | | |
3554 | HT_IRQ_LOW_RQEOI_EDGE | | |
3555 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3556 | HT_IRQ_LOW_MT_FIXED : | |
3557 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3558 | HT_IRQ_LOW_IRQ_MASKED; | |
3559 | ||
ec68307c | 3560 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3561 | |
a460e745 IM |
3562 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3563 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3564 | |
3565 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3566 | } |
497c9a19 | 3567 | return err; |
8b955b0d EB |
3568 | } |
3569 | #endif /* CONFIG_HT_IRQ */ | |
3570 | ||
4173a0e7 DN |
3571 | #ifdef CONFIG_X86_64 |
3572 | /* | |
3573 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3574 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3575 | */ | |
3576 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3577 | unsigned long mmr_offset) | |
3578 | { | |
3579 | const cpumask_t *eligible_cpu = get_cpu_mask(cpu); | |
3580 | struct irq_cfg *cfg; | |
3581 | int mmr_pnode; | |
3582 | unsigned long mmr_value; | |
3583 | struct uv_IO_APIC_route_entry *entry; | |
3584 | unsigned long flags; | |
3585 | int err; | |
3586 | ||
3587 | err = assign_irq_vector(irq, *eligible_cpu); | |
3588 | if (err != 0) | |
3589 | return err; | |
3590 | ||
3591 | spin_lock_irqsave(&vector_lock, flags); | |
3592 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3593 | irq_name); | |
3594 | spin_unlock_irqrestore(&vector_lock, flags); | |
3595 | ||
3596 | cfg = irq_cfg(irq); | |
3597 | ||
3598 | mmr_value = 0; | |
3599 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3600 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3601 | ||
3602 | entry->vector = cfg->vector; | |
3603 | entry->delivery_mode = INT_DELIVERY_MODE; | |
3604 | entry->dest_mode = INT_DEST_MODE; | |
3605 | entry->polarity = 0; | |
3606 | entry->trigger = 0; | |
3607 | entry->mask = 0; | |
3608 | entry->dest = cpu_mask_to_apicid(*eligible_cpu); | |
3609 | ||
3610 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3611 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3612 | ||
3613 | return irq; | |
3614 | } | |
3615 | ||
3616 | /* | |
3617 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3618 | * longer allowed to be sent. | |
3619 | */ | |
3620 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3621 | { | |
3622 | unsigned long mmr_value; | |
3623 | struct uv_IO_APIC_route_entry *entry; | |
3624 | int mmr_pnode; | |
3625 | ||
3626 | mmr_value = 0; | |
3627 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3628 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3629 | ||
3630 | entry->mask = 1; | |
3631 | ||
3632 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3633 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3634 | } | |
3635 | #endif /* CONFIG_X86_64 */ | |
3636 | ||
9d6a4d08 YL |
3637 | int __init io_apic_get_redir_entries (int ioapic) |
3638 | { | |
3639 | union IO_APIC_reg_01 reg_01; | |
3640 | unsigned long flags; | |
3641 | ||
3642 | spin_lock_irqsave(&ioapic_lock, flags); | |
3643 | reg_01.raw = io_apic_read(ioapic, 1); | |
3644 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3645 | ||
3646 | return reg_01.bits.entries; | |
3647 | } | |
3648 | ||
3649 | int __init probe_nr_irqs(void) | |
3650 | { | |
3651 | int idx; | |
3652 | int nr = 0; | |
052c0bff YL |
3653 | #ifndef CONFIG_XEN |
3654 | int nr_min = 32; | |
3655 | #else | |
3656 | int nr_min = NR_IRQS; | |
3657 | #endif | |
9d6a4d08 YL |
3658 | |
3659 | for (idx = 0; idx < nr_ioapics; idx++) | |
052c0bff | 3660 | nr += io_apic_get_redir_entries(idx) + 1; |
9d6a4d08 YL |
3661 | |
3662 | /* double it for hotplug and msi and nmi */ | |
3663 | nr <<= 1; | |
3664 | ||
3665 | /* something wrong ? */ | |
052c0bff YL |
3666 | if (nr < nr_min) |
3667 | nr = nr_min; | |
9d6a4d08 YL |
3668 | |
3669 | return nr; | |
3670 | } | |
3671 | ||
1da177e4 | 3672 | /* -------------------------------------------------------------------------- |
54168ed7 | 3673 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3674 | -------------------------------------------------------------------------- */ |
3675 | ||
888ba6c6 | 3676 | #ifdef CONFIG_ACPI |
1da177e4 | 3677 | |
54168ed7 | 3678 | #ifdef CONFIG_X86_32 |
36062448 | 3679 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3680 | { |
3681 | union IO_APIC_reg_00 reg_00; | |
3682 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3683 | physid_mask_t tmp; | |
3684 | unsigned long flags; | |
3685 | int i = 0; | |
3686 | ||
3687 | /* | |
36062448 PC |
3688 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3689 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3690 | * supports up to 16 on one shared APIC bus. |
36062448 | 3691 | * |
1da177e4 LT |
3692 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3693 | * advantage of new APIC bus architecture. | |
3694 | */ | |
3695 | ||
3696 | if (physids_empty(apic_id_map)) | |
3697 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3698 | ||
3699 | spin_lock_irqsave(&ioapic_lock, flags); | |
3700 | reg_00.raw = io_apic_read(ioapic, 0); | |
3701 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3702 | ||
3703 | if (apic_id >= get_physical_broadcast()) { | |
3704 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3705 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3706 | apic_id = reg_00.bits.ID; | |
3707 | } | |
3708 | ||
3709 | /* | |
36062448 | 3710 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3711 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3712 | */ | |
3713 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3714 | ||
3715 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3716 | if (!check_apicid_used(apic_id_map, i)) | |
3717 | break; | |
3718 | } | |
3719 | ||
3720 | if (i == get_physical_broadcast()) | |
3721 | panic("Max apic_id exceeded!\n"); | |
3722 | ||
3723 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3724 | "trying %d\n", ioapic, apic_id, i); | |
3725 | ||
3726 | apic_id = i; | |
36062448 | 3727 | } |
1da177e4 LT |
3728 | |
3729 | tmp = apicid_to_cpu_present(apic_id); | |
3730 | physids_or(apic_id_map, apic_id_map, tmp); | |
3731 | ||
3732 | if (reg_00.bits.ID != apic_id) { | |
3733 | reg_00.bits.ID = apic_id; | |
3734 | ||
3735 | spin_lock_irqsave(&ioapic_lock, flags); | |
3736 | io_apic_write(ioapic, 0, reg_00.raw); | |
3737 | reg_00.raw = io_apic_read(ioapic, 0); | |
3738 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3739 | ||
3740 | /* Sanity check */ | |
6070f9ec AD |
3741 | if (reg_00.bits.ID != apic_id) { |
3742 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3743 | return -1; | |
3744 | } | |
1da177e4 LT |
3745 | } |
3746 | ||
3747 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3748 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3749 | ||
3750 | return apic_id; | |
3751 | } | |
3752 | ||
36062448 | 3753 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3754 | { |
3755 | union IO_APIC_reg_01 reg_01; | |
3756 | unsigned long flags; | |
3757 | ||
3758 | spin_lock_irqsave(&ioapic_lock, flags); | |
3759 | reg_01.raw = io_apic_read(ioapic, 1); | |
3760 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3761 | ||
3762 | return reg_01.bits.version; | |
3763 | } | |
54168ed7 | 3764 | #endif |
1da177e4 | 3765 | |
54168ed7 | 3766 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3767 | { |
1da177e4 | 3768 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3769 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3770 | ioapic); |
3771 | return -EINVAL; | |
3772 | } | |
3773 | ||
1da177e4 LT |
3774 | /* |
3775 | * IRQs < 16 are already in the irq_2_pin[] map | |
3776 | */ | |
3777 | if (irq >= 16) | |
3778 | add_pin_to_irq(irq, ioapic, pin); | |
3779 | ||
497c9a19 | 3780 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
1da177e4 LT |
3781 | |
3782 | return 0; | |
3783 | } | |
3784 | ||
54168ed7 | 3785 | |
61fd47e0 SL |
3786 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3787 | { | |
3788 | int i; | |
3789 | ||
3790 | if (skip_ioapic_setup) | |
3791 | return -1; | |
3792 | ||
3793 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
3794 | if (mp_irqs[i].mp_irqtype == mp_INT && |
3795 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
3796 | break; |
3797 | if (i >= mp_irq_entries) | |
3798 | return -1; | |
3799 | ||
3800 | *trigger = irq_trigger(i); | |
3801 | *polarity = irq_polarity(i); | |
3802 | return 0; | |
3803 | } | |
3804 | ||
888ba6c6 | 3805 | #endif /* CONFIG_ACPI */ |
1a3f239d | 3806 | |
497c9a19 YL |
3807 | /* |
3808 | * This function currently is only a helper for the i386 smp boot process where | |
3809 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
3810 | * so mask in all cases should simply be TARGET_CPUS | |
3811 | */ | |
3812 | #ifdef CONFIG_SMP | |
3813 | void __init setup_ioapic_dest(void) | |
3814 | { | |
3815 | int pin, ioapic, irq, irq_entry; | |
3816 | struct irq_cfg *cfg; | |
497c9a19 YL |
3817 | |
3818 | if (skip_ioapic_setup == 1) | |
3819 | return; | |
3820 | ||
3821 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
3822 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
3823 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3824 | if (irq_entry == -1) | |
3825 | continue; | |
3826 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
3827 | ||
3828 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
3829 | * when you have too many devices, because at that time only boot | |
3830 | * cpu is online. | |
3831 | */ | |
3832 | cfg = irq_cfg(irq); | |
3833 | if (!cfg->vector) | |
3834 | setup_IO_APIC_irq(ioapic, pin, irq, | |
3835 | irq_trigger(irq_entry), | |
3836 | irq_polarity(irq_entry)); | |
54168ed7 IM |
3837 | #ifdef CONFIG_INTR_REMAP |
3838 | else if (intr_remapping_enabled) | |
3839 | set_ir_ioapic_affinity_irq(irq, TARGET_CPUS); | |
3840 | #endif | |
3841 | else | |
497c9a19 | 3842 | set_ioapic_affinity_irq(irq, TARGET_CPUS); |
497c9a19 YL |
3843 | } |
3844 | ||
3845 | } | |
3846 | } | |
3847 | #endif | |
3848 | ||
54168ed7 IM |
3849 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3850 | ||
3851 | static struct resource *ioapic_resources; | |
3852 | ||
3853 | static struct resource * __init ioapic_setup_resources(void) | |
3854 | { | |
3855 | unsigned long n; | |
3856 | struct resource *res; | |
3857 | char *mem; | |
3858 | int i; | |
3859 | ||
3860 | if (nr_ioapics <= 0) | |
3861 | return NULL; | |
3862 | ||
3863 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3864 | n *= nr_ioapics; | |
3865 | ||
3866 | mem = alloc_bootmem(n); | |
3867 | res = (void *)mem; | |
3868 | ||
3869 | if (mem != NULL) { | |
3870 | mem += sizeof(struct resource) * nr_ioapics; | |
3871 | ||
3872 | for (i = 0; i < nr_ioapics; i++) { | |
3873 | res[i].name = mem; | |
3874 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
3875 | sprintf(mem, "IOAPIC %u", i); | |
3876 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
3877 | } | |
3878 | } | |
3879 | ||
3880 | ioapic_resources = res; | |
3881 | ||
3882 | return res; | |
3883 | } | |
54168ed7 | 3884 | |
f3294a33 YL |
3885 | void __init ioapic_init_mappings(void) |
3886 | { | |
3887 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
3888 | int i; | |
54168ed7 | 3889 | struct resource *ioapic_res; |
f3294a33 | 3890 | |
54168ed7 | 3891 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
3892 | for (i = 0; i < nr_ioapics; i++) { |
3893 | if (smp_found_config) { | |
3894 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
54168ed7 IM |
3895 | #ifdef CONFIG_X86_32 |
3896 | if (!ioapic_phys) { | |
3897 | printk(KERN_ERR | |
3898 | "WARNING: bogus zero IO-APIC " | |
3899 | "address found in MPTABLE, " | |
3900 | "disabling IO/APIC support!\n"); | |
3901 | smp_found_config = 0; | |
3902 | skip_ioapic_setup = 1; | |
3903 | goto fake_ioapic_page; | |
3904 | } | |
3905 | #endif | |
f3294a33 | 3906 | } else { |
54168ed7 | 3907 | #ifdef CONFIG_X86_32 |
f3294a33 | 3908 | fake_ioapic_page: |
54168ed7 | 3909 | #endif |
f3294a33 | 3910 | ioapic_phys = (unsigned long) |
54168ed7 | 3911 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3912 | ioapic_phys = __pa(ioapic_phys); |
3913 | } | |
3914 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
3915 | apic_printk(APIC_VERBOSE, |
3916 | "mapped IOAPIC to %08lx (%08lx)\n", | |
3917 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 3918 | idx++; |
54168ed7 | 3919 | |
54168ed7 IM |
3920 | if (ioapic_res != NULL) { |
3921 | ioapic_res->start = ioapic_phys; | |
3922 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
3923 | ioapic_res++; | |
3924 | } | |
f3294a33 YL |
3925 | } |
3926 | } | |
3927 | ||
54168ed7 IM |
3928 | static int __init ioapic_insert_resources(void) |
3929 | { | |
3930 | int i; | |
3931 | struct resource *r = ioapic_resources; | |
3932 | ||
3933 | if (!r) { | |
3934 | printk(KERN_ERR | |
3935 | "IO APIC resources could be not be allocated.\n"); | |
3936 | return -1; | |
3937 | } | |
3938 | ||
3939 | for (i = 0; i < nr_ioapics; i++) { | |
3940 | insert_resource(&iomem_resource, r); | |
3941 | r++; | |
3942 | } | |
3943 | ||
3944 | return 0; | |
3945 | } | |
3946 | ||
3947 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
3948 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
3949 | late_initcall(ioapic_insert_resources); |