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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
58ac1e76 | 44 | #include <linux/hpet.h> |
54d5d424 | 45 | |
d4057bdb | 46 | #include <asm/idle.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/smp.h> | |
49 | #include <asm/desc.h> | |
d4057bdb YL |
50 | #include <asm/proto.h> |
51 | #include <asm/acpi.h> | |
52 | #include <asm/dma.h> | |
1da177e4 | 53 | #include <asm/timer.h> |
306e440d | 54 | #include <asm/i8259.h> |
3e4ff115 | 55 | #include <asm/nmi.h> |
2d3fcc1c | 56 | #include <asm/msidef.h> |
8b955b0d | 57 | #include <asm/hypertransport.h> |
a4dbc34d | 58 | #include <asm/setup.h> |
d4057bdb | 59 | #include <asm/irq_remapping.h> |
58ac1e76 | 60 | #include <asm/hpet.h> |
4173a0e7 DN |
61 | #include <asm/uv/uv_hub.h> |
62 | #include <asm/uv/uv_irq.h> | |
1da177e4 | 63 | |
497c9a19 | 64 | #include <mach_ipi.h> |
1da177e4 | 65 | #include <mach_apic.h> |
874c4fe3 | 66 | #include <mach_apicdef.h> |
1da177e4 | 67 | |
32f71aff MR |
68 | #define __apicdebuginit(type) static type __init |
69 | ||
1da177e4 | 70 | /* |
54168ed7 IM |
71 | * Is the SiS APIC rmw bug present ? |
72 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
73 | */ |
74 | int sis_apic_bug = -1; | |
75 | ||
efa2559f YL |
76 | static DEFINE_SPINLOCK(ioapic_lock); |
77 | static DEFINE_SPINLOCK(vector_lock); | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * # of IRQ routing registers | |
81 | */ | |
82 | int nr_ioapic_registers[MAX_IO_APICS]; | |
83 | ||
9f640ccb | 84 | /* I/O APIC entries */ |
ec2cd0a2 | 85 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
86 | int nr_ioapics; |
87 | ||
584f734d | 88 | /* MP IRQ source entries */ |
2fddb6e2 | 89 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
90 | |
91 | /* # of MP IRQ source entries */ | |
92 | int mp_irq_entries; | |
93 | ||
8732fc4b AS |
94 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
95 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
96 | #endif | |
97 | ||
98 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
99 | ||
efa2559f YL |
100 | int skip_ioapic_setup; |
101 | ||
54168ed7 | 102 | static int __init parse_noapic(char *str) |
efa2559f YL |
103 | { |
104 | /* disable IO-APIC */ | |
105 | disable_ioapic_setup(); | |
106 | return 0; | |
107 | } | |
108 | early_param("noapic", parse_noapic); | |
66759a01 | 109 | |
0f978f45 | 110 | struct irq_pin_list; |
0b8f1efa YL |
111 | |
112 | /* | |
113 | * This is performance-critical, we want to do it O(1) | |
114 | * | |
115 | * the indexing order of this array favors 1:1 mappings | |
116 | * between pins and IRQs. | |
117 | */ | |
118 | ||
119 | struct irq_pin_list { | |
120 | int apic, pin; | |
121 | struct irq_pin_list *next; | |
122 | }; | |
123 | ||
124 | static struct irq_pin_list *get_one_free_irq_2_pin(int cpu) | |
125 | { | |
126 | struct irq_pin_list *pin; | |
127 | int node; | |
128 | ||
129 | node = cpu_to_node(cpu); | |
130 | ||
131 | pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node); | |
0b8f1efa YL |
132 | |
133 | return pin; | |
134 | } | |
135 | ||
a1420f39 | 136 | struct irq_cfg { |
0f978f45 | 137 | struct irq_pin_list *irq_2_pin; |
22f65d31 MT |
138 | cpumask_var_t domain; |
139 | cpumask_var_t old_domain; | |
497c9a19 | 140 | unsigned move_cleanup_count; |
a1420f39 | 141 | u8 vector; |
497c9a19 | 142 | u8 move_in_progress : 1; |
48a1b10a YL |
143 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
144 | u8 move_desc_pending : 1; | |
145 | #endif | |
a1420f39 YL |
146 | }; |
147 | ||
a1420f39 | 148 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
0b8f1efa YL |
149 | #ifdef CONFIG_SPARSE_IRQ |
150 | static struct irq_cfg irq_cfgx[] = { | |
151 | #else | |
d6c88a50 | 152 | static struct irq_cfg irq_cfgx[NR_IRQS] = { |
0b8f1efa | 153 | #endif |
22f65d31 MT |
154 | [0] = { .vector = IRQ0_VECTOR, }, |
155 | [1] = { .vector = IRQ1_VECTOR, }, | |
156 | [2] = { .vector = IRQ2_VECTOR, }, | |
157 | [3] = { .vector = IRQ3_VECTOR, }, | |
158 | [4] = { .vector = IRQ4_VECTOR, }, | |
159 | [5] = { .vector = IRQ5_VECTOR, }, | |
160 | [6] = { .vector = IRQ6_VECTOR, }, | |
161 | [7] = { .vector = IRQ7_VECTOR, }, | |
162 | [8] = { .vector = IRQ8_VECTOR, }, | |
163 | [9] = { .vector = IRQ9_VECTOR, }, | |
164 | [10] = { .vector = IRQ10_VECTOR, }, | |
165 | [11] = { .vector = IRQ11_VECTOR, }, | |
166 | [12] = { .vector = IRQ12_VECTOR, }, | |
167 | [13] = { .vector = IRQ13_VECTOR, }, | |
168 | [14] = { .vector = IRQ14_VECTOR, }, | |
169 | [15] = { .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
170 | }; |
171 | ||
13a0c3c2 | 172 | int __init arch_early_irq_init(void) |
8f09cd20 | 173 | { |
0b8f1efa YL |
174 | struct irq_cfg *cfg; |
175 | struct irq_desc *desc; | |
176 | int count; | |
177 | int i; | |
d6c88a50 | 178 | |
0b8f1efa YL |
179 | cfg = irq_cfgx; |
180 | count = ARRAY_SIZE(irq_cfgx); | |
8f09cd20 | 181 | |
0b8f1efa YL |
182 | for (i = 0; i < count; i++) { |
183 | desc = irq_to_desc(i); | |
184 | desc->chip_data = &cfg[i]; | |
22f65d31 MT |
185 | alloc_bootmem_cpumask_var(&cfg[i].domain); |
186 | alloc_bootmem_cpumask_var(&cfg[i].old_domain); | |
187 | if (i < NR_IRQS_LEGACY) | |
188 | cpumask_setall(cfg[i].domain); | |
0b8f1efa | 189 | } |
13a0c3c2 YL |
190 | |
191 | return 0; | |
0b8f1efa | 192 | } |
8f09cd20 | 193 | |
0b8f1efa | 194 | #ifdef CONFIG_SPARSE_IRQ |
d6c88a50 | 195 | static struct irq_cfg *irq_cfg(unsigned int irq) |
8f09cd20 | 196 | { |
0b8f1efa YL |
197 | struct irq_cfg *cfg = NULL; |
198 | struct irq_desc *desc; | |
1da177e4 | 199 | |
0b8f1efa YL |
200 | desc = irq_to_desc(irq); |
201 | if (desc) | |
202 | cfg = desc->chip_data; | |
0f978f45 | 203 | |
0b8f1efa | 204 | return cfg; |
8f09cd20 | 205 | } |
d6c88a50 | 206 | |
0b8f1efa | 207 | static struct irq_cfg *get_one_free_irq_cfg(int cpu) |
8f09cd20 | 208 | { |
0b8f1efa YL |
209 | struct irq_cfg *cfg; |
210 | int node; | |
211 | ||
212 | node = cpu_to_node(cpu); | |
0f978f45 | 213 | |
0b8f1efa | 214 | cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node); |
22f65d31 | 215 | if (cfg) { |
80855f73 | 216 | if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) { |
22f65d31 MT |
217 | kfree(cfg); |
218 | cfg = NULL; | |
80855f73 MT |
219 | } else if (!alloc_cpumask_var_node(&cfg->old_domain, |
220 | GFP_ATOMIC, node)) { | |
22f65d31 MT |
221 | free_cpumask_var(cfg->domain); |
222 | kfree(cfg); | |
223 | cfg = NULL; | |
224 | } else { | |
225 | cpumask_clear(cfg->domain); | |
226 | cpumask_clear(cfg->old_domain); | |
227 | } | |
228 | } | |
0f978f45 | 229 | |
0b8f1efa | 230 | return cfg; |
8f09cd20 YL |
231 | } |
232 | ||
13a0c3c2 | 233 | int arch_init_chip_data(struct irq_desc *desc, int cpu) |
0f978f45 | 234 | { |
0b8f1efa | 235 | struct irq_cfg *cfg; |
d6c88a50 | 236 | |
0b8f1efa YL |
237 | cfg = desc->chip_data; |
238 | if (!cfg) { | |
239 | desc->chip_data = get_one_free_irq_cfg(cpu); | |
240 | if (!desc->chip_data) { | |
241 | printk(KERN_ERR "can not alloc irq_cfg\n"); | |
242 | BUG_ON(1); | |
243 | } | |
244 | } | |
1da177e4 | 245 | |
13a0c3c2 | 246 | return 0; |
0b8f1efa | 247 | } |
0f978f45 | 248 | |
48a1b10a | 249 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
d6c88a50 | 250 | |
48a1b10a YL |
251 | static void |
252 | init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu) | |
0f978f45 | 253 | { |
48a1b10a YL |
254 | struct irq_pin_list *old_entry, *head, *tail, *entry; |
255 | ||
256 | cfg->irq_2_pin = NULL; | |
257 | old_entry = old_cfg->irq_2_pin; | |
258 | if (!old_entry) | |
259 | return; | |
0f978f45 | 260 | |
48a1b10a YL |
261 | entry = get_one_free_irq_2_pin(cpu); |
262 | if (!entry) | |
263 | return; | |
0f978f45 | 264 | |
48a1b10a YL |
265 | entry->apic = old_entry->apic; |
266 | entry->pin = old_entry->pin; | |
267 | head = entry; | |
268 | tail = entry; | |
269 | old_entry = old_entry->next; | |
270 | while (old_entry) { | |
271 | entry = get_one_free_irq_2_pin(cpu); | |
272 | if (!entry) { | |
273 | entry = head; | |
274 | while (entry) { | |
275 | head = entry->next; | |
276 | kfree(entry); | |
277 | entry = head; | |
278 | } | |
279 | /* still use the old one */ | |
280 | return; | |
281 | } | |
282 | entry->apic = old_entry->apic; | |
283 | entry->pin = old_entry->pin; | |
284 | tail->next = entry; | |
285 | tail = entry; | |
286 | old_entry = old_entry->next; | |
287 | } | |
0f978f45 | 288 | |
48a1b10a YL |
289 | tail->next = NULL; |
290 | cfg->irq_2_pin = head; | |
0f978f45 | 291 | } |
0f978f45 | 292 | |
48a1b10a | 293 | static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg) |
0f978f45 | 294 | { |
48a1b10a | 295 | struct irq_pin_list *entry, *next; |
0f978f45 | 296 | |
48a1b10a YL |
297 | if (old_cfg->irq_2_pin == cfg->irq_2_pin) |
298 | return; | |
301e6190 | 299 | |
48a1b10a | 300 | entry = old_cfg->irq_2_pin; |
0f978f45 | 301 | |
48a1b10a YL |
302 | while (entry) { |
303 | next = entry->next; | |
304 | kfree(entry); | |
305 | entry = next; | |
306 | } | |
307 | old_cfg->irq_2_pin = NULL; | |
0f978f45 | 308 | } |
0f978f45 | 309 | |
48a1b10a YL |
310 | void arch_init_copy_chip_data(struct irq_desc *old_desc, |
311 | struct irq_desc *desc, int cpu) | |
0f978f45 | 312 | { |
48a1b10a YL |
313 | struct irq_cfg *cfg; |
314 | struct irq_cfg *old_cfg; | |
0f978f45 | 315 | |
48a1b10a | 316 | cfg = get_one_free_irq_cfg(cpu); |
301e6190 | 317 | |
48a1b10a YL |
318 | if (!cfg) |
319 | return; | |
320 | ||
321 | desc->chip_data = cfg; | |
322 | ||
323 | old_cfg = old_desc->chip_data; | |
324 | ||
325 | memcpy(cfg, old_cfg, sizeof(struct irq_cfg)); | |
326 | ||
327 | init_copy_irq_2_pin(old_cfg, cfg, cpu); | |
0f978f45 | 328 | } |
1da177e4 | 329 | |
48a1b10a YL |
330 | static void free_irq_cfg(struct irq_cfg *old_cfg) |
331 | { | |
332 | kfree(old_cfg); | |
333 | } | |
334 | ||
335 | void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc) | |
336 | { | |
337 | struct irq_cfg *old_cfg, *cfg; | |
338 | ||
339 | old_cfg = old_desc->chip_data; | |
340 | cfg = desc->chip_data; | |
341 | ||
342 | if (old_cfg == cfg) | |
343 | return; | |
344 | ||
345 | if (old_cfg) { | |
346 | free_irq_2_pin(old_cfg, cfg); | |
347 | free_irq_cfg(old_cfg); | |
348 | old_desc->chip_data = NULL; | |
349 | } | |
350 | } | |
351 | ||
d733e00d IM |
352 | static void |
353 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
48a1b10a YL |
354 | { |
355 | struct irq_cfg *cfg = desc->chip_data; | |
356 | ||
357 | if (!cfg->move_in_progress) { | |
358 | /* it means that domain is not changed */ | |
d733e00d | 359 | if (!cpumask_intersects(&desc->affinity, mask)) |
48a1b10a YL |
360 | cfg->move_desc_pending = 1; |
361 | } | |
0f978f45 | 362 | } |
48a1b10a YL |
363 | #endif |
364 | ||
0b8f1efa YL |
365 | #else |
366 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
367 | { | |
368 | return irq < nr_irqs ? irq_cfgx + irq : NULL; | |
0f978f45 | 369 | } |
1da177e4 | 370 | |
0b8f1efa YL |
371 | #endif |
372 | ||
48a1b10a | 373 | #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC |
e7986739 MT |
374 | static inline void |
375 | set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask) | |
3145e941 YL |
376 | { |
377 | } | |
48a1b10a | 378 | #endif |
1da177e4 | 379 | |
130fe05d LT |
380 | struct io_apic { |
381 | unsigned int index; | |
382 | unsigned int unused[3]; | |
383 | unsigned int data; | |
384 | }; | |
385 | ||
386 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
387 | { | |
388 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 389 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
390 | } |
391 | ||
392 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
393 | { | |
394 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
395 | writel(reg, &io_apic->index); | |
396 | return readl(&io_apic->data); | |
397 | } | |
398 | ||
399 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
400 | { | |
401 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
402 | writel(reg, &io_apic->index); | |
403 | writel(value, &io_apic->data); | |
404 | } | |
405 | ||
406 | /* | |
407 | * Re-write a value: to be used for read-modify-write | |
408 | * cycles where the read already set up the index register. | |
409 | * | |
410 | * Older SiS APIC requires we rewrite the index register | |
411 | */ | |
412 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
413 | { | |
54168ed7 | 414 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
d6c88a50 TG |
415 | |
416 | if (sis_apic_bug) | |
417 | writel(reg, &io_apic->index); | |
130fe05d LT |
418 | writel(value, &io_apic->data); |
419 | } | |
420 | ||
3145e941 | 421 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
047c8fdb YL |
422 | { |
423 | struct irq_pin_list *entry; | |
424 | unsigned long flags; | |
047c8fdb YL |
425 | |
426 | spin_lock_irqsave(&ioapic_lock, flags); | |
427 | entry = cfg->irq_2_pin; | |
428 | for (;;) { | |
429 | unsigned int reg; | |
430 | int pin; | |
431 | ||
432 | if (!entry) | |
433 | break; | |
434 | pin = entry->pin; | |
435 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
436 | /* Is the remote IRR bit set? */ | |
437 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
438 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
439 | return true; | |
440 | } | |
441 | if (!entry->next) | |
442 | break; | |
443 | entry = entry->next; | |
444 | } | |
445 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
446 | ||
447 | return false; | |
448 | } | |
047c8fdb | 449 | |
cf4c6a2f AK |
450 | union entry_union { |
451 | struct { u32 w1, w2; }; | |
452 | struct IO_APIC_route_entry entry; | |
453 | }; | |
454 | ||
455 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
456 | { | |
457 | union entry_union eu; | |
458 | unsigned long flags; | |
459 | spin_lock_irqsave(&ioapic_lock, flags); | |
460 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
461 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
462 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
463 | return eu.entry; | |
464 | } | |
465 | ||
f9dadfa7 LT |
466 | /* |
467 | * When we write a new IO APIC routing entry, we need to write the high | |
468 | * word first! If the mask bit in the low word is clear, we will enable | |
469 | * the interrupt, and we need to make sure the entry is fully populated | |
470 | * before that happens. | |
471 | */ | |
d15512f4 AK |
472 | static void |
473 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 474 | { |
cf4c6a2f AK |
475 | union entry_union eu; |
476 | eu.entry = e; | |
f9dadfa7 LT |
477 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
478 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
479 | } |
480 | ||
481 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
482 | { | |
483 | unsigned long flags; | |
484 | spin_lock_irqsave(&ioapic_lock, flags); | |
485 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
486 | spin_unlock_irqrestore(&ioapic_lock, flags); |
487 | } | |
488 | ||
489 | /* | |
490 | * When we mask an IO APIC routing entry, we need to write the low | |
491 | * word first, in order to set the mask bit before we change the | |
492 | * high bits! | |
493 | */ | |
494 | static void ioapic_mask_entry(int apic, int pin) | |
495 | { | |
496 | unsigned long flags; | |
497 | union entry_union eu = { .entry.mask = 1 }; | |
498 | ||
cf4c6a2f AK |
499 | spin_lock_irqsave(&ioapic_lock, flags); |
500 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
501 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
502 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
503 | } | |
504 | ||
497c9a19 | 505 | #ifdef CONFIG_SMP |
22f65d31 MT |
506 | static void send_cleanup_vector(struct irq_cfg *cfg) |
507 | { | |
508 | cpumask_var_t cleanup_mask; | |
509 | ||
510 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
511 | unsigned int i; | |
512 | cfg->move_cleanup_count = 0; | |
513 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
514 | cfg->move_cleanup_count++; | |
515 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
516 | send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); | |
517 | } else { | |
518 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
519 | cfg->move_cleanup_count = cpumask_weight(cleanup_mask); | |
520 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
521 | free_cpumask_var(cleanup_mask); | |
522 | } | |
523 | cfg->move_in_progress = 0; | |
524 | } | |
525 | ||
3145e941 | 526 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
497c9a19 YL |
527 | { |
528 | int apic, pin; | |
497c9a19 | 529 | struct irq_pin_list *entry; |
3145e941 | 530 | u8 vector = cfg->vector; |
497c9a19 | 531 | |
497c9a19 YL |
532 | entry = cfg->irq_2_pin; |
533 | for (;;) { | |
534 | unsigned int reg; | |
535 | ||
536 | if (!entry) | |
537 | break; | |
538 | ||
539 | apic = entry->apic; | |
540 | pin = entry->pin; | |
54168ed7 IM |
541 | #ifdef CONFIG_INTR_REMAP |
542 | /* | |
543 | * With interrupt-remapping, destination information comes | |
544 | * from interrupt-remapping table entry. | |
545 | */ | |
546 | if (!irq_remapped(irq)) | |
547 | io_apic_write(apic, 0x11 + pin*2, dest); | |
548 | #else | |
497c9a19 | 549 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 550 | #endif |
497c9a19 YL |
551 | reg = io_apic_read(apic, 0x10 + pin*2); |
552 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
553 | reg |= vector; | |
54168ed7 | 554 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
555 | if (!entry->next) |
556 | break; | |
557 | entry = entry->next; | |
558 | } | |
559 | } | |
efa2559f | 560 | |
e7986739 MT |
561 | static int |
562 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask); | |
efa2559f | 563 | |
22f65d31 MT |
564 | /* |
565 | * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid | |
566 | * of that, or returns BAD_APICID and leaves desc->affinity untouched. | |
567 | */ | |
568 | static unsigned int | |
569 | set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
570 | { |
571 | struct irq_cfg *cfg; | |
3145e941 | 572 | unsigned int irq; |
497c9a19 | 573 | |
0de26520 | 574 | if (!cpumask_intersects(mask, cpu_online_mask)) |
22f65d31 | 575 | return BAD_APICID; |
497c9a19 | 576 | |
3145e941 YL |
577 | irq = desc->irq; |
578 | cfg = desc->chip_data; | |
579 | if (assign_irq_vector(irq, cfg, mask)) | |
22f65d31 | 580 | return BAD_APICID; |
497c9a19 | 581 | |
22f65d31 | 582 | cpumask_and(&desc->affinity, cfg->domain, mask); |
3145e941 | 583 | set_extra_move_desc(desc, mask); |
22f65d31 MT |
584 | return cpu_mask_to_apicid_and(&desc->affinity, cpu_online_mask); |
585 | } | |
3145e941 | 586 | |
22f65d31 MT |
587 | static void |
588 | set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 YL |
589 | { |
590 | struct irq_cfg *cfg; | |
591 | unsigned long flags; | |
592 | unsigned int dest; | |
22f65d31 | 593 | unsigned int irq; |
497c9a19 | 594 | |
22f65d31 MT |
595 | irq = desc->irq; |
596 | cfg = desc->chip_data; | |
497c9a19 | 597 | |
497c9a19 | 598 | spin_lock_irqsave(&ioapic_lock, flags); |
22f65d31 MT |
599 | dest = set_desc_affinity(desc, mask); |
600 | if (dest != BAD_APICID) { | |
601 | /* Only the high 8 bits are valid. */ | |
602 | dest = SET_APIC_LOGICAL_ID(dest); | |
603 | __target_IO_APIC_irq(irq, dest, cfg); | |
604 | } | |
497c9a19 YL |
605 | spin_unlock_irqrestore(&ioapic_lock, flags); |
606 | } | |
497c9a19 | 607 | |
22f65d31 MT |
608 | static void |
609 | set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask) | |
3145e941 YL |
610 | { |
611 | struct irq_desc *desc; | |
497c9a19 | 612 | |
54168ed7 | 613 | desc = irq_to_desc(irq); |
3145e941 YL |
614 | |
615 | set_ioapic_affinity_irq_desc(desc, mask); | |
497c9a19 | 616 | } |
497c9a19 YL |
617 | #endif /* CONFIG_SMP */ |
618 | ||
1da177e4 LT |
619 | /* |
620 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
621 | * shared ISA-space IRQs, so we have to support them. We are super | |
622 | * fast in the common case, and fast for shared ISA-space IRQs. | |
623 | */ | |
3145e941 | 624 | static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin) |
1da177e4 | 625 | { |
0f978f45 YL |
626 | struct irq_pin_list *entry; |
627 | ||
0f978f45 YL |
628 | entry = cfg->irq_2_pin; |
629 | if (!entry) { | |
0b8f1efa YL |
630 | entry = get_one_free_irq_2_pin(cpu); |
631 | if (!entry) { | |
632 | printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n", | |
633 | apic, pin); | |
634 | return; | |
635 | } | |
0f978f45 YL |
636 | cfg->irq_2_pin = entry; |
637 | entry->apic = apic; | |
638 | entry->pin = pin; | |
0f978f45 YL |
639 | return; |
640 | } | |
1da177e4 | 641 | |
0f978f45 YL |
642 | while (entry->next) { |
643 | /* not again, please */ | |
644 | if (entry->apic == apic && entry->pin == pin) | |
645 | return; | |
1da177e4 | 646 | |
0f978f45 | 647 | entry = entry->next; |
1da177e4 | 648 | } |
0f978f45 | 649 | |
0b8f1efa | 650 | entry->next = get_one_free_irq_2_pin(cpu); |
0f978f45 | 651 | entry = entry->next; |
1da177e4 LT |
652 | entry->apic = apic; |
653 | entry->pin = pin; | |
654 | } | |
655 | ||
656 | /* | |
657 | * Reroute an IRQ to a different pin. | |
658 | */ | |
3145e941 | 659 | static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu, |
1da177e4 LT |
660 | int oldapic, int oldpin, |
661 | int newapic, int newpin) | |
662 | { | |
0f978f45 YL |
663 | struct irq_pin_list *entry = cfg->irq_2_pin; |
664 | int replaced = 0; | |
1da177e4 | 665 | |
0f978f45 | 666 | while (entry) { |
1da177e4 LT |
667 | if (entry->apic == oldapic && entry->pin == oldpin) { |
668 | entry->apic = newapic; | |
669 | entry->pin = newpin; | |
0f978f45 YL |
670 | replaced = 1; |
671 | /* every one is different, right? */ | |
1da177e4 | 672 | break; |
0f978f45 YL |
673 | } |
674 | entry = entry->next; | |
1da177e4 | 675 | } |
0f978f45 YL |
676 | |
677 | /* why? call replace before add? */ | |
678 | if (!replaced) | |
3145e941 | 679 | add_pin_to_irq_cpu(cfg, cpu, newapic, newpin); |
1da177e4 LT |
680 | } |
681 | ||
3145e941 | 682 | static inline void io_apic_modify_irq(struct irq_cfg *cfg, |
87783be4 CG |
683 | int mask_and, int mask_or, |
684 | void (*final)(struct irq_pin_list *entry)) | |
685 | { | |
686 | int pin; | |
87783be4 | 687 | struct irq_pin_list *entry; |
047c8fdb | 688 | |
87783be4 CG |
689 | for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) { |
690 | unsigned int reg; | |
691 | pin = entry->pin; | |
692 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); | |
693 | reg &= mask_and; | |
694 | reg |= mask_or; | |
695 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); | |
696 | if (final) | |
697 | final(entry); | |
698 | } | |
699 | } | |
047c8fdb | 700 | |
3145e941 | 701 | static void __unmask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 702 | { |
3145e941 | 703 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
87783be4 | 704 | } |
047c8fdb | 705 | |
4e738e2f | 706 | #ifdef CONFIG_X86_64 |
7f3e632f | 707 | static void io_apic_sync(struct irq_pin_list *entry) |
1da177e4 | 708 | { |
87783be4 CG |
709 | /* |
710 | * Synchronize the IO-APIC and the CPU by doing | |
711 | * a dummy read from the IO-APIC | |
712 | */ | |
713 | struct io_apic __iomem *io_apic; | |
714 | io_apic = io_apic_base(entry->apic); | |
4e738e2f | 715 | readl(&io_apic->data); |
1da177e4 LT |
716 | } |
717 | ||
3145e941 | 718 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 719 | { |
3145e941 | 720 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
87783be4 CG |
721 | } |
722 | #else /* CONFIG_X86_32 */ | |
3145e941 | 723 | static void __mask_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 724 | { |
3145e941 | 725 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL); |
87783be4 | 726 | } |
1da177e4 | 727 | |
3145e941 | 728 | static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 729 | { |
3145e941 | 730 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER, |
87783be4 CG |
731 | IO_APIC_REDIR_MASKED, NULL); |
732 | } | |
1da177e4 | 733 | |
3145e941 | 734 | static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg) |
87783be4 | 735 | { |
3145e941 | 736 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, |
87783be4 CG |
737 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); |
738 | } | |
739 | #endif /* CONFIG_X86_32 */ | |
047c8fdb | 740 | |
3145e941 | 741 | static void mask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 742 | { |
3145e941 | 743 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
744 | unsigned long flags; |
745 | ||
3145e941 YL |
746 | BUG_ON(!cfg); |
747 | ||
1da177e4 | 748 | spin_lock_irqsave(&ioapic_lock, flags); |
3145e941 | 749 | __mask_IO_APIC_irq(cfg); |
1da177e4 LT |
750 | spin_unlock_irqrestore(&ioapic_lock, flags); |
751 | } | |
752 | ||
3145e941 | 753 | static void unmask_IO_APIC_irq_desc(struct irq_desc *desc) |
1da177e4 | 754 | { |
3145e941 | 755 | struct irq_cfg *cfg = desc->chip_data; |
1da177e4 LT |
756 | unsigned long flags; |
757 | ||
758 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 759 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
760 | spin_unlock_irqrestore(&ioapic_lock, flags); |
761 | } | |
762 | ||
3145e941 YL |
763 | static void mask_IO_APIC_irq(unsigned int irq) |
764 | { | |
765 | struct irq_desc *desc = irq_to_desc(irq); | |
766 | ||
767 | mask_IO_APIC_irq_desc(desc); | |
768 | } | |
769 | static void unmask_IO_APIC_irq(unsigned int irq) | |
770 | { | |
771 | struct irq_desc *desc = irq_to_desc(irq); | |
772 | ||
773 | unmask_IO_APIC_irq_desc(desc); | |
774 | } | |
775 | ||
1da177e4 LT |
776 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
777 | { | |
778 | struct IO_APIC_route_entry entry; | |
36062448 | 779 | |
1da177e4 | 780 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 781 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
782 | if (entry.delivery_mode == dest_SMI) |
783 | return; | |
1da177e4 LT |
784 | /* |
785 | * Disable it in the IO-APIC irq-routing table: | |
786 | */ | |
f9dadfa7 | 787 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
788 | } |
789 | ||
54168ed7 | 790 | static void clear_IO_APIC (void) |
1da177e4 LT |
791 | { |
792 | int apic, pin; | |
793 | ||
794 | for (apic = 0; apic < nr_ioapics; apic++) | |
795 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
796 | clear_IO_APIC_pin(apic, pin); | |
797 | } | |
798 | ||
54168ed7 | 799 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 800 | void send_IPI_self(int vector) |
1da177e4 LT |
801 | { |
802 | unsigned int cfg; | |
803 | ||
804 | /* | |
805 | * Wait for idle. | |
806 | */ | |
807 | apic_wait_icr_idle(); | |
808 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
809 | /* | |
810 | * Send the IPI. The write to APIC_ICR fires this off. | |
811 | */ | |
593f4a78 | 812 | apic_write(APIC_ICR, cfg); |
1da177e4 | 813 | } |
54168ed7 | 814 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 815 | |
54168ed7 | 816 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
817 | /* |
818 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
819 | * specific CPU-side IRQs. | |
820 | */ | |
821 | ||
822 | #define MAX_PIRQS 8 | |
823 | static int pirq_entries [MAX_PIRQS]; | |
824 | static int pirqs_enabled; | |
1da177e4 | 825 | |
1da177e4 LT |
826 | static int __init ioapic_pirq_setup(char *str) |
827 | { | |
828 | int i, max; | |
829 | int ints[MAX_PIRQS+1]; | |
830 | ||
831 | get_options(str, ARRAY_SIZE(ints), ints); | |
832 | ||
833 | for (i = 0; i < MAX_PIRQS; i++) | |
834 | pirq_entries[i] = -1; | |
835 | ||
836 | pirqs_enabled = 1; | |
837 | apic_printk(APIC_VERBOSE, KERN_INFO | |
838 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
839 | max = MAX_PIRQS; | |
840 | if (ints[0] < MAX_PIRQS) | |
841 | max = ints[0]; | |
842 | ||
843 | for (i = 0; i < max; i++) { | |
844 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
845 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
846 | /* | |
847 | * PIRQs are mapped upside down, usually. | |
848 | */ | |
849 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
850 | } | |
851 | return 1; | |
852 | } | |
853 | ||
854 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
855 | #endif /* CONFIG_X86_32 */ |
856 | ||
857 | #ifdef CONFIG_INTR_REMAP | |
858 | /* I/O APIC RTE contents at the OS boot up */ | |
859 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
860 | ||
861 | /* | |
862 | * Saves and masks all the unmasked IO-APIC RTE's | |
863 | */ | |
864 | int save_mask_IO_APIC_setup(void) | |
865 | { | |
866 | union IO_APIC_reg_01 reg_01; | |
867 | unsigned long flags; | |
868 | int apic, pin; | |
869 | ||
870 | /* | |
871 | * The number of IO-APIC IRQ registers (== #pins): | |
872 | */ | |
873 | for (apic = 0; apic < nr_ioapics; apic++) { | |
874 | spin_lock_irqsave(&ioapic_lock, flags); | |
875 | reg_01.raw = io_apic_read(apic, 1); | |
876 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
877 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
878 | } | |
879 | ||
880 | for (apic = 0; apic < nr_ioapics; apic++) { | |
881 | early_ioapic_entries[apic] = | |
882 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
883 | nr_ioapic_registers[apic], GFP_KERNEL); | |
884 | if (!early_ioapic_entries[apic]) | |
5ffa4eb2 | 885 | goto nomem; |
54168ed7 IM |
886 | } |
887 | ||
888 | for (apic = 0; apic < nr_ioapics; apic++) | |
889 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
890 | struct IO_APIC_route_entry entry; | |
891 | ||
892 | entry = early_ioapic_entries[apic][pin] = | |
893 | ioapic_read_entry(apic, pin); | |
894 | if (!entry.mask) { | |
895 | entry.mask = 1; | |
896 | ioapic_write_entry(apic, pin, entry); | |
897 | } | |
898 | } | |
5ffa4eb2 | 899 | |
54168ed7 | 900 | return 0; |
5ffa4eb2 CG |
901 | |
902 | nomem: | |
c1370b49 CG |
903 | while (apic >= 0) |
904 | kfree(early_ioapic_entries[apic--]); | |
5ffa4eb2 CG |
905 | memset(early_ioapic_entries, 0, |
906 | ARRAY_SIZE(early_ioapic_entries)); | |
907 | ||
908 | return -ENOMEM; | |
54168ed7 IM |
909 | } |
910 | ||
911 | void restore_IO_APIC_setup(void) | |
912 | { | |
913 | int apic, pin; | |
914 | ||
5ffa4eb2 CG |
915 | for (apic = 0; apic < nr_ioapics; apic++) { |
916 | if (!early_ioapic_entries[apic]) | |
917 | break; | |
54168ed7 IM |
918 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) |
919 | ioapic_write_entry(apic, pin, | |
920 | early_ioapic_entries[apic][pin]); | |
5ffa4eb2 CG |
921 | kfree(early_ioapic_entries[apic]); |
922 | early_ioapic_entries[apic] = NULL; | |
923 | } | |
54168ed7 IM |
924 | } |
925 | ||
926 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
927 | { | |
928 | /* | |
929 | * for now plain restore of previous settings. | |
930 | * TBD: In the case of OS enabling interrupt-remapping, | |
931 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
932 | * table entries. for now, do a plain restore, and wait for | |
933 | * the setup_IO_APIC_irqs() to do proper initialization. | |
934 | */ | |
935 | restore_IO_APIC_setup(); | |
936 | } | |
937 | #endif | |
1da177e4 LT |
938 | |
939 | /* | |
940 | * Find the IRQ entry number of a certain pin. | |
941 | */ | |
942 | static int find_irq_entry(int apic, int pin, int type) | |
943 | { | |
944 | int i; | |
945 | ||
946 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
947 | if (mp_irqs[i].mp_irqtype == type && |
948 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
949 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
950 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
951 | return i; |
952 | ||
953 | return -1; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Find the pin to which IRQ[irq] (ISA) is connected | |
958 | */ | |
fcfd636a | 959 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
960 | { |
961 | int i; | |
962 | ||
963 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 964 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 965 | |
d27e2b8e | 966 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
967 | (mp_irqs[i].mp_irqtype == type) && |
968 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 969 | |
2fddb6e2 | 970 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
971 | } |
972 | return -1; | |
973 | } | |
974 | ||
fcfd636a EB |
975 | static int __init find_isa_irq_apic(int irq, int type) |
976 | { | |
977 | int i; | |
978 | ||
979 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 980 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 981 | |
73b2961b | 982 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
983 | (mp_irqs[i].mp_irqtype == type) && |
984 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
985 | break; |
986 | } | |
987 | if (i < mp_irq_entries) { | |
988 | int apic; | |
54168ed7 | 989 | for(apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 990 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
991 | return apic; |
992 | } | |
993 | } | |
994 | ||
995 | return -1; | |
996 | } | |
997 | ||
1da177e4 LT |
998 | /* |
999 | * Find a specific PCI IRQ entry. | |
1000 | * Not an __init, possibly needed by modules | |
1001 | */ | |
1002 | static int pin_2_irq(int idx, int apic, int pin); | |
1003 | ||
1004 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
1005 | { | |
1006 | int apic, i, best_guess = -1; | |
1007 | ||
54168ed7 IM |
1008 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
1009 | bus, slot, pin); | |
ce6444d3 | 1010 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 1011 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
1012 | return -1; |
1013 | } | |
1014 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 1015 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
1016 | |
1017 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
1018 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
1019 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
1020 | break; |
1021 | ||
47cab822 | 1022 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 1023 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 1024 | (bus == lbus) && |
2fddb6e2 | 1025 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
54168ed7 | 1026 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
1da177e4 LT |
1027 | |
1028 | if (!(apic || IO_APIC_IRQ(irq))) | |
1029 | continue; | |
1030 | ||
2fddb6e2 | 1031 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
1032 | return irq; |
1033 | /* | |
1034 | * Use the first all-but-pin matching entry as a | |
1035 | * best-guess fuzzy result for broken mptables. | |
1036 | */ | |
1037 | if (best_guess < 0) | |
1038 | best_guess = irq; | |
1039 | } | |
1040 | } | |
1041 | return best_guess; | |
1042 | } | |
54168ed7 | 1043 | |
129f6946 | 1044 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 1045 | |
c0a282c2 | 1046 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
1047 | /* |
1048 | * EISA Edge/Level control register, ELCR | |
1049 | */ | |
1050 | static int EISA_ELCR(unsigned int irq) | |
1051 | { | |
99d093d1 | 1052 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
1053 | unsigned int port = 0x4d0 + (irq >> 3); |
1054 | return (inb(port) >> (irq & 7)) & 1; | |
1055 | } | |
1056 | apic_printk(APIC_VERBOSE, KERN_INFO | |
1057 | "Broken MPtable reports ISA irq %d\n", irq); | |
1058 | return 0; | |
1059 | } | |
54168ed7 | 1060 | |
c0a282c2 | 1061 | #endif |
1da177e4 | 1062 | |
6728801d AS |
1063 | /* ISA interrupts are always polarity zero edge triggered, |
1064 | * when listed as conforming in the MP table. */ | |
1065 | ||
1066 | #define default_ISA_trigger(idx) (0) | |
1067 | #define default_ISA_polarity(idx) (0) | |
1068 | ||
1da177e4 LT |
1069 | /* EISA interrupts are always polarity zero and can be edge or level |
1070 | * trigger depending on the ELCR value. If an interrupt is listed as | |
1071 | * EISA conforming in the MP table, that means its trigger type must | |
1072 | * be read in from the ELCR */ | |
1073 | ||
2fddb6e2 | 1074 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 1075 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
1076 | |
1077 | /* PCI interrupts are always polarity one level triggered, | |
1078 | * when listed as conforming in the MP table. */ | |
1079 | ||
1080 | #define default_PCI_trigger(idx) (1) | |
1081 | #define default_PCI_polarity(idx) (1) | |
1082 | ||
1083 | /* MCA interrupts are always polarity zero level triggered, | |
1084 | * when listed as conforming in the MP table. */ | |
1085 | ||
1086 | #define default_MCA_trigger(idx) (1) | |
6728801d | 1087 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 1088 | |
61fd47e0 | 1089 | static int MPBIOS_polarity(int idx) |
1da177e4 | 1090 | { |
2fddb6e2 | 1091 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1092 | int polarity; |
1093 | ||
1094 | /* | |
1095 | * Determine IRQ line polarity (high active or low active): | |
1096 | */ | |
54168ed7 | 1097 | switch (mp_irqs[idx].mp_irqflag & 3) |
36062448 | 1098 | { |
54168ed7 IM |
1099 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1100 | if (test_bit(bus, mp_bus_not_pci)) | |
1101 | polarity = default_ISA_polarity(idx); | |
1102 | else | |
1103 | polarity = default_PCI_polarity(idx); | |
1104 | break; | |
1105 | case 1: /* high active */ | |
1106 | { | |
1107 | polarity = 0; | |
1108 | break; | |
1109 | } | |
1110 | case 2: /* reserved */ | |
1111 | { | |
1112 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1113 | polarity = 1; | |
1114 | break; | |
1115 | } | |
1116 | case 3: /* low active */ | |
1117 | { | |
1118 | polarity = 1; | |
1119 | break; | |
1120 | } | |
1121 | default: /* invalid */ | |
1122 | { | |
1123 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1124 | polarity = 1; | |
1125 | break; | |
1126 | } | |
1da177e4 LT |
1127 | } |
1128 | return polarity; | |
1129 | } | |
1130 | ||
1131 | static int MPBIOS_trigger(int idx) | |
1132 | { | |
2fddb6e2 | 1133 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1134 | int trigger; |
1135 | ||
1136 | /* | |
1137 | * Determine IRQ trigger mode (edge or level sensitive): | |
1138 | */ | |
54168ed7 | 1139 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 | 1140 | { |
54168ed7 IM |
1141 | case 0: /* conforms, ie. bus-type dependent */ |
1142 | if (test_bit(bus, mp_bus_not_pci)) | |
1143 | trigger = default_ISA_trigger(idx); | |
1144 | else | |
1145 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1146 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1147 | switch (mp_bus_id_to_type[bus]) { |
1148 | case MP_BUS_ISA: /* ISA pin */ | |
1149 | { | |
1150 | /* set before the switch */ | |
1151 | break; | |
1152 | } | |
1153 | case MP_BUS_EISA: /* EISA pin */ | |
1154 | { | |
1155 | trigger = default_EISA_trigger(idx); | |
1156 | break; | |
1157 | } | |
1158 | case MP_BUS_PCI: /* PCI pin */ | |
1159 | { | |
1160 | /* set before the switch */ | |
1161 | break; | |
1162 | } | |
1163 | case MP_BUS_MCA: /* MCA pin */ | |
1164 | { | |
1165 | trigger = default_MCA_trigger(idx); | |
1166 | break; | |
1167 | } | |
1168 | default: | |
1169 | { | |
1170 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1171 | trigger = 1; | |
1172 | break; | |
1173 | } | |
1174 | } | |
1175 | #endif | |
1da177e4 | 1176 | break; |
54168ed7 | 1177 | case 1: /* edge */ |
1da177e4 | 1178 | { |
54168ed7 | 1179 | trigger = 0; |
1da177e4 LT |
1180 | break; |
1181 | } | |
54168ed7 | 1182 | case 2: /* reserved */ |
1da177e4 | 1183 | { |
54168ed7 IM |
1184 | printk(KERN_WARNING "broken BIOS!!\n"); |
1185 | trigger = 1; | |
1da177e4 LT |
1186 | break; |
1187 | } | |
54168ed7 | 1188 | case 3: /* level */ |
1da177e4 | 1189 | { |
54168ed7 | 1190 | trigger = 1; |
1da177e4 LT |
1191 | break; |
1192 | } | |
54168ed7 | 1193 | default: /* invalid */ |
1da177e4 LT |
1194 | { |
1195 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1196 | trigger = 0; |
1da177e4 LT |
1197 | break; |
1198 | } | |
1199 | } | |
1200 | return trigger; | |
1201 | } | |
1202 | ||
1203 | static inline int irq_polarity(int idx) | |
1204 | { | |
1205 | return MPBIOS_polarity(idx); | |
1206 | } | |
1207 | ||
1208 | static inline int irq_trigger(int idx) | |
1209 | { | |
1210 | return MPBIOS_trigger(idx); | |
1211 | } | |
1212 | ||
efa2559f | 1213 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1214 | static int pin_2_irq(int idx, int apic, int pin) |
1215 | { | |
1216 | int irq, i; | |
2fddb6e2 | 1217 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1218 | |
1219 | /* | |
1220 | * Debugging check, we are in big trouble if this message pops up! | |
1221 | */ | |
2fddb6e2 | 1222 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1223 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1224 | ||
54168ed7 | 1225 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 1226 | irq = mp_irqs[idx].mp_srcbusirq; |
54168ed7 | 1227 | } else { |
643befed AS |
1228 | /* |
1229 | * PCI IRQs are mapped in order | |
1230 | */ | |
1231 | i = irq = 0; | |
1232 | while (i < apic) | |
1233 | irq += nr_ioapic_registers[i++]; | |
1234 | irq += pin; | |
d6c88a50 | 1235 | /* |
54168ed7 IM |
1236 | * For MPS mode, so far only needed by ES7000 platform |
1237 | */ | |
d6c88a50 TG |
1238 | if (ioapic_renumber_irq) |
1239 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1240 | } |
1241 | ||
54168ed7 | 1242 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1243 | /* |
1244 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1245 | */ | |
1246 | if ((pin >= 16) && (pin <= 23)) { | |
1247 | if (pirq_entries[pin-16] != -1) { | |
1248 | if (!pirq_entries[pin-16]) { | |
1249 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1250 | "disabling PIRQ%d\n", pin-16); | |
1251 | } else { | |
1252 | irq = pirq_entries[pin-16]; | |
1253 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1254 | "using PIRQ%d -> IRQ %d\n", | |
1255 | pin-16, irq); | |
1256 | } | |
1257 | } | |
1258 | } | |
54168ed7 IM |
1259 | #endif |
1260 | ||
1da177e4 LT |
1261 | return irq; |
1262 | } | |
1263 | ||
497c9a19 YL |
1264 | void lock_vector_lock(void) |
1265 | { | |
1266 | /* Used to the online set of cpus does not change | |
1267 | * during assign_irq_vector. | |
1268 | */ | |
1269 | spin_lock(&vector_lock); | |
1270 | } | |
1da177e4 | 1271 | |
497c9a19 | 1272 | void unlock_vector_lock(void) |
1da177e4 | 1273 | { |
497c9a19 YL |
1274 | spin_unlock(&vector_lock); |
1275 | } | |
1da177e4 | 1276 | |
e7986739 MT |
1277 | static int |
1278 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 | 1279 | { |
047c8fdb YL |
1280 | /* |
1281 | * NOTE! The local APIC isn't very good at handling | |
1282 | * multiple interrupts at the same interrupt level. | |
1283 | * As the interrupt level is determined by taking the | |
1284 | * vector number and shifting that right by 4, we | |
1285 | * want to spread these out a bit so that they don't | |
1286 | * all fall in the same interrupt level. | |
1287 | * | |
1288 | * Also, we've got to be careful not to trash gate | |
1289 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1290 | */ | |
54168ed7 IM |
1291 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1292 | unsigned int old_vector; | |
22f65d31 MT |
1293 | int cpu, err; |
1294 | cpumask_var_t tmp_mask; | |
ace80ab7 | 1295 | |
54168ed7 IM |
1296 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1297 | return -EBUSY; | |
0a1ad60d | 1298 | |
22f65d31 MT |
1299 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1300 | return -ENOMEM; | |
ace80ab7 | 1301 | |
54168ed7 IM |
1302 | old_vector = cfg->vector; |
1303 | if (old_vector) { | |
22f65d31 MT |
1304 | cpumask_and(tmp_mask, mask, cpu_online_mask); |
1305 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | |
1306 | if (!cpumask_empty(tmp_mask)) { | |
1307 | free_cpumask_var(tmp_mask); | |
54168ed7 | 1308 | return 0; |
22f65d31 | 1309 | } |
54168ed7 | 1310 | } |
497c9a19 | 1311 | |
e7986739 | 1312 | /* Only try and allocate irqs on cpus that are present */ |
22f65d31 MT |
1313 | err = -ENOSPC; |
1314 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | |
54168ed7 IM |
1315 | int new_cpu; |
1316 | int vector, offset; | |
497c9a19 | 1317 | |
22f65d31 | 1318 | vector_allocation_domain(cpu, tmp_mask); |
497c9a19 | 1319 | |
54168ed7 IM |
1320 | vector = current_vector; |
1321 | offset = current_offset; | |
497c9a19 | 1322 | next: |
54168ed7 IM |
1323 | vector += 8; |
1324 | if (vector >= first_system_vector) { | |
e7986739 | 1325 | /* If out of vectors on large boxen, must share them. */ |
54168ed7 IM |
1326 | offset = (offset + 1) % 8; |
1327 | vector = FIRST_DEVICE_VECTOR + offset; | |
1328 | } | |
1329 | if (unlikely(current_vector == vector)) | |
1330 | continue; | |
b77b881f YL |
1331 | |
1332 | if (test_bit(vector, used_vectors)) | |
54168ed7 | 1333 | goto next; |
b77b881f | 1334 | |
22f65d31 | 1335 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1336 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) |
1337 | goto next; | |
1338 | /* Found one! */ | |
1339 | current_vector = vector; | |
1340 | current_offset = offset; | |
1341 | if (old_vector) { | |
1342 | cfg->move_in_progress = 1; | |
22f65d31 | 1343 | cpumask_copy(cfg->old_domain, cfg->domain); |
7a959cff | 1344 | } |
22f65d31 | 1345 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
54168ed7 IM |
1346 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
1347 | cfg->vector = vector; | |
22f65d31 MT |
1348 | cpumask_copy(cfg->domain, tmp_mask); |
1349 | err = 0; | |
1350 | break; | |
54168ed7 | 1351 | } |
22f65d31 MT |
1352 | free_cpumask_var(tmp_mask); |
1353 | return err; | |
497c9a19 YL |
1354 | } |
1355 | ||
e7986739 MT |
1356 | static int |
1357 | assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
497c9a19 YL |
1358 | { |
1359 | int err; | |
ace80ab7 | 1360 | unsigned long flags; |
ace80ab7 EB |
1361 | |
1362 | spin_lock_irqsave(&vector_lock, flags); | |
3145e941 | 1363 | err = __assign_irq_vector(irq, cfg, mask); |
26a3c49c | 1364 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1365 | return err; |
1366 | } | |
1367 | ||
3145e941 | 1368 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
497c9a19 | 1369 | { |
497c9a19 YL |
1370 | int cpu, vector; |
1371 | ||
497c9a19 YL |
1372 | BUG_ON(!cfg->vector); |
1373 | ||
1374 | vector = cfg->vector; | |
22f65d31 | 1375 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
497c9a19 YL |
1376 | per_cpu(vector_irq, cpu)[vector] = -1; |
1377 | ||
1378 | cfg->vector = 0; | |
22f65d31 | 1379 | cpumask_clear(cfg->domain); |
0ca4b6b0 MW |
1380 | |
1381 | if (likely(!cfg->move_in_progress)) | |
1382 | return; | |
22f65d31 | 1383 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
0ca4b6b0 MW |
1384 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
1385 | vector++) { | |
1386 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
1387 | continue; | |
1388 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1389 | break; | |
1390 | } | |
1391 | } | |
1392 | cfg->move_in_progress = 0; | |
497c9a19 YL |
1393 | } |
1394 | ||
1395 | void __setup_vector_irq(int cpu) | |
1396 | { | |
1397 | /* Initialize vector_irq on a new cpu */ | |
1398 | /* This function must be called with vector_lock held */ | |
1399 | int irq, vector; | |
1400 | struct irq_cfg *cfg; | |
0b8f1efa | 1401 | struct irq_desc *desc; |
497c9a19 YL |
1402 | |
1403 | /* Mark the inuse vectors */ | |
0b8f1efa | 1404 | for_each_irq_desc(irq, desc) { |
0b8f1efa | 1405 | cfg = desc->chip_data; |
22f65d31 | 1406 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 YL |
1407 | continue; |
1408 | vector = cfg->vector; | |
497c9a19 YL |
1409 | per_cpu(vector_irq, cpu)[vector] = irq; |
1410 | } | |
1411 | /* Mark the free vectors */ | |
1412 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1413 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1414 | if (irq < 0) | |
1415 | continue; | |
1416 | ||
1417 | cfg = irq_cfg(irq); | |
22f65d31 | 1418 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
497c9a19 | 1419 | per_cpu(vector_irq, cpu)[vector] = -1; |
54168ed7 | 1420 | } |
1da177e4 | 1421 | } |
3fde6900 | 1422 | |
f5b9ed7a | 1423 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1424 | #ifdef CONFIG_INTR_REMAP |
1425 | static struct irq_chip ir_ioapic_chip; | |
1426 | #endif | |
1da177e4 | 1427 | |
54168ed7 IM |
1428 | #define IOAPIC_AUTO -1 |
1429 | #define IOAPIC_EDGE 0 | |
1430 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1431 | |
047c8fdb | 1432 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1433 | static inline int IO_APIC_irq_trigger(int irq) |
1434 | { | |
d6c88a50 | 1435 | int apic, idx, pin; |
1d025192 | 1436 | |
d6c88a50 TG |
1437 | for (apic = 0; apic < nr_ioapics; apic++) { |
1438 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1439 | idx = find_irq_entry(apic, pin, mp_INT); | |
1440 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1441 | return irq_trigger(idx); | |
1442 | } | |
1443 | } | |
1444 | /* | |
54168ed7 IM |
1445 | * nonexistent IRQs are edge default |
1446 | */ | |
d6c88a50 | 1447 | return 0; |
1d025192 | 1448 | } |
047c8fdb YL |
1449 | #else |
1450 | static inline int IO_APIC_irq_trigger(int irq) | |
1451 | { | |
54168ed7 | 1452 | return 1; |
047c8fdb YL |
1453 | } |
1454 | #endif | |
1d025192 | 1455 | |
3145e941 | 1456 | static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger) |
1da177e4 | 1457 | { |
199751d7 | 1458 | |
6ebcc00e | 1459 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1460 | trigger == IOAPIC_LEVEL) |
08678b08 | 1461 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1462 | else |
1463 | desc->status &= ~IRQ_LEVEL; | |
1464 | ||
54168ed7 IM |
1465 | #ifdef CONFIG_INTR_REMAP |
1466 | if (irq_remapped(irq)) { | |
1467 | desc->status |= IRQ_MOVE_PCNTXT; | |
1468 | if (trigger) | |
1469 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1470 | handle_fasteoi_irq, | |
1471 | "fasteoi"); | |
1472 | else | |
1473 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1474 | handle_edge_irq, "edge"); | |
1475 | return; | |
1476 | } | |
1477 | #endif | |
047c8fdb YL |
1478 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1479 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1480 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1481 | handle_fasteoi_irq, |
1482 | "fasteoi"); | |
047c8fdb | 1483 | else |
a460e745 | 1484 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1485 | handle_edge_irq, "edge"); |
1da177e4 LT |
1486 | } |
1487 | ||
497c9a19 YL |
1488 | static int setup_ioapic_entry(int apic, int irq, |
1489 | struct IO_APIC_route_entry *entry, | |
1490 | unsigned int destination, int trigger, | |
1491 | int polarity, int vector) | |
1da177e4 | 1492 | { |
497c9a19 YL |
1493 | /* |
1494 | * add it to the IO-APIC irq-routing table: | |
1495 | */ | |
1496 | memset(entry,0,sizeof(*entry)); | |
1497 | ||
54168ed7 IM |
1498 | #ifdef CONFIG_INTR_REMAP |
1499 | if (intr_remapping_enabled) { | |
1500 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1501 | struct irte irte; | |
1502 | struct IR_IO_APIC_route_entry *ir_entry = | |
1503 | (struct IR_IO_APIC_route_entry *) entry; | |
1504 | int index; | |
1505 | ||
1506 | if (!iommu) | |
1507 | panic("No mapping iommu for ioapic %d\n", apic); | |
1508 | ||
1509 | index = alloc_irte(iommu, irq, 1); | |
1510 | if (index < 0) | |
1511 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1512 | ||
1513 | memset(&irte, 0, sizeof(irte)); | |
1514 | ||
1515 | irte.present = 1; | |
1516 | irte.dst_mode = INT_DEST_MODE; | |
1517 | irte.trigger_mode = trigger; | |
1518 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1519 | irte.vector = vector; | |
1520 | irte.dest_id = IRTE_DEST(destination); | |
1521 | ||
1522 | modify_irte(irq, &irte); | |
1523 | ||
1524 | ir_entry->index2 = (index >> 15) & 0x1; | |
1525 | ir_entry->zero = 0; | |
1526 | ir_entry->format = 1; | |
1527 | ir_entry->index = (index & 0x7fff); | |
1528 | } else | |
1529 | #endif | |
1530 | { | |
1531 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1532 | entry->dest_mode = INT_DEST_MODE; | |
1533 | entry->dest = destination; | |
1534 | } | |
497c9a19 | 1535 | |
54168ed7 | 1536 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1537 | entry->trigger = trigger; |
1538 | entry->polarity = polarity; | |
1539 | entry->vector = vector; | |
1540 | ||
1541 | /* Mask level triggered irqs. | |
1542 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1543 | */ | |
1544 | if (trigger) | |
1545 | entry->mask = 1; | |
497c9a19 YL |
1546 | return 0; |
1547 | } | |
1548 | ||
3145e941 | 1549 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_desc *desc, |
54168ed7 | 1550 | int trigger, int polarity) |
497c9a19 YL |
1551 | { |
1552 | struct irq_cfg *cfg; | |
1da177e4 | 1553 | struct IO_APIC_route_entry entry; |
22f65d31 | 1554 | unsigned int dest; |
497c9a19 YL |
1555 | |
1556 | if (!IO_APIC_IRQ(irq)) | |
1557 | return; | |
1558 | ||
3145e941 | 1559 | cfg = desc->chip_data; |
497c9a19 | 1560 | |
22f65d31 | 1561 | if (assign_irq_vector(irq, cfg, TARGET_CPUS)) |
497c9a19 YL |
1562 | return; |
1563 | ||
22f65d31 | 1564 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
497c9a19 YL |
1565 | |
1566 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1567 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1568 | "IRQ %d Mode:%i Active:%i)\n", | |
1569 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1570 | irq, trigger, polarity); | |
1571 | ||
1572 | ||
1573 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
22f65d31 | 1574 | dest, trigger, polarity, cfg->vector)) { |
497c9a19 YL |
1575 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
1576 | mp_ioapics[apic].mp_apicid, pin); | |
3145e941 | 1577 | __clear_irq_vector(irq, cfg); |
497c9a19 YL |
1578 | return; |
1579 | } | |
1580 | ||
3145e941 | 1581 | ioapic_register_intr(irq, desc, trigger); |
99d093d1 | 1582 | if (irq < NR_IRQS_LEGACY) |
497c9a19 YL |
1583 | disable_8259A_irq(irq); |
1584 | ||
1585 | ioapic_write_entry(apic, pin, entry); | |
1586 | } | |
1587 | ||
1588 | static void __init setup_IO_APIC_irqs(void) | |
1589 | { | |
3c2cbd24 CG |
1590 | int apic, pin, idx, irq; |
1591 | int notcon = 0; | |
0b8f1efa | 1592 | struct irq_desc *desc; |
3145e941 | 1593 | struct irq_cfg *cfg; |
0b8f1efa | 1594 | int cpu = boot_cpu_id; |
1da177e4 LT |
1595 | |
1596 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1597 | ||
1598 | for (apic = 0; apic < nr_ioapics; apic++) { | |
3c2cbd24 | 1599 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
20d225b9 | 1600 | |
3c2cbd24 CG |
1601 | idx = find_irq_entry(apic, pin, mp_INT); |
1602 | if (idx == -1) { | |
2a554fb1 | 1603 | if (!notcon) { |
3c2cbd24 | 1604 | notcon = 1; |
2a554fb1 CG |
1605 | apic_printk(APIC_VERBOSE, |
1606 | KERN_DEBUG " %d-%d", | |
1607 | mp_ioapics[apic].mp_apicid, | |
1608 | pin); | |
1609 | } else | |
1610 | apic_printk(APIC_VERBOSE, " %d-%d", | |
1611 | mp_ioapics[apic].mp_apicid, | |
1612 | pin); | |
3c2cbd24 CG |
1613 | continue; |
1614 | } | |
56ffa1a0 CG |
1615 | if (notcon) { |
1616 | apic_printk(APIC_VERBOSE, | |
1617 | " (apicid-pin) not connected\n"); | |
1618 | notcon = 0; | |
1619 | } | |
3c2cbd24 CG |
1620 | |
1621 | irq = pin_2_irq(idx, apic, pin); | |
54168ed7 | 1622 | #ifdef CONFIG_X86_32 |
3c2cbd24 CG |
1623 | if (multi_timer_check(apic, irq)) |
1624 | continue; | |
54168ed7 | 1625 | #endif |
0b8f1efa YL |
1626 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
1627 | if (!desc) { | |
1628 | printk(KERN_INFO "can not get irq_desc for %d\n", irq); | |
1629 | continue; | |
1630 | } | |
3145e941 YL |
1631 | cfg = desc->chip_data; |
1632 | add_pin_to_irq_cpu(cfg, cpu, apic, pin); | |
36062448 | 1633 | |
3145e941 | 1634 | setup_IO_APIC_irq(apic, pin, irq, desc, |
3c2cbd24 CG |
1635 | irq_trigger(idx), irq_polarity(idx)); |
1636 | } | |
1da177e4 LT |
1637 | } |
1638 | ||
3c2cbd24 CG |
1639 | if (notcon) |
1640 | apic_printk(APIC_VERBOSE, | |
2a554fb1 | 1641 | " (apicid-pin) not connected\n"); |
1da177e4 LT |
1642 | } |
1643 | ||
1644 | /* | |
f7633ce5 | 1645 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1646 | */ |
f7633ce5 MR |
1647 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1648 | int vector) | |
1da177e4 LT |
1649 | { |
1650 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1651 | |
54168ed7 IM |
1652 | #ifdef CONFIG_INTR_REMAP |
1653 | if (intr_remapping_enabled) | |
1654 | return; | |
1655 | #endif | |
1656 | ||
36062448 | 1657 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1658 | |
1659 | /* | |
1660 | * We use logical delivery to get the timer IRQ | |
1661 | * to the first CPU. | |
1662 | */ | |
1663 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1664 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1665 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1666 | entry.delivery_mode = INT_DELIVERY_MODE; |
1667 | entry.polarity = 0; | |
1668 | entry.trigger = 0; | |
1669 | entry.vector = vector; | |
1670 | ||
1671 | /* | |
1672 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1673 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1674 | */ |
54168ed7 | 1675 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1676 | |
1677 | /* | |
1678 | * Add it to the IO-APIC irq-routing table: | |
1679 | */ | |
cf4c6a2f | 1680 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1681 | } |
1682 | ||
32f71aff MR |
1683 | |
1684 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1685 | { |
1686 | int apic, i; | |
1687 | union IO_APIC_reg_00 reg_00; | |
1688 | union IO_APIC_reg_01 reg_01; | |
1689 | union IO_APIC_reg_02 reg_02; | |
1690 | union IO_APIC_reg_03 reg_03; | |
1691 | unsigned long flags; | |
0f978f45 | 1692 | struct irq_cfg *cfg; |
0b8f1efa | 1693 | struct irq_desc *desc; |
8f09cd20 | 1694 | unsigned int irq; |
1da177e4 LT |
1695 | |
1696 | if (apic_verbosity == APIC_QUIET) | |
1697 | return; | |
1698 | ||
36062448 | 1699 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1700 | for (i = 0; i < nr_ioapics; i++) |
1701 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1702 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1703 | |
1704 | /* | |
1705 | * We are a bit conservative about what we expect. We have to | |
1706 | * know about every hardware change ASAP. | |
1707 | */ | |
1708 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1709 | ||
1710 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1711 | ||
1712 | spin_lock_irqsave(&ioapic_lock, flags); | |
1713 | reg_00.raw = io_apic_read(apic, 0); | |
1714 | reg_01.raw = io_apic_read(apic, 1); | |
1715 | if (reg_01.bits.version >= 0x10) | |
1716 | reg_02.raw = io_apic_read(apic, 2); | |
d6c88a50 TG |
1717 | if (reg_01.bits.version >= 0x20) |
1718 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1719 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1720 | ||
54168ed7 | 1721 | printk("\n"); |
ec2cd0a2 | 1722 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1723 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1724 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1725 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1726 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1727 | |
54168ed7 | 1728 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1729 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1730 | |
1731 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1732 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1733 | |
1734 | /* | |
1735 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1736 | * but the value of reg_02 is read as the previous read register | |
1737 | * value, so ignore it if reg_02 == reg_01. | |
1738 | */ | |
1739 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1740 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1741 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1742 | } |
1743 | ||
1744 | /* | |
1745 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1746 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1747 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1748 | */ | |
1749 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1750 | reg_03.raw != reg_01.raw) { | |
1751 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1752 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1753 | } |
1754 | ||
1755 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1756 | ||
d83e94ac YL |
1757 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1758 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1759 | |
1760 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1761 | struct IO_APIC_route_entry entry; | |
1762 | ||
cf4c6a2f | 1763 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1764 | |
54168ed7 IM |
1765 | printk(KERN_DEBUG " %02x %03X ", |
1766 | i, | |
1767 | entry.dest | |
1768 | ); | |
1da177e4 LT |
1769 | |
1770 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1771 | entry.mask, | |
1772 | entry.trigger, | |
1773 | entry.irr, | |
1774 | entry.polarity, | |
1775 | entry.delivery_status, | |
1776 | entry.dest_mode, | |
1777 | entry.delivery_mode, | |
1778 | entry.vector | |
1779 | ); | |
1780 | } | |
1781 | } | |
1da177e4 | 1782 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0b8f1efa YL |
1783 | for_each_irq_desc(irq, desc) { |
1784 | struct irq_pin_list *entry; | |
1785 | ||
0b8f1efa YL |
1786 | cfg = desc->chip_data; |
1787 | entry = cfg->irq_2_pin; | |
0f978f45 | 1788 | if (!entry) |
1da177e4 | 1789 | continue; |
8f09cd20 | 1790 | printk(KERN_DEBUG "IRQ%d ", irq); |
1da177e4 LT |
1791 | for (;;) { |
1792 | printk("-> %d:%d", entry->apic, entry->pin); | |
1793 | if (!entry->next) | |
1794 | break; | |
0f978f45 | 1795 | entry = entry->next; |
1da177e4 LT |
1796 | } |
1797 | printk("\n"); | |
1798 | } | |
1799 | ||
1800 | printk(KERN_INFO ".................................... done.\n"); | |
1801 | ||
1802 | return; | |
1803 | } | |
1804 | ||
32f71aff | 1805 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1806 | { |
1807 | unsigned int v; | |
1808 | int i, j; | |
1809 | ||
1810 | if (apic_verbosity == APIC_QUIET) | |
1811 | return; | |
1812 | ||
1813 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1814 | for (i = 0; i < 8; i++) { | |
1815 | v = apic_read(base + i*0x10); | |
1816 | for (j = 0; j < 32; j++) { | |
1817 | if (v & (1<<j)) | |
1818 | printk("1"); | |
1819 | else | |
1820 | printk("0"); | |
1821 | } | |
1822 | printk("\n"); | |
1823 | } | |
1824 | } | |
1825 | ||
32f71aff | 1826 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1827 | { |
1828 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1829 | u64 icr; |
1da177e4 LT |
1830 | |
1831 | if (apic_verbosity == APIC_QUIET) | |
1832 | return; | |
1833 | ||
1834 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1835 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1836 | v = apic_read(APIC_ID); |
54168ed7 | 1837 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1838 | v = apic_read(APIC_LVR); |
1839 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1840 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1841 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1842 | |
1843 | v = apic_read(APIC_TASKPRI); | |
1844 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1845 | ||
54168ed7 | 1846 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
a11b5abe YL |
1847 | if (!APIC_XAPIC(ver)) { |
1848 | v = apic_read(APIC_ARBPRI); | |
1849 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1850 | v & APIC_ARBPRI_MASK); | |
1851 | } | |
1da177e4 LT |
1852 | v = apic_read(APIC_PROCPRI); |
1853 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1854 | } | |
1855 | ||
a11b5abe YL |
1856 | /* |
1857 | * Remote read supported only in the 82489DX and local APIC for | |
1858 | * Pentium processors. | |
1859 | */ | |
1860 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
1861 | v = apic_read(APIC_RRR); | |
1862 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1863 | } | |
1864 | ||
1da177e4 LT |
1865 | v = apic_read(APIC_LDR); |
1866 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
a11b5abe YL |
1867 | if (!x2apic_enabled()) { |
1868 | v = apic_read(APIC_DFR); | |
1869 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1870 | } | |
1da177e4 LT |
1871 | v = apic_read(APIC_SPIV); |
1872 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1873 | ||
1874 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1875 | print_APIC_bitfield(APIC_ISR); | |
1876 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1877 | print_APIC_bitfield(APIC_TMR); | |
1878 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1879 | print_APIC_bitfield(APIC_IRR); | |
1880 | ||
54168ed7 IM |
1881 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1882 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1883 | apic_write(APIC_ESR, 0); |
54168ed7 | 1884 | |
1da177e4 LT |
1885 | v = apic_read(APIC_ESR); |
1886 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1887 | } | |
1888 | ||
7ab6af7a | 1889 | icr = apic_icr_read(); |
0c425cec IM |
1890 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
1891 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
1da177e4 LT |
1892 | |
1893 | v = apic_read(APIC_LVTT); | |
1894 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1895 | ||
1896 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1897 | v = apic_read(APIC_LVTPC); | |
1898 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1899 | } | |
1900 | v = apic_read(APIC_LVT0); | |
1901 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1902 | v = apic_read(APIC_LVT1); | |
1903 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1904 | ||
1905 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1906 | v = apic_read(APIC_LVTERR); | |
1907 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1908 | } | |
1909 | ||
1910 | v = apic_read(APIC_TMICT); | |
1911 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1912 | v = apic_read(APIC_TMCCT); | |
1913 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1914 | v = apic_read(APIC_TDCR); | |
1915 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1916 | printk("\n"); | |
1917 | } | |
1918 | ||
32f71aff | 1919 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1920 | { |
ffd5aae7 YL |
1921 | int cpu; |
1922 | ||
1923 | preempt_disable(); | |
1924 | for_each_online_cpu(cpu) | |
1925 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1926 | preempt_enable(); | |
1da177e4 LT |
1927 | } |
1928 | ||
32f71aff | 1929 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1930 | { |
1da177e4 LT |
1931 | unsigned int v; |
1932 | unsigned long flags; | |
1933 | ||
1934 | if (apic_verbosity == APIC_QUIET) | |
1935 | return; | |
1936 | ||
1937 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1938 | ||
1939 | spin_lock_irqsave(&i8259A_lock, flags); | |
1940 | ||
1941 | v = inb(0xa1) << 8 | inb(0x21); | |
1942 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1943 | ||
1944 | v = inb(0xa0) << 8 | inb(0x20); | |
1945 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1946 | ||
54168ed7 IM |
1947 | outb(0x0b,0xa0); |
1948 | outb(0x0b,0x20); | |
1da177e4 | 1949 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1950 | outb(0x0a,0xa0); |
1951 | outb(0x0a,0x20); | |
1da177e4 LT |
1952 | |
1953 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1954 | ||
1955 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1956 | ||
1957 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1958 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1959 | } | |
1960 | ||
32f71aff MR |
1961 | __apicdebuginit(int) print_all_ICs(void) |
1962 | { | |
1963 | print_PIC(); | |
1964 | print_all_local_APICs(); | |
1965 | print_IO_APIC(); | |
1966 | ||
1967 | return 0; | |
1968 | } | |
1969 | ||
1970 | fs_initcall(print_all_ICs); | |
1971 | ||
1da177e4 | 1972 | |
efa2559f YL |
1973 | /* Where if anywhere is the i8259 connect in external int mode */ |
1974 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1975 | ||
54168ed7 | 1976 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1977 | { |
1978 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1979 | int i8259_apic, i8259_pin; |
54168ed7 | 1980 | int apic; |
1da177e4 LT |
1981 | unsigned long flags; |
1982 | ||
54168ed7 IM |
1983 | #ifdef CONFIG_X86_32 |
1984 | int i; | |
1da177e4 LT |
1985 | if (!pirqs_enabled) |
1986 | for (i = 0; i < MAX_PIRQS; i++) | |
1987 | pirq_entries[i] = -1; | |
54168ed7 | 1988 | #endif |
1da177e4 LT |
1989 | |
1990 | /* | |
1991 | * The number of IO-APIC IRQ registers (== #pins): | |
1992 | */ | |
fcfd636a | 1993 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1994 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1995 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1996 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1997 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1998 | } | |
54168ed7 | 1999 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
2000 | int pin; |
2001 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 2002 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 2003 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 2004 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 2005 | |
fcfd636a EB |
2006 | /* If the interrupt line is enabled and in ExtInt mode |
2007 | * I have found the pin where the i8259 is connected. | |
2008 | */ | |
2009 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
2010 | ioapic_i8259.apic = apic; | |
2011 | ioapic_i8259.pin = pin; | |
2012 | goto found_i8259; | |
2013 | } | |
2014 | } | |
2015 | } | |
2016 | found_i8259: | |
2017 | /* Look to see what if the MP table has reported the ExtINT */ | |
2018 | /* If we could not find the appropriate pin by looking at the ioapic | |
2019 | * the i8259 probably is not connected the ioapic but give the | |
2020 | * mptable a chance anyway. | |
2021 | */ | |
2022 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
2023 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
2024 | /* Trust the MP table if nothing is setup in the hardware */ | |
2025 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
2026 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
2027 | ioapic_i8259.pin = i8259_pin; | |
2028 | ioapic_i8259.apic = i8259_apic; | |
2029 | } | |
2030 | /* Complain if the MP table and the hardware disagree */ | |
2031 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
2032 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
2033 | { | |
2034 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
2035 | } |
2036 | ||
2037 | /* | |
2038 | * Do not trust the IO-APIC being empty at bootup | |
2039 | */ | |
2040 | clear_IO_APIC(); | |
2041 | } | |
2042 | ||
2043 | /* | |
2044 | * Not an __init, needed by the reboot code | |
2045 | */ | |
2046 | void disable_IO_APIC(void) | |
2047 | { | |
2048 | /* | |
2049 | * Clear the IO-APIC before rebooting: | |
2050 | */ | |
2051 | clear_IO_APIC(); | |
2052 | ||
650927ef | 2053 | /* |
0b968d23 | 2054 | * If the i8259 is routed through an IOAPIC |
650927ef | 2055 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 2056 | * so legacy interrupts can be delivered. |
650927ef | 2057 | */ |
fcfd636a | 2058 | if (ioapic_i8259.pin != -1) { |
650927ef | 2059 | struct IO_APIC_route_entry entry; |
650927ef EB |
2060 | |
2061 | memset(&entry, 0, sizeof(entry)); | |
2062 | entry.mask = 0; /* Enabled */ | |
2063 | entry.trigger = 0; /* Edge */ | |
2064 | entry.irr = 0; | |
2065 | entry.polarity = 0; /* High */ | |
2066 | entry.delivery_status = 0; | |
2067 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 2068 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 2069 | entry.vector = 0; |
54168ed7 | 2070 | entry.dest = read_apic_id(); |
650927ef EB |
2071 | |
2072 | /* | |
2073 | * Add it to the IO-APIC irq-routing table: | |
2074 | */ | |
cf4c6a2f | 2075 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 2076 | } |
54168ed7 | 2077 | |
fcfd636a | 2078 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
2079 | } |
2080 | ||
54168ed7 | 2081 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
2082 | /* |
2083 | * function to set the IO-APIC physical IDs based on the | |
2084 | * values stored in the MPC table. | |
2085 | * | |
2086 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
2087 | */ | |
2088 | ||
1da177e4 LT |
2089 | static void __init setup_ioapic_ids_from_mpc(void) |
2090 | { | |
2091 | union IO_APIC_reg_00 reg_00; | |
2092 | physid_mask_t phys_id_present_map; | |
2093 | int apic; | |
2094 | int i; | |
2095 | unsigned char old_id; | |
2096 | unsigned long flags; | |
2097 | ||
a4dbc34d | 2098 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 2099 | return; |
d49c4288 | 2100 | |
ca05fea6 NP |
2101 | /* |
2102 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
2103 | * no meaning without the serial APIC bus. | |
2104 | */ | |
7c5c1e42 SL |
2105 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2106 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 2107 | return; |
1da177e4 LT |
2108 | /* |
2109 | * This is broken; anything with a real cpu count has to | |
2110 | * circumvent this idiocy regardless. | |
2111 | */ | |
2112 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2113 | ||
2114 | /* | |
2115 | * Set the IOAPIC ID to the value stored in the MPC table. | |
2116 | */ | |
2117 | for (apic = 0; apic < nr_ioapics; apic++) { | |
2118 | ||
2119 | /* Read the register 0 value */ | |
2120 | spin_lock_irqsave(&ioapic_lock, flags); | |
2121 | reg_00.raw = io_apic_read(apic, 0); | |
2122 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 2123 | |
ec2cd0a2 | 2124 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2125 | |
ec2cd0a2 | 2126 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 2127 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 2128 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2129 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
2130 | reg_00.bits.ID); | |
ec2cd0a2 | 2131 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
2132 | } |
2133 | ||
1da177e4 LT |
2134 | /* |
2135 | * Sanity check, is the ID really free? Every APIC in a | |
2136 | * system must have a unique ID or we get lots of nice | |
2137 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
2138 | */ | |
2139 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 2140 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 2141 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 2142 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2143 | for (i = 0; i < get_physical_broadcast(); i++) |
2144 | if (!physid_isset(i, phys_id_present_map)) | |
2145 | break; | |
2146 | if (i >= get_physical_broadcast()) | |
2147 | panic("Max APIC ID exceeded!\n"); | |
2148 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2149 | i); | |
2150 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 2151 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
2152 | } else { |
2153 | physid_mask_t tmp; | |
ec2cd0a2 | 2154 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2155 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2156 | "phys_id_present_map\n", | |
ec2cd0a2 | 2157 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2158 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2159 | } | |
2160 | ||
2161 | ||
2162 | /* | |
2163 | * We need to adjust the IRQ routing table | |
2164 | * if the ID changed. | |
2165 | */ | |
ec2cd0a2 | 2166 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 2167 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
2168 | if (mp_irqs[i].mp_dstapic == old_id) |
2169 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 2170 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
2171 | |
2172 | /* | |
2173 | * Read the right value from the MPC table and | |
2174 | * write it into the ID register. | |
36062448 | 2175 | */ |
1da177e4 LT |
2176 | apic_printk(APIC_VERBOSE, KERN_INFO |
2177 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 2178 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 2179 | |
ec2cd0a2 | 2180 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2181 | spin_lock_irqsave(&ioapic_lock, flags); |
a2d332fa YL |
2182 | io_apic_write(apic, 0, reg_00.raw); |
2183 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1da177e4 LT |
2184 | |
2185 | /* | |
2186 | * Sanity check | |
2187 | */ | |
2188 | spin_lock_irqsave(&ioapic_lock, flags); | |
2189 | reg_00.raw = io_apic_read(apic, 0); | |
2190 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 2191 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
2192 | printk("could not set ID!\n"); |
2193 | else | |
2194 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2195 | } | |
2196 | } | |
54168ed7 | 2197 | #endif |
1da177e4 | 2198 | |
7ce0bcfd | 2199 | int no_timer_check __initdata; |
8542b200 ZA |
2200 | |
2201 | static int __init notimercheck(char *s) | |
2202 | { | |
2203 | no_timer_check = 1; | |
2204 | return 1; | |
2205 | } | |
2206 | __setup("no_timer_check", notimercheck); | |
2207 | ||
1da177e4 LT |
2208 | /* |
2209 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2210 | * about the timer IRQ. We do the following to work around the situation: | |
2211 | * | |
2212 | * - timer IRQ defaults to IO-APIC IRQ | |
2213 | * - if this function detects that timer IRQs are defunct, then we fall | |
2214 | * back to ISA timer IRQs | |
2215 | */ | |
f0a7a5c9 | 2216 | static int __init timer_irq_works(void) |
1da177e4 LT |
2217 | { |
2218 | unsigned long t1 = jiffies; | |
4aae0702 | 2219 | unsigned long flags; |
1da177e4 | 2220 | |
8542b200 ZA |
2221 | if (no_timer_check) |
2222 | return 1; | |
2223 | ||
4aae0702 | 2224 | local_save_flags(flags); |
1da177e4 LT |
2225 | local_irq_enable(); |
2226 | /* Let ten ticks pass... */ | |
2227 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2228 | local_irq_restore(flags); |
1da177e4 LT |
2229 | |
2230 | /* | |
2231 | * Expect a few ticks at least, to be sure some possible | |
2232 | * glue logic does not lock up after one or two first | |
2233 | * ticks in a non-ExtINT mode. Also the local APIC | |
2234 | * might have cached one ExtINT interrupt. Finally, at | |
2235 | * least one tick may be lost due to delays. | |
2236 | */ | |
54168ed7 IM |
2237 | |
2238 | /* jiffies wrap? */ | |
1d16b53e | 2239 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2240 | return 1; |
1da177e4 LT |
2241 | return 0; |
2242 | } | |
2243 | ||
2244 | /* | |
2245 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2246 | * number of pending IRQ events unhandled. These cases are very rare, | |
2247 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2248 | * better to do it this way as thus we do not have to be aware of | |
2249 | * 'pending' interrupts in the IRQ path, except at this point. | |
2250 | */ | |
2251 | /* | |
2252 | * Edge triggered needs to resend any interrupt | |
2253 | * that was delayed but this is now handled in the device | |
2254 | * independent code. | |
2255 | */ | |
2256 | ||
2257 | /* | |
2258 | * Starting up a edge-triggered IO-APIC interrupt is | |
2259 | * nasty - we need to make sure that we get the edge. | |
2260 | * If it is already asserted for some reason, we need | |
2261 | * return 1 to indicate that is was pending. | |
2262 | * | |
2263 | * This is not complete - we should be able to fake | |
2264 | * an edge even if it isn't on the 8259A... | |
2265 | */ | |
54168ed7 | 2266 | |
f5b9ed7a | 2267 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2268 | { |
2269 | int was_pending = 0; | |
2270 | unsigned long flags; | |
0b8f1efa | 2271 | struct irq_cfg *cfg; |
1da177e4 LT |
2272 | |
2273 | spin_lock_irqsave(&ioapic_lock, flags); | |
99d093d1 | 2274 | if (irq < NR_IRQS_LEGACY) { |
1da177e4 LT |
2275 | disable_8259A_irq(irq); |
2276 | if (i8259A_irq_pending(irq)) | |
2277 | was_pending = 1; | |
2278 | } | |
0b8f1efa | 2279 | cfg = irq_cfg(irq); |
3145e941 | 2280 | __unmask_IO_APIC_irq(cfg); |
1da177e4 LT |
2281 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2282 | ||
2283 | return was_pending; | |
2284 | } | |
2285 | ||
54168ed7 | 2286 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2287 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2288 | { |
54168ed7 IM |
2289 | |
2290 | struct irq_cfg *cfg = irq_cfg(irq); | |
2291 | unsigned long flags; | |
2292 | ||
2293 | spin_lock_irqsave(&vector_lock, flags); | |
22f65d31 | 2294 | send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); |
54168ed7 | 2295 | spin_unlock_irqrestore(&vector_lock, flags); |
c0ad90a3 IM |
2296 | |
2297 | return 1; | |
2298 | } | |
54168ed7 IM |
2299 | #else |
2300 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2301 | { |
d6c88a50 | 2302 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2303 | |
d6c88a50 | 2304 | return 1; |
54168ed7 IM |
2305 | } |
2306 | #endif | |
497c9a19 | 2307 | |
54168ed7 IM |
2308 | /* |
2309 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2310 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2311 | * handled with the level-triggered descriptor, but that one has slightly | |
2312 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2313 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2314 | * races. | |
2315 | */ | |
497c9a19 | 2316 | |
54168ed7 | 2317 | #ifdef CONFIG_SMP |
497c9a19 | 2318 | |
54168ed7 IM |
2319 | #ifdef CONFIG_INTR_REMAP |
2320 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2321 | |
54168ed7 | 2322 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2323 | |
54168ed7 IM |
2324 | /* |
2325 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2326 | * | |
2327 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2328 | * and cpu destination) of IRTE and flush the hardware cache. | |
2329 | * | |
2330 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2331 | * vector information, along with modifying IRTE with vector and destination. | |
2332 | * So irq migration for level triggered is little bit more complex compared to | |
2333 | * edge triggered migration. But the good news is, we use the same algorithm | |
2334 | * for level triggered migration as we have today, only difference being, | |
2335 | * we now initiate the irq migration from process context instead of the | |
2336 | * interrupt context. | |
2337 | * | |
2338 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2339 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2340 | * as simple as edge triggered migration and we can do the irq migration | |
2341 | * with a simple atomic update to IO-APIC RTE. | |
2342 | */ | |
e7986739 MT |
2343 | static void |
2344 | migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask) | |
497c9a19 | 2345 | { |
54168ed7 | 2346 | struct irq_cfg *cfg; |
54168ed7 IM |
2347 | struct irte irte; |
2348 | int modify_ioapic_rte; | |
2349 | unsigned int dest; | |
2350 | unsigned long flags; | |
3145e941 | 2351 | unsigned int irq; |
497c9a19 | 2352 | |
22f65d31 | 2353 | if (!cpumask_intersects(mask, cpu_online_mask)) |
497c9a19 YL |
2354 | return; |
2355 | ||
3145e941 | 2356 | irq = desc->irq; |
54168ed7 IM |
2357 | if (get_irte(irq, &irte)) |
2358 | return; | |
497c9a19 | 2359 | |
3145e941 YL |
2360 | cfg = desc->chip_data; |
2361 | if (assign_irq_vector(irq, cfg, mask)) | |
54168ed7 IM |
2362 | return; |
2363 | ||
3145e941 YL |
2364 | set_extra_move_desc(desc, mask); |
2365 | ||
22f65d31 | 2366 | dest = cpu_mask_to_apicid_and(cfg->domain, mask); |
54168ed7 | 2367 | |
54168ed7 IM |
2368 | modify_ioapic_rte = desc->status & IRQ_LEVEL; |
2369 | if (modify_ioapic_rte) { | |
2370 | spin_lock_irqsave(&ioapic_lock, flags); | |
3145e941 | 2371 | __target_IO_APIC_irq(irq, dest, cfg); |
54168ed7 IM |
2372 | spin_unlock_irqrestore(&ioapic_lock, flags); |
2373 | } | |
2374 | ||
2375 | irte.vector = cfg->vector; | |
2376 | irte.dest_id = IRTE_DEST(dest); | |
2377 | ||
2378 | /* | |
2379 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2380 | */ | |
2381 | modify_irte(irq, &irte); | |
2382 | ||
22f65d31 MT |
2383 | if (cfg->move_in_progress) |
2384 | send_cleanup_vector(cfg); | |
54168ed7 | 2385 | |
22f65d31 | 2386 | cpumask_copy(&desc->affinity, mask); |
54168ed7 IM |
2387 | } |
2388 | ||
3145e941 | 2389 | static int migrate_irq_remapped_level_desc(struct irq_desc *desc) |
54168ed7 IM |
2390 | { |
2391 | int ret = -1; | |
3145e941 | 2392 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 2393 | |
3145e941 | 2394 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2395 | |
3145e941 | 2396 | if (io_apic_level_ack_pending(cfg)) { |
54168ed7 | 2397 | /* |
d6c88a50 | 2398 | * Interrupt in progress. Migrating irq now will change the |
54168ed7 IM |
2399 | * vector information in the IO-APIC RTE and that will confuse |
2400 | * the EOI broadcast performed by cpu. | |
2401 | * So, delay the irq migration to the next instance. | |
2402 | */ | |
2403 | schedule_delayed_work(&ir_migration_work, 1); | |
2404 | goto unmask; | |
2405 | } | |
2406 | ||
2407 | /* everthing is clear. we have right of way */ | |
e7986739 | 2408 | migrate_ioapic_irq_desc(desc, &desc->pending_mask); |
54168ed7 IM |
2409 | |
2410 | ret = 0; | |
2411 | desc->status &= ~IRQ_MOVE_PENDING; | |
22f65d31 | 2412 | cpumask_clear(&desc->pending_mask); |
54168ed7 IM |
2413 | |
2414 | unmask: | |
3145e941 YL |
2415 | unmask_IO_APIC_irq_desc(desc); |
2416 | ||
54168ed7 IM |
2417 | return ret; |
2418 | } | |
2419 | ||
2420 | static void ir_irq_migration(struct work_struct *work) | |
2421 | { | |
2422 | unsigned int irq; | |
2423 | struct irq_desc *desc; | |
2424 | ||
2425 | for_each_irq_desc(irq, desc) { | |
2426 | if (desc->status & IRQ_MOVE_PENDING) { | |
2427 | unsigned long flags; | |
2428 | ||
2429 | spin_lock_irqsave(&desc->lock, flags); | |
2430 | if (!desc->chip->set_affinity || | |
2431 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2432 | desc->status &= ~IRQ_MOVE_PENDING; | |
2433 | spin_unlock_irqrestore(&desc->lock, flags); | |
2434 | continue; | |
2435 | } | |
2436 | ||
0de26520 | 2437 | desc->chip->set_affinity(irq, &desc->pending_mask); |
54168ed7 IM |
2438 | spin_unlock_irqrestore(&desc->lock, flags); |
2439 | } | |
2440 | } | |
2441 | } | |
2442 | ||
2443 | /* | |
2444 | * Migrates the IRQ destination in the process context. | |
2445 | */ | |
968ea6d8 RR |
2446 | static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc, |
2447 | const struct cpumask *mask) | |
54168ed7 | 2448 | { |
54168ed7 IM |
2449 | if (desc->status & IRQ_LEVEL) { |
2450 | desc->status |= IRQ_MOVE_PENDING; | |
0de26520 | 2451 | cpumask_copy(&desc->pending_mask, mask); |
3145e941 | 2452 | migrate_irq_remapped_level_desc(desc); |
54168ed7 IM |
2453 | return; |
2454 | } | |
2455 | ||
3145e941 YL |
2456 | migrate_ioapic_irq_desc(desc, mask); |
2457 | } | |
968ea6d8 RR |
2458 | static void set_ir_ioapic_affinity_irq(unsigned int irq, |
2459 | const struct cpumask *mask) | |
3145e941 YL |
2460 | { |
2461 | struct irq_desc *desc = irq_to_desc(irq); | |
2462 | ||
2463 | set_ir_ioapic_affinity_irq_desc(desc, mask); | |
54168ed7 IM |
2464 | } |
2465 | #endif | |
2466 | ||
2467 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2468 | { | |
2469 | unsigned vector, me; | |
8f2466f4 | 2470 | |
54168ed7 | 2471 | ack_APIC_irq(); |
54168ed7 | 2472 | exit_idle(); |
54168ed7 IM |
2473 | irq_enter(); |
2474 | ||
2475 | me = smp_processor_id(); | |
2476 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2477 | unsigned int irq; | |
2478 | struct irq_desc *desc; | |
2479 | struct irq_cfg *cfg; | |
2480 | irq = __get_cpu_var(vector_irq)[vector]; | |
2481 | ||
0b8f1efa YL |
2482 | if (irq == -1) |
2483 | continue; | |
2484 | ||
54168ed7 IM |
2485 | desc = irq_to_desc(irq); |
2486 | if (!desc) | |
2487 | continue; | |
2488 | ||
2489 | cfg = irq_cfg(irq); | |
2490 | spin_lock(&desc->lock); | |
2491 | if (!cfg->move_cleanup_count) | |
2492 | goto unlock; | |
2493 | ||
22f65d31 | 2494 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
54168ed7 IM |
2495 | goto unlock; |
2496 | ||
2497 | __get_cpu_var(vector_irq)[vector] = -1; | |
2498 | cfg->move_cleanup_count--; | |
2499 | unlock: | |
2500 | spin_unlock(&desc->lock); | |
2501 | } | |
2502 | ||
2503 | irq_exit(); | |
2504 | } | |
2505 | ||
3145e941 | 2506 | static void irq_complete_move(struct irq_desc **descp) |
54168ed7 | 2507 | { |
3145e941 YL |
2508 | struct irq_desc *desc = *descp; |
2509 | struct irq_cfg *cfg = desc->chip_data; | |
54168ed7 IM |
2510 | unsigned vector, me; |
2511 | ||
48a1b10a YL |
2512 | if (likely(!cfg->move_in_progress)) { |
2513 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC | |
2514 | if (likely(!cfg->move_desc_pending)) | |
2515 | return; | |
2516 | ||
b9098957 | 2517 | /* domain has not changed, but affinity did */ |
48a1b10a YL |
2518 | me = smp_processor_id(); |
2519 | if (cpu_isset(me, desc->affinity)) { | |
2520 | *descp = desc = move_irq_desc(desc, me); | |
2521 | /* get the new one */ | |
2522 | cfg = desc->chip_data; | |
2523 | cfg->move_desc_pending = 0; | |
2524 | } | |
2525 | #endif | |
54168ed7 | 2526 | return; |
48a1b10a | 2527 | } |
54168ed7 IM |
2528 | |
2529 | vector = ~get_irq_regs()->orig_ax; | |
2530 | me = smp_processor_id(); | |
10b888d6 YL |
2531 | |
2532 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) { | |
48a1b10a YL |
2533 | #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC |
2534 | *descp = desc = move_irq_desc(desc, me); | |
2535 | /* get the new one */ | |
2536 | cfg = desc->chip_data; | |
2537 | #endif | |
22f65d31 | 2538 | send_cleanup_vector(cfg); |
10b888d6 | 2539 | } |
497c9a19 YL |
2540 | } |
2541 | #else | |
3145e941 | 2542 | static inline void irq_complete_move(struct irq_desc **descp) {} |
497c9a19 | 2543 | #endif |
3145e941 | 2544 | |
54168ed7 IM |
2545 | #ifdef CONFIG_INTR_REMAP |
2546 | static void ack_x2apic_level(unsigned int irq) | |
2547 | { | |
2548 | ack_x2APIC_irq(); | |
2549 | } | |
2550 | ||
2551 | static void ack_x2apic_edge(unsigned int irq) | |
2552 | { | |
2553 | ack_x2APIC_irq(); | |
2554 | } | |
3145e941 | 2555 | |
54168ed7 | 2556 | #endif |
497c9a19 | 2557 | |
1d025192 YL |
2558 | static void ack_apic_edge(unsigned int irq) |
2559 | { | |
3145e941 YL |
2560 | struct irq_desc *desc = irq_to_desc(irq); |
2561 | ||
2562 | irq_complete_move(&desc); | |
1d025192 YL |
2563 | move_native_irq(irq); |
2564 | ack_APIC_irq(); | |
2565 | } | |
2566 | ||
3eb2cce8 | 2567 | atomic_t irq_mis_count; |
3eb2cce8 | 2568 | |
047c8fdb YL |
2569 | static void ack_apic_level(unsigned int irq) |
2570 | { | |
3145e941 YL |
2571 | struct irq_desc *desc = irq_to_desc(irq); |
2572 | ||
3eb2cce8 YL |
2573 | #ifdef CONFIG_X86_32 |
2574 | unsigned long v; | |
2575 | int i; | |
2576 | #endif | |
3145e941 | 2577 | struct irq_cfg *cfg; |
54168ed7 | 2578 | int do_unmask_irq = 0; |
047c8fdb | 2579 | |
3145e941 | 2580 | irq_complete_move(&desc); |
047c8fdb | 2581 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 | 2582 | /* If we are moving the irq we need to mask it */ |
3145e941 | 2583 | if (unlikely(desc->status & IRQ_MOVE_PENDING)) { |
54168ed7 | 2584 | do_unmask_irq = 1; |
3145e941 | 2585 | mask_IO_APIC_irq_desc(desc); |
54168ed7 | 2586 | } |
047c8fdb YL |
2587 | #endif |
2588 | ||
3eb2cce8 YL |
2589 | #ifdef CONFIG_X86_32 |
2590 | /* | |
2591 | * It appears there is an erratum which affects at least version 0x11 | |
2592 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2593 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2594 | * erroneously delivered as edge-triggered one but the respective IRR | |
2595 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2596 | * message but it will never arrive and further interrupts are blocked | |
2597 | * from the source. The exact reason is so far unknown, but the | |
2598 | * phenomenon was observed when two consecutive interrupt requests | |
2599 | * from a given source get delivered to the same CPU and the source is | |
2600 | * temporarily disabled in between. | |
2601 | * | |
2602 | * A workaround is to simulate an EOI message manually. We achieve it | |
2603 | * by setting the trigger mode to edge and then to level when the edge | |
2604 | * trigger mode gets detected in the TMR of a local APIC for a | |
2605 | * level-triggered interrupt. We mask the source for the time of the | |
2606 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2607 | * The idea is from Manfred Spraul. --macro | |
2608 | */ | |
3145e941 YL |
2609 | cfg = desc->chip_data; |
2610 | i = cfg->vector; | |
3eb2cce8 YL |
2611 | |
2612 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2613 | #endif | |
2614 | ||
54168ed7 IM |
2615 | /* |
2616 | * We must acknowledge the irq before we move it or the acknowledge will | |
2617 | * not propagate properly. | |
2618 | */ | |
2619 | ack_APIC_irq(); | |
2620 | ||
2621 | /* Now we can move and renable the irq */ | |
2622 | if (unlikely(do_unmask_irq)) { | |
2623 | /* Only migrate the irq if the ack has been received. | |
2624 | * | |
2625 | * On rare occasions the broadcast level triggered ack gets | |
2626 | * delayed going to ioapics, and if we reprogram the | |
2627 | * vector while Remote IRR is still set the irq will never | |
2628 | * fire again. | |
2629 | * | |
2630 | * To prevent this scenario we read the Remote IRR bit | |
2631 | * of the ioapic. This has two effects. | |
2632 | * - On any sane system the read of the ioapic will | |
2633 | * flush writes (and acks) going to the ioapic from | |
2634 | * this cpu. | |
2635 | * - We get to see if the ACK has actually been delivered. | |
2636 | * | |
2637 | * Based on failed experiments of reprogramming the | |
2638 | * ioapic entry from outside of irq context starting | |
2639 | * with masking the ioapic entry and then polling until | |
2640 | * Remote IRR was clear before reprogramming the | |
2641 | * ioapic I don't trust the Remote IRR bit to be | |
2642 | * completey accurate. | |
2643 | * | |
2644 | * However there appears to be no other way to plug | |
2645 | * this race, so if the Remote IRR bit is not | |
2646 | * accurate and is causing problems then it is a hardware bug | |
2647 | * and you can go talk to the chipset vendor about it. | |
2648 | */ | |
3145e941 YL |
2649 | cfg = desc->chip_data; |
2650 | if (!io_apic_level_ack_pending(cfg)) | |
54168ed7 | 2651 | move_masked_irq(irq); |
3145e941 | 2652 | unmask_IO_APIC_irq_desc(desc); |
54168ed7 | 2653 | } |
1d025192 | 2654 | |
3eb2cce8 | 2655 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2656 | if (!(v & (1 << (i & 0x1f)))) { |
2657 | atomic_inc(&irq_mis_count); | |
2658 | spin_lock(&ioapic_lock); | |
3145e941 YL |
2659 | __mask_and_edge_IO_APIC_irq(cfg); |
2660 | __unmask_and_level_IO_APIC_irq(cfg); | |
1d025192 YL |
2661 | spin_unlock(&ioapic_lock); |
2662 | } | |
047c8fdb | 2663 | #endif |
3eb2cce8 | 2664 | } |
1d025192 | 2665 | |
f5b9ed7a | 2666 | static struct irq_chip ioapic_chip __read_mostly = { |
d6c88a50 TG |
2667 | .name = "IO-APIC", |
2668 | .startup = startup_ioapic_irq, | |
2669 | .mask = mask_IO_APIC_irq, | |
2670 | .unmask = unmask_IO_APIC_irq, | |
2671 | .ack = ack_apic_edge, | |
2672 | .eoi = ack_apic_level, | |
54d5d424 | 2673 | #ifdef CONFIG_SMP |
d6c88a50 | 2674 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2675 | #endif |
ace80ab7 | 2676 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2677 | }; |
2678 | ||
54168ed7 IM |
2679 | #ifdef CONFIG_INTR_REMAP |
2680 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
d6c88a50 TG |
2681 | .name = "IR-IO-APIC", |
2682 | .startup = startup_ioapic_irq, | |
2683 | .mask = mask_IO_APIC_irq, | |
2684 | .unmask = unmask_IO_APIC_irq, | |
2685 | .ack = ack_x2apic_edge, | |
2686 | .eoi = ack_x2apic_level, | |
54168ed7 | 2687 | #ifdef CONFIG_SMP |
d6c88a50 | 2688 | .set_affinity = set_ir_ioapic_affinity_irq, |
54168ed7 IM |
2689 | #endif |
2690 | .retrigger = ioapic_retrigger_irq, | |
2691 | }; | |
2692 | #endif | |
1da177e4 LT |
2693 | |
2694 | static inline void init_IO_APIC_traps(void) | |
2695 | { | |
2696 | int irq; | |
08678b08 | 2697 | struct irq_desc *desc; |
da51a821 | 2698 | struct irq_cfg *cfg; |
1da177e4 LT |
2699 | |
2700 | /* | |
2701 | * NOTE! The local APIC isn't very good at handling | |
2702 | * multiple interrupts at the same interrupt level. | |
2703 | * As the interrupt level is determined by taking the | |
2704 | * vector number and shifting that right by 4, we | |
2705 | * want to spread these out a bit so that they don't | |
2706 | * all fall in the same interrupt level. | |
2707 | * | |
2708 | * Also, we've got to be careful not to trash gate | |
2709 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2710 | */ | |
0b8f1efa | 2711 | for_each_irq_desc(irq, desc) { |
0b8f1efa YL |
2712 | cfg = desc->chip_data; |
2713 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { | |
1da177e4 LT |
2714 | /* |
2715 | * Hmm.. We don't have an entry for this, | |
2716 | * so default to an old-fashioned 8259 | |
2717 | * interrupt if we can.. | |
2718 | */ | |
99d093d1 | 2719 | if (irq < NR_IRQS_LEGACY) |
1da177e4 | 2720 | make_8259A_irq(irq); |
0b8f1efa | 2721 | else |
1da177e4 | 2722 | /* Strange. Oh, well.. */ |
08678b08 | 2723 | desc->chip = &no_irq_chip; |
1da177e4 LT |
2724 | } |
2725 | } | |
2726 | } | |
2727 | ||
f5b9ed7a IM |
2728 | /* |
2729 | * The local APIC irq-chip implementation: | |
2730 | */ | |
1da177e4 | 2731 | |
36062448 | 2732 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2733 | { |
2734 | unsigned long v; | |
2735 | ||
2736 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2737 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2738 | } |
2739 | ||
36062448 | 2740 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2741 | { |
f5b9ed7a | 2742 | unsigned long v; |
1da177e4 | 2743 | |
f5b9ed7a | 2744 | v = apic_read(APIC_LVT0); |
593f4a78 | 2745 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2746 | } |
1da177e4 | 2747 | |
3145e941 | 2748 | static void ack_lapic_irq(unsigned int irq) |
1d025192 YL |
2749 | { |
2750 | ack_APIC_irq(); | |
2751 | } | |
2752 | ||
f5b9ed7a | 2753 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2754 | .name = "local-APIC", |
f5b9ed7a IM |
2755 | .mask = mask_lapic_irq, |
2756 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2757 | .ack = ack_lapic_irq, |
1da177e4 LT |
2758 | }; |
2759 | ||
3145e941 | 2760 | static void lapic_register_intr(int irq, struct irq_desc *desc) |
c88ac1df | 2761 | { |
08678b08 | 2762 | desc->status &= ~IRQ_LEVEL; |
c88ac1df MR |
2763 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2764 | "edge"); | |
c88ac1df MR |
2765 | } |
2766 | ||
e9427101 | 2767 | static void __init setup_nmi(void) |
1da177e4 LT |
2768 | { |
2769 | /* | |
36062448 | 2770 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2771 | * We put the 8259A master into AEOI mode and |
2772 | * unmask on all local APICs LVT0 as NMI. | |
2773 | * | |
2774 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2775 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2776 | * the NMI handler or the timer interrupt. | |
36062448 | 2777 | */ |
1da177e4 LT |
2778 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2779 | ||
e9427101 | 2780 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2781 | |
2782 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2783 | } | |
2784 | ||
2785 | /* | |
2786 | * This looks a bit hackish but it's about the only one way of sending | |
2787 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2788 | * not support the ExtINT mode, unfortunately. We need to send these | |
2789 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2790 | * 8259A interrupt line asserted until INTA. --macro | |
2791 | */ | |
28acf285 | 2792 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2793 | { |
fcfd636a | 2794 | int apic, pin, i; |
1da177e4 LT |
2795 | struct IO_APIC_route_entry entry0, entry1; |
2796 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2797 | |
fcfd636a | 2798 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2799 | if (pin == -1) { |
2800 | WARN_ON_ONCE(1); | |
2801 | return; | |
2802 | } | |
fcfd636a | 2803 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2804 | if (apic == -1) { |
2805 | WARN_ON_ONCE(1); | |
1da177e4 | 2806 | return; |
956fb531 | 2807 | } |
1da177e4 | 2808 | |
cf4c6a2f | 2809 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2810 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2811 | |
2812 | memset(&entry1, 0, sizeof(entry1)); | |
2813 | ||
2814 | entry1.dest_mode = 0; /* physical delivery */ | |
2815 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2816 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2817 | entry1.delivery_mode = dest_ExtINT; |
2818 | entry1.polarity = entry0.polarity; | |
2819 | entry1.trigger = 0; | |
2820 | entry1.vector = 0; | |
2821 | ||
cf4c6a2f | 2822 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2823 | |
2824 | save_control = CMOS_READ(RTC_CONTROL); | |
2825 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2826 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2827 | RTC_FREQ_SELECT); | |
2828 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2829 | ||
2830 | i = 100; | |
2831 | while (i-- > 0) { | |
2832 | mdelay(10); | |
2833 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2834 | i -= 10; | |
2835 | } | |
2836 | ||
2837 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2838 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2839 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2840 | |
cf4c6a2f | 2841 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2842 | } |
2843 | ||
efa2559f | 2844 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2845 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2846 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2847 | { |
2848 | disable_timer_pin_1 = 1; | |
2849 | return 0; | |
2850 | } | |
54168ed7 | 2851 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2852 | |
2853 | int timer_through_8259 __initdata; | |
2854 | ||
1da177e4 LT |
2855 | /* |
2856 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2857 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2858 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2859 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2860 | * |
2861 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2862 | */ |
8542b200 | 2863 | static inline void __init check_timer(void) |
1da177e4 | 2864 | { |
3145e941 YL |
2865 | struct irq_desc *desc = irq_to_desc(0); |
2866 | struct irq_cfg *cfg = desc->chip_data; | |
2867 | int cpu = boot_cpu_id; | |
fcfd636a | 2868 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2869 | unsigned long flags; |
047c8fdb YL |
2870 | unsigned int ver; |
2871 | int no_pin1 = 0; | |
4aae0702 IM |
2872 | |
2873 | local_irq_save(flags); | |
d4d25dec | 2874 | |
d6c88a50 TG |
2875 | ver = apic_read(APIC_LVR); |
2876 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2877 | |
1da177e4 LT |
2878 | /* |
2879 | * get/set the timer IRQ vector: | |
2880 | */ | |
2881 | disable_8259A_irq(0); | |
3145e941 | 2882 | assign_irq_vector(0, cfg, TARGET_CPUS); |
1da177e4 LT |
2883 | |
2884 | /* | |
d11d5794 MR |
2885 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2886 | * wire has to be disabled in the local APIC. Also | |
2887 | * timer interrupts need to be acknowledged manually in | |
2888 | * the 8259A for the i82489DX when using the NMI | |
2889 | * watchdog as that APIC treats NMIs as level-triggered. | |
2890 | * The AEOI mode will finish them in the 8259A | |
2891 | * automatically. | |
1da177e4 | 2892 | */ |
593f4a78 | 2893 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2894 | init_8259A(1); |
54168ed7 | 2895 | #ifdef CONFIG_X86_32 |
d11d5794 | 2896 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2897 | #endif |
1da177e4 | 2898 | |
fcfd636a EB |
2899 | pin1 = find_isa_irq_pin(0, mp_INT); |
2900 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2901 | pin2 = ioapic_i8259.pin; | |
2902 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2903 | |
49a66a0b MR |
2904 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2905 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2906 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2907 | |
691874fa MR |
2908 | /* |
2909 | * Some BIOS writers are clueless and report the ExtINTA | |
2910 | * I/O APIC input from the cascaded 8259A as the timer | |
2911 | * interrupt input. So just in case, if only one pin | |
2912 | * was found above, try it both directly and through the | |
2913 | * 8259A. | |
2914 | */ | |
2915 | if (pin1 == -1) { | |
54168ed7 IM |
2916 | #ifdef CONFIG_INTR_REMAP |
2917 | if (intr_remapping_enabled) | |
2918 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2919 | #endif | |
691874fa MR |
2920 | pin1 = pin2; |
2921 | apic1 = apic2; | |
2922 | no_pin1 = 1; | |
2923 | } else if (pin2 == -1) { | |
2924 | pin2 = pin1; | |
2925 | apic2 = apic1; | |
2926 | } | |
2927 | ||
1da177e4 LT |
2928 | if (pin1 != -1) { |
2929 | /* | |
2930 | * Ok, does IRQ0 through the IOAPIC work? | |
2931 | */ | |
691874fa | 2932 | if (no_pin1) { |
3145e941 | 2933 | add_pin_to_irq_cpu(cfg, cpu, apic1, pin1); |
497c9a19 | 2934 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2935 | } |
3145e941 | 2936 | unmask_IO_APIC_irq_desc(desc); |
1da177e4 LT |
2937 | if (timer_irq_works()) { |
2938 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2939 | setup_nmi(); |
2940 | enable_8259A_irq(0); | |
1da177e4 | 2941 | } |
66759a01 CE |
2942 | if (disable_timer_pin_1 > 0) |
2943 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2944 | goto out; |
1da177e4 | 2945 | } |
54168ed7 IM |
2946 | #ifdef CONFIG_INTR_REMAP |
2947 | if (intr_remapping_enabled) | |
2948 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2949 | #endif | |
fcfd636a | 2950 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2951 | if (!no_pin1) |
49a66a0b MR |
2952 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2953 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2954 | |
49a66a0b MR |
2955 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2956 | "(IRQ0) through the 8259A ...\n"); | |
2957 | apic_printk(APIC_QUIET, KERN_INFO | |
2958 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2959 | /* |
2960 | * legacy devices should be connected to IO APIC #0 | |
2961 | */ | |
3145e941 | 2962 | replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2); |
497c9a19 | 2963 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
3145e941 | 2964 | unmask_IO_APIC_irq_desc(desc); |
ecd29476 | 2965 | enable_8259A_irq(0); |
1da177e4 | 2966 | if (timer_irq_works()) { |
49a66a0b | 2967 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2968 | timer_through_8259 = 1; |
1da177e4 | 2969 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2970 | disable_8259A_irq(0); |
1da177e4 | 2971 | setup_nmi(); |
60134ebe | 2972 | enable_8259A_irq(0); |
1da177e4 | 2973 | } |
4aae0702 | 2974 | goto out; |
1da177e4 LT |
2975 | } |
2976 | /* | |
2977 | * Cleanup, just in case ... | |
2978 | */ | |
ecd29476 | 2979 | disable_8259A_irq(0); |
fcfd636a | 2980 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2981 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2982 | } |
1da177e4 LT |
2983 | |
2984 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2985 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2986 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2987 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2988 | } |
54168ed7 | 2989 | #ifdef CONFIG_X86_32 |
d11d5794 | 2990 | timer_ack = 0; |
54168ed7 | 2991 | #endif |
1da177e4 | 2992 | |
49a66a0b MR |
2993 | apic_printk(APIC_QUIET, KERN_INFO |
2994 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2995 | |
3145e941 | 2996 | lapic_register_intr(0, desc); |
497c9a19 | 2997 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
1da177e4 LT |
2998 | enable_8259A_irq(0); |
2999 | ||
3000 | if (timer_irq_works()) { | |
49a66a0b | 3001 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3002 | goto out; |
1da177e4 | 3003 | } |
e67465f1 | 3004 | disable_8259A_irq(0); |
497c9a19 | 3005 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 3006 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 3007 | |
49a66a0b MR |
3008 | apic_printk(APIC_QUIET, KERN_INFO |
3009 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 3010 | |
1da177e4 LT |
3011 | init_8259A(0); |
3012 | make_8259A_irq(0); | |
593f4a78 | 3013 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
3014 | |
3015 | unlock_ExtINT_logic(); | |
3016 | ||
3017 | if (timer_irq_works()) { | |
49a66a0b | 3018 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 3019 | goto out; |
1da177e4 | 3020 | } |
49a66a0b | 3021 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 3022 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 3023 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
3024 | out: |
3025 | local_irq_restore(flags); | |
1da177e4 LT |
3026 | } |
3027 | ||
3028 | /* | |
af174783 MR |
3029 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
3030 | * to devices. However there may be an I/O APIC pin available for | |
3031 | * this interrupt regardless. The pin may be left unconnected, but | |
3032 | * typically it will be reused as an ExtINT cascade interrupt for | |
3033 | * the master 8259A. In the MPS case such a pin will normally be | |
3034 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
3035 | * there is no provision for ExtINT interrupts, and in the absence | |
3036 | * of an override it would be treated as an ordinary ISA I/O APIC | |
3037 | * interrupt, that is edge-triggered and unmasked by default. We | |
3038 | * used to do this, but it caused problems on some systems because | |
3039 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
3040 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
3041 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
3042 | * the I/O APIC in all cases now. No actual device should request | |
3043 | * it anyway. --macro | |
1da177e4 LT |
3044 | */ |
3045 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
3046 | ||
3047 | void __init setup_IO_APIC(void) | |
3048 | { | |
54168ed7 IM |
3049 | |
3050 | #ifdef CONFIG_X86_32 | |
1da177e4 | 3051 | enable_IO_APIC(); |
54168ed7 IM |
3052 | #else |
3053 | /* | |
3054 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
3055 | */ | |
3056 | #endif | |
1da177e4 | 3057 | |
af174783 | 3058 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 3059 | |
54168ed7 | 3060 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
d6c88a50 | 3061 | /* |
54168ed7 IM |
3062 | * Set up IO-APIC IRQ routing. |
3063 | */ | |
3064 | #ifdef CONFIG_X86_32 | |
d6c88a50 TG |
3065 | if (!acpi_ioapic) |
3066 | setup_ioapic_ids_from_mpc(); | |
54168ed7 | 3067 | #endif |
1da177e4 LT |
3068 | sync_Arb_IDs(); |
3069 | setup_IO_APIC_irqs(); | |
3070 | init_IO_APIC_traps(); | |
1e4c85f9 | 3071 | check_timer(); |
1da177e4 LT |
3072 | } |
3073 | ||
3074 | /* | |
54168ed7 IM |
3075 | * Called after all the initialization is done. If we didnt find any |
3076 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 3077 | */ |
36062448 | 3078 | |
1da177e4 LT |
3079 | static int __init io_apic_bug_finalize(void) |
3080 | { | |
d6c88a50 TG |
3081 | if (sis_apic_bug == -1) |
3082 | sis_apic_bug = 0; | |
3083 | return 0; | |
1da177e4 LT |
3084 | } |
3085 | ||
3086 | late_initcall(io_apic_bug_finalize); | |
3087 | ||
3088 | struct sysfs_ioapic_data { | |
3089 | struct sys_device dev; | |
3090 | struct IO_APIC_route_entry entry[0]; | |
3091 | }; | |
54168ed7 | 3092 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 3093 | |
438510f6 | 3094 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
3095 | { |
3096 | struct IO_APIC_route_entry *entry; | |
3097 | struct sysfs_ioapic_data *data; | |
1da177e4 | 3098 | int i; |
36062448 | 3099 | |
1da177e4 LT |
3100 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3101 | entry = data->entry; | |
54168ed7 IM |
3102 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
3103 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
3104 | |
3105 | return 0; | |
3106 | } | |
3107 | ||
3108 | static int ioapic_resume(struct sys_device *dev) | |
3109 | { | |
3110 | struct IO_APIC_route_entry *entry; | |
3111 | struct sysfs_ioapic_data *data; | |
3112 | unsigned long flags; | |
3113 | union IO_APIC_reg_00 reg_00; | |
3114 | int i; | |
36062448 | 3115 | |
1da177e4 LT |
3116 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
3117 | entry = data->entry; | |
3118 | ||
3119 | spin_lock_irqsave(&ioapic_lock, flags); | |
3120 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
3121 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
3122 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
3123 | io_apic_write(dev->id, 0, reg_00.raw); |
3124 | } | |
1da177e4 | 3125 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 3126 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 3127 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
3128 | |
3129 | return 0; | |
3130 | } | |
3131 | ||
3132 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 3133 | .name = "ioapic", |
1da177e4 LT |
3134 | .suspend = ioapic_suspend, |
3135 | .resume = ioapic_resume, | |
3136 | }; | |
3137 | ||
3138 | static int __init ioapic_init_sysfs(void) | |
3139 | { | |
54168ed7 IM |
3140 | struct sys_device * dev; |
3141 | int i, size, error; | |
1da177e4 LT |
3142 | |
3143 | error = sysdev_class_register(&ioapic_sysdev_class); | |
3144 | if (error) | |
3145 | return error; | |
3146 | ||
54168ed7 | 3147 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 3148 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 3149 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 3150 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
3151 | if (!mp_ioapic_data[i]) { |
3152 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3153 | continue; | |
3154 | } | |
1da177e4 | 3155 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 3156 | dev->id = i; |
1da177e4 LT |
3157 | dev->cls = &ioapic_sysdev_class; |
3158 | error = sysdev_register(dev); | |
3159 | if (error) { | |
3160 | kfree(mp_ioapic_data[i]); | |
3161 | mp_ioapic_data[i] = NULL; | |
3162 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
3163 | continue; | |
3164 | } | |
3165 | } | |
3166 | ||
3167 | return 0; | |
3168 | } | |
3169 | ||
3170 | device_initcall(ioapic_init_sysfs); | |
3171 | ||
3fc471ed | 3172 | /* |
95d77884 | 3173 | * Dynamic irq allocate and deallocation |
3fc471ed | 3174 | */ |
199751d7 | 3175 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3176 | { |
ace80ab7 | 3177 | /* Allocate an unused irq */ |
54168ed7 IM |
3178 | unsigned int irq; |
3179 | unsigned int new; | |
3fc471ed | 3180 | unsigned long flags; |
0b8f1efa YL |
3181 | struct irq_cfg *cfg_new = NULL; |
3182 | int cpu = boot_cpu_id; | |
3183 | struct irq_desc *desc_new = NULL; | |
199751d7 YL |
3184 | |
3185 | irq = 0; | |
ace80ab7 | 3186 | spin_lock_irqsave(&vector_lock, flags); |
be5d5350 | 3187 | for (new = irq_want; new < NR_IRQS; new++) { |
ace80ab7 EB |
3188 | if (platform_legacy_irq(new)) |
3189 | continue; | |
0b8f1efa YL |
3190 | |
3191 | desc_new = irq_to_desc_alloc_cpu(new, cpu); | |
3192 | if (!desc_new) { | |
3193 | printk(KERN_INFO "can not get irq_desc for %d\n", new); | |
ace80ab7 | 3194 | continue; |
0b8f1efa YL |
3195 | } |
3196 | cfg_new = desc_new->chip_data; | |
3197 | ||
3198 | if (cfg_new->vector != 0) | |
ace80ab7 | 3199 | continue; |
3145e941 | 3200 | if (__assign_irq_vector(new, cfg_new, TARGET_CPUS) == 0) |
ace80ab7 EB |
3201 | irq = new; |
3202 | break; | |
3203 | } | |
3204 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3205 | |
199751d7 | 3206 | if (irq > 0) { |
3fc471ed | 3207 | dynamic_irq_init(irq); |
0b8f1efa YL |
3208 | /* restore it, in case dynamic_irq_init clear it */ |
3209 | if (desc_new) | |
3210 | desc_new->chip_data = cfg_new; | |
3fc471ed EB |
3211 | } |
3212 | return irq; | |
3213 | } | |
3214 | ||
be5d5350 | 3215 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
199751d7 YL |
3216 | int create_irq(void) |
3217 | { | |
be5d5350 | 3218 | unsigned int irq_want; |
54168ed7 IM |
3219 | int irq; |
3220 | ||
be5d5350 YL |
3221 | irq_want = nr_irqs_gsi; |
3222 | irq = create_irq_nr(irq_want); | |
54168ed7 IM |
3223 | |
3224 | if (irq == 0) | |
3225 | irq = -1; | |
3226 | ||
3227 | return irq; | |
199751d7 YL |
3228 | } |
3229 | ||
3fc471ed EB |
3230 | void destroy_irq(unsigned int irq) |
3231 | { | |
3232 | unsigned long flags; | |
0b8f1efa YL |
3233 | struct irq_cfg *cfg; |
3234 | struct irq_desc *desc; | |
3fc471ed | 3235 | |
0b8f1efa YL |
3236 | /* store it, in case dynamic_irq_cleanup clear it */ |
3237 | desc = irq_to_desc(irq); | |
3238 | cfg = desc->chip_data; | |
3fc471ed | 3239 | dynamic_irq_cleanup(irq); |
0b8f1efa YL |
3240 | /* connect back irq_cfg */ |
3241 | if (desc) | |
3242 | desc->chip_data = cfg; | |
3fc471ed | 3243 | |
54168ed7 IM |
3244 | #ifdef CONFIG_INTR_REMAP |
3245 | free_irte(irq); | |
3246 | #endif | |
3fc471ed | 3247 | spin_lock_irqsave(&vector_lock, flags); |
3145e941 | 3248 | __clear_irq_vector(irq, cfg); |
3fc471ed EB |
3249 | spin_unlock_irqrestore(&vector_lock, flags); |
3250 | } | |
3fc471ed | 3251 | |
2d3fcc1c | 3252 | /* |
27b46d76 | 3253 | * MSI message composition |
2d3fcc1c EB |
3254 | */ |
3255 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3256 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3257 | { |
497c9a19 YL |
3258 | struct irq_cfg *cfg; |
3259 | int err; | |
2d3fcc1c EB |
3260 | unsigned dest; |
3261 | ||
3145e941 | 3262 | cfg = irq_cfg(irq); |
22f65d31 | 3263 | err = assign_irq_vector(irq, cfg, TARGET_CPUS); |
497c9a19 YL |
3264 | if (err) |
3265 | return err; | |
2d3fcc1c | 3266 | |
22f65d31 | 3267 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
497c9a19 | 3268 | |
54168ed7 IM |
3269 | #ifdef CONFIG_INTR_REMAP |
3270 | if (irq_remapped(irq)) { | |
3271 | struct irte irte; | |
3272 | int ir_index; | |
3273 | u16 sub_handle; | |
3274 | ||
3275 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3276 | BUG_ON(ir_index == -1); | |
3277 | ||
3278 | memset (&irte, 0, sizeof(irte)); | |
3279 | ||
3280 | irte.present = 1; | |
3281 | irte.dst_mode = INT_DEST_MODE; | |
3282 | irte.trigger_mode = 0; /* edge */ | |
3283 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
3284 | irte.vector = cfg->vector; | |
3285 | irte.dest_id = IRTE_DEST(dest); | |
3286 | ||
3287 | modify_irte(irq, &irte); | |
3288 | ||
3289 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3290 | msg->data = sub_handle; | |
3291 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3292 | MSI_ADDR_IR_SHV | | |
3293 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3294 | MSI_ADDR_IR_INDEX2(ir_index); | |
3295 | } else | |
3296 | #endif | |
3297 | { | |
3298 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3299 | msg->address_lo = | |
3300 | MSI_ADDR_BASE_LO | | |
3301 | ((INT_DEST_MODE == 0) ? | |
3302 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3303 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3304 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3305 | MSI_ADDR_REDIRECTION_CPU: | |
3306 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3307 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3308 | |
54168ed7 IM |
3309 | msg->data = |
3310 | MSI_DATA_TRIGGER_EDGE | | |
3311 | MSI_DATA_LEVEL_ASSERT | | |
3312 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3313 | MSI_DATA_DELIVERY_FIXED: | |
3314 | MSI_DATA_DELIVERY_LOWPRI) | | |
3315 | MSI_DATA_VECTOR(cfg->vector); | |
3316 | } | |
497c9a19 | 3317 | return err; |
2d3fcc1c EB |
3318 | } |
3319 | ||
3b7d1921 | 3320 | #ifdef CONFIG_SMP |
0de26520 | 3321 | static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) |
2d3fcc1c | 3322 | { |
3145e941 | 3323 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3324 | struct irq_cfg *cfg; |
3b7d1921 EB |
3325 | struct msi_msg msg; |
3326 | unsigned int dest; | |
3b7d1921 | 3327 | |
22f65d31 MT |
3328 | dest = set_desc_affinity(desc, mask); |
3329 | if (dest == BAD_APICID) | |
497c9a19 | 3330 | return; |
2d3fcc1c | 3331 | |
3145e941 | 3332 | cfg = desc->chip_data; |
2d3fcc1c | 3333 | |
3145e941 | 3334 | read_msi_msg_desc(desc, &msg); |
3b7d1921 EB |
3335 | |
3336 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3337 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3338 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3339 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3340 | ||
3145e941 | 3341 | write_msi_msg_desc(desc, &msg); |
2d3fcc1c | 3342 | } |
54168ed7 IM |
3343 | #ifdef CONFIG_INTR_REMAP |
3344 | /* | |
3345 | * Migrate the MSI irq to another cpumask. This migration is | |
3346 | * done in the process context using interrupt-remapping hardware. | |
3347 | */ | |
e7986739 MT |
3348 | static void |
3349 | ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask) | |
54168ed7 | 3350 | { |
3145e941 | 3351 | struct irq_desc *desc = irq_to_desc(irq); |
a7883dec | 3352 | struct irq_cfg *cfg = desc->chip_data; |
54168ed7 | 3353 | unsigned int dest; |
54168ed7 | 3354 | struct irte irte; |
54168ed7 IM |
3355 | |
3356 | if (get_irte(irq, &irte)) | |
3357 | return; | |
3358 | ||
22f65d31 MT |
3359 | dest = set_desc_affinity(desc, mask); |
3360 | if (dest == BAD_APICID) | |
54168ed7 IM |
3361 | return; |
3362 | ||
54168ed7 IM |
3363 | irte.vector = cfg->vector; |
3364 | irte.dest_id = IRTE_DEST(dest); | |
3365 | ||
3366 | /* | |
3367 | * atomically update the IRTE with the new destination and vector. | |
3368 | */ | |
3369 | modify_irte(irq, &irte); | |
3370 | ||
3371 | /* | |
3372 | * After this point, all the interrupts will start arriving | |
3373 | * at the new destination. So, time to cleanup the previous | |
3374 | * vector allocation. | |
3375 | */ | |
22f65d31 MT |
3376 | if (cfg->move_in_progress) |
3377 | send_cleanup_vector(cfg); | |
54168ed7 | 3378 | } |
3145e941 | 3379 | |
54168ed7 | 3380 | #endif |
3b7d1921 | 3381 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3382 | |
3b7d1921 EB |
3383 | /* |
3384 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3385 | * which implement the MSI or MSI-X Capability Structure. | |
3386 | */ | |
3387 | static struct irq_chip msi_chip = { | |
3388 | .name = "PCI-MSI", | |
3389 | .unmask = unmask_msi_irq, | |
3390 | .mask = mask_msi_irq, | |
1d025192 | 3391 | .ack = ack_apic_edge, |
3b7d1921 EB |
3392 | #ifdef CONFIG_SMP |
3393 | .set_affinity = set_msi_irq_affinity, | |
3394 | #endif | |
3395 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3396 | }; |
3397 | ||
54168ed7 IM |
3398 | #ifdef CONFIG_INTR_REMAP |
3399 | static struct irq_chip msi_ir_chip = { | |
3400 | .name = "IR-PCI-MSI", | |
3401 | .unmask = unmask_msi_irq, | |
3402 | .mask = mask_msi_irq, | |
3403 | .ack = ack_x2apic_edge, | |
3404 | #ifdef CONFIG_SMP | |
3405 | .set_affinity = ir_set_msi_irq_affinity, | |
3406 | #endif | |
3407 | .retrigger = ioapic_retrigger_irq, | |
3408 | }; | |
3409 | ||
3410 | /* | |
3411 | * Map the PCI dev to the corresponding remapping hardware unit | |
3412 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3413 | * in it. | |
3414 | */ | |
3415 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3416 | { | |
3417 | struct intel_iommu *iommu; | |
3418 | int index; | |
3419 | ||
3420 | iommu = map_dev_to_ir(dev); | |
3421 | if (!iommu) { | |
3422 | printk(KERN_ERR | |
3423 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3424 | return -ENOENT; | |
3425 | } | |
3426 | ||
3427 | index = alloc_irte(iommu, irq, nvec); | |
3428 | if (index < 0) { | |
3429 | printk(KERN_ERR | |
3430 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
d6c88a50 | 3431 | pci_name(dev)); |
54168ed7 IM |
3432 | return -ENOSPC; |
3433 | } | |
3434 | return index; | |
3435 | } | |
3436 | #endif | |
1d025192 | 3437 | |
3145e941 | 3438 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) |
1d025192 YL |
3439 | { |
3440 | int ret; | |
3441 | struct msi_msg msg; | |
3442 | ||
3443 | ret = msi_compose_msg(dev, irq, &msg); | |
3444 | if (ret < 0) | |
3445 | return ret; | |
3446 | ||
3145e941 | 3447 | set_irq_msi(irq, msidesc); |
1d025192 YL |
3448 | write_msi_msg(irq, &msg); |
3449 | ||
54168ed7 IM |
3450 | #ifdef CONFIG_INTR_REMAP |
3451 | if (irq_remapped(irq)) { | |
3452 | struct irq_desc *desc = irq_to_desc(irq); | |
3453 | /* | |
3454 | * irq migration in process context | |
3455 | */ | |
3456 | desc->status |= IRQ_MOVE_PCNTXT; | |
3457 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3458 | } else | |
3459 | #endif | |
3460 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 | 3461 | |
c81bba49 YL |
3462 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
3463 | ||
1d025192 YL |
3464 | return 0; |
3465 | } | |
3466 | ||
0b8f1efa | 3467 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc) |
3b7d1921 | 3468 | { |
54168ed7 IM |
3469 | unsigned int irq; |
3470 | int ret; | |
199751d7 YL |
3471 | unsigned int irq_want; |
3472 | ||
be5d5350 | 3473 | irq_want = nr_irqs_gsi; |
199751d7 | 3474 | irq = create_irq_nr(irq_want); |
199751d7 YL |
3475 | if (irq == 0) |
3476 | return -1; | |
f7feaca7 | 3477 | |
54168ed7 IM |
3478 | #ifdef CONFIG_INTR_REMAP |
3479 | if (!intr_remapping_enabled) | |
3480 | goto no_ir; | |
3481 | ||
3482 | ret = msi_alloc_irte(dev, irq, 1); | |
3483 | if (ret < 0) | |
3484 | goto error; | |
3485 | no_ir: | |
3486 | #endif | |
0b8f1efa | 3487 | ret = setup_msi_irq(dev, msidesc, irq); |
f7feaca7 EB |
3488 | if (ret < 0) { |
3489 | destroy_irq(irq); | |
3b7d1921 | 3490 | return ret; |
54168ed7 | 3491 | } |
7fe3730d | 3492 | return 0; |
54168ed7 IM |
3493 | |
3494 | #ifdef CONFIG_INTR_REMAP | |
3495 | error: | |
3496 | destroy_irq(irq); | |
3497 | return ret; | |
3498 | #endif | |
3b7d1921 EB |
3499 | } |
3500 | ||
047c8fdb YL |
3501 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3502 | { | |
54168ed7 IM |
3503 | unsigned int irq; |
3504 | int ret, sub_handle; | |
0b8f1efa | 3505 | struct msi_desc *msidesc; |
54168ed7 IM |
3506 | unsigned int irq_want; |
3507 | ||
3508 | #ifdef CONFIG_INTR_REMAP | |
3509 | struct intel_iommu *iommu = 0; | |
3510 | int index = 0; | |
3511 | #endif | |
3512 | ||
be5d5350 | 3513 | irq_want = nr_irqs_gsi; |
54168ed7 | 3514 | sub_handle = 0; |
0b8f1efa YL |
3515 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
3516 | irq = create_irq_nr(irq_want); | |
be5d5350 | 3517 | irq_want++; |
54168ed7 IM |
3518 | if (irq == 0) |
3519 | return -1; | |
3520 | #ifdef CONFIG_INTR_REMAP | |
3521 | if (!intr_remapping_enabled) | |
3522 | goto no_ir; | |
3523 | ||
3524 | if (!sub_handle) { | |
3525 | /* | |
3526 | * allocate the consecutive block of IRTE's | |
3527 | * for 'nvec' | |
3528 | */ | |
3529 | index = msi_alloc_irte(dev, irq, nvec); | |
3530 | if (index < 0) { | |
3531 | ret = index; | |
3532 | goto error; | |
3533 | } | |
3534 | } else { | |
3535 | iommu = map_dev_to_ir(dev); | |
3536 | if (!iommu) { | |
3537 | ret = -ENOENT; | |
3538 | goto error; | |
3539 | } | |
3540 | /* | |
3541 | * setup the mapping between the irq and the IRTE | |
3542 | * base index, the sub_handle pointing to the | |
3543 | * appropriate interrupt remap table entry. | |
3544 | */ | |
3545 | set_irte_irq(irq, iommu, index, sub_handle); | |
3546 | } | |
3547 | no_ir: | |
3548 | #endif | |
0b8f1efa | 3549 | ret = setup_msi_irq(dev, msidesc, irq); |
54168ed7 IM |
3550 | if (ret < 0) |
3551 | goto error; | |
3552 | sub_handle++; | |
3553 | } | |
3554 | return 0; | |
047c8fdb YL |
3555 | |
3556 | error: | |
54168ed7 IM |
3557 | destroy_irq(irq); |
3558 | return ret; | |
047c8fdb YL |
3559 | } |
3560 | ||
3b7d1921 EB |
3561 | void arch_teardown_msi_irq(unsigned int irq) |
3562 | { | |
f7feaca7 | 3563 | destroy_irq(irq); |
3b7d1921 EB |
3564 | } |
3565 | ||
54168ed7 IM |
3566 | #ifdef CONFIG_DMAR |
3567 | #ifdef CONFIG_SMP | |
22f65d31 | 3568 | static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
54168ed7 | 3569 | { |
3145e941 | 3570 | struct irq_desc *desc = irq_to_desc(irq); |
54168ed7 IM |
3571 | struct irq_cfg *cfg; |
3572 | struct msi_msg msg; | |
3573 | unsigned int dest; | |
54168ed7 | 3574 | |
22f65d31 MT |
3575 | dest = set_desc_affinity(desc, mask); |
3576 | if (dest == BAD_APICID) | |
54168ed7 IM |
3577 | return; |
3578 | ||
3145e941 | 3579 | cfg = desc->chip_data; |
54168ed7 IM |
3580 | |
3581 | dmar_msi_read(irq, &msg); | |
3582 | ||
3583 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3584 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3585 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3586 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3587 | ||
3588 | dmar_msi_write(irq, &msg); | |
54168ed7 | 3589 | } |
3145e941 | 3590 | |
54168ed7 IM |
3591 | #endif /* CONFIG_SMP */ |
3592 | ||
3593 | struct irq_chip dmar_msi_type = { | |
3594 | .name = "DMAR_MSI", | |
3595 | .unmask = dmar_msi_unmask, | |
3596 | .mask = dmar_msi_mask, | |
3597 | .ack = ack_apic_edge, | |
3598 | #ifdef CONFIG_SMP | |
3599 | .set_affinity = dmar_msi_set_affinity, | |
3600 | #endif | |
3601 | .retrigger = ioapic_retrigger_irq, | |
3602 | }; | |
3603 | ||
3604 | int arch_setup_dmar_msi(unsigned int irq) | |
3605 | { | |
3606 | int ret; | |
3607 | struct msi_msg msg; | |
2d3fcc1c | 3608 | |
54168ed7 IM |
3609 | ret = msi_compose_msg(NULL, irq, &msg); |
3610 | if (ret < 0) | |
3611 | return ret; | |
3612 | dmar_msi_write(irq, &msg); | |
3613 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3614 | "edge"); | |
3615 | return 0; | |
3616 | } | |
3617 | #endif | |
3618 | ||
58ac1e76 | 3619 | #ifdef CONFIG_HPET_TIMER |
3620 | ||
3621 | #ifdef CONFIG_SMP | |
22f65d31 | 3622 | static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask) |
58ac1e76 | 3623 | { |
3145e941 | 3624 | struct irq_desc *desc = irq_to_desc(irq); |
58ac1e76 | 3625 | struct irq_cfg *cfg; |
58ac1e76 | 3626 | struct msi_msg msg; |
3627 | unsigned int dest; | |
58ac1e76 | 3628 | |
22f65d31 MT |
3629 | dest = set_desc_affinity(desc, mask); |
3630 | if (dest == BAD_APICID) | |
58ac1e76 | 3631 | return; |
3632 | ||
3145e941 | 3633 | cfg = desc->chip_data; |
58ac1e76 | 3634 | |
3635 | hpet_msi_read(irq, &msg); | |
3636 | ||
3637 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3638 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3639 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3640 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3641 | ||
3642 | hpet_msi_write(irq, &msg); | |
58ac1e76 | 3643 | } |
3145e941 | 3644 | |
58ac1e76 | 3645 | #endif /* CONFIG_SMP */ |
3646 | ||
3647 | struct irq_chip hpet_msi_type = { | |
3648 | .name = "HPET_MSI", | |
3649 | .unmask = hpet_msi_unmask, | |
3650 | .mask = hpet_msi_mask, | |
3651 | .ack = ack_apic_edge, | |
3652 | #ifdef CONFIG_SMP | |
3653 | .set_affinity = hpet_msi_set_affinity, | |
3654 | #endif | |
3655 | .retrigger = ioapic_retrigger_irq, | |
3656 | }; | |
3657 | ||
3658 | int arch_setup_hpet_msi(unsigned int irq) | |
3659 | { | |
3660 | int ret; | |
3661 | struct msi_msg msg; | |
3662 | ||
3663 | ret = msi_compose_msg(NULL, irq, &msg); | |
3664 | if (ret < 0) | |
3665 | return ret; | |
3666 | ||
3667 | hpet_msi_write(irq, &msg); | |
3668 | set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq, | |
3669 | "edge"); | |
c81bba49 | 3670 | |
58ac1e76 | 3671 | return 0; |
3672 | } | |
3673 | #endif | |
3674 | ||
54168ed7 | 3675 | #endif /* CONFIG_PCI_MSI */ |
8b955b0d EB |
3676 | /* |
3677 | * Hypertransport interrupt support | |
3678 | */ | |
3679 | #ifdef CONFIG_HT_IRQ | |
3680 | ||
3681 | #ifdef CONFIG_SMP | |
3682 | ||
497c9a19 | 3683 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3684 | { |
ec68307c EB |
3685 | struct ht_irq_msg msg; |
3686 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3687 | |
497c9a19 | 3688 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3689 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3690 | |
497c9a19 | 3691 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3692 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3693 | |
ec68307c | 3694 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3695 | } |
3696 | ||
22f65d31 | 3697 | static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask) |
8b955b0d | 3698 | { |
3145e941 | 3699 | struct irq_desc *desc = irq_to_desc(irq); |
497c9a19 | 3700 | struct irq_cfg *cfg; |
8b955b0d | 3701 | unsigned int dest; |
8b955b0d | 3702 | |
22f65d31 MT |
3703 | dest = set_desc_affinity(desc, mask); |
3704 | if (dest == BAD_APICID) | |
497c9a19 | 3705 | return; |
8b955b0d | 3706 | |
3145e941 | 3707 | cfg = desc->chip_data; |
8b955b0d | 3708 | |
497c9a19 | 3709 | target_ht_irq(irq, dest, cfg->vector); |
8b955b0d | 3710 | } |
3145e941 | 3711 | |
8b955b0d EB |
3712 | #endif |
3713 | ||
c37e108d | 3714 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3715 | .name = "PCI-HT", |
3716 | .mask = mask_ht_irq, | |
3717 | .unmask = unmask_ht_irq, | |
1d025192 | 3718 | .ack = ack_apic_edge, |
8b955b0d EB |
3719 | #ifdef CONFIG_SMP |
3720 | .set_affinity = set_ht_irq_affinity, | |
3721 | #endif | |
3722 | .retrigger = ioapic_retrigger_irq, | |
3723 | }; | |
3724 | ||
3725 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3726 | { | |
497c9a19 YL |
3727 | struct irq_cfg *cfg; |
3728 | int err; | |
8b955b0d | 3729 | |
3145e941 | 3730 | cfg = irq_cfg(irq); |
e7986739 | 3731 | err = assign_irq_vector(irq, cfg, TARGET_CPUS); |
54168ed7 | 3732 | if (!err) { |
ec68307c | 3733 | struct ht_irq_msg msg; |
8b955b0d | 3734 | unsigned dest; |
8b955b0d | 3735 | |
22f65d31 | 3736 | dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS); |
8b955b0d | 3737 | |
ec68307c | 3738 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3739 | |
ec68307c EB |
3740 | msg.address_lo = |
3741 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3742 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3743 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3744 | ((INT_DEST_MODE == 0) ? |
3745 | HT_IRQ_LOW_DM_PHYSICAL : | |
3746 | HT_IRQ_LOW_DM_LOGICAL) | | |
3747 | HT_IRQ_LOW_RQEOI_EDGE | | |
3748 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3749 | HT_IRQ_LOW_MT_FIXED : | |
3750 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3751 | HT_IRQ_LOW_IRQ_MASKED; | |
3752 | ||
ec68307c | 3753 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3754 | |
a460e745 IM |
3755 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3756 | handle_edge_irq, "edge"); | |
c81bba49 YL |
3757 | |
3758 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | |
8b955b0d | 3759 | } |
497c9a19 | 3760 | return err; |
8b955b0d EB |
3761 | } |
3762 | #endif /* CONFIG_HT_IRQ */ | |
3763 | ||
4173a0e7 DN |
3764 | #ifdef CONFIG_X86_64 |
3765 | /* | |
3766 | * Re-target the irq to the specified CPU and enable the specified MMR located | |
3767 | * on the specified blade to allow the sending of MSIs to the specified CPU. | |
3768 | */ | |
3769 | int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |
3770 | unsigned long mmr_offset) | |
3771 | { | |
22f65d31 | 3772 | const struct cpumask *eligible_cpu = cpumask_of(cpu); |
4173a0e7 DN |
3773 | struct irq_cfg *cfg; |
3774 | int mmr_pnode; | |
3775 | unsigned long mmr_value; | |
3776 | struct uv_IO_APIC_route_entry *entry; | |
3777 | unsigned long flags; | |
3778 | int err; | |
3779 | ||
3145e941 YL |
3780 | cfg = irq_cfg(irq); |
3781 | ||
e7986739 | 3782 | err = assign_irq_vector(irq, cfg, eligible_cpu); |
4173a0e7 DN |
3783 | if (err != 0) |
3784 | return err; | |
3785 | ||
3786 | spin_lock_irqsave(&vector_lock, flags); | |
3787 | set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, | |
3788 | irq_name); | |
3789 | spin_unlock_irqrestore(&vector_lock, flags); | |
3790 | ||
4173a0e7 DN |
3791 | mmr_value = 0; |
3792 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3793 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3794 | ||
3795 | entry->vector = cfg->vector; | |
3796 | entry->delivery_mode = INT_DELIVERY_MODE; | |
3797 | entry->dest_mode = INT_DEST_MODE; | |
3798 | entry->polarity = 0; | |
3799 | entry->trigger = 0; | |
3800 | entry->mask = 0; | |
e7986739 | 3801 | entry->dest = cpu_mask_to_apicid(eligible_cpu); |
4173a0e7 DN |
3802 | |
3803 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3804 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3805 | ||
3806 | return irq; | |
3807 | } | |
3808 | ||
3809 | /* | |
3810 | * Disable the specified MMR located on the specified blade so that MSIs are | |
3811 | * longer allowed to be sent. | |
3812 | */ | |
3813 | void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset) | |
3814 | { | |
3815 | unsigned long mmr_value; | |
3816 | struct uv_IO_APIC_route_entry *entry; | |
3817 | int mmr_pnode; | |
3818 | ||
3819 | mmr_value = 0; | |
3820 | entry = (struct uv_IO_APIC_route_entry *)&mmr_value; | |
3821 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | |
3822 | ||
3823 | entry->mask = 1; | |
3824 | ||
3825 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | |
3826 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | |
3827 | } | |
3828 | #endif /* CONFIG_X86_64 */ | |
3829 | ||
9d6a4d08 YL |
3830 | int __init io_apic_get_redir_entries (int ioapic) |
3831 | { | |
3832 | union IO_APIC_reg_01 reg_01; | |
3833 | unsigned long flags; | |
3834 | ||
3835 | spin_lock_irqsave(&ioapic_lock, flags); | |
3836 | reg_01.raw = io_apic_read(ioapic, 1); | |
3837 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3838 | ||
3839 | return reg_01.bits.entries; | |
3840 | } | |
3841 | ||
be5d5350 | 3842 | void __init probe_nr_irqs_gsi(void) |
9d6a4d08 | 3843 | { |
be5d5350 YL |
3844 | int nr = 0; |
3845 | ||
3f4a739c YL |
3846 | nr = acpi_probe_gsi(); |
3847 | if (nr > nr_irqs_gsi) { | |
be5d5350 | 3848 | nr_irqs_gsi = nr; |
3f4a739c YL |
3849 | } else { |
3850 | /* for acpi=off or acpi is not compiled in */ | |
3851 | int idx; | |
3852 | ||
3853 | nr = 0; | |
3854 | for (idx = 0; idx < nr_ioapics; idx++) | |
3855 | nr += io_apic_get_redir_entries(idx) + 1; | |
3856 | ||
3857 | if (nr > nr_irqs_gsi) | |
3858 | nr_irqs_gsi = nr; | |
3859 | } | |
3860 | ||
3861 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); | |
9d6a4d08 YL |
3862 | } |
3863 | ||
1da177e4 | 3864 | /* -------------------------------------------------------------------------- |
54168ed7 | 3865 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3866 | -------------------------------------------------------------------------- */ |
3867 | ||
888ba6c6 | 3868 | #ifdef CONFIG_ACPI |
1da177e4 | 3869 | |
54168ed7 | 3870 | #ifdef CONFIG_X86_32 |
36062448 | 3871 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3872 | { |
3873 | union IO_APIC_reg_00 reg_00; | |
3874 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3875 | physid_mask_t tmp; | |
3876 | unsigned long flags; | |
3877 | int i = 0; | |
3878 | ||
3879 | /* | |
36062448 PC |
3880 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3881 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3882 | * supports up to 16 on one shared APIC bus. |
36062448 | 3883 | * |
1da177e4 LT |
3884 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3885 | * advantage of new APIC bus architecture. | |
3886 | */ | |
3887 | ||
3888 | if (physids_empty(apic_id_map)) | |
3889 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3890 | ||
3891 | spin_lock_irqsave(&ioapic_lock, flags); | |
3892 | reg_00.raw = io_apic_read(ioapic, 0); | |
3893 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3894 | ||
3895 | if (apic_id >= get_physical_broadcast()) { | |
3896 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3897 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3898 | apic_id = reg_00.bits.ID; | |
3899 | } | |
3900 | ||
3901 | /* | |
36062448 | 3902 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3903 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3904 | */ | |
3905 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3906 | ||
3907 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3908 | if (!check_apicid_used(apic_id_map, i)) | |
3909 | break; | |
3910 | } | |
3911 | ||
3912 | if (i == get_physical_broadcast()) | |
3913 | panic("Max apic_id exceeded!\n"); | |
3914 | ||
3915 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3916 | "trying %d\n", ioapic, apic_id, i); | |
3917 | ||
3918 | apic_id = i; | |
36062448 | 3919 | } |
1da177e4 LT |
3920 | |
3921 | tmp = apicid_to_cpu_present(apic_id); | |
3922 | physids_or(apic_id_map, apic_id_map, tmp); | |
3923 | ||
3924 | if (reg_00.bits.ID != apic_id) { | |
3925 | reg_00.bits.ID = apic_id; | |
3926 | ||
3927 | spin_lock_irqsave(&ioapic_lock, flags); | |
3928 | io_apic_write(ioapic, 0, reg_00.raw); | |
3929 | reg_00.raw = io_apic_read(ioapic, 0); | |
3930 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3931 | ||
3932 | /* Sanity check */ | |
6070f9ec AD |
3933 | if (reg_00.bits.ID != apic_id) { |
3934 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3935 | return -1; | |
3936 | } | |
1da177e4 LT |
3937 | } |
3938 | ||
3939 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3940 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3941 | ||
3942 | return apic_id; | |
3943 | } | |
3944 | ||
36062448 | 3945 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3946 | { |
3947 | union IO_APIC_reg_01 reg_01; | |
3948 | unsigned long flags; | |
3949 | ||
3950 | spin_lock_irqsave(&ioapic_lock, flags); | |
3951 | reg_01.raw = io_apic_read(ioapic, 1); | |
3952 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3953 | ||
3954 | return reg_01.bits.version; | |
3955 | } | |
54168ed7 | 3956 | #endif |
1da177e4 | 3957 | |
54168ed7 | 3958 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3959 | { |
0b8f1efa YL |
3960 | struct irq_desc *desc; |
3961 | struct irq_cfg *cfg; | |
3962 | int cpu = boot_cpu_id; | |
3963 | ||
1da177e4 | 3964 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3965 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3966 | ioapic); |
3967 | return -EINVAL; | |
3968 | } | |
3969 | ||
0b8f1efa YL |
3970 | desc = irq_to_desc_alloc_cpu(irq, cpu); |
3971 | if (!desc) { | |
3972 | printk(KERN_INFO "can not get irq_desc %d\n", irq); | |
3973 | return 0; | |
3974 | } | |
3975 | ||
1da177e4 LT |
3976 | /* |
3977 | * IRQs < 16 are already in the irq_2_pin[] map | |
3978 | */ | |
99d093d1 | 3979 | if (irq >= NR_IRQS_LEGACY) { |
0b8f1efa | 3980 | cfg = desc->chip_data; |
3145e941 | 3981 | add_pin_to_irq_cpu(cfg, cpu, ioapic, pin); |
0b8f1efa | 3982 | } |
1da177e4 | 3983 | |
3145e941 | 3984 | setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity); |
1da177e4 LT |
3985 | |
3986 | return 0; | |
3987 | } | |
3988 | ||
54168ed7 | 3989 | |
61fd47e0 SL |
3990 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3991 | { | |
3992 | int i; | |
3993 | ||
3994 | if (skip_ioapic_setup) | |
3995 | return -1; | |
3996 | ||
3997 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
3998 | if (mp_irqs[i].mp_irqtype == mp_INT && |
3999 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
4000 | break; |
4001 | if (i >= mp_irq_entries) | |
4002 | return -1; | |
4003 | ||
4004 | *trigger = irq_trigger(i); | |
4005 | *polarity = irq_polarity(i); | |
4006 | return 0; | |
4007 | } | |
4008 | ||
888ba6c6 | 4009 | #endif /* CONFIG_ACPI */ |
1a3f239d | 4010 | |
497c9a19 YL |
4011 | /* |
4012 | * This function currently is only a helper for the i386 smp boot process where | |
4013 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
4014 | * so mask in all cases should simply be TARGET_CPUS | |
4015 | */ | |
4016 | #ifdef CONFIG_SMP | |
4017 | void __init setup_ioapic_dest(void) | |
4018 | { | |
4019 | int pin, ioapic, irq, irq_entry; | |
6c2e9403 | 4020 | struct irq_desc *desc; |
497c9a19 | 4021 | struct irq_cfg *cfg; |
22f65d31 | 4022 | const struct cpumask *mask; |
497c9a19 YL |
4023 | |
4024 | if (skip_ioapic_setup == 1) | |
4025 | return; | |
4026 | ||
4027 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
4028 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
4029 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
4030 | if (irq_entry == -1) | |
4031 | continue; | |
4032 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
4033 | ||
4034 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
4035 | * when you have too many devices, because at that time only boot | |
4036 | * cpu is online. | |
4037 | */ | |
0b8f1efa YL |
4038 | desc = irq_to_desc(irq); |
4039 | cfg = desc->chip_data; | |
6c2e9403 | 4040 | if (!cfg->vector) { |
3145e941 | 4041 | setup_IO_APIC_irq(ioapic, pin, irq, desc, |
497c9a19 YL |
4042 | irq_trigger(irq_entry), |
4043 | irq_polarity(irq_entry)); | |
6c2e9403 TG |
4044 | continue; |
4045 | ||
4046 | } | |
4047 | ||
4048 | /* | |
4049 | * Honour affinities which have been set in early boot | |
4050 | */ | |
6c2e9403 TG |
4051 | if (desc->status & |
4052 | (IRQ_NO_BALANCING | IRQ_AFFINITY_SET)) | |
e7986739 | 4053 | mask = &desc->affinity; |
6c2e9403 TG |
4054 | else |
4055 | mask = TARGET_CPUS; | |
4056 | ||
54168ed7 | 4057 | #ifdef CONFIG_INTR_REMAP |
6c2e9403 | 4058 | if (intr_remapping_enabled) |
3145e941 | 4059 | set_ir_ioapic_affinity_irq_desc(desc, mask); |
54168ed7 | 4060 | else |
6c2e9403 | 4061 | #endif |
3145e941 | 4062 | set_ioapic_affinity_irq_desc(desc, mask); |
497c9a19 YL |
4063 | } |
4064 | ||
4065 | } | |
4066 | } | |
4067 | #endif | |
4068 | ||
54168ed7 IM |
4069 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
4070 | ||
4071 | static struct resource *ioapic_resources; | |
4072 | ||
4073 | static struct resource * __init ioapic_setup_resources(void) | |
4074 | { | |
4075 | unsigned long n; | |
4076 | struct resource *res; | |
4077 | char *mem; | |
4078 | int i; | |
4079 | ||
4080 | if (nr_ioapics <= 0) | |
4081 | return NULL; | |
4082 | ||
4083 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
4084 | n *= nr_ioapics; | |
4085 | ||
4086 | mem = alloc_bootmem(n); | |
4087 | res = (void *)mem; | |
4088 | ||
4089 | if (mem != NULL) { | |
4090 | mem += sizeof(struct resource) * nr_ioapics; | |
4091 | ||
4092 | for (i = 0; i < nr_ioapics; i++) { | |
4093 | res[i].name = mem; | |
4094 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
4095 | sprintf(mem, "IOAPIC %u", i); | |
4096 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
4097 | } | |
4098 | } | |
4099 | ||
4100 | ioapic_resources = res; | |
4101 | ||
4102 | return res; | |
4103 | } | |
54168ed7 | 4104 | |
f3294a33 YL |
4105 | void __init ioapic_init_mappings(void) |
4106 | { | |
4107 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
54168ed7 | 4108 | struct resource *ioapic_res; |
d6c88a50 | 4109 | int i; |
f3294a33 | 4110 | |
54168ed7 | 4111 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
4112 | for (i = 0; i < nr_ioapics; i++) { |
4113 | if (smp_found_config) { | |
4114 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
54168ed7 | 4115 | #ifdef CONFIG_X86_32 |
d6c88a50 TG |
4116 | if (!ioapic_phys) { |
4117 | printk(KERN_ERR | |
4118 | "WARNING: bogus zero IO-APIC " | |
4119 | "address found in MPTABLE, " | |
4120 | "disabling IO/APIC support!\n"); | |
4121 | smp_found_config = 0; | |
4122 | skip_ioapic_setup = 1; | |
4123 | goto fake_ioapic_page; | |
4124 | } | |
54168ed7 | 4125 | #endif |
f3294a33 | 4126 | } else { |
54168ed7 | 4127 | #ifdef CONFIG_X86_32 |
f3294a33 | 4128 | fake_ioapic_page: |
54168ed7 | 4129 | #endif |
f3294a33 | 4130 | ioapic_phys = (unsigned long) |
54168ed7 | 4131 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
4132 | ioapic_phys = __pa(ioapic_phys); |
4133 | } | |
4134 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
4135 | apic_printk(APIC_VERBOSE, |
4136 | "mapped IOAPIC to %08lx (%08lx)\n", | |
4137 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 4138 | idx++; |
54168ed7 | 4139 | |
54168ed7 IM |
4140 | if (ioapic_res != NULL) { |
4141 | ioapic_res->start = ioapic_phys; | |
4142 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
4143 | ioapic_res++; | |
4144 | } | |
f3294a33 YL |
4145 | } |
4146 | } | |
4147 | ||
54168ed7 IM |
4148 | static int __init ioapic_insert_resources(void) |
4149 | { | |
4150 | int i; | |
4151 | struct resource *r = ioapic_resources; | |
4152 | ||
4153 | if (!r) { | |
4154 | printk(KERN_ERR | |
4155 | "IO APIC resources could be not be allocated.\n"); | |
4156 | return -1; | |
4157 | } | |
4158 | ||
4159 | for (i = 0; i < nr_ioapics; i++) { | |
4160 | insert_resource(&iomem_resource, r); | |
4161 | r++; | |
4162 | } | |
4163 | ||
4164 | return 0; | |
4165 | } | |
4166 | ||
4167 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
4168 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
4169 | late_initcall(ioapic_insert_resources); |