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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
d4057bdb | 28 | #include <linux/pci.h> |
1da177e4 LT |
29 | #include <linux/mc146818rtc.h> |
30 | #include <linux/compiler.h> | |
31 | #include <linux/acpi.h> | |
129f6946 | 32 | #include <linux/module.h> |
1da177e4 | 33 | #include <linux/sysdev.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
54168ed7 | 38 | #include <linux/jiffies.h> /* time_after() */ |
d4057bdb YL |
39 | #ifdef CONFIG_ACPI |
40 | #include <acpi/acpi_bus.h> | |
41 | #endif | |
42 | #include <linux/bootmem.h> | |
43 | #include <linux/dmar.h> | |
54d5d424 | 44 | |
d4057bdb | 45 | #include <asm/idle.h> |
1da177e4 LT |
46 | #include <asm/io.h> |
47 | #include <asm/smp.h> | |
48 | #include <asm/desc.h> | |
d4057bdb YL |
49 | #include <asm/proto.h> |
50 | #include <asm/acpi.h> | |
51 | #include <asm/dma.h> | |
1da177e4 | 52 | #include <asm/timer.h> |
306e440d | 53 | #include <asm/i8259.h> |
3e4ff115 | 54 | #include <asm/nmi.h> |
2d3fcc1c | 55 | #include <asm/msidef.h> |
8b955b0d | 56 | #include <asm/hypertransport.h> |
a4dbc34d | 57 | #include <asm/setup.h> |
d4057bdb | 58 | #include <asm/irq_remapping.h> |
1da177e4 | 59 | |
497c9a19 | 60 | #include <mach_ipi.h> |
1da177e4 | 61 | #include <mach_apic.h> |
874c4fe3 | 62 | #include <mach_apicdef.h> |
1da177e4 | 63 | |
32f71aff MR |
64 | #define __apicdebuginit(type) static type __init |
65 | ||
1da177e4 | 66 | /* |
54168ed7 IM |
67 | * Is the SiS APIC rmw bug present ? |
68 | * -1 = don't know, 0 = no, 1 = yes | |
1da177e4 LT |
69 | */ |
70 | int sis_apic_bug = -1; | |
71 | ||
efa2559f YL |
72 | static DEFINE_SPINLOCK(ioapic_lock); |
73 | static DEFINE_SPINLOCK(vector_lock); | |
74 | ||
1da177e4 LT |
75 | /* |
76 | * # of IRQ routing registers | |
77 | */ | |
78 | int nr_ioapic_registers[MAX_IO_APICS]; | |
79 | ||
9f640ccb | 80 | /* I/O APIC entries */ |
ec2cd0a2 | 81 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
82 | int nr_ioapics; |
83 | ||
584f734d | 84 | /* MP IRQ source entries */ |
2fddb6e2 | 85 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
86 | |
87 | /* # of MP IRQ source entries */ | |
88 | int mp_irq_entries; | |
89 | ||
8732fc4b AS |
90 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
91 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
92 | #endif | |
93 | ||
94 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
95 | ||
efa2559f YL |
96 | int skip_ioapic_setup; |
97 | ||
54168ed7 | 98 | static int __init parse_noapic(char *str) |
efa2559f YL |
99 | { |
100 | /* disable IO-APIC */ | |
101 | disable_ioapic_setup(); | |
102 | return 0; | |
103 | } | |
104 | early_param("noapic", parse_noapic); | |
66759a01 | 105 | |
da51a821 | 106 | struct irq_cfg; |
0f978f45 | 107 | struct irq_pin_list; |
a1420f39 | 108 | struct irq_cfg { |
da51a821 YL |
109 | unsigned int irq; |
110 | struct irq_cfg *next; | |
0f978f45 | 111 | struct irq_pin_list *irq_2_pin; |
497c9a19 YL |
112 | cpumask_t domain; |
113 | cpumask_t old_domain; | |
114 | unsigned move_cleanup_count; | |
a1420f39 | 115 | u8 vector; |
497c9a19 | 116 | u8 move_in_progress : 1; |
a1420f39 YL |
117 | }; |
118 | ||
a1420f39 YL |
119 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
120 | static struct irq_cfg irq_cfg_legacy[] __initdata = { | |
497c9a19 YL |
121 | [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, }, |
122 | [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, }, | |
123 | [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, }, | |
124 | [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, }, | |
125 | [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, }, | |
126 | [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, }, | |
127 | [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, }, | |
128 | [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, }, | |
129 | [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, }, | |
130 | [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, }, | |
131 | [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, }, | |
132 | [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, }, | |
133 | [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, }, | |
134 | [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, }, | |
135 | [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, }, | |
136 | [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, }, | |
a1420f39 YL |
137 | }; |
138 | ||
da51a821 YL |
139 | static struct irq_cfg irq_cfg_init = { .irq = -1U, }; |
140 | /* need to be biger than size of irq_cfg_legacy */ | |
141 | static int nr_irq_cfg = 32; | |
142 | ||
143 | static int __init parse_nr_irq_cfg(char *arg) | |
144 | { | |
145 | if (arg) { | |
146 | nr_irq_cfg = simple_strtoul(arg, NULL, 0); | |
147 | if (nr_irq_cfg < 32) | |
148 | nr_irq_cfg = 32; | |
149 | } | |
150 | return 0; | |
151 | } | |
152 | ||
153 | early_param("nr_irq_cfg", parse_nr_irq_cfg); | |
154 | ||
155 | static void init_one_irq_cfg(struct irq_cfg *cfg) | |
156 | { | |
157 | memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg)); | |
158 | } | |
159 | ||
160 | static struct irq_cfg *irq_cfgx; | |
161 | static struct irq_cfg *irq_cfgx_free; | |
a1420f39 YL |
162 | static void __init init_work(void *data) |
163 | { | |
da51a821 YL |
164 | struct dyn_array *da = data; |
165 | struct irq_cfg *cfg; | |
166 | int legacy_count; | |
167 | int i; | |
168 | ||
169 | cfg = *da->name; | |
a1420f39 | 170 | |
da51a821 | 171 | memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy)); |
a1420f39 | 172 | |
da51a821 YL |
173 | legacy_count = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]); |
174 | for (i = legacy_count; i < *da->nr; i++) | |
175 | init_one_irq_cfg(&cfg[i]); | |
a1420f39 | 176 | |
da51a821 YL |
177 | for (i = 1; i < *da->nr; i++) |
178 | cfg[i-1].next = &cfg[i]; | |
a1420f39 | 179 | |
da51a821 YL |
180 | irq_cfgx_free = &irq_cfgx[legacy_count]; |
181 | irq_cfgx[legacy_count - 1].next = NULL; | |
a1420f39 YL |
182 | } |
183 | ||
54168ed7 | 184 | #define for_each_irq_cfg(cfg) \ |
da51a821 YL |
185 | for (cfg = irq_cfgx; cfg; cfg = cfg->next) |
186 | ||
187 | DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work); | |
a1420f39 YL |
188 | |
189 | static struct irq_cfg *irq_cfg(unsigned int irq) | |
190 | { | |
da51a821 YL |
191 | struct irq_cfg *cfg; |
192 | ||
193 | cfg = irq_cfgx; | |
194 | while (cfg) { | |
195 | if (cfg->irq == irq) | |
196 | return cfg; | |
197 | ||
198 | cfg = cfg->next; | |
199 | } | |
200 | ||
201 | return NULL; | |
202 | } | |
203 | ||
204 | static struct irq_cfg *irq_cfg_alloc(unsigned int irq) | |
205 | { | |
206 | struct irq_cfg *cfg, *cfg_pri; | |
207 | int i; | |
208 | int count = 0; | |
209 | ||
210 | cfg_pri = cfg = irq_cfgx; | |
211 | while (cfg) { | |
212 | if (cfg->irq == irq) | |
213 | return cfg; | |
214 | ||
215 | cfg_pri = cfg; | |
216 | cfg = cfg->next; | |
217 | count++; | |
218 | } | |
219 | ||
220 | if (!irq_cfgx_free) { | |
221 | unsigned long phys; | |
222 | unsigned long total_bytes; | |
223 | /* | |
224 | * we run out of pre-allocate ones, allocate more | |
225 | */ | |
226 | printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg); | |
227 | ||
228 | total_bytes = sizeof(struct irq_cfg) * nr_irq_cfg; | |
229 | if (after_bootmem) | |
230 | cfg = kzalloc(total_bytes, GFP_ATOMIC); | |
231 | else | |
232 | cfg = __alloc_bootmem_nopanic(total_bytes, PAGE_SIZE, 0); | |
a1420f39 | 233 | |
da51a821 YL |
234 | if (!cfg) |
235 | panic("please boot with nr_irq_cfg= %d\n", count * 2); | |
236 | ||
237 | phys = __pa(cfg); | |
238 | printk(KERN_DEBUG "irq_irq ==> [%#lx - %#lx]\n", phys, phys + total_bytes); | |
239 | ||
240 | for (i = 0; i < nr_irq_cfg; i++) | |
241 | init_one_irq_cfg(&cfg[i]); | |
242 | ||
243 | for (i = 1; i < nr_irq_cfg; i++) | |
244 | cfg[i-1].next = &cfg[i]; | |
245 | ||
246 | irq_cfgx_free = cfg; | |
247 | } | |
248 | ||
249 | cfg = irq_cfgx_free; | |
250 | irq_cfgx_free = irq_cfgx_free->next; | |
251 | cfg->next = NULL; | |
252 | if (cfg_pri) | |
253 | cfg_pri->next = cfg; | |
254 | else | |
255 | irq_cfgx = cfg; | |
256 | cfg->irq = irq; | |
257 | printk(KERN_DEBUG "found new irq_cfg for irq %d\n", cfg->irq); | |
da51a821 YL |
258 | #ifdef CONFIG_HAVE_SPARSE_IRQ_DEBUG |
259 | { | |
260 | /* dump the results */ | |
261 | struct irq_cfg *cfg; | |
262 | unsigned long phys; | |
263 | unsigned long bytes = sizeof(struct irq_cfg); | |
264 | ||
265 | printk(KERN_DEBUG "=========================== %d\n", irq); | |
266 | printk(KERN_DEBUG "irq_cfg dump after get that for %d\n", irq); | |
267 | for_each_irq_cfg(cfg) { | |
268 | phys = __pa(cfg); | |
269 | printk(KERN_DEBUG "irq_cfg %d ==> [%#lx - %#lx]\n", cfg->irq, phys, phys + bytes); | |
270 | } | |
271 | printk(KERN_DEBUG "===========================\n"); | |
272 | } | |
273 | #endif | |
274 | return cfg; | |
a1420f39 YL |
275 | } |
276 | ||
1da177e4 LT |
277 | /* |
278 | * This is performance-critical, we want to do it O(1) | |
279 | * | |
280 | * the indexing order of this array favors 1:1 mappings | |
281 | * between pins and IRQs. | |
282 | */ | |
283 | ||
0f978f45 YL |
284 | struct irq_pin_list { |
285 | int apic, pin; | |
286 | struct irq_pin_list *next; | |
287 | }; | |
288 | ||
289 | static struct irq_pin_list *irq_2_pin_head; | |
290 | /* fill one page ? */ | |
291 | static int nr_irq_2_pin = 0x100; | |
292 | static struct irq_pin_list *irq_2_pin_ptr; | |
293 | static void __init irq_2_pin_init_work(void *data) | |
294 | { | |
295 | struct dyn_array *da = data; | |
296 | struct irq_pin_list *pin; | |
297 | int i; | |
298 | ||
299 | pin = *da->name; | |
300 | ||
301 | for (i = 1; i < *da->nr; i++) | |
302 | pin[i-1].next = &pin[i]; | |
303 | ||
304 | irq_2_pin_ptr = &pin[0]; | |
305 | } | |
306 | DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work); | |
307 | ||
308 | static struct irq_pin_list *get_one_free_irq_2_pin(void) | |
309 | { | |
310 | struct irq_pin_list *pin; | |
311 | int i; | |
312 | ||
313 | pin = irq_2_pin_ptr; | |
314 | ||
315 | if (pin) { | |
316 | irq_2_pin_ptr = pin->next; | |
317 | pin->next = NULL; | |
318 | return pin; | |
319 | } | |
320 | ||
321 | /* | |
322 | * we run out of pre-allocate ones, allocate more | |
323 | */ | |
324 | printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin); | |
325 | ||
326 | if (after_bootmem) | |
327 | pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin, | |
328 | GFP_ATOMIC); | |
329 | else | |
330 | pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) * | |
331 | nr_irq_2_pin, PAGE_SIZE, 0); | |
332 | ||
333 | if (!pin) | |
334 | panic("can not get more irq_2_pin\n"); | |
301e6190 | 335 | |
0f978f45 YL |
336 | for (i = 1; i < nr_irq_2_pin; i++) |
337 | pin[i-1].next = &pin[i]; | |
338 | ||
339 | irq_2_pin_ptr = pin->next; | |
340 | pin->next = NULL; | |
341 | ||
342 | return pin; | |
343 | } | |
1da177e4 | 344 | |
130fe05d LT |
345 | struct io_apic { |
346 | unsigned int index; | |
347 | unsigned int unused[3]; | |
348 | unsigned int data; | |
349 | }; | |
350 | ||
351 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
352 | { | |
353 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 354 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
355 | } |
356 | ||
357 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
358 | { | |
359 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
360 | writel(reg, &io_apic->index); | |
361 | return readl(&io_apic->data); | |
362 | } | |
363 | ||
364 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
365 | { | |
366 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
367 | writel(reg, &io_apic->index); | |
368 | writel(value, &io_apic->data); | |
369 | } | |
370 | ||
371 | /* | |
372 | * Re-write a value: to be used for read-modify-write | |
373 | * cycles where the read already set up the index register. | |
374 | * | |
375 | * Older SiS APIC requires we rewrite the index register | |
376 | */ | |
377 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
378 | { | |
54168ed7 IM |
379 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
380 | if (sis_apic_bug) | |
381 | writel(reg, &io_apic->index); | |
130fe05d LT |
382 | writel(value, &io_apic->data); |
383 | } | |
384 | ||
047c8fdb YL |
385 | static bool io_apic_level_ack_pending(unsigned int irq) |
386 | { | |
387 | struct irq_pin_list *entry; | |
388 | unsigned long flags; | |
389 | struct irq_cfg *cfg = irq_cfg(irq); | |
390 | ||
391 | spin_lock_irqsave(&ioapic_lock, flags); | |
392 | entry = cfg->irq_2_pin; | |
393 | for (;;) { | |
394 | unsigned int reg; | |
395 | int pin; | |
396 | ||
397 | if (!entry) | |
398 | break; | |
399 | pin = entry->pin; | |
400 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
401 | /* Is the remote IRR bit set? */ | |
402 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { | |
403 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
404 | return true; | |
405 | } | |
406 | if (!entry->next) | |
407 | break; | |
408 | entry = entry->next; | |
409 | } | |
410 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
411 | ||
412 | return false; | |
413 | } | |
047c8fdb | 414 | |
cf4c6a2f AK |
415 | union entry_union { |
416 | struct { u32 w1, w2; }; | |
417 | struct IO_APIC_route_entry entry; | |
418 | }; | |
419 | ||
420 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
421 | { | |
422 | union entry_union eu; | |
423 | unsigned long flags; | |
424 | spin_lock_irqsave(&ioapic_lock, flags); | |
425 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
426 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
427 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
428 | return eu.entry; | |
429 | } | |
430 | ||
f9dadfa7 LT |
431 | /* |
432 | * When we write a new IO APIC routing entry, we need to write the high | |
433 | * word first! If the mask bit in the low word is clear, we will enable | |
434 | * the interrupt, and we need to make sure the entry is fully populated | |
435 | * before that happens. | |
436 | */ | |
d15512f4 AK |
437 | static void |
438 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 439 | { |
cf4c6a2f AK |
440 | union entry_union eu; |
441 | eu.entry = e; | |
f9dadfa7 LT |
442 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
443 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
444 | } |
445 | ||
446 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
447 | { | |
448 | unsigned long flags; | |
449 | spin_lock_irqsave(&ioapic_lock, flags); | |
450 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
451 | spin_unlock_irqrestore(&ioapic_lock, flags); |
452 | } | |
453 | ||
454 | /* | |
455 | * When we mask an IO APIC routing entry, we need to write the low | |
456 | * word first, in order to set the mask bit before we change the | |
457 | * high bits! | |
458 | */ | |
459 | static void ioapic_mask_entry(int apic, int pin) | |
460 | { | |
461 | unsigned long flags; | |
462 | union entry_union eu = { .entry.mask = 1 }; | |
463 | ||
cf4c6a2f AK |
464 | spin_lock_irqsave(&ioapic_lock, flags); |
465 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
466 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
467 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
468 | } | |
469 | ||
497c9a19 YL |
470 | #ifdef CONFIG_SMP |
471 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector) | |
472 | { | |
473 | int apic, pin; | |
474 | struct irq_cfg *cfg; | |
475 | struct irq_pin_list *entry; | |
476 | ||
477 | cfg = irq_cfg(irq); | |
478 | entry = cfg->irq_2_pin; | |
479 | for (;;) { | |
480 | unsigned int reg; | |
481 | ||
482 | if (!entry) | |
483 | break; | |
484 | ||
485 | apic = entry->apic; | |
486 | pin = entry->pin; | |
54168ed7 IM |
487 | #ifdef CONFIG_INTR_REMAP |
488 | /* | |
489 | * With interrupt-remapping, destination information comes | |
490 | * from interrupt-remapping table entry. | |
491 | */ | |
492 | if (!irq_remapped(irq)) | |
493 | io_apic_write(apic, 0x11 + pin*2, dest); | |
494 | #else | |
497c9a19 | 495 | io_apic_write(apic, 0x11 + pin*2, dest); |
54168ed7 | 496 | #endif |
497c9a19 YL |
497 | reg = io_apic_read(apic, 0x10 + pin*2); |
498 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | |
499 | reg |= vector; | |
54168ed7 | 500 | io_apic_modify(apic, 0x10 + pin*2, reg); |
497c9a19 YL |
501 | if (!entry->next) |
502 | break; | |
503 | entry = entry->next; | |
504 | } | |
505 | } | |
efa2559f YL |
506 | |
507 | static int assign_irq_vector(int irq, cpumask_t mask); | |
508 | ||
497c9a19 YL |
509 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) |
510 | { | |
511 | struct irq_cfg *cfg; | |
512 | unsigned long flags; | |
513 | unsigned int dest; | |
514 | cpumask_t tmp; | |
54168ed7 | 515 | struct irq_desc *desc; |
497c9a19 | 516 | |
497c9a19 YL |
517 | cpus_and(tmp, mask, cpu_online_map); |
518 | if (cpus_empty(tmp)) | |
519 | return; | |
520 | ||
047c8fdb | 521 | cfg = irq_cfg(irq); |
497c9a19 YL |
522 | if (assign_irq_vector(irq, mask)) |
523 | return; | |
524 | ||
525 | cpus_and(tmp, cfg->domain, mask); | |
497c9a19 YL |
526 | dest = cpu_mask_to_apicid(tmp); |
527 | /* | |
528 | * Only the high 8 bits are valid. | |
529 | */ | |
530 | dest = SET_APIC_LOGICAL_ID(dest); | |
531 | ||
54168ed7 | 532 | desc = irq_to_desc(irq); |
497c9a19 YL |
533 | spin_lock_irqsave(&ioapic_lock, flags); |
534 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
54168ed7 | 535 | desc->affinity = mask; |
497c9a19 YL |
536 | spin_unlock_irqrestore(&ioapic_lock, flags); |
537 | } | |
497c9a19 YL |
538 | #endif /* CONFIG_SMP */ |
539 | ||
1da177e4 LT |
540 | /* |
541 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
542 | * shared ISA-space IRQs, so we have to support them. We are super | |
543 | * fast in the common case, and fast for shared ISA-space IRQs. | |
544 | */ | |
545 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
546 | { | |
0f978f45 YL |
547 | struct irq_cfg *cfg; |
548 | struct irq_pin_list *entry; | |
549 | ||
550 | /* first time to refer irq_cfg, so with new */ | |
551 | cfg = irq_cfg_alloc(irq); | |
552 | entry = cfg->irq_2_pin; | |
553 | if (!entry) { | |
554 | entry = get_one_free_irq_2_pin(); | |
555 | cfg->irq_2_pin = entry; | |
556 | entry->apic = apic; | |
557 | entry->pin = pin; | |
558 | printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin); | |
559 | return; | |
560 | } | |
1da177e4 | 561 | |
0f978f45 YL |
562 | while (entry->next) { |
563 | /* not again, please */ | |
564 | if (entry->apic == apic && entry->pin == pin) | |
565 | return; | |
1da177e4 | 566 | |
0f978f45 | 567 | entry = entry->next; |
1da177e4 | 568 | } |
0f978f45 YL |
569 | |
570 | entry->next = get_one_free_irq_2_pin(); | |
571 | entry = entry->next; | |
1da177e4 LT |
572 | entry->apic = apic; |
573 | entry->pin = pin; | |
0f978f45 | 574 | printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin); |
1da177e4 LT |
575 | } |
576 | ||
577 | /* | |
578 | * Reroute an IRQ to a different pin. | |
579 | */ | |
580 | static void __init replace_pin_at_irq(unsigned int irq, | |
581 | int oldapic, int oldpin, | |
582 | int newapic, int newpin) | |
583 | { | |
0f978f45 YL |
584 | struct irq_cfg *cfg = irq_cfg(irq); |
585 | struct irq_pin_list *entry = cfg->irq_2_pin; | |
586 | int replaced = 0; | |
1da177e4 | 587 | |
0f978f45 | 588 | while (entry) { |
1da177e4 LT |
589 | if (entry->apic == oldapic && entry->pin == oldpin) { |
590 | entry->apic = newapic; | |
591 | entry->pin = newpin; | |
0f978f45 YL |
592 | replaced = 1; |
593 | /* every one is different, right? */ | |
1da177e4 | 594 | break; |
0f978f45 YL |
595 | } |
596 | entry = entry->next; | |
1da177e4 | 597 | } |
0f978f45 YL |
598 | |
599 | /* why? call replace before add? */ | |
600 | if (!replaced) | |
601 | add_pin_to_irq(irq, newapic, newpin); | |
1da177e4 LT |
602 | } |
603 | ||
4e738e2f | 604 | #define __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \ |
047c8fdb YL |
605 | \ |
606 | { \ | |
607 | int pin; \ | |
608 | struct irq_cfg *cfg; \ | |
609 | struct irq_pin_list *entry; \ | |
610 | \ | |
611 | cfg = irq_cfg(irq); \ | |
612 | entry = cfg->irq_2_pin; \ | |
613 | for (;;) { \ | |
614 | unsigned int reg; \ | |
615 | if (!entry) \ | |
616 | break; \ | |
617 | pin = entry->pin; \ | |
618 | reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ | |
4e738e2f YL |
619 | reg ACTION_DISABLE; \ |
620 | reg ACTION_ENABLE; \ | |
047c8fdb YL |
621 | io_apic_modify(entry->apic, 0x10 + R + pin*2, reg); \ |
622 | FINAL; \ | |
623 | if (!entry->next) \ | |
624 | break; \ | |
625 | entry = entry->next; \ | |
626 | } \ | |
627 | } | |
628 | ||
4e738e2f | 629 | #define DO_ACTION(name,R, ACTION_ENABLE, ACTION_DISABLE, FINAL) \ |
047c8fdb YL |
630 | \ |
631 | static void name##_IO_APIC_irq (unsigned int irq) \ | |
4e738e2f | 632 | __DO_ACTION(R, ACTION_ENABLE, ACTION_DISABLE, FINAL) |
047c8fdb YL |
633 | |
634 | /* mask = 0 */ | |
4e738e2f | 635 | DO_ACTION(__unmask, 0, |= 0, &= ~IO_APIC_REDIR_MASKED, ) |
047c8fdb | 636 | |
4e738e2f YL |
637 | #ifdef CONFIG_X86_64 |
638 | /* | |
639 | * Synchronize the IO-APIC and the CPU by doing | |
640 | * a dummy read from the IO-APIC | |
641 | */ | |
642 | static inline void io_apic_sync(unsigned int apic) | |
1da177e4 | 643 | { |
4e738e2f YL |
644 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
645 | readl(&io_apic->data); | |
1da177e4 LT |
646 | } |
647 | ||
648 | /* mask = 1 */ | |
4e738e2f | 649 | DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, io_apic_sync(entry->apic)) |
1da177e4 | 650 | |
4e738e2f YL |
651 | #else |
652 | ||
653 | /* mask = 1 */ | |
654 | DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, &= ~0, ) | |
1da177e4 LT |
655 | |
656 | /* mask = 1, trigger = 0 */ | |
4e738e2f | 657 | DO_ACTION(__mask_and_edge, 0, |= IO_APIC_REDIR_MASKED, &= ~IO_APIC_REDIR_LEVEL_TRIGGER, ) |
1da177e4 LT |
658 | |
659 | /* mask = 0, trigger = 1 */ | |
4e738e2f | 660 | DO_ACTION(__unmask_and_level, 0, |= IO_APIC_REDIR_LEVEL_TRIGGER, &= ~IO_APIC_REDIR_MASKED, ) |
1da177e4 | 661 | |
047c8fdb YL |
662 | #endif |
663 | ||
54168ed7 | 664 | static void mask_IO_APIC_irq (unsigned int irq) |
1da177e4 LT |
665 | { |
666 | unsigned long flags; | |
667 | ||
668 | spin_lock_irqsave(&ioapic_lock, flags); | |
669 | __mask_IO_APIC_irq(irq); | |
670 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
671 | } | |
672 | ||
54168ed7 | 673 | static void unmask_IO_APIC_irq (unsigned int irq) |
1da177e4 LT |
674 | { |
675 | unsigned long flags; | |
676 | ||
677 | spin_lock_irqsave(&ioapic_lock, flags); | |
678 | __unmask_IO_APIC_irq(irq); | |
679 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
680 | } | |
681 | ||
682 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
683 | { | |
684 | struct IO_APIC_route_entry entry; | |
36062448 | 685 | |
1da177e4 | 686 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 687 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
688 | if (entry.delivery_mode == dest_SMI) |
689 | return; | |
1da177e4 LT |
690 | /* |
691 | * Disable it in the IO-APIC irq-routing table: | |
692 | */ | |
f9dadfa7 | 693 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
694 | } |
695 | ||
54168ed7 | 696 | static void clear_IO_APIC (void) |
1da177e4 LT |
697 | { |
698 | int apic, pin; | |
699 | ||
700 | for (apic = 0; apic < nr_ioapics; apic++) | |
701 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
702 | clear_IO_APIC_pin(apic, pin); | |
703 | } | |
704 | ||
54168ed7 | 705 | #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32) |
75604d7f | 706 | void send_IPI_self(int vector) |
1da177e4 LT |
707 | { |
708 | unsigned int cfg; | |
709 | ||
710 | /* | |
711 | * Wait for idle. | |
712 | */ | |
713 | apic_wait_icr_idle(); | |
714 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
715 | /* | |
716 | * Send the IPI. The write to APIC_ICR fires this off. | |
717 | */ | |
593f4a78 | 718 | apic_write(APIC_ICR, cfg); |
1da177e4 | 719 | } |
54168ed7 | 720 | #endif /* !CONFIG_SMP && CONFIG_X86_32*/ |
1da177e4 | 721 | |
54168ed7 | 722 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
723 | /* |
724 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
725 | * specific CPU-side IRQs. | |
726 | */ | |
727 | ||
728 | #define MAX_PIRQS 8 | |
729 | static int pirq_entries [MAX_PIRQS]; | |
730 | static int pirqs_enabled; | |
1da177e4 | 731 | |
1da177e4 LT |
732 | static int __init ioapic_pirq_setup(char *str) |
733 | { | |
734 | int i, max; | |
735 | int ints[MAX_PIRQS+1]; | |
736 | ||
737 | get_options(str, ARRAY_SIZE(ints), ints); | |
738 | ||
739 | for (i = 0; i < MAX_PIRQS; i++) | |
740 | pirq_entries[i] = -1; | |
741 | ||
742 | pirqs_enabled = 1; | |
743 | apic_printk(APIC_VERBOSE, KERN_INFO | |
744 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
745 | max = MAX_PIRQS; | |
746 | if (ints[0] < MAX_PIRQS) | |
747 | max = ints[0]; | |
748 | ||
749 | for (i = 0; i < max; i++) { | |
750 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
751 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
752 | /* | |
753 | * PIRQs are mapped upside down, usually. | |
754 | */ | |
755 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
756 | } | |
757 | return 1; | |
758 | } | |
759 | ||
760 | __setup("pirq=", ioapic_pirq_setup); | |
54168ed7 IM |
761 | #endif /* CONFIG_X86_32 */ |
762 | ||
763 | #ifdef CONFIG_INTR_REMAP | |
764 | /* I/O APIC RTE contents at the OS boot up */ | |
765 | static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS]; | |
766 | ||
767 | /* | |
768 | * Saves and masks all the unmasked IO-APIC RTE's | |
769 | */ | |
770 | int save_mask_IO_APIC_setup(void) | |
771 | { | |
772 | union IO_APIC_reg_01 reg_01; | |
773 | unsigned long flags; | |
774 | int apic, pin; | |
775 | ||
776 | /* | |
777 | * The number of IO-APIC IRQ registers (== #pins): | |
778 | */ | |
779 | for (apic = 0; apic < nr_ioapics; apic++) { | |
780 | spin_lock_irqsave(&ioapic_lock, flags); | |
781 | reg_01.raw = io_apic_read(apic, 1); | |
782 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
783 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; | |
784 | } | |
785 | ||
786 | for (apic = 0; apic < nr_ioapics; apic++) { | |
787 | early_ioapic_entries[apic] = | |
788 | kzalloc(sizeof(struct IO_APIC_route_entry) * | |
789 | nr_ioapic_registers[apic], GFP_KERNEL); | |
790 | if (!early_ioapic_entries[apic]) | |
791 | return -ENOMEM; | |
792 | } | |
793 | ||
794 | for (apic = 0; apic < nr_ioapics; apic++) | |
795 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
796 | struct IO_APIC_route_entry entry; | |
797 | ||
798 | entry = early_ioapic_entries[apic][pin] = | |
799 | ioapic_read_entry(apic, pin); | |
800 | if (!entry.mask) { | |
801 | entry.mask = 1; | |
802 | ioapic_write_entry(apic, pin, entry); | |
803 | } | |
804 | } | |
805 | return 0; | |
806 | } | |
807 | ||
808 | void restore_IO_APIC_setup(void) | |
809 | { | |
810 | int apic, pin; | |
811 | ||
812 | for (apic = 0; apic < nr_ioapics; apic++) | |
813 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
814 | ioapic_write_entry(apic, pin, | |
815 | early_ioapic_entries[apic][pin]); | |
816 | } | |
817 | ||
818 | void reinit_intr_remapped_IO_APIC(int intr_remapping) | |
819 | { | |
820 | /* | |
821 | * for now plain restore of previous settings. | |
822 | * TBD: In the case of OS enabling interrupt-remapping, | |
823 | * IO-APIC RTE's need to be setup to point to interrupt-remapping | |
824 | * table entries. for now, do a plain restore, and wait for | |
825 | * the setup_IO_APIC_irqs() to do proper initialization. | |
826 | */ | |
827 | restore_IO_APIC_setup(); | |
828 | } | |
829 | #endif | |
1da177e4 LT |
830 | |
831 | /* | |
832 | * Find the IRQ entry number of a certain pin. | |
833 | */ | |
834 | static int find_irq_entry(int apic, int pin, int type) | |
835 | { | |
836 | int i; | |
837 | ||
838 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
839 | if (mp_irqs[i].mp_irqtype == type && |
840 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
841 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
842 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
843 | return i; |
844 | ||
845 | return -1; | |
846 | } | |
847 | ||
848 | /* | |
849 | * Find the pin to which IRQ[irq] (ISA) is connected | |
850 | */ | |
fcfd636a | 851 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
852 | { |
853 | int i; | |
854 | ||
855 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 856 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 857 | |
d27e2b8e | 858 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
859 | (mp_irqs[i].mp_irqtype == type) && |
860 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 861 | |
2fddb6e2 | 862 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
863 | } |
864 | return -1; | |
865 | } | |
866 | ||
fcfd636a EB |
867 | static int __init find_isa_irq_apic(int irq, int type) |
868 | { | |
869 | int i; | |
870 | ||
871 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 872 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 873 | |
73b2961b | 874 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
875 | (mp_irqs[i].mp_irqtype == type) && |
876 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
877 | break; |
878 | } | |
879 | if (i < mp_irq_entries) { | |
880 | int apic; | |
54168ed7 | 881 | for(apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 882 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
883 | return apic; |
884 | } | |
885 | } | |
886 | ||
887 | return -1; | |
888 | } | |
889 | ||
1da177e4 LT |
890 | /* |
891 | * Find a specific PCI IRQ entry. | |
892 | * Not an __init, possibly needed by modules | |
893 | */ | |
894 | static int pin_2_irq(int idx, int apic, int pin); | |
895 | ||
896 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
897 | { | |
898 | int apic, i, best_guess = -1; | |
899 | ||
54168ed7 IM |
900 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
901 | bus, slot, pin); | |
ce6444d3 | 902 | if (test_bit(bus, mp_bus_not_pci)) { |
54168ed7 | 903 | apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
1da177e4 LT |
904 | return -1; |
905 | } | |
906 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 907 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
908 | |
909 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
910 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
911 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
912 | break; |
913 | ||
47cab822 | 914 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 915 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 916 | (bus == lbus) && |
2fddb6e2 | 917 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
54168ed7 | 918 | int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq); |
1da177e4 LT |
919 | |
920 | if (!(apic || IO_APIC_IRQ(irq))) | |
921 | continue; | |
922 | ||
2fddb6e2 | 923 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
924 | return irq; |
925 | /* | |
926 | * Use the first all-but-pin matching entry as a | |
927 | * best-guess fuzzy result for broken mptables. | |
928 | */ | |
929 | if (best_guess < 0) | |
930 | best_guess = irq; | |
931 | } | |
932 | } | |
933 | return best_guess; | |
934 | } | |
54168ed7 | 935 | |
129f6946 | 936 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 | 937 | |
c0a282c2 | 938 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
939 | /* |
940 | * EISA Edge/Level control register, ELCR | |
941 | */ | |
942 | static int EISA_ELCR(unsigned int irq) | |
943 | { | |
944 | if (irq < 16) { | |
945 | unsigned int port = 0x4d0 + (irq >> 3); | |
946 | return (inb(port) >> (irq & 7)) & 1; | |
947 | } | |
948 | apic_printk(APIC_VERBOSE, KERN_INFO | |
949 | "Broken MPtable reports ISA irq %d\n", irq); | |
950 | return 0; | |
951 | } | |
54168ed7 | 952 | |
c0a282c2 | 953 | #endif |
1da177e4 | 954 | |
6728801d AS |
955 | /* ISA interrupts are always polarity zero edge triggered, |
956 | * when listed as conforming in the MP table. */ | |
957 | ||
958 | #define default_ISA_trigger(idx) (0) | |
959 | #define default_ISA_polarity(idx) (0) | |
960 | ||
1da177e4 LT |
961 | /* EISA interrupts are always polarity zero and can be edge or level |
962 | * trigger depending on the ELCR value. If an interrupt is listed as | |
963 | * EISA conforming in the MP table, that means its trigger type must | |
964 | * be read in from the ELCR */ | |
965 | ||
2fddb6e2 | 966 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 967 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
968 | |
969 | /* PCI interrupts are always polarity one level triggered, | |
970 | * when listed as conforming in the MP table. */ | |
971 | ||
972 | #define default_PCI_trigger(idx) (1) | |
973 | #define default_PCI_polarity(idx) (1) | |
974 | ||
975 | /* MCA interrupts are always polarity zero level triggered, | |
976 | * when listed as conforming in the MP table. */ | |
977 | ||
978 | #define default_MCA_trigger(idx) (1) | |
6728801d | 979 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 980 | |
61fd47e0 | 981 | static int MPBIOS_polarity(int idx) |
1da177e4 | 982 | { |
2fddb6e2 | 983 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
984 | int polarity; |
985 | ||
986 | /* | |
987 | * Determine IRQ line polarity (high active or low active): | |
988 | */ | |
54168ed7 | 989 | switch (mp_irqs[idx].mp_irqflag & 3) |
36062448 | 990 | { |
54168ed7 IM |
991 | case 0: /* conforms, ie. bus-type dependent polarity */ |
992 | if (test_bit(bus, mp_bus_not_pci)) | |
993 | polarity = default_ISA_polarity(idx); | |
994 | else | |
995 | polarity = default_PCI_polarity(idx); | |
996 | break; | |
997 | case 1: /* high active */ | |
998 | { | |
999 | polarity = 0; | |
1000 | break; | |
1001 | } | |
1002 | case 2: /* reserved */ | |
1003 | { | |
1004 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1005 | polarity = 1; | |
1006 | break; | |
1007 | } | |
1008 | case 3: /* low active */ | |
1009 | { | |
1010 | polarity = 1; | |
1011 | break; | |
1012 | } | |
1013 | default: /* invalid */ | |
1014 | { | |
1015 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1016 | polarity = 1; | |
1017 | break; | |
1018 | } | |
1da177e4 LT |
1019 | } |
1020 | return polarity; | |
1021 | } | |
1022 | ||
1023 | static int MPBIOS_trigger(int idx) | |
1024 | { | |
2fddb6e2 | 1025 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1026 | int trigger; |
1027 | ||
1028 | /* | |
1029 | * Determine IRQ trigger mode (edge or level sensitive): | |
1030 | */ | |
54168ed7 | 1031 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) |
1da177e4 | 1032 | { |
54168ed7 IM |
1033 | case 0: /* conforms, ie. bus-type dependent */ |
1034 | if (test_bit(bus, mp_bus_not_pci)) | |
1035 | trigger = default_ISA_trigger(idx); | |
1036 | else | |
1037 | trigger = default_PCI_trigger(idx); | |
c0a282c2 | 1038 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
54168ed7 IM |
1039 | switch (mp_bus_id_to_type[bus]) { |
1040 | case MP_BUS_ISA: /* ISA pin */ | |
1041 | { | |
1042 | /* set before the switch */ | |
1043 | break; | |
1044 | } | |
1045 | case MP_BUS_EISA: /* EISA pin */ | |
1046 | { | |
1047 | trigger = default_EISA_trigger(idx); | |
1048 | break; | |
1049 | } | |
1050 | case MP_BUS_PCI: /* PCI pin */ | |
1051 | { | |
1052 | /* set before the switch */ | |
1053 | break; | |
1054 | } | |
1055 | case MP_BUS_MCA: /* MCA pin */ | |
1056 | { | |
1057 | trigger = default_MCA_trigger(idx); | |
1058 | break; | |
1059 | } | |
1060 | default: | |
1061 | { | |
1062 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1063 | trigger = 1; | |
1064 | break; | |
1065 | } | |
1066 | } | |
1067 | #endif | |
1da177e4 | 1068 | break; |
54168ed7 | 1069 | case 1: /* edge */ |
1da177e4 | 1070 | { |
54168ed7 | 1071 | trigger = 0; |
1da177e4 LT |
1072 | break; |
1073 | } | |
54168ed7 | 1074 | case 2: /* reserved */ |
1da177e4 | 1075 | { |
54168ed7 IM |
1076 | printk(KERN_WARNING "broken BIOS!!\n"); |
1077 | trigger = 1; | |
1da177e4 LT |
1078 | break; |
1079 | } | |
54168ed7 | 1080 | case 3: /* level */ |
1da177e4 | 1081 | { |
54168ed7 | 1082 | trigger = 1; |
1da177e4 LT |
1083 | break; |
1084 | } | |
54168ed7 | 1085 | default: /* invalid */ |
1da177e4 LT |
1086 | { |
1087 | printk(KERN_WARNING "broken BIOS!!\n"); | |
54168ed7 | 1088 | trigger = 0; |
1da177e4 LT |
1089 | break; |
1090 | } | |
1091 | } | |
1092 | return trigger; | |
1093 | } | |
1094 | ||
1095 | static inline int irq_polarity(int idx) | |
1096 | { | |
1097 | return MPBIOS_polarity(idx); | |
1098 | } | |
1099 | ||
1100 | static inline int irq_trigger(int idx) | |
1101 | { | |
1102 | return MPBIOS_trigger(idx); | |
1103 | } | |
1104 | ||
efa2559f | 1105 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
1da177e4 LT |
1106 | static int pin_2_irq(int idx, int apic, int pin) |
1107 | { | |
1108 | int irq, i; | |
2fddb6e2 | 1109 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1110 | |
1111 | /* | |
1112 | * Debugging check, we are in big trouble if this message pops up! | |
1113 | */ | |
2fddb6e2 | 1114 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1115 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1116 | ||
54168ed7 | 1117 | if (test_bit(bus, mp_bus_not_pci)) { |
2fddb6e2 | 1118 | irq = mp_irqs[idx].mp_srcbusirq; |
54168ed7 | 1119 | } else { |
643befed AS |
1120 | /* |
1121 | * PCI IRQs are mapped in order | |
1122 | */ | |
1123 | i = irq = 0; | |
1124 | while (i < apic) | |
1125 | irq += nr_ioapic_registers[i++]; | |
1126 | irq += pin; | |
54168ed7 IM |
1127 | /* |
1128 | * For MPS mode, so far only needed by ES7000 platform | |
1129 | */ | |
1130 | if (ioapic_renumber_irq) | |
1131 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1132 | } |
1133 | ||
54168ed7 | 1134 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1135 | /* |
1136 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1137 | */ | |
1138 | if ((pin >= 16) && (pin <= 23)) { | |
1139 | if (pirq_entries[pin-16] != -1) { | |
1140 | if (!pirq_entries[pin-16]) { | |
1141 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1142 | "disabling PIRQ%d\n", pin-16); | |
1143 | } else { | |
1144 | irq = pirq_entries[pin-16]; | |
1145 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1146 | "using PIRQ%d -> IRQ %d\n", | |
1147 | pin-16, irq); | |
1148 | } | |
1149 | } | |
1150 | } | |
54168ed7 IM |
1151 | #endif |
1152 | ||
1da177e4 LT |
1153 | return irq; |
1154 | } | |
1155 | ||
497c9a19 YL |
1156 | void lock_vector_lock(void) |
1157 | { | |
1158 | /* Used to the online set of cpus does not change | |
1159 | * during assign_irq_vector. | |
1160 | */ | |
1161 | spin_lock(&vector_lock); | |
1162 | } | |
1da177e4 | 1163 | |
497c9a19 | 1164 | void unlock_vector_lock(void) |
1da177e4 | 1165 | { |
497c9a19 YL |
1166 | spin_unlock(&vector_lock); |
1167 | } | |
1da177e4 | 1168 | |
497c9a19 YL |
1169 | static int __assign_irq_vector(int irq, cpumask_t mask) |
1170 | { | |
047c8fdb YL |
1171 | /* |
1172 | * NOTE! The local APIC isn't very good at handling | |
1173 | * multiple interrupts at the same interrupt level. | |
1174 | * As the interrupt level is determined by taking the | |
1175 | * vector number and shifting that right by 4, we | |
1176 | * want to spread these out a bit so that they don't | |
1177 | * all fall in the same interrupt level. | |
1178 | * | |
1179 | * Also, we've got to be careful not to trash gate | |
1180 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
1181 | */ | |
54168ed7 IM |
1182 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0; |
1183 | unsigned int old_vector; | |
1184 | int cpu; | |
1185 | struct irq_cfg *cfg; | |
ace80ab7 | 1186 | |
54168ed7 | 1187 | cfg = irq_cfg(irq); |
8339f000 | 1188 | |
54168ed7 IM |
1189 | /* Only try and allocate irqs on cpus that are present */ |
1190 | cpus_and(mask, mask, cpu_online_map); | |
ace80ab7 | 1191 | |
54168ed7 IM |
1192 | if ((cfg->move_in_progress) || cfg->move_cleanup_count) |
1193 | return -EBUSY; | |
0a1ad60d | 1194 | |
54168ed7 IM |
1195 | old_vector = cfg->vector; |
1196 | if (old_vector) { | |
1197 | cpumask_t tmp; | |
1198 | cpus_and(tmp, cfg->domain, mask); | |
1199 | if (!cpus_empty(tmp)) | |
1200 | return 0; | |
1201 | } | |
497c9a19 | 1202 | |
54168ed7 IM |
1203 | for_each_cpu_mask_nr(cpu, mask) { |
1204 | cpumask_t domain, new_mask; | |
1205 | int new_cpu; | |
1206 | int vector, offset; | |
497c9a19 | 1207 | |
54168ed7 IM |
1208 | domain = vector_allocation_domain(cpu); |
1209 | cpus_and(new_mask, domain, cpu_online_map); | |
497c9a19 | 1210 | |
54168ed7 IM |
1211 | vector = current_vector; |
1212 | offset = current_offset; | |
497c9a19 | 1213 | next: |
54168ed7 IM |
1214 | vector += 8; |
1215 | if (vector >= first_system_vector) { | |
1216 | /* If we run out of vectors on large boxen, must share them. */ | |
1217 | offset = (offset + 1) % 8; | |
1218 | vector = FIRST_DEVICE_VECTOR + offset; | |
1219 | } | |
1220 | if (unlikely(current_vector == vector)) | |
1221 | continue; | |
047c8fdb | 1222 | #ifdef CONFIG_X86_64 |
54168ed7 IM |
1223 | if (vector == IA32_SYSCALL_VECTOR) |
1224 | goto next; | |
047c8fdb | 1225 | #else |
54168ed7 IM |
1226 | if (vector == SYSCALL_VECTOR) |
1227 | goto next; | |
047c8fdb | 1228 | #endif |
54168ed7 IM |
1229 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1230 | if (per_cpu(vector_irq, new_cpu)[vector] != -1) | |
1231 | goto next; | |
1232 | /* Found one! */ | |
1233 | current_vector = vector; | |
1234 | current_offset = offset; | |
1235 | if (old_vector) { | |
1236 | cfg->move_in_progress = 1; | |
1237 | cfg->old_domain = cfg->domain; | |
7a959cff | 1238 | } |
54168ed7 IM |
1239 | for_each_cpu_mask_nr(new_cpu, new_mask) |
1240 | per_cpu(vector_irq, new_cpu)[vector] = irq; | |
1241 | cfg->vector = vector; | |
1242 | cfg->domain = domain; | |
1243 | return 0; | |
1244 | } | |
1245 | return -ENOSPC; | |
497c9a19 YL |
1246 | } |
1247 | ||
1248 | static int assign_irq_vector(int irq, cpumask_t mask) | |
1249 | { | |
1250 | int err; | |
ace80ab7 | 1251 | unsigned long flags; |
ace80ab7 EB |
1252 | |
1253 | spin_lock_irqsave(&vector_lock, flags); | |
497c9a19 | 1254 | err = __assign_irq_vector(irq, mask); |
26a3c49c | 1255 | spin_unlock_irqrestore(&vector_lock, flags); |
497c9a19 YL |
1256 | return err; |
1257 | } | |
1258 | ||
1259 | static void __clear_irq_vector(int irq) | |
1260 | { | |
1261 | struct irq_cfg *cfg; | |
1262 | cpumask_t mask; | |
1263 | int cpu, vector; | |
1264 | ||
1265 | cfg = irq_cfg(irq); | |
1266 | BUG_ON(!cfg->vector); | |
1267 | ||
1268 | vector = cfg->vector; | |
1269 | cpus_and(mask, cfg->domain, cpu_online_map); | |
1270 | for_each_cpu_mask_nr(cpu, mask) | |
1271 | per_cpu(vector_irq, cpu)[vector] = -1; | |
1272 | ||
1273 | cfg->vector = 0; | |
1274 | cpus_clear(cfg->domain); | |
1275 | } | |
1276 | ||
1277 | void __setup_vector_irq(int cpu) | |
1278 | { | |
1279 | /* Initialize vector_irq on a new cpu */ | |
1280 | /* This function must be called with vector_lock held */ | |
1281 | int irq, vector; | |
1282 | struct irq_cfg *cfg; | |
1283 | ||
1284 | /* Mark the inuse vectors */ | |
1285 | for_each_irq_cfg(cfg) { | |
1286 | if (!cpu_isset(cpu, cfg->domain)) | |
1287 | continue; | |
1288 | vector = cfg->vector; | |
1289 | irq = cfg->irq; | |
1290 | per_cpu(vector_irq, cpu)[vector] = irq; | |
1291 | } | |
1292 | /* Mark the free vectors */ | |
1293 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
1294 | irq = per_cpu(vector_irq, cpu)[vector]; | |
1295 | if (irq < 0) | |
1296 | continue; | |
1297 | ||
1298 | cfg = irq_cfg(irq); | |
1299 | if (!cpu_isset(cpu, cfg->domain)) | |
1300 | per_cpu(vector_irq, cpu)[vector] = -1; | |
54168ed7 | 1301 | } |
1da177e4 | 1302 | } |
3fde6900 | 1303 | |
f5b9ed7a | 1304 | static struct irq_chip ioapic_chip; |
54168ed7 IM |
1305 | #ifdef CONFIG_INTR_REMAP |
1306 | static struct irq_chip ir_ioapic_chip; | |
1307 | #endif | |
1da177e4 | 1308 | |
54168ed7 IM |
1309 | #define IOAPIC_AUTO -1 |
1310 | #define IOAPIC_EDGE 0 | |
1311 | #define IOAPIC_LEVEL 1 | |
1da177e4 | 1312 | |
047c8fdb | 1313 | #ifdef CONFIG_X86_32 |
1d025192 YL |
1314 | static inline int IO_APIC_irq_trigger(int irq) |
1315 | { | |
54168ed7 | 1316 | int apic, idx, pin; |
1d025192 | 1317 | |
54168ed7 IM |
1318 | for (apic = 0; apic < nr_ioapics; apic++) { |
1319 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1320 | idx = find_irq_entry(apic, pin, mp_INT); | |
1321 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1322 | return irq_trigger(idx); | |
1323 | } | |
1324 | } | |
1325 | /* | |
1326 | * nonexistent IRQs are edge default | |
1327 | */ | |
1328 | return 0; | |
1d025192 | 1329 | } |
047c8fdb YL |
1330 | #else |
1331 | static inline int IO_APIC_irq_trigger(int irq) | |
1332 | { | |
54168ed7 | 1333 | return 1; |
047c8fdb YL |
1334 | } |
1335 | #endif | |
1d025192 | 1336 | |
497c9a19 | 1337 | static void ioapic_register_intr(int irq, unsigned long trigger) |
1da177e4 | 1338 | { |
08678b08 YL |
1339 | struct irq_desc *desc; |
1340 | ||
199751d7 YL |
1341 | /* first time to use this irq_desc */ |
1342 | if (irq < 16) | |
1343 | desc = irq_to_desc(irq); | |
1344 | else | |
1345 | desc = irq_to_desc_alloc(irq); | |
1346 | ||
6ebcc00e | 1347 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
047c8fdb | 1348 | trigger == IOAPIC_LEVEL) |
08678b08 | 1349 | desc->status |= IRQ_LEVEL; |
047c8fdb YL |
1350 | else |
1351 | desc->status &= ~IRQ_LEVEL; | |
1352 | ||
54168ed7 IM |
1353 | #ifdef CONFIG_INTR_REMAP |
1354 | if (irq_remapped(irq)) { | |
1355 | desc->status |= IRQ_MOVE_PCNTXT; | |
1356 | if (trigger) | |
1357 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1358 | handle_fasteoi_irq, | |
1359 | "fasteoi"); | |
1360 | else | |
1361 | set_irq_chip_and_handler_name(irq, &ir_ioapic_chip, | |
1362 | handle_edge_irq, "edge"); | |
1363 | return; | |
1364 | } | |
1365 | #endif | |
047c8fdb YL |
1366 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
1367 | trigger == IOAPIC_LEVEL) | |
a460e745 | 1368 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 IM |
1369 | handle_fasteoi_irq, |
1370 | "fasteoi"); | |
047c8fdb | 1371 | else |
a460e745 | 1372 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
54168ed7 | 1373 | handle_edge_irq, "edge"); |
1da177e4 LT |
1374 | } |
1375 | ||
497c9a19 YL |
1376 | static int setup_ioapic_entry(int apic, int irq, |
1377 | struct IO_APIC_route_entry *entry, | |
1378 | unsigned int destination, int trigger, | |
1379 | int polarity, int vector) | |
1da177e4 | 1380 | { |
497c9a19 YL |
1381 | /* |
1382 | * add it to the IO-APIC irq-routing table: | |
1383 | */ | |
1384 | memset(entry,0,sizeof(*entry)); | |
1385 | ||
54168ed7 IM |
1386 | #ifdef CONFIG_INTR_REMAP |
1387 | if (intr_remapping_enabled) { | |
1388 | struct intel_iommu *iommu = map_ioapic_to_ir(apic); | |
1389 | struct irte irte; | |
1390 | struct IR_IO_APIC_route_entry *ir_entry = | |
1391 | (struct IR_IO_APIC_route_entry *) entry; | |
1392 | int index; | |
1393 | ||
1394 | if (!iommu) | |
1395 | panic("No mapping iommu for ioapic %d\n", apic); | |
1396 | ||
1397 | index = alloc_irte(iommu, irq, 1); | |
1398 | if (index < 0) | |
1399 | panic("Failed to allocate IRTE for ioapic %d\n", apic); | |
1400 | ||
1401 | memset(&irte, 0, sizeof(irte)); | |
1402 | ||
1403 | irte.present = 1; | |
1404 | irte.dst_mode = INT_DEST_MODE; | |
1405 | irte.trigger_mode = trigger; | |
1406 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
1407 | irte.vector = vector; | |
1408 | irte.dest_id = IRTE_DEST(destination); | |
1409 | ||
1410 | modify_irte(irq, &irte); | |
1411 | ||
1412 | ir_entry->index2 = (index >> 15) & 0x1; | |
1413 | ir_entry->zero = 0; | |
1414 | ir_entry->format = 1; | |
1415 | ir_entry->index = (index & 0x7fff); | |
1416 | } else | |
1417 | #endif | |
1418 | { | |
1419 | entry->delivery_mode = INT_DELIVERY_MODE; | |
1420 | entry->dest_mode = INT_DEST_MODE; | |
1421 | entry->dest = destination; | |
1422 | } | |
497c9a19 | 1423 | |
54168ed7 | 1424 | entry->mask = 0; /* enable IRQ */ |
497c9a19 YL |
1425 | entry->trigger = trigger; |
1426 | entry->polarity = polarity; | |
1427 | entry->vector = vector; | |
1428 | ||
1429 | /* Mask level triggered irqs. | |
1430 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
1431 | */ | |
1432 | if (trigger) | |
1433 | entry->mask = 1; | |
497c9a19 YL |
1434 | return 0; |
1435 | } | |
1436 | ||
1437 | static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, | |
54168ed7 | 1438 | int trigger, int polarity) |
497c9a19 YL |
1439 | { |
1440 | struct irq_cfg *cfg; | |
1da177e4 | 1441 | struct IO_APIC_route_entry entry; |
497c9a19 YL |
1442 | cpumask_t mask; |
1443 | ||
1444 | if (!IO_APIC_IRQ(irq)) | |
1445 | return; | |
1446 | ||
1447 | cfg = irq_cfg(irq); | |
1448 | ||
1449 | mask = TARGET_CPUS; | |
1450 | if (assign_irq_vector(irq, mask)) | |
1451 | return; | |
1452 | ||
1453 | cpus_and(mask, cfg->domain, mask); | |
1454 | ||
1455 | apic_printk(APIC_VERBOSE,KERN_DEBUG | |
1456 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | |
1457 | "IRQ %d Mode:%i Active:%i)\n", | |
1458 | apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector, | |
1459 | irq, trigger, polarity); | |
1460 | ||
1461 | ||
1462 | if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry, | |
1463 | cpu_mask_to_apicid(mask), trigger, polarity, | |
1464 | cfg->vector)) { | |
1465 | printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", | |
1466 | mp_ioapics[apic].mp_apicid, pin); | |
1467 | __clear_irq_vector(irq); | |
1468 | return; | |
1469 | } | |
1470 | ||
1471 | ioapic_register_intr(irq, trigger); | |
1472 | if (irq < 16) | |
1473 | disable_8259A_irq(irq); | |
1474 | ||
1475 | ioapic_write_entry(apic, pin, entry); | |
1476 | } | |
1477 | ||
1478 | static void __init setup_IO_APIC_irqs(void) | |
1479 | { | |
1480 | int apic, pin, idx, irq, first_notcon = 1; | |
1da177e4 LT |
1481 | |
1482 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1483 | ||
1484 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1485 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1486 | ||
497c9a19 | 1487 | idx = find_irq_entry(apic,pin,mp_INT); |
1da177e4 LT |
1488 | if (idx == -1) { |
1489 | if (first_notcon) { | |
497c9a19 | 1490 | apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1491 | first_notcon = 0; |
1492 | } else | |
497c9a19 | 1493 | apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1494 | continue; |
1495 | } | |
20d225b9 YL |
1496 | if (!first_notcon) { |
1497 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1498 | first_notcon = 1; | |
1499 | } | |
1500 | ||
1da177e4 | 1501 | irq = pin_2_irq(idx, apic, pin); |
54168ed7 | 1502 | #ifdef CONFIG_X86_32 |
497c9a19 YL |
1503 | if (multi_timer_check(apic, irq)) |
1504 | continue; | |
54168ed7 | 1505 | #endif |
497c9a19 | 1506 | add_pin_to_irq(irq, apic, pin); |
36062448 | 1507 | |
497c9a19 YL |
1508 | setup_IO_APIC_irq(apic, pin, irq, |
1509 | irq_trigger(idx), irq_polarity(idx)); | |
1da177e4 LT |
1510 | } |
1511 | } | |
1512 | ||
1513 | if (!first_notcon) | |
1514 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1515 | } | |
1516 | ||
1517 | /* | |
f7633ce5 | 1518 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1519 | */ |
f7633ce5 MR |
1520 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1521 | int vector) | |
1da177e4 LT |
1522 | { |
1523 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1524 | |
54168ed7 IM |
1525 | #ifdef CONFIG_INTR_REMAP |
1526 | if (intr_remapping_enabled) | |
1527 | return; | |
1528 | #endif | |
1529 | ||
36062448 | 1530 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1531 | |
1532 | /* | |
1533 | * We use logical delivery to get the timer IRQ | |
1534 | * to the first CPU. | |
1535 | */ | |
1536 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1537 | entry.mask = 1; /* mask IRQ now */ |
d83e94ac | 1538 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1da177e4 LT |
1539 | entry.delivery_mode = INT_DELIVERY_MODE; |
1540 | entry.polarity = 0; | |
1541 | entry.trigger = 0; | |
1542 | entry.vector = vector; | |
1543 | ||
1544 | /* | |
1545 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1546 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1547 | */ |
54168ed7 | 1548 | set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge"); |
1da177e4 LT |
1549 | |
1550 | /* | |
1551 | * Add it to the IO-APIC irq-routing table: | |
1552 | */ | |
cf4c6a2f | 1553 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1554 | } |
1555 | ||
32f71aff MR |
1556 | |
1557 | __apicdebuginit(void) print_IO_APIC(void) | |
1da177e4 LT |
1558 | { |
1559 | int apic, i; | |
1560 | union IO_APIC_reg_00 reg_00; | |
1561 | union IO_APIC_reg_01 reg_01; | |
1562 | union IO_APIC_reg_02 reg_02; | |
1563 | union IO_APIC_reg_03 reg_03; | |
1564 | unsigned long flags; | |
0f978f45 | 1565 | struct irq_cfg *cfg; |
1da177e4 LT |
1566 | |
1567 | if (apic_verbosity == APIC_QUIET) | |
1568 | return; | |
1569 | ||
36062448 | 1570 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1571 | for (i = 0; i < nr_ioapics; i++) |
1572 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1573 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1574 | |
1575 | /* | |
1576 | * We are a bit conservative about what we expect. We have to | |
1577 | * know about every hardware change ASAP. | |
1578 | */ | |
1579 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1580 | ||
1581 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1582 | ||
1583 | spin_lock_irqsave(&ioapic_lock, flags); | |
1584 | reg_00.raw = io_apic_read(apic, 0); | |
1585 | reg_01.raw = io_apic_read(apic, 1); | |
1586 | if (reg_01.bits.version >= 0x10) | |
1587 | reg_02.raw = io_apic_read(apic, 2); | |
54168ed7 IM |
1588 | if (reg_01.bits.version >= 0x20) |
1589 | reg_03.raw = io_apic_read(apic, 3); | |
1da177e4 LT |
1590 | spin_unlock_irqrestore(&ioapic_lock, flags); |
1591 | ||
54168ed7 | 1592 | printk("\n"); |
ec2cd0a2 | 1593 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1594 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1595 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1596 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1597 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 | 1598 | |
54168ed7 | 1599 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
1da177e4 | 1600 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); |
1da177e4 LT |
1601 | |
1602 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1603 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1604 | |
1605 | /* | |
1606 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1607 | * but the value of reg_02 is read as the previous read register | |
1608 | * value, so ignore it if reg_02 == reg_01. | |
1609 | */ | |
1610 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1611 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1612 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1613 | } |
1614 | ||
1615 | /* | |
1616 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1617 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1618 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1619 | */ | |
1620 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1621 | reg_03.raw != reg_01.raw) { | |
1622 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1623 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1624 | } |
1625 | ||
1626 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1627 | ||
d83e94ac YL |
1628 | printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" |
1629 | " Stat Dmod Deli Vect: \n"); | |
1da177e4 LT |
1630 | |
1631 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1632 | struct IO_APIC_route_entry entry; | |
1633 | ||
cf4c6a2f | 1634 | entry = ioapic_read_entry(apic, i); |
1da177e4 | 1635 | |
54168ed7 IM |
1636 | printk(KERN_DEBUG " %02x %03X ", |
1637 | i, | |
1638 | entry.dest | |
1639 | ); | |
1da177e4 LT |
1640 | |
1641 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1642 | entry.mask, | |
1643 | entry.trigger, | |
1644 | entry.irr, | |
1645 | entry.polarity, | |
1646 | entry.delivery_status, | |
1647 | entry.dest_mode, | |
1648 | entry.delivery_mode, | |
1649 | entry.vector | |
1650 | ); | |
1651 | } | |
1652 | } | |
1da177e4 | 1653 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
0f978f45 YL |
1654 | for_each_irq_cfg(cfg) { |
1655 | struct irq_pin_list *entry = cfg->irq_2_pin; | |
1656 | if (!entry) | |
1da177e4 | 1657 | continue; |
54168ed7 | 1658 | printk(KERN_DEBUG "IRQ%d ", cfg->irq); |
1da177e4 LT |
1659 | for (;;) { |
1660 | printk("-> %d:%d", entry->apic, entry->pin); | |
1661 | if (!entry->next) | |
1662 | break; | |
0f978f45 | 1663 | entry = entry->next; |
1da177e4 LT |
1664 | } |
1665 | printk("\n"); | |
1666 | } | |
1667 | ||
1668 | printk(KERN_INFO ".................................... done.\n"); | |
1669 | ||
1670 | return; | |
1671 | } | |
1672 | ||
32f71aff | 1673 | __apicdebuginit(void) print_APIC_bitfield(int base) |
1da177e4 LT |
1674 | { |
1675 | unsigned int v; | |
1676 | int i, j; | |
1677 | ||
1678 | if (apic_verbosity == APIC_QUIET) | |
1679 | return; | |
1680 | ||
1681 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1682 | for (i = 0; i < 8; i++) { | |
1683 | v = apic_read(base + i*0x10); | |
1684 | for (j = 0; j < 32; j++) { | |
1685 | if (v & (1<<j)) | |
1686 | printk("1"); | |
1687 | else | |
1688 | printk("0"); | |
1689 | } | |
1690 | printk("\n"); | |
1691 | } | |
1692 | } | |
1693 | ||
32f71aff | 1694 | __apicdebuginit(void) print_local_APIC(void *dummy) |
1da177e4 LT |
1695 | { |
1696 | unsigned int v, ver, maxlvt; | |
7ab6af7a | 1697 | u64 icr; |
1da177e4 LT |
1698 | |
1699 | if (apic_verbosity == APIC_QUIET) | |
1700 | return; | |
1701 | ||
1702 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1703 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1704 | v = apic_read(APIC_ID); |
54168ed7 | 1705 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
1da177e4 LT |
1706 | v = apic_read(APIC_LVR); |
1707 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1708 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1709 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1710 | |
1711 | v = apic_read(APIC_TASKPRI); | |
1712 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1713 | ||
54168ed7 | 1714 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1da177e4 LT |
1715 | v = apic_read(APIC_ARBPRI); |
1716 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1717 | v & APIC_ARBPRI_MASK); | |
1718 | v = apic_read(APIC_PROCPRI); | |
1719 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1720 | } | |
1721 | ||
1722 | v = apic_read(APIC_EOI); | |
1723 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1724 | v = apic_read(APIC_RRR); | |
1725 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1726 | v = apic_read(APIC_LDR); | |
1727 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1728 | v = apic_read(APIC_DFR); | |
1729 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1730 | v = apic_read(APIC_SPIV); | |
1731 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1732 | ||
1733 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1734 | print_APIC_bitfield(APIC_ISR); | |
1735 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1736 | print_APIC_bitfield(APIC_TMR); | |
1737 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1738 | print_APIC_bitfield(APIC_IRR); | |
1739 | ||
54168ed7 IM |
1740 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
1741 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1da177e4 | 1742 | apic_write(APIC_ESR, 0); |
54168ed7 | 1743 | |
1da177e4 LT |
1744 | v = apic_read(APIC_ESR); |
1745 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1746 | } | |
1747 | ||
7ab6af7a HS |
1748 | icr = apic_icr_read(); |
1749 | printk(KERN_DEBUG "... APIC ICR: %08x\n", icr); | |
1750 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", icr >> 32); | |
1da177e4 LT |
1751 | |
1752 | v = apic_read(APIC_LVTT); | |
1753 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1754 | ||
1755 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1756 | v = apic_read(APIC_LVTPC); | |
1757 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1758 | } | |
1759 | v = apic_read(APIC_LVT0); | |
1760 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1761 | v = apic_read(APIC_LVT1); | |
1762 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1763 | ||
1764 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1765 | v = apic_read(APIC_LVTERR); | |
1766 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1767 | } | |
1768 | ||
1769 | v = apic_read(APIC_TMICT); | |
1770 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1771 | v = apic_read(APIC_TMCCT); | |
1772 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1773 | v = apic_read(APIC_TDCR); | |
1774 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1775 | printk("\n"); | |
1776 | } | |
1777 | ||
32f71aff | 1778 | __apicdebuginit(void) print_all_local_APICs(void) |
1da177e4 | 1779 | { |
ffd5aae7 YL |
1780 | int cpu; |
1781 | ||
1782 | preempt_disable(); | |
1783 | for_each_online_cpu(cpu) | |
1784 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
1785 | preempt_enable(); | |
1da177e4 LT |
1786 | } |
1787 | ||
32f71aff | 1788 | __apicdebuginit(void) print_PIC(void) |
1da177e4 | 1789 | { |
1da177e4 LT |
1790 | unsigned int v; |
1791 | unsigned long flags; | |
1792 | ||
1793 | if (apic_verbosity == APIC_QUIET) | |
1794 | return; | |
1795 | ||
1796 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1797 | ||
1798 | spin_lock_irqsave(&i8259A_lock, flags); | |
1799 | ||
1800 | v = inb(0xa1) << 8 | inb(0x21); | |
1801 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1802 | ||
1803 | v = inb(0xa0) << 8 | inb(0x20); | |
1804 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1805 | ||
54168ed7 IM |
1806 | outb(0x0b,0xa0); |
1807 | outb(0x0b,0x20); | |
1da177e4 | 1808 | v = inb(0xa0) << 8 | inb(0x20); |
54168ed7 IM |
1809 | outb(0x0a,0xa0); |
1810 | outb(0x0a,0x20); | |
1da177e4 LT |
1811 | |
1812 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1813 | ||
1814 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1815 | ||
1816 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1817 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1818 | } | |
1819 | ||
32f71aff MR |
1820 | __apicdebuginit(int) print_all_ICs(void) |
1821 | { | |
1822 | print_PIC(); | |
1823 | print_all_local_APICs(); | |
1824 | print_IO_APIC(); | |
1825 | ||
1826 | return 0; | |
1827 | } | |
1828 | ||
1829 | fs_initcall(print_all_ICs); | |
1830 | ||
1da177e4 | 1831 | |
efa2559f YL |
1832 | /* Where if anywhere is the i8259 connect in external int mode */ |
1833 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
1834 | ||
54168ed7 | 1835 | void __init enable_IO_APIC(void) |
1da177e4 LT |
1836 | { |
1837 | union IO_APIC_reg_01 reg_01; | |
fcfd636a | 1838 | int i8259_apic, i8259_pin; |
54168ed7 | 1839 | int apic; |
1da177e4 LT |
1840 | unsigned long flags; |
1841 | ||
54168ed7 IM |
1842 | #ifdef CONFIG_X86_32 |
1843 | int i; | |
1da177e4 LT |
1844 | if (!pirqs_enabled) |
1845 | for (i = 0; i < MAX_PIRQS; i++) | |
1846 | pirq_entries[i] = -1; | |
54168ed7 | 1847 | #endif |
1da177e4 LT |
1848 | |
1849 | /* | |
1850 | * The number of IO-APIC IRQ registers (== #pins): | |
1851 | */ | |
fcfd636a | 1852 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1853 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1854 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1855 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1856 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1857 | } | |
54168ed7 | 1858 | for(apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1859 | int pin; |
1860 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1861 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1862 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1863 | entry = ioapic_read_entry(apic, pin); |
fcfd636a | 1864 | |
fcfd636a EB |
1865 | /* If the interrupt line is enabled and in ExtInt mode |
1866 | * I have found the pin where the i8259 is connected. | |
1867 | */ | |
1868 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1869 | ioapic_i8259.apic = apic; | |
1870 | ioapic_i8259.pin = pin; | |
1871 | goto found_i8259; | |
1872 | } | |
1873 | } | |
1874 | } | |
1875 | found_i8259: | |
1876 | /* Look to see what if the MP table has reported the ExtINT */ | |
1877 | /* If we could not find the appropriate pin by looking at the ioapic | |
1878 | * the i8259 probably is not connected the ioapic but give the | |
1879 | * mptable a chance anyway. | |
1880 | */ | |
1881 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1882 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1883 | /* Trust the MP table if nothing is setup in the hardware */ | |
1884 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1885 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1886 | ioapic_i8259.pin = i8259_pin; | |
1887 | ioapic_i8259.apic = i8259_apic; | |
1888 | } | |
1889 | /* Complain if the MP table and the hardware disagree */ | |
1890 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1891 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1892 | { | |
1893 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1894 | } |
1895 | ||
1896 | /* | |
1897 | * Do not trust the IO-APIC being empty at bootup | |
1898 | */ | |
1899 | clear_IO_APIC(); | |
1900 | } | |
1901 | ||
1902 | /* | |
1903 | * Not an __init, needed by the reboot code | |
1904 | */ | |
1905 | void disable_IO_APIC(void) | |
1906 | { | |
1907 | /* | |
1908 | * Clear the IO-APIC before rebooting: | |
1909 | */ | |
1910 | clear_IO_APIC(); | |
1911 | ||
650927ef | 1912 | /* |
0b968d23 | 1913 | * If the i8259 is routed through an IOAPIC |
650927ef | 1914 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1915 | * so legacy interrupts can be delivered. |
650927ef | 1916 | */ |
fcfd636a | 1917 | if (ioapic_i8259.pin != -1) { |
650927ef | 1918 | struct IO_APIC_route_entry entry; |
650927ef EB |
1919 | |
1920 | memset(&entry, 0, sizeof(entry)); | |
1921 | entry.mask = 0; /* Enabled */ | |
1922 | entry.trigger = 0; /* Edge */ | |
1923 | entry.irr = 0; | |
1924 | entry.polarity = 0; /* High */ | |
1925 | entry.delivery_status = 0; | |
1926 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1927 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1928 | entry.vector = 0; |
54168ed7 | 1929 | entry.dest = read_apic_id(); |
650927ef EB |
1930 | |
1931 | /* | |
1932 | * Add it to the IO-APIC irq-routing table: | |
1933 | */ | |
cf4c6a2f | 1934 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1935 | } |
54168ed7 | 1936 | |
fcfd636a | 1937 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1938 | } |
1939 | ||
54168ed7 | 1940 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
1941 | /* |
1942 | * function to set the IO-APIC physical IDs based on the | |
1943 | * values stored in the MPC table. | |
1944 | * | |
1945 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1946 | */ | |
1947 | ||
1da177e4 LT |
1948 | static void __init setup_ioapic_ids_from_mpc(void) |
1949 | { | |
1950 | union IO_APIC_reg_00 reg_00; | |
1951 | physid_mask_t phys_id_present_map; | |
1952 | int apic; | |
1953 | int i; | |
1954 | unsigned char old_id; | |
1955 | unsigned long flags; | |
1956 | ||
a4dbc34d | 1957 | if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids()) |
d49c4288 | 1958 | return; |
d49c4288 | 1959 | |
ca05fea6 NP |
1960 | /* |
1961 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1962 | * no meaning without the serial APIC bus. | |
1963 | */ | |
7c5c1e42 SL |
1964 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1965 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1966 | return; |
1da177e4 LT |
1967 | /* |
1968 | * This is broken; anything with a real cpu count has to | |
1969 | * circumvent this idiocy regardless. | |
1970 | */ | |
1971 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1972 | ||
1973 | /* | |
1974 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1975 | */ | |
1976 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1977 | ||
1978 | /* Read the register 0 value */ | |
1979 | spin_lock_irqsave(&ioapic_lock, flags); | |
1980 | reg_00.raw = io_apic_read(apic, 0); | |
1981 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1982 | |
ec2cd0a2 | 1983 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1984 | |
ec2cd0a2 | 1985 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1986 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1987 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1988 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1989 | reg_00.bits.ID); | |
ec2cd0a2 | 1990 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1991 | } |
1992 | ||
1da177e4 LT |
1993 | /* |
1994 | * Sanity check, is the ID really free? Every APIC in a | |
1995 | * system must have a unique ID or we get lots of nice | |
1996 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1997 | */ | |
1998 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1999 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 2000 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 2001 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2002 | for (i = 0; i < get_physical_broadcast(); i++) |
2003 | if (!physid_isset(i, phys_id_present_map)) | |
2004 | break; | |
2005 | if (i >= get_physical_broadcast()) | |
2006 | panic("Max APIC ID exceeded!\n"); | |
2007 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
2008 | i); | |
2009 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 2010 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
2011 | } else { |
2012 | physid_mask_t tmp; | |
ec2cd0a2 | 2013 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2014 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
2015 | "phys_id_present_map\n", | |
ec2cd0a2 | 2016 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
2017 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
2018 | } | |
2019 | ||
2020 | ||
2021 | /* | |
2022 | * We need to adjust the IRQ routing table | |
2023 | * if the ID changed. | |
2024 | */ | |
ec2cd0a2 | 2025 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 2026 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
2027 | if (mp_irqs[i].mp_dstapic == old_id) |
2028 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 2029 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
2030 | |
2031 | /* | |
2032 | * Read the right value from the MPC table and | |
2033 | * write it into the ID register. | |
36062448 | 2034 | */ |
1da177e4 LT |
2035 | apic_printk(APIC_VERBOSE, KERN_INFO |
2036 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 2037 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 2038 | |
ec2cd0a2 | 2039 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 | 2040 | spin_lock_irqsave(&ioapic_lock, flags); |
1da177e4 LT |
2041 | |
2042 | /* | |
2043 | * Sanity check | |
2044 | */ | |
2045 | spin_lock_irqsave(&ioapic_lock, flags); | |
2046 | reg_00.raw = io_apic_read(apic, 0); | |
2047 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 2048 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
2049 | printk("could not set ID!\n"); |
2050 | else | |
2051 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
2052 | } | |
2053 | } | |
54168ed7 | 2054 | #endif |
1da177e4 | 2055 | |
7ce0bcfd | 2056 | int no_timer_check __initdata; |
8542b200 ZA |
2057 | |
2058 | static int __init notimercheck(char *s) | |
2059 | { | |
2060 | no_timer_check = 1; | |
2061 | return 1; | |
2062 | } | |
2063 | __setup("no_timer_check", notimercheck); | |
2064 | ||
1da177e4 LT |
2065 | /* |
2066 | * There is a nasty bug in some older SMP boards, their mptable lies | |
2067 | * about the timer IRQ. We do the following to work around the situation: | |
2068 | * | |
2069 | * - timer IRQ defaults to IO-APIC IRQ | |
2070 | * - if this function detects that timer IRQs are defunct, then we fall | |
2071 | * back to ISA timer IRQs | |
2072 | */ | |
f0a7a5c9 | 2073 | static int __init timer_irq_works(void) |
1da177e4 LT |
2074 | { |
2075 | unsigned long t1 = jiffies; | |
4aae0702 | 2076 | unsigned long flags; |
1da177e4 | 2077 | |
8542b200 ZA |
2078 | if (no_timer_check) |
2079 | return 1; | |
2080 | ||
4aae0702 | 2081 | local_save_flags(flags); |
1da177e4 LT |
2082 | local_irq_enable(); |
2083 | /* Let ten ticks pass... */ | |
2084 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 2085 | local_irq_restore(flags); |
1da177e4 LT |
2086 | |
2087 | /* | |
2088 | * Expect a few ticks at least, to be sure some possible | |
2089 | * glue logic does not lock up after one or two first | |
2090 | * ticks in a non-ExtINT mode. Also the local APIC | |
2091 | * might have cached one ExtINT interrupt. Finally, at | |
2092 | * least one tick may be lost due to delays. | |
2093 | */ | |
54168ed7 IM |
2094 | |
2095 | /* jiffies wrap? */ | |
1d16b53e | 2096 | if (time_after(jiffies, t1 + 4)) |
1da177e4 | 2097 | return 1; |
1da177e4 LT |
2098 | return 0; |
2099 | } | |
2100 | ||
2101 | /* | |
2102 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
2103 | * number of pending IRQ events unhandled. These cases are very rare, | |
2104 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
2105 | * better to do it this way as thus we do not have to be aware of | |
2106 | * 'pending' interrupts in the IRQ path, except at this point. | |
2107 | */ | |
2108 | /* | |
2109 | * Edge triggered needs to resend any interrupt | |
2110 | * that was delayed but this is now handled in the device | |
2111 | * independent code. | |
2112 | */ | |
2113 | ||
2114 | /* | |
2115 | * Starting up a edge-triggered IO-APIC interrupt is | |
2116 | * nasty - we need to make sure that we get the edge. | |
2117 | * If it is already asserted for some reason, we need | |
2118 | * return 1 to indicate that is was pending. | |
2119 | * | |
2120 | * This is not complete - we should be able to fake | |
2121 | * an edge even if it isn't on the 8259A... | |
2122 | */ | |
54168ed7 | 2123 | |
f5b9ed7a | 2124 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
2125 | { |
2126 | int was_pending = 0; | |
2127 | unsigned long flags; | |
2128 | ||
2129 | spin_lock_irqsave(&ioapic_lock, flags); | |
2130 | if (irq < 16) { | |
2131 | disable_8259A_irq(irq); | |
2132 | if (i8259A_irq_pending(irq)) | |
2133 | was_pending = 1; | |
2134 | } | |
2135 | __unmask_IO_APIC_irq(irq); | |
2136 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2137 | ||
2138 | return was_pending; | |
2139 | } | |
2140 | ||
54168ed7 | 2141 | #ifdef CONFIG_X86_64 |
ace80ab7 | 2142 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 2143 | { |
54168ed7 IM |
2144 | |
2145 | struct irq_cfg *cfg = irq_cfg(irq); | |
2146 | unsigned long flags; | |
2147 | ||
2148 | spin_lock_irqsave(&vector_lock, flags); | |
2149 | send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector); | |
2150 | spin_unlock_irqrestore(&vector_lock, flags); | |
c0ad90a3 IM |
2151 | |
2152 | return 1; | |
2153 | } | |
54168ed7 IM |
2154 | #else |
2155 | static int ioapic_retrigger_irq(unsigned int irq) | |
497c9a19 | 2156 | { |
54168ed7 | 2157 | send_IPI_self(irq_cfg(irq)->vector); |
497c9a19 | 2158 | |
54168ed7 IM |
2159 | return 1; |
2160 | } | |
2161 | #endif | |
497c9a19 | 2162 | |
54168ed7 IM |
2163 | /* |
2164 | * Level and edge triggered IO-APIC interrupts need different handling, | |
2165 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be | |
2166 | * handled with the level-triggered descriptor, but that one has slightly | |
2167 | * more overhead. Level-triggered interrupts cannot be handled with the | |
2168 | * edge-triggered handler, without risking IRQ storms and other ugly | |
2169 | * races. | |
2170 | */ | |
497c9a19 | 2171 | |
54168ed7 | 2172 | #ifdef CONFIG_SMP |
497c9a19 | 2173 | |
54168ed7 IM |
2174 | #ifdef CONFIG_INTR_REMAP |
2175 | static void ir_irq_migration(struct work_struct *work); | |
497c9a19 | 2176 | |
54168ed7 | 2177 | static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration); |
497c9a19 | 2178 | |
54168ed7 IM |
2179 | /* |
2180 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
2181 | * | |
2182 | * For edge triggered, irq migration is a simple atomic update(of vector | |
2183 | * and cpu destination) of IRTE and flush the hardware cache. | |
2184 | * | |
2185 | * For level triggered, we need to modify the io-apic RTE aswell with the update | |
2186 | * vector information, along with modifying IRTE with vector and destination. | |
2187 | * So irq migration for level triggered is little bit more complex compared to | |
2188 | * edge triggered migration. But the good news is, we use the same algorithm | |
2189 | * for level triggered migration as we have today, only difference being, | |
2190 | * we now initiate the irq migration from process context instead of the | |
2191 | * interrupt context. | |
2192 | * | |
2193 | * In future, when we do a directed EOI (combined with cpu EOI broadcast | |
2194 | * suppression) to the IO-APIC, level triggered irq migration will also be | |
2195 | * as simple as edge triggered migration and we can do the irq migration | |
2196 | * with a simple atomic update to IO-APIC RTE. | |
2197 | */ | |
2198 | static void migrate_ioapic_irq(int irq, cpumask_t mask) | |
497c9a19 | 2199 | { |
54168ed7 IM |
2200 | struct irq_cfg *cfg; |
2201 | struct irq_desc *desc; | |
2202 | cpumask_t tmp, cleanup_mask; | |
2203 | struct irte irte; | |
2204 | int modify_ioapic_rte; | |
2205 | unsigned int dest; | |
2206 | unsigned long flags; | |
497c9a19 | 2207 | |
54168ed7 IM |
2208 | cpus_and(tmp, mask, cpu_online_map); |
2209 | if (cpus_empty(tmp)) | |
497c9a19 YL |
2210 | return; |
2211 | ||
54168ed7 IM |
2212 | if (get_irte(irq, &irte)) |
2213 | return; | |
497c9a19 | 2214 | |
54168ed7 IM |
2215 | if (assign_irq_vector(irq, mask)) |
2216 | return; | |
2217 | ||
2218 | cfg = irq_cfg(irq); | |
2219 | cpus_and(tmp, cfg->domain, mask); | |
2220 | dest = cpu_mask_to_apicid(tmp); | |
2221 | ||
2222 | desc = irq_to_desc(irq); | |
2223 | modify_ioapic_rte = desc->status & IRQ_LEVEL; | |
2224 | if (modify_ioapic_rte) { | |
2225 | spin_lock_irqsave(&ioapic_lock, flags); | |
2226 | __target_IO_APIC_irq(irq, dest, cfg->vector); | |
2227 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2228 | } | |
2229 | ||
2230 | irte.vector = cfg->vector; | |
2231 | irte.dest_id = IRTE_DEST(dest); | |
2232 | ||
2233 | /* | |
2234 | * Modified the IRTE and flushes the Interrupt entry cache. | |
2235 | */ | |
2236 | modify_irte(irq, &irte); | |
2237 | ||
2238 | if (cfg->move_in_progress) { | |
2239 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2240 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2241 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
2242 | cfg->move_in_progress = 0; | |
2243 | } | |
2244 | ||
2245 | desc->affinity = mask; | |
2246 | } | |
2247 | ||
2248 | static int migrate_irq_remapped_level(int irq) | |
2249 | { | |
2250 | int ret = -1; | |
2251 | struct irq_desc *desc = irq_to_desc(irq); | |
2252 | ||
2253 | mask_IO_APIC_irq(irq); | |
2254 | ||
2255 | if (io_apic_level_ack_pending(irq)) { | |
2256 | /* | |
2257 | * Interrupt in progress. Migrating irq now will change the | |
2258 | * vector information in the IO-APIC RTE and that will confuse | |
2259 | * the EOI broadcast performed by cpu. | |
2260 | * So, delay the irq migration to the next instance. | |
2261 | */ | |
2262 | schedule_delayed_work(&ir_migration_work, 1); | |
2263 | goto unmask; | |
2264 | } | |
2265 | ||
2266 | /* everthing is clear. we have right of way */ | |
2267 | migrate_ioapic_irq(irq, desc->pending_mask); | |
2268 | ||
2269 | ret = 0; | |
2270 | desc->status &= ~IRQ_MOVE_PENDING; | |
2271 | cpus_clear(desc->pending_mask); | |
2272 | ||
2273 | unmask: | |
2274 | unmask_IO_APIC_irq(irq); | |
2275 | return ret; | |
2276 | } | |
2277 | ||
2278 | static void ir_irq_migration(struct work_struct *work) | |
2279 | { | |
2280 | unsigned int irq; | |
2281 | struct irq_desc *desc; | |
2282 | ||
2283 | for_each_irq_desc(irq, desc) { | |
2284 | if (desc->status & IRQ_MOVE_PENDING) { | |
2285 | unsigned long flags; | |
2286 | ||
2287 | spin_lock_irqsave(&desc->lock, flags); | |
2288 | if (!desc->chip->set_affinity || | |
2289 | !(desc->status & IRQ_MOVE_PENDING)) { | |
2290 | desc->status &= ~IRQ_MOVE_PENDING; | |
2291 | spin_unlock_irqrestore(&desc->lock, flags); | |
2292 | continue; | |
2293 | } | |
2294 | ||
2295 | desc->chip->set_affinity(irq, desc->pending_mask); | |
2296 | spin_unlock_irqrestore(&desc->lock, flags); | |
2297 | } | |
2298 | } | |
2299 | } | |
2300 | ||
2301 | /* | |
2302 | * Migrates the IRQ destination in the process context. | |
2303 | */ | |
2304 | static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask) | |
2305 | { | |
2306 | struct irq_desc *desc = irq_to_desc(irq); | |
2307 | ||
2308 | if (desc->status & IRQ_LEVEL) { | |
2309 | desc->status |= IRQ_MOVE_PENDING; | |
2310 | desc->pending_mask = mask; | |
2311 | migrate_irq_remapped_level(irq); | |
2312 | return; | |
2313 | } | |
2314 | ||
2315 | migrate_ioapic_irq(irq, mask); | |
2316 | } | |
2317 | #endif | |
2318 | ||
2319 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | |
2320 | { | |
2321 | unsigned vector, me; | |
2322 | ack_APIC_irq(); | |
2323 | #ifdef CONFIG_X86_64 | |
2324 | exit_idle(); | |
2325 | #endif | |
2326 | irq_enter(); | |
2327 | ||
2328 | me = smp_processor_id(); | |
2329 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
2330 | unsigned int irq; | |
2331 | struct irq_desc *desc; | |
2332 | struct irq_cfg *cfg; | |
2333 | irq = __get_cpu_var(vector_irq)[vector]; | |
2334 | ||
2335 | desc = irq_to_desc(irq); | |
2336 | if (!desc) | |
2337 | continue; | |
2338 | ||
2339 | cfg = irq_cfg(irq); | |
2340 | spin_lock(&desc->lock); | |
2341 | if (!cfg->move_cleanup_count) | |
2342 | goto unlock; | |
2343 | ||
2344 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) | |
2345 | goto unlock; | |
2346 | ||
2347 | __get_cpu_var(vector_irq)[vector] = -1; | |
2348 | cfg->move_cleanup_count--; | |
2349 | unlock: | |
2350 | spin_unlock(&desc->lock); | |
2351 | } | |
2352 | ||
2353 | irq_exit(); | |
2354 | } | |
2355 | ||
2356 | static void irq_complete_move(unsigned int irq) | |
2357 | { | |
2358 | struct irq_cfg *cfg = irq_cfg(irq); | |
2359 | unsigned vector, me; | |
2360 | ||
2361 | if (likely(!cfg->move_in_progress)) | |
2362 | return; | |
2363 | ||
2364 | vector = ~get_irq_regs()->orig_ax; | |
2365 | me = smp_processor_id(); | |
2366 | if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) { | |
2367 | cpumask_t cleanup_mask; | |
2368 | ||
2369 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
2370 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
2371 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
497c9a19 YL |
2372 | cfg->move_in_progress = 0; |
2373 | } | |
2374 | } | |
2375 | #else | |
2376 | static inline void irq_complete_move(unsigned int irq) {} | |
2377 | #endif | |
54168ed7 IM |
2378 | #ifdef CONFIG_INTR_REMAP |
2379 | static void ack_x2apic_level(unsigned int irq) | |
2380 | { | |
2381 | ack_x2APIC_irq(); | |
2382 | } | |
2383 | ||
2384 | static void ack_x2apic_edge(unsigned int irq) | |
2385 | { | |
2386 | ack_x2APIC_irq(); | |
2387 | } | |
2388 | #endif | |
497c9a19 | 2389 | |
1d025192 YL |
2390 | static void ack_apic_edge(unsigned int irq) |
2391 | { | |
2392 | irq_complete_move(irq); | |
2393 | move_native_irq(irq); | |
2394 | ack_APIC_irq(); | |
2395 | } | |
2396 | ||
3eb2cce8 YL |
2397 | #ifdef CONFIG_X86_32 |
2398 | atomic_t irq_mis_count; | |
2399 | #endif | |
2400 | ||
047c8fdb YL |
2401 | static void ack_apic_level(unsigned int irq) |
2402 | { | |
3eb2cce8 YL |
2403 | #ifdef CONFIG_X86_32 |
2404 | unsigned long v; | |
2405 | int i; | |
2406 | #endif | |
54168ed7 | 2407 | int do_unmask_irq = 0; |
047c8fdb | 2408 | |
54168ed7 | 2409 | irq_complete_move(irq); |
047c8fdb | 2410 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
54168ed7 IM |
2411 | /* If we are moving the irq we need to mask it */ |
2412 | if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) { | |
2413 | do_unmask_irq = 1; | |
2414 | mask_IO_APIC_irq(irq); | |
2415 | } | |
047c8fdb YL |
2416 | #endif |
2417 | ||
3eb2cce8 YL |
2418 | #ifdef CONFIG_X86_32 |
2419 | /* | |
2420 | * It appears there is an erratum which affects at least version 0x11 | |
2421 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
2422 | * chipsets). Under certain conditions a level-triggered interrupt is | |
2423 | * erroneously delivered as edge-triggered one but the respective IRR | |
2424 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
2425 | * message but it will never arrive and further interrupts are blocked | |
2426 | * from the source. The exact reason is so far unknown, but the | |
2427 | * phenomenon was observed when two consecutive interrupt requests | |
2428 | * from a given source get delivered to the same CPU and the source is | |
2429 | * temporarily disabled in between. | |
2430 | * | |
2431 | * A workaround is to simulate an EOI message manually. We achieve it | |
2432 | * by setting the trigger mode to edge and then to level when the edge | |
2433 | * trigger mode gets detected in the TMR of a local APIC for a | |
2434 | * level-triggered interrupt. We mask the source for the time of the | |
2435 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
2436 | * The idea is from Manfred Spraul. --macro | |
2437 | */ | |
2438 | i = irq_cfg(irq)->vector; | |
2439 | ||
2440 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
2441 | #endif | |
2442 | ||
54168ed7 IM |
2443 | /* |
2444 | * We must acknowledge the irq before we move it or the acknowledge will | |
2445 | * not propagate properly. | |
2446 | */ | |
2447 | ack_APIC_irq(); | |
2448 | ||
2449 | /* Now we can move and renable the irq */ | |
2450 | if (unlikely(do_unmask_irq)) { | |
2451 | /* Only migrate the irq if the ack has been received. | |
2452 | * | |
2453 | * On rare occasions the broadcast level triggered ack gets | |
2454 | * delayed going to ioapics, and if we reprogram the | |
2455 | * vector while Remote IRR is still set the irq will never | |
2456 | * fire again. | |
2457 | * | |
2458 | * To prevent this scenario we read the Remote IRR bit | |
2459 | * of the ioapic. This has two effects. | |
2460 | * - On any sane system the read of the ioapic will | |
2461 | * flush writes (and acks) going to the ioapic from | |
2462 | * this cpu. | |
2463 | * - We get to see if the ACK has actually been delivered. | |
2464 | * | |
2465 | * Based on failed experiments of reprogramming the | |
2466 | * ioapic entry from outside of irq context starting | |
2467 | * with masking the ioapic entry and then polling until | |
2468 | * Remote IRR was clear before reprogramming the | |
2469 | * ioapic I don't trust the Remote IRR bit to be | |
2470 | * completey accurate. | |
2471 | * | |
2472 | * However there appears to be no other way to plug | |
2473 | * this race, so if the Remote IRR bit is not | |
2474 | * accurate and is causing problems then it is a hardware bug | |
2475 | * and you can go talk to the chipset vendor about it. | |
2476 | */ | |
2477 | if (!io_apic_level_ack_pending(irq)) | |
2478 | move_masked_irq(irq); | |
2479 | unmask_IO_APIC_irq(irq); | |
2480 | } | |
1d025192 | 2481 | |
3eb2cce8 | 2482 | #ifdef CONFIG_X86_32 |
1d025192 YL |
2483 | if (!(v & (1 << (i & 0x1f)))) { |
2484 | atomic_inc(&irq_mis_count); | |
2485 | spin_lock(&ioapic_lock); | |
2486 | __mask_and_edge_IO_APIC_irq(irq); | |
2487 | __unmask_and_level_IO_APIC_irq(irq); | |
2488 | spin_unlock(&ioapic_lock); | |
2489 | } | |
047c8fdb | 2490 | #endif |
3eb2cce8 | 2491 | } |
1d025192 | 2492 | |
f5b9ed7a IM |
2493 | static struct irq_chip ioapic_chip __read_mostly = { |
2494 | .name = "IO-APIC", | |
ace80ab7 EB |
2495 | .startup = startup_ioapic_irq, |
2496 | .mask = mask_IO_APIC_irq, | |
2497 | .unmask = unmask_IO_APIC_irq, | |
1d025192 YL |
2498 | .ack = ack_apic_edge, |
2499 | .eoi = ack_apic_level, | |
54d5d424 | 2500 | #ifdef CONFIG_SMP |
ace80ab7 | 2501 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 2502 | #endif |
ace80ab7 | 2503 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
2504 | }; |
2505 | ||
54168ed7 IM |
2506 | #ifdef CONFIG_INTR_REMAP |
2507 | static struct irq_chip ir_ioapic_chip __read_mostly = { | |
2508 | .name = "IR-IO-APIC", | |
2509 | .startup = startup_ioapic_irq, | |
2510 | .mask = mask_IO_APIC_irq, | |
2511 | .unmask = unmask_IO_APIC_irq, | |
2512 | .ack = ack_x2apic_edge, | |
2513 | .eoi = ack_x2apic_level, | |
2514 | #ifdef CONFIG_SMP | |
2515 | .set_affinity = set_ir_ioapic_affinity_irq, | |
2516 | #endif | |
2517 | .retrigger = ioapic_retrigger_irq, | |
2518 | }; | |
2519 | #endif | |
1da177e4 LT |
2520 | |
2521 | static inline void init_IO_APIC_traps(void) | |
2522 | { | |
2523 | int irq; | |
08678b08 | 2524 | struct irq_desc *desc; |
da51a821 | 2525 | struct irq_cfg *cfg; |
1da177e4 LT |
2526 | |
2527 | /* | |
2528 | * NOTE! The local APIC isn't very good at handling | |
2529 | * multiple interrupts at the same interrupt level. | |
2530 | * As the interrupt level is determined by taking the | |
2531 | * vector number and shifting that right by 4, we | |
2532 | * want to spread these out a bit so that they don't | |
2533 | * all fall in the same interrupt level. | |
2534 | * | |
2535 | * Also, we've got to be careful not to trash gate | |
2536 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2537 | */ | |
da51a821 YL |
2538 | for_each_irq_cfg(cfg) { |
2539 | irq = cfg->irq; | |
2540 | if (IO_APIC_IRQ(irq) && !cfg->vector) { | |
1da177e4 LT |
2541 | /* |
2542 | * Hmm.. We don't have an entry for this, | |
2543 | * so default to an old-fashioned 8259 | |
2544 | * interrupt if we can.. | |
2545 | */ | |
2546 | if (irq < 16) | |
2547 | make_8259A_irq(irq); | |
08678b08 YL |
2548 | else { |
2549 | desc = irq_to_desc(irq); | |
1da177e4 | 2550 | /* Strange. Oh, well.. */ |
08678b08 YL |
2551 | desc->chip = &no_irq_chip; |
2552 | } | |
1da177e4 LT |
2553 | } |
2554 | } | |
2555 | } | |
2556 | ||
f5b9ed7a IM |
2557 | /* |
2558 | * The local APIC irq-chip implementation: | |
2559 | */ | |
1da177e4 | 2560 | |
36062448 | 2561 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2562 | { |
2563 | unsigned long v; | |
2564 | ||
2565 | v = apic_read(APIC_LVT0); | |
593f4a78 | 2566 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
1da177e4 LT |
2567 | } |
2568 | ||
36062448 | 2569 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2570 | { |
f5b9ed7a | 2571 | unsigned long v; |
1da177e4 | 2572 | |
f5b9ed7a | 2573 | v = apic_read(APIC_LVT0); |
593f4a78 | 2574 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
f5b9ed7a | 2575 | } |
1da177e4 | 2576 | |
54168ed7 | 2577 | static void ack_lapic_irq (unsigned int irq) |
1d025192 YL |
2578 | { |
2579 | ack_APIC_irq(); | |
2580 | } | |
2581 | ||
f5b9ed7a | 2582 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2583 | .name = "local-APIC", |
f5b9ed7a IM |
2584 | .mask = mask_lapic_irq, |
2585 | .unmask = unmask_lapic_irq, | |
c88ac1df | 2586 | .ack = ack_lapic_irq, |
1da177e4 LT |
2587 | }; |
2588 | ||
497c9a19 | 2589 | static void lapic_register_intr(int irq) |
c88ac1df | 2590 | { |
08678b08 YL |
2591 | struct irq_desc *desc; |
2592 | ||
2593 | desc = irq_to_desc(irq); | |
2594 | desc->status &= ~IRQ_LEVEL; | |
c88ac1df MR |
2595 | set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
2596 | "edge"); | |
c88ac1df MR |
2597 | } |
2598 | ||
e9427101 | 2599 | static void __init setup_nmi(void) |
1da177e4 LT |
2600 | { |
2601 | /* | |
36062448 | 2602 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2603 | * We put the 8259A master into AEOI mode and |
2604 | * unmask on all local APICs LVT0 as NMI. | |
2605 | * | |
2606 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2607 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2608 | * the NMI handler or the timer interrupt. | |
36062448 | 2609 | */ |
1da177e4 LT |
2610 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2611 | ||
e9427101 | 2612 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2613 | |
2614 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2615 | } | |
2616 | ||
2617 | /* | |
2618 | * This looks a bit hackish but it's about the only one way of sending | |
2619 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2620 | * not support the ExtINT mode, unfortunately. We need to send these | |
2621 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2622 | * 8259A interrupt line asserted until INTA. --macro | |
2623 | */ | |
28acf285 | 2624 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2625 | { |
fcfd636a | 2626 | int apic, pin, i; |
1da177e4 LT |
2627 | struct IO_APIC_route_entry entry0, entry1; |
2628 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2629 | |
fcfd636a | 2630 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2631 | if (pin == -1) { |
2632 | WARN_ON_ONCE(1); | |
2633 | return; | |
2634 | } | |
fcfd636a | 2635 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2636 | if (apic == -1) { |
2637 | WARN_ON_ONCE(1); | |
1da177e4 | 2638 | return; |
956fb531 | 2639 | } |
1da177e4 | 2640 | |
cf4c6a2f | 2641 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2642 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2643 | |
2644 | memset(&entry1, 0, sizeof(entry1)); | |
2645 | ||
2646 | entry1.dest_mode = 0; /* physical delivery */ | |
2647 | entry1.mask = 0; /* unmask IRQ now */ | |
d83e94ac | 2648 | entry1.dest = hard_smp_processor_id(); |
1da177e4 LT |
2649 | entry1.delivery_mode = dest_ExtINT; |
2650 | entry1.polarity = entry0.polarity; | |
2651 | entry1.trigger = 0; | |
2652 | entry1.vector = 0; | |
2653 | ||
cf4c6a2f | 2654 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2655 | |
2656 | save_control = CMOS_READ(RTC_CONTROL); | |
2657 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2658 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2659 | RTC_FREQ_SELECT); | |
2660 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2661 | ||
2662 | i = 100; | |
2663 | while (i-- > 0) { | |
2664 | mdelay(10); | |
2665 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2666 | i -= 10; | |
2667 | } | |
2668 | ||
2669 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2670 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2671 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2672 | |
cf4c6a2f | 2673 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2674 | } |
2675 | ||
efa2559f | 2676 | static int disable_timer_pin_1 __initdata; |
047c8fdb | 2677 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
54168ed7 | 2678 | static int __init disable_timer_pin_setup(char *arg) |
efa2559f YL |
2679 | { |
2680 | disable_timer_pin_1 = 1; | |
2681 | return 0; | |
2682 | } | |
54168ed7 | 2683 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
efa2559f YL |
2684 | |
2685 | int timer_through_8259 __initdata; | |
2686 | ||
1da177e4 LT |
2687 | /* |
2688 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2689 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2690 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2691 | * fanatically on his truly buggy board. | |
54168ed7 IM |
2692 | * |
2693 | * FIXME: really need to revamp this for all platforms. | |
1da177e4 | 2694 | */ |
8542b200 | 2695 | static inline void __init check_timer(void) |
1da177e4 | 2696 | { |
497c9a19 | 2697 | struct irq_cfg *cfg = irq_cfg(0); |
fcfd636a | 2698 | int apic1, pin1, apic2, pin2; |
4aae0702 | 2699 | unsigned long flags; |
047c8fdb YL |
2700 | unsigned int ver; |
2701 | int no_pin1 = 0; | |
4aae0702 IM |
2702 | |
2703 | local_irq_save(flags); | |
d4d25dec | 2704 | |
54168ed7 IM |
2705 | ver = apic_read(APIC_LVR); |
2706 | ver = GET_APIC_VERSION(ver); | |
6e908947 | 2707 | |
1da177e4 LT |
2708 | /* |
2709 | * get/set the timer IRQ vector: | |
2710 | */ | |
2711 | disable_8259A_irq(0); | |
497c9a19 | 2712 | assign_irq_vector(0, TARGET_CPUS); |
1da177e4 LT |
2713 | |
2714 | /* | |
d11d5794 MR |
2715 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2716 | * wire has to be disabled in the local APIC. Also | |
2717 | * timer interrupts need to be acknowledged manually in | |
2718 | * the 8259A for the i82489DX when using the NMI | |
2719 | * watchdog as that APIC treats NMIs as level-triggered. | |
2720 | * The AEOI mode will finish them in the 8259A | |
2721 | * automatically. | |
1da177e4 | 2722 | */ |
593f4a78 | 2723 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
1da177e4 | 2724 | init_8259A(1); |
54168ed7 | 2725 | #ifdef CONFIG_X86_32 |
d11d5794 | 2726 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
54168ed7 | 2727 | #endif |
1da177e4 | 2728 | |
fcfd636a EB |
2729 | pin1 = find_isa_irq_pin(0, mp_INT); |
2730 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2731 | pin2 = ioapic_i8259.pin; | |
2732 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2733 | |
49a66a0b MR |
2734 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
2735 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", | |
497c9a19 | 2736 | cfg->vector, apic1, pin1, apic2, pin2); |
1da177e4 | 2737 | |
691874fa MR |
2738 | /* |
2739 | * Some BIOS writers are clueless and report the ExtINTA | |
2740 | * I/O APIC input from the cascaded 8259A as the timer | |
2741 | * interrupt input. So just in case, if only one pin | |
2742 | * was found above, try it both directly and through the | |
2743 | * 8259A. | |
2744 | */ | |
2745 | if (pin1 == -1) { | |
54168ed7 IM |
2746 | #ifdef CONFIG_INTR_REMAP |
2747 | if (intr_remapping_enabled) | |
2748 | panic("BIOS bug: timer not connected to IO-APIC"); | |
2749 | #endif | |
691874fa MR |
2750 | pin1 = pin2; |
2751 | apic1 = apic2; | |
2752 | no_pin1 = 1; | |
2753 | } else if (pin2 == -1) { | |
2754 | pin2 = pin1; | |
2755 | apic2 = apic1; | |
2756 | } | |
2757 | ||
1da177e4 LT |
2758 | if (pin1 != -1) { |
2759 | /* | |
2760 | * Ok, does IRQ0 through the IOAPIC work? | |
2761 | */ | |
691874fa MR |
2762 | if (no_pin1) { |
2763 | add_pin_to_irq(0, apic1, pin1); | |
497c9a19 | 2764 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
691874fa | 2765 | } |
1da177e4 LT |
2766 | unmask_IO_APIC_irq(0); |
2767 | if (timer_irq_works()) { | |
2768 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2769 | setup_nmi(); |
2770 | enable_8259A_irq(0); | |
1da177e4 | 2771 | } |
66759a01 CE |
2772 | if (disable_timer_pin_1 > 0) |
2773 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2774 | goto out; |
1da177e4 | 2775 | } |
54168ed7 IM |
2776 | #ifdef CONFIG_INTR_REMAP |
2777 | if (intr_remapping_enabled) | |
2778 | panic("timer doesn't work through Interrupt-remapped IO-APIC"); | |
2779 | #endif | |
fcfd636a | 2780 | clear_IO_APIC_pin(apic1, pin1); |
691874fa | 2781 | if (!no_pin1) |
49a66a0b MR |
2782 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
2783 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2784 | |
49a66a0b MR |
2785 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
2786 | "(IRQ0) through the 8259A ...\n"); | |
2787 | apic_printk(APIC_QUIET, KERN_INFO | |
2788 | "..... (found apic %d pin %d) ...\n", apic2, pin2); | |
1da177e4 LT |
2789 | /* |
2790 | * legacy devices should be connected to IO APIC #0 | |
2791 | */ | |
691874fa | 2792 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
497c9a19 | 2793 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
24742ece | 2794 | unmask_IO_APIC_irq(0); |
ecd29476 | 2795 | enable_8259A_irq(0); |
1da177e4 | 2796 | if (timer_irq_works()) { |
49a66a0b | 2797 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
35542c5e | 2798 | timer_through_8259 = 1; |
1da177e4 | 2799 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2800 | disable_8259A_irq(0); |
1da177e4 | 2801 | setup_nmi(); |
60134ebe | 2802 | enable_8259A_irq(0); |
1da177e4 | 2803 | } |
4aae0702 | 2804 | goto out; |
1da177e4 LT |
2805 | } |
2806 | /* | |
2807 | * Cleanup, just in case ... | |
2808 | */ | |
ecd29476 | 2809 | disable_8259A_irq(0); |
fcfd636a | 2810 | clear_IO_APIC_pin(apic2, pin2); |
49a66a0b | 2811 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
1da177e4 | 2812 | } |
1da177e4 LT |
2813 | |
2814 | if (nmi_watchdog == NMI_IO_APIC) { | |
49a66a0b MR |
2815 | apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work " |
2816 | "through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2817 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2818 | } |
54168ed7 | 2819 | #ifdef CONFIG_X86_32 |
d11d5794 | 2820 | timer_ack = 0; |
54168ed7 | 2821 | #endif |
1da177e4 | 2822 | |
49a66a0b MR |
2823 | apic_printk(APIC_QUIET, KERN_INFO |
2824 | "...trying to set up timer as Virtual Wire IRQ...\n"); | |
1da177e4 | 2825 | |
497c9a19 YL |
2826 | lapic_register_intr(0); |
2827 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ | |
1da177e4 LT |
2828 | enable_8259A_irq(0); |
2829 | ||
2830 | if (timer_irq_works()) { | |
49a66a0b | 2831 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2832 | goto out; |
1da177e4 | 2833 | } |
e67465f1 | 2834 | disable_8259A_irq(0); |
497c9a19 | 2835 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
49a66a0b | 2836 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
1da177e4 | 2837 | |
49a66a0b MR |
2838 | apic_printk(APIC_QUIET, KERN_INFO |
2839 | "...trying to set up timer as ExtINT IRQ...\n"); | |
1da177e4 | 2840 | |
1da177e4 LT |
2841 | init_8259A(0); |
2842 | make_8259A_irq(0); | |
593f4a78 | 2843 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
1da177e4 LT |
2844 | |
2845 | unlock_ExtINT_logic(); | |
2846 | ||
2847 | if (timer_irq_works()) { | |
49a66a0b | 2848 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
4aae0702 | 2849 | goto out; |
1da177e4 | 2850 | } |
49a66a0b | 2851 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
1da177e4 | 2852 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
49a66a0b | 2853 | "report. Then try booting with the 'noapic' option.\n"); |
4aae0702 IM |
2854 | out: |
2855 | local_irq_restore(flags); | |
1da177e4 LT |
2856 | } |
2857 | ||
2858 | /* | |
af174783 MR |
2859 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
2860 | * to devices. However there may be an I/O APIC pin available for | |
2861 | * this interrupt regardless. The pin may be left unconnected, but | |
2862 | * typically it will be reused as an ExtINT cascade interrupt for | |
2863 | * the master 8259A. In the MPS case such a pin will normally be | |
2864 | * reported as an ExtINT interrupt in the MP table. With ACPI | |
2865 | * there is no provision for ExtINT interrupts, and in the absence | |
2866 | * of an override it would be treated as an ordinary ISA I/O APIC | |
2867 | * interrupt, that is edge-triggered and unmasked by default. We | |
2868 | * used to do this, but it caused problems on some systems because | |
2869 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using | |
2870 | * the same ExtINT cascade interrupt to drive the local APIC of the | |
2871 | * bootstrap processor. Therefore we refrain from routing IRQ2 to | |
2872 | * the I/O APIC in all cases now. No actual device should request | |
2873 | * it anyway. --macro | |
1da177e4 LT |
2874 | */ |
2875 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2876 | ||
2877 | void __init setup_IO_APIC(void) | |
2878 | { | |
54168ed7 IM |
2879 | |
2880 | #ifdef CONFIG_X86_32 | |
1da177e4 | 2881 | enable_IO_APIC(); |
54168ed7 IM |
2882 | #else |
2883 | /* | |
2884 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP | |
2885 | */ | |
2886 | #endif | |
1da177e4 | 2887 | |
af174783 | 2888 | io_apic_irqs = ~PIC_IRQS; |
1da177e4 | 2889 | |
54168ed7 IM |
2890 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
2891 | /* | |
2892 | * Set up IO-APIC IRQ routing. | |
2893 | */ | |
2894 | #ifdef CONFIG_X86_32 | |
2895 | if (!acpi_ioapic) | |
2896 | setup_ioapic_ids_from_mpc(); | |
2897 | #endif | |
1da177e4 LT |
2898 | sync_Arb_IDs(); |
2899 | setup_IO_APIC_irqs(); | |
2900 | init_IO_APIC_traps(); | |
1e4c85f9 | 2901 | check_timer(); |
1da177e4 LT |
2902 | } |
2903 | ||
2904 | /* | |
54168ed7 IM |
2905 | * Called after all the initialization is done. If we didnt find any |
2906 | * APIC bugs then we can allow the modify fast path | |
1da177e4 | 2907 | */ |
36062448 | 2908 | |
1da177e4 LT |
2909 | static int __init io_apic_bug_finalize(void) |
2910 | { | |
54168ed7 IM |
2911 | if (sis_apic_bug == -1) |
2912 | sis_apic_bug = 0; | |
2913 | return 0; | |
1da177e4 LT |
2914 | } |
2915 | ||
2916 | late_initcall(io_apic_bug_finalize); | |
2917 | ||
2918 | struct sysfs_ioapic_data { | |
2919 | struct sys_device dev; | |
2920 | struct IO_APIC_route_entry entry[0]; | |
2921 | }; | |
54168ed7 | 2922 | static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2923 | |
438510f6 | 2924 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2925 | { |
2926 | struct IO_APIC_route_entry *entry; | |
2927 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2928 | int i; |
36062448 | 2929 | |
1da177e4 LT |
2930 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2931 | entry = data->entry; | |
54168ed7 IM |
2932 | for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) |
2933 | *entry = ioapic_read_entry(dev->id, i); | |
1da177e4 LT |
2934 | |
2935 | return 0; | |
2936 | } | |
2937 | ||
2938 | static int ioapic_resume(struct sys_device *dev) | |
2939 | { | |
2940 | struct IO_APIC_route_entry *entry; | |
2941 | struct sysfs_ioapic_data *data; | |
2942 | unsigned long flags; | |
2943 | union IO_APIC_reg_00 reg_00; | |
2944 | int i; | |
36062448 | 2945 | |
1da177e4 LT |
2946 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2947 | entry = data->entry; | |
2948 | ||
2949 | spin_lock_irqsave(&ioapic_lock, flags); | |
2950 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2951 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2952 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2953 | io_apic_write(dev->id, 0, reg_00.raw); |
2954 | } | |
1da177e4 | 2955 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2956 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2957 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2958 | |
2959 | return 0; | |
2960 | } | |
2961 | ||
2962 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2963 | .name = "ioapic", |
1da177e4 LT |
2964 | .suspend = ioapic_suspend, |
2965 | .resume = ioapic_resume, | |
2966 | }; | |
2967 | ||
2968 | static int __init ioapic_init_sysfs(void) | |
2969 | { | |
54168ed7 IM |
2970 | struct sys_device * dev; |
2971 | int i, size, error; | |
1da177e4 LT |
2972 | |
2973 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2974 | if (error) | |
2975 | return error; | |
2976 | ||
54168ed7 | 2977 | for (i = 0; i < nr_ioapics; i++ ) { |
36062448 | 2978 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] |
1da177e4 | 2979 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2980 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2981 | if (!mp_ioapic_data[i]) { |
2982 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2983 | continue; | |
2984 | } | |
1da177e4 | 2985 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2986 | dev->id = i; |
1da177e4 LT |
2987 | dev->cls = &ioapic_sysdev_class; |
2988 | error = sysdev_register(dev); | |
2989 | if (error) { | |
2990 | kfree(mp_ioapic_data[i]); | |
2991 | mp_ioapic_data[i] = NULL; | |
2992 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2993 | continue; | |
2994 | } | |
2995 | } | |
2996 | ||
2997 | return 0; | |
2998 | } | |
2999 | ||
3000 | device_initcall(ioapic_init_sysfs); | |
3001 | ||
3fc471ed | 3002 | /* |
95d77884 | 3003 | * Dynamic irq allocate and deallocation |
3fc471ed | 3004 | */ |
199751d7 | 3005 | unsigned int create_irq_nr(unsigned int irq_want) |
3fc471ed | 3006 | { |
ace80ab7 | 3007 | /* Allocate an unused irq */ |
54168ed7 IM |
3008 | unsigned int irq; |
3009 | unsigned int new; | |
3fc471ed | 3010 | unsigned long flags; |
da51a821 | 3011 | struct irq_cfg *cfg_new; |
3fc471ed | 3012 | |
497c9a19 | 3013 | #ifndef CONFIG_HAVE_SPARSE_IRQ |
199751d7 | 3014 | irq_want = nr_irqs - 1; |
497c9a19 | 3015 | #endif |
199751d7 YL |
3016 | |
3017 | irq = 0; | |
ace80ab7 | 3018 | spin_lock_irqsave(&vector_lock, flags); |
54168ed7 | 3019 | for (new = irq_want; new > 0; new--) { |
ace80ab7 EB |
3020 | if (platform_legacy_irq(new)) |
3021 | continue; | |
da51a821 YL |
3022 | cfg_new = irq_cfg(new); |
3023 | if (cfg_new && cfg_new->vector != 0) | |
ace80ab7 | 3024 | continue; |
047c8fdb | 3025 | /* check if need to create one */ |
da51a821 YL |
3026 | if (!cfg_new) |
3027 | cfg_new = irq_cfg_alloc(new); | |
497c9a19 | 3028 | if (__assign_irq_vector(new, TARGET_CPUS) == 0) |
ace80ab7 EB |
3029 | irq = new; |
3030 | break; | |
3031 | } | |
3032 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 3033 | |
199751d7 | 3034 | if (irq > 0) { |
3fc471ed EB |
3035 | dynamic_irq_init(irq); |
3036 | } | |
3037 | return irq; | |
3038 | } | |
3039 | ||
199751d7 YL |
3040 | int create_irq(void) |
3041 | { | |
54168ed7 IM |
3042 | int irq; |
3043 | ||
3044 | irq = create_irq_nr(nr_irqs - 1); | |
3045 | ||
3046 | if (irq == 0) | |
3047 | irq = -1; | |
3048 | ||
3049 | return irq; | |
199751d7 YL |
3050 | } |
3051 | ||
3fc471ed EB |
3052 | void destroy_irq(unsigned int irq) |
3053 | { | |
3054 | unsigned long flags; | |
3fc471ed EB |
3055 | |
3056 | dynamic_irq_cleanup(irq); | |
3057 | ||
54168ed7 IM |
3058 | #ifdef CONFIG_INTR_REMAP |
3059 | free_irte(irq); | |
3060 | #endif | |
3fc471ed | 3061 | spin_lock_irqsave(&vector_lock, flags); |
497c9a19 | 3062 | __clear_irq_vector(irq); |
3fc471ed EB |
3063 | spin_unlock_irqrestore(&vector_lock, flags); |
3064 | } | |
3fc471ed | 3065 | |
2d3fcc1c | 3066 | /* |
27b46d76 | 3067 | * MSI message composition |
2d3fcc1c EB |
3068 | */ |
3069 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 3070 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 3071 | { |
497c9a19 YL |
3072 | struct irq_cfg *cfg; |
3073 | int err; | |
2d3fcc1c | 3074 | unsigned dest; |
497c9a19 | 3075 | cpumask_t tmp; |
2d3fcc1c | 3076 | |
497c9a19 YL |
3077 | tmp = TARGET_CPUS; |
3078 | err = assign_irq_vector(irq, tmp); | |
3079 | if (err) | |
3080 | return err; | |
2d3fcc1c | 3081 | |
497c9a19 YL |
3082 | cfg = irq_cfg(irq); |
3083 | cpus_and(tmp, cfg->domain, tmp); | |
3084 | dest = cpu_mask_to_apicid(tmp); | |
3085 | ||
54168ed7 IM |
3086 | #ifdef CONFIG_INTR_REMAP |
3087 | if (irq_remapped(irq)) { | |
3088 | struct irte irte; | |
3089 | int ir_index; | |
3090 | u16 sub_handle; | |
3091 | ||
3092 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
3093 | BUG_ON(ir_index == -1); | |
3094 | ||
3095 | memset (&irte, 0, sizeof(irte)); | |
3096 | ||
3097 | irte.present = 1; | |
3098 | irte.dst_mode = INT_DEST_MODE; | |
3099 | irte.trigger_mode = 0; /* edge */ | |
3100 | irte.dlvry_mode = INT_DELIVERY_MODE; | |
3101 | irte.vector = cfg->vector; | |
3102 | irte.dest_id = IRTE_DEST(dest); | |
3103 | ||
3104 | modify_irte(irq, &irte); | |
3105 | ||
3106 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3107 | msg->data = sub_handle; | |
3108 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
3109 | MSI_ADDR_IR_SHV | | |
3110 | MSI_ADDR_IR_INDEX1(ir_index) | | |
3111 | MSI_ADDR_IR_INDEX2(ir_index); | |
3112 | } else | |
3113 | #endif | |
3114 | { | |
3115 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3116 | msg->address_lo = | |
3117 | MSI_ADDR_BASE_LO | | |
3118 | ((INT_DEST_MODE == 0) ? | |
3119 | MSI_ADDR_DEST_MODE_PHYSICAL: | |
3120 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
3121 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3122 | MSI_ADDR_REDIRECTION_CPU: | |
3123 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
3124 | MSI_ADDR_DEST_ID(dest); | |
497c9a19 | 3125 | |
54168ed7 IM |
3126 | msg->data = |
3127 | MSI_DATA_TRIGGER_EDGE | | |
3128 | MSI_DATA_LEVEL_ASSERT | | |
3129 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3130 | MSI_DATA_DELIVERY_FIXED: | |
3131 | MSI_DATA_DELIVERY_LOWPRI) | | |
3132 | MSI_DATA_VECTOR(cfg->vector); | |
3133 | } | |
497c9a19 | 3134 | return err; |
2d3fcc1c EB |
3135 | } |
3136 | ||
3b7d1921 EB |
3137 | #ifdef CONFIG_SMP |
3138 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 3139 | { |
497c9a19 | 3140 | struct irq_cfg *cfg; |
3b7d1921 EB |
3141 | struct msi_msg msg; |
3142 | unsigned int dest; | |
3143 | cpumask_t tmp; | |
54168ed7 | 3144 | struct irq_desc *desc; |
3b7d1921 EB |
3145 | |
3146 | cpus_and(tmp, mask, cpu_online_map); | |
3147 | if (cpus_empty(tmp)) | |
497c9a19 | 3148 | return; |
2d3fcc1c | 3149 | |
497c9a19 | 3150 | if (assign_irq_vector(irq, mask)) |
3b7d1921 | 3151 | return; |
2d3fcc1c | 3152 | |
497c9a19 YL |
3153 | cfg = irq_cfg(irq); |
3154 | cpus_and(tmp, cfg->domain, mask); | |
3155 | dest = cpu_mask_to_apicid(tmp); | |
3b7d1921 EB |
3156 | |
3157 | read_msi_msg(irq, &msg); | |
3158 | ||
3159 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
497c9a19 | 3160 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
3b7d1921 EB |
3161 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
3162 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3163 | ||
3164 | write_msi_msg(irq, &msg); | |
54168ed7 IM |
3165 | desc = irq_to_desc(irq); |
3166 | desc->affinity = mask; | |
2d3fcc1c | 3167 | } |
54168ed7 IM |
3168 | |
3169 | #ifdef CONFIG_INTR_REMAP | |
3170 | /* | |
3171 | * Migrate the MSI irq to another cpumask. This migration is | |
3172 | * done in the process context using interrupt-remapping hardware. | |
3173 | */ | |
3174 | static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
3175 | { | |
3176 | struct irq_cfg *cfg; | |
3177 | unsigned int dest; | |
3178 | cpumask_t tmp, cleanup_mask; | |
3179 | struct irte irte; | |
3180 | struct irq_desc *desc; | |
3181 | ||
3182 | cpus_and(tmp, mask, cpu_online_map); | |
3183 | if (cpus_empty(tmp)) | |
3184 | return; | |
3185 | ||
3186 | if (get_irte(irq, &irte)) | |
3187 | return; | |
3188 | ||
3189 | if (assign_irq_vector(irq, mask)) | |
3190 | return; | |
3191 | ||
3192 | cfg = irq_cfg(irq); | |
3193 | cpus_and(tmp, cfg->domain, mask); | |
3194 | dest = cpu_mask_to_apicid(tmp); | |
3195 | ||
3196 | irte.vector = cfg->vector; | |
3197 | irte.dest_id = IRTE_DEST(dest); | |
3198 | ||
3199 | /* | |
3200 | * atomically update the IRTE with the new destination and vector. | |
3201 | */ | |
3202 | modify_irte(irq, &irte); | |
3203 | ||
3204 | /* | |
3205 | * After this point, all the interrupts will start arriving | |
3206 | * at the new destination. So, time to cleanup the previous | |
3207 | * vector allocation. | |
3208 | */ | |
3209 | if (cfg->move_in_progress) { | |
3210 | cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map); | |
3211 | cfg->move_cleanup_count = cpus_weight(cleanup_mask); | |
3212 | send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
3213 | cfg->move_in_progress = 0; | |
3214 | } | |
3215 | ||
3216 | desc = irq_to_desc(irq); | |
3217 | desc->affinity = mask; | |
3218 | } | |
3219 | #endif | |
3b7d1921 | 3220 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 3221 | |
3b7d1921 EB |
3222 | /* |
3223 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
3224 | * which implement the MSI or MSI-X Capability Structure. | |
3225 | */ | |
3226 | static struct irq_chip msi_chip = { | |
3227 | .name = "PCI-MSI", | |
3228 | .unmask = unmask_msi_irq, | |
3229 | .mask = mask_msi_irq, | |
1d025192 | 3230 | .ack = ack_apic_edge, |
3b7d1921 EB |
3231 | #ifdef CONFIG_SMP |
3232 | .set_affinity = set_msi_irq_affinity, | |
3233 | #endif | |
3234 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
3235 | }; |
3236 | ||
54168ed7 IM |
3237 | #ifdef CONFIG_INTR_REMAP |
3238 | static struct irq_chip msi_ir_chip = { | |
3239 | .name = "IR-PCI-MSI", | |
3240 | .unmask = unmask_msi_irq, | |
3241 | .mask = mask_msi_irq, | |
3242 | .ack = ack_x2apic_edge, | |
3243 | #ifdef CONFIG_SMP | |
3244 | .set_affinity = ir_set_msi_irq_affinity, | |
3245 | #endif | |
3246 | .retrigger = ioapic_retrigger_irq, | |
3247 | }; | |
3248 | ||
3249 | /* | |
3250 | * Map the PCI dev to the corresponding remapping hardware unit | |
3251 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
3252 | * in it. | |
3253 | */ | |
3254 | static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) | |
3255 | { | |
3256 | struct intel_iommu *iommu; | |
3257 | int index; | |
3258 | ||
3259 | iommu = map_dev_to_ir(dev); | |
3260 | if (!iommu) { | |
3261 | printk(KERN_ERR | |
3262 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
3263 | return -ENOENT; | |
3264 | } | |
3265 | ||
3266 | index = alloc_irte(iommu, irq, nvec); | |
3267 | if (index < 0) { | |
3268 | printk(KERN_ERR | |
3269 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
3270 | pci_name(dev)); | |
3271 | return -ENOSPC; | |
3272 | } | |
3273 | return index; | |
3274 | } | |
3275 | #endif | |
1d025192 YL |
3276 | |
3277 | static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq) | |
3278 | { | |
3279 | int ret; | |
3280 | struct msi_msg msg; | |
3281 | ||
3282 | ret = msi_compose_msg(dev, irq, &msg); | |
3283 | if (ret < 0) | |
3284 | return ret; | |
3285 | ||
3286 | set_irq_msi(irq, desc); | |
3287 | write_msi_msg(irq, &msg); | |
3288 | ||
54168ed7 IM |
3289 | #ifdef CONFIG_INTR_REMAP |
3290 | if (irq_remapped(irq)) { | |
3291 | struct irq_desc *desc = irq_to_desc(irq); | |
3292 | /* | |
3293 | * irq migration in process context | |
3294 | */ | |
3295 | desc->status |= IRQ_MOVE_PCNTXT; | |
3296 | set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge"); | |
3297 | } else | |
3298 | #endif | |
3299 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge"); | |
1d025192 YL |
3300 | |
3301 | return 0; | |
3302 | } | |
3303 | ||
199751d7 YL |
3304 | static unsigned int build_irq_for_pci_dev(struct pci_dev *dev) |
3305 | { | |
3306 | unsigned int irq; | |
3307 | ||
3308 | irq = dev->bus->number; | |
3309 | irq <<= 8; | |
3310 | irq |= dev->devfn; | |
3311 | irq <<= 12; | |
3312 | ||
3313 | return irq; | |
3314 | } | |
3315 | ||
f7feaca7 | 3316 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 | 3317 | { |
54168ed7 IM |
3318 | unsigned int irq; |
3319 | int ret; | |
199751d7 YL |
3320 | unsigned int irq_want; |
3321 | ||
3322 | irq_want = build_irq_for_pci_dev(dev) + 0x100; | |
3323 | ||
3324 | irq = create_irq_nr(irq_want); | |
199751d7 YL |
3325 | if (irq == 0) |
3326 | return -1; | |
f7feaca7 | 3327 | |
54168ed7 IM |
3328 | #ifdef CONFIG_INTR_REMAP |
3329 | if (!intr_remapping_enabled) | |
3330 | goto no_ir; | |
3331 | ||
3332 | ret = msi_alloc_irte(dev, irq, 1); | |
3333 | if (ret < 0) | |
3334 | goto error; | |
3335 | no_ir: | |
3336 | #endif | |
1d025192 | 3337 | ret = setup_msi_irq(dev, desc, irq); |
f7feaca7 EB |
3338 | if (ret < 0) { |
3339 | destroy_irq(irq); | |
3b7d1921 | 3340 | return ret; |
54168ed7 | 3341 | } |
7fe3730d | 3342 | return 0; |
54168ed7 IM |
3343 | |
3344 | #ifdef CONFIG_INTR_REMAP | |
3345 | error: | |
3346 | destroy_irq(irq); | |
3347 | return ret; | |
3348 | #endif | |
3b7d1921 EB |
3349 | } |
3350 | ||
047c8fdb YL |
3351 | int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
3352 | { | |
54168ed7 IM |
3353 | unsigned int irq; |
3354 | int ret, sub_handle; | |
3355 | struct msi_desc *desc; | |
3356 | unsigned int irq_want; | |
3357 | ||
3358 | #ifdef CONFIG_INTR_REMAP | |
3359 | struct intel_iommu *iommu = 0; | |
3360 | int index = 0; | |
3361 | #endif | |
3362 | ||
3363 | irq_want = build_irq_for_pci_dev(dev) + 0x100; | |
3364 | sub_handle = 0; | |
3365 | list_for_each_entry(desc, &dev->msi_list, list) { | |
3366 | irq = create_irq_nr(irq_want--); | |
3367 | if (irq == 0) | |
3368 | return -1; | |
3369 | #ifdef CONFIG_INTR_REMAP | |
3370 | if (!intr_remapping_enabled) | |
3371 | goto no_ir; | |
3372 | ||
3373 | if (!sub_handle) { | |
3374 | /* | |
3375 | * allocate the consecutive block of IRTE's | |
3376 | * for 'nvec' | |
3377 | */ | |
3378 | index = msi_alloc_irte(dev, irq, nvec); | |
3379 | if (index < 0) { | |
3380 | ret = index; | |
3381 | goto error; | |
3382 | } | |
3383 | } else { | |
3384 | iommu = map_dev_to_ir(dev); | |
3385 | if (!iommu) { | |
3386 | ret = -ENOENT; | |
3387 | goto error; | |
3388 | } | |
3389 | /* | |
3390 | * setup the mapping between the irq and the IRTE | |
3391 | * base index, the sub_handle pointing to the | |
3392 | * appropriate interrupt remap table entry. | |
3393 | */ | |
3394 | set_irte_irq(irq, iommu, index, sub_handle); | |
3395 | } | |
3396 | no_ir: | |
3397 | #endif | |
3398 | ret = setup_msi_irq(dev, desc, irq); | |
3399 | if (ret < 0) | |
3400 | goto error; | |
3401 | sub_handle++; | |
3402 | } | |
3403 | return 0; | |
047c8fdb YL |
3404 | |
3405 | error: | |
54168ed7 IM |
3406 | destroy_irq(irq); |
3407 | return ret; | |
047c8fdb YL |
3408 | } |
3409 | ||
3b7d1921 EB |
3410 | void arch_teardown_msi_irq(unsigned int irq) |
3411 | { | |
f7feaca7 | 3412 | destroy_irq(irq); |
3b7d1921 EB |
3413 | } |
3414 | ||
54168ed7 IM |
3415 | #ifdef CONFIG_DMAR |
3416 | #ifdef CONFIG_SMP | |
3417 | static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask) | |
3418 | { | |
3419 | struct irq_cfg *cfg; | |
3420 | struct msi_msg msg; | |
3421 | unsigned int dest; | |
3422 | cpumask_t tmp; | |
3423 | struct irq_desc *desc; | |
3424 | ||
3425 | cpus_and(tmp, mask, cpu_online_map); | |
3426 | if (cpus_empty(tmp)) | |
3427 | return; | |
3428 | ||
3429 | if (assign_irq_vector(irq, mask)) | |
3430 | return; | |
3431 | ||
3432 | cfg = irq_cfg(irq); | |
3433 | cpus_and(tmp, cfg->domain, mask); | |
3434 | dest = cpu_mask_to_apicid(tmp); | |
3435 | ||
3436 | dmar_msi_read(irq, &msg); | |
3437 | ||
3438 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
3439 | msg.data |= MSI_DATA_VECTOR(cfg->vector); | |
3440 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
3441 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
3442 | ||
3443 | dmar_msi_write(irq, &msg); | |
3444 | desc = irq_to_desc(irq); | |
3445 | desc->affinity = mask; | |
3446 | } | |
3447 | #endif /* CONFIG_SMP */ | |
3448 | ||
3449 | struct irq_chip dmar_msi_type = { | |
3450 | .name = "DMAR_MSI", | |
3451 | .unmask = dmar_msi_unmask, | |
3452 | .mask = dmar_msi_mask, | |
3453 | .ack = ack_apic_edge, | |
3454 | #ifdef CONFIG_SMP | |
3455 | .set_affinity = dmar_msi_set_affinity, | |
3456 | #endif | |
3457 | .retrigger = ioapic_retrigger_irq, | |
3458 | }; | |
3459 | ||
3460 | int arch_setup_dmar_msi(unsigned int irq) | |
3461 | { | |
3462 | int ret; | |
3463 | struct msi_msg msg; | |
2d3fcc1c | 3464 | |
54168ed7 IM |
3465 | ret = msi_compose_msg(NULL, irq, &msg); |
3466 | if (ret < 0) | |
3467 | return ret; | |
3468 | dmar_msi_write(irq, &msg); | |
3469 | set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, | |
3470 | "edge"); | |
3471 | return 0; | |
3472 | } | |
3473 | #endif | |
3474 | ||
3475 | #endif /* CONFIG_PCI_MSI */ | |
8b955b0d EB |
3476 | /* |
3477 | * Hypertransport interrupt support | |
3478 | */ | |
3479 | #ifdef CONFIG_HT_IRQ | |
3480 | ||
3481 | #ifdef CONFIG_SMP | |
3482 | ||
497c9a19 | 3483 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
8b955b0d | 3484 | { |
ec68307c EB |
3485 | struct ht_irq_msg msg; |
3486 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 3487 | |
497c9a19 | 3488 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
ec68307c | 3489 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
8b955b0d | 3490 | |
497c9a19 | 3491 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
ec68307c | 3492 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3493 | |
ec68307c | 3494 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
3495 | } |
3496 | ||
3497 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
3498 | { | |
497c9a19 | 3499 | struct irq_cfg *cfg; |
8b955b0d EB |
3500 | unsigned int dest; |
3501 | cpumask_t tmp; | |
54168ed7 | 3502 | struct irq_desc *desc; |
8b955b0d EB |
3503 | |
3504 | cpus_and(tmp, mask, cpu_online_map); | |
3505 | if (cpus_empty(tmp)) | |
497c9a19 | 3506 | return; |
8b955b0d | 3507 | |
497c9a19 YL |
3508 | if (assign_irq_vector(irq, mask)) |
3509 | return; | |
8b955b0d | 3510 | |
497c9a19 YL |
3511 | cfg = irq_cfg(irq); |
3512 | cpus_and(tmp, cfg->domain, mask); | |
3513 | dest = cpu_mask_to_apicid(tmp); | |
8b955b0d | 3514 | |
497c9a19 | 3515 | target_ht_irq(irq, dest, cfg->vector); |
54168ed7 IM |
3516 | desc = irq_to_desc(irq); |
3517 | desc->affinity = mask; | |
8b955b0d EB |
3518 | } |
3519 | #endif | |
3520 | ||
c37e108d | 3521 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
3522 | .name = "PCI-HT", |
3523 | .mask = mask_ht_irq, | |
3524 | .unmask = unmask_ht_irq, | |
1d025192 | 3525 | .ack = ack_apic_edge, |
8b955b0d EB |
3526 | #ifdef CONFIG_SMP |
3527 | .set_affinity = set_ht_irq_affinity, | |
3528 | #endif | |
3529 | .retrigger = ioapic_retrigger_irq, | |
3530 | }; | |
3531 | ||
3532 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
3533 | { | |
497c9a19 YL |
3534 | struct irq_cfg *cfg; |
3535 | int err; | |
3536 | cpumask_t tmp; | |
8b955b0d | 3537 | |
497c9a19 YL |
3538 | tmp = TARGET_CPUS; |
3539 | err = assign_irq_vector(irq, tmp); | |
54168ed7 | 3540 | if (!err) { |
ec68307c | 3541 | struct ht_irq_msg msg; |
8b955b0d | 3542 | unsigned dest; |
8b955b0d | 3543 | |
497c9a19 YL |
3544 | cfg = irq_cfg(irq); |
3545 | cpus_and(tmp, cfg->domain, tmp); | |
8b955b0d EB |
3546 | dest = cpu_mask_to_apicid(tmp); |
3547 | ||
ec68307c | 3548 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 3549 | |
ec68307c EB |
3550 | msg.address_lo = |
3551 | HT_IRQ_LOW_BASE | | |
8b955b0d | 3552 | HT_IRQ_LOW_DEST_ID(dest) | |
497c9a19 | 3553 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
8b955b0d EB |
3554 | ((INT_DEST_MODE == 0) ? |
3555 | HT_IRQ_LOW_DM_PHYSICAL : | |
3556 | HT_IRQ_LOW_DM_LOGICAL) | | |
3557 | HT_IRQ_LOW_RQEOI_EDGE | | |
3558 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
3559 | HT_IRQ_LOW_MT_FIXED : | |
3560 | HT_IRQ_LOW_MT_ARBITRATED) | | |
3561 | HT_IRQ_LOW_IRQ_MASKED; | |
3562 | ||
ec68307c | 3563 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 3564 | |
a460e745 IM |
3565 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
3566 | handle_edge_irq, "edge"); | |
8b955b0d | 3567 | } |
497c9a19 | 3568 | return err; |
8b955b0d EB |
3569 | } |
3570 | #endif /* CONFIG_HT_IRQ */ | |
3571 | ||
1da177e4 | 3572 | /* -------------------------------------------------------------------------- |
54168ed7 | 3573 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
3574 | -------------------------------------------------------------------------- */ |
3575 | ||
888ba6c6 | 3576 | #ifdef CONFIG_ACPI |
1da177e4 | 3577 | |
54168ed7 | 3578 | #ifdef CONFIG_X86_32 |
36062448 | 3579 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
3580 | { |
3581 | union IO_APIC_reg_00 reg_00; | |
3582 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
3583 | physid_mask_t tmp; | |
3584 | unsigned long flags; | |
3585 | int i = 0; | |
3586 | ||
3587 | /* | |
36062448 PC |
3588 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
3589 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 3590 | * supports up to 16 on one shared APIC bus. |
36062448 | 3591 | * |
1da177e4 LT |
3592 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
3593 | * advantage of new APIC bus architecture. | |
3594 | */ | |
3595 | ||
3596 | if (physids_empty(apic_id_map)) | |
3597 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
3598 | ||
3599 | spin_lock_irqsave(&ioapic_lock, flags); | |
3600 | reg_00.raw = io_apic_read(ioapic, 0); | |
3601 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3602 | ||
3603 | if (apic_id >= get_physical_broadcast()) { | |
3604 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
3605 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
3606 | apic_id = reg_00.bits.ID; | |
3607 | } | |
3608 | ||
3609 | /* | |
36062448 | 3610 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
3611 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
3612 | */ | |
3613 | if (check_apicid_used(apic_id_map, apic_id)) { | |
3614 | ||
3615 | for (i = 0; i < get_physical_broadcast(); i++) { | |
3616 | if (!check_apicid_used(apic_id_map, i)) | |
3617 | break; | |
3618 | } | |
3619 | ||
3620 | if (i == get_physical_broadcast()) | |
3621 | panic("Max apic_id exceeded!\n"); | |
3622 | ||
3623 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
3624 | "trying %d\n", ioapic, apic_id, i); | |
3625 | ||
3626 | apic_id = i; | |
36062448 | 3627 | } |
1da177e4 LT |
3628 | |
3629 | tmp = apicid_to_cpu_present(apic_id); | |
3630 | physids_or(apic_id_map, apic_id_map, tmp); | |
3631 | ||
3632 | if (reg_00.bits.ID != apic_id) { | |
3633 | reg_00.bits.ID = apic_id; | |
3634 | ||
3635 | spin_lock_irqsave(&ioapic_lock, flags); | |
3636 | io_apic_write(ioapic, 0, reg_00.raw); | |
3637 | reg_00.raw = io_apic_read(ioapic, 0); | |
3638 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3639 | ||
3640 | /* Sanity check */ | |
6070f9ec AD |
3641 | if (reg_00.bits.ID != apic_id) { |
3642 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
3643 | return -1; | |
3644 | } | |
1da177e4 LT |
3645 | } |
3646 | ||
3647 | apic_printk(APIC_VERBOSE, KERN_INFO | |
3648 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
3649 | ||
3650 | return apic_id; | |
3651 | } | |
3652 | ||
36062448 | 3653 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
3654 | { |
3655 | union IO_APIC_reg_01 reg_01; | |
3656 | unsigned long flags; | |
3657 | ||
3658 | spin_lock_irqsave(&ioapic_lock, flags); | |
3659 | reg_01.raw = io_apic_read(ioapic, 1); | |
3660 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3661 | ||
3662 | return reg_01.bits.version; | |
3663 | } | |
54168ed7 | 3664 | #endif |
1da177e4 | 3665 | |
54168ed7 | 3666 | int __init io_apic_get_redir_entries (int ioapic) |
1da177e4 LT |
3667 | { |
3668 | union IO_APIC_reg_01 reg_01; | |
3669 | unsigned long flags; | |
3670 | ||
3671 | spin_lock_irqsave(&ioapic_lock, flags); | |
3672 | reg_01.raw = io_apic_read(ioapic, 1); | |
3673 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
3674 | ||
3675 | return reg_01.bits.entries; | |
3676 | } | |
3677 | ||
3678 | ||
54168ed7 | 3679 | int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity) |
1da177e4 | 3680 | { |
1da177e4 | 3681 | if (!IO_APIC_IRQ(irq)) { |
54168ed7 | 3682 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
1da177e4 LT |
3683 | ioapic); |
3684 | return -EINVAL; | |
3685 | } | |
3686 | ||
1da177e4 LT |
3687 | /* |
3688 | * IRQs < 16 are already in the irq_2_pin[] map | |
3689 | */ | |
3690 | if (irq >= 16) | |
3691 | add_pin_to_irq(irq, ioapic, pin); | |
3692 | ||
497c9a19 | 3693 | setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity); |
1da177e4 LT |
3694 | |
3695 | return 0; | |
3696 | } | |
3697 | ||
54168ed7 | 3698 | |
61fd47e0 SL |
3699 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
3700 | { | |
3701 | int i; | |
3702 | ||
3703 | if (skip_ioapic_setup) | |
3704 | return -1; | |
3705 | ||
3706 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
3707 | if (mp_irqs[i].mp_irqtype == mp_INT && |
3708 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
3709 | break; |
3710 | if (i >= mp_irq_entries) | |
3711 | return -1; | |
3712 | ||
3713 | *trigger = irq_trigger(i); | |
3714 | *polarity = irq_polarity(i); | |
3715 | return 0; | |
3716 | } | |
3717 | ||
888ba6c6 | 3718 | #endif /* CONFIG_ACPI */ |
1a3f239d | 3719 | |
497c9a19 YL |
3720 | /* |
3721 | * This function currently is only a helper for the i386 smp boot process where | |
3722 | * we need to reprogram the ioredtbls to cater for the cpus which have come online | |
3723 | * so mask in all cases should simply be TARGET_CPUS | |
3724 | */ | |
3725 | #ifdef CONFIG_SMP | |
3726 | void __init setup_ioapic_dest(void) | |
3727 | { | |
3728 | int pin, ioapic, irq, irq_entry; | |
3729 | struct irq_cfg *cfg; | |
497c9a19 YL |
3730 | |
3731 | if (skip_ioapic_setup == 1) | |
3732 | return; | |
3733 | ||
3734 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
3735 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
3736 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
3737 | if (irq_entry == -1) | |
3738 | continue; | |
3739 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
3740 | ||
3741 | /* setup_IO_APIC_irqs could fail to get vector for some device | |
3742 | * when you have too many devices, because at that time only boot | |
3743 | * cpu is online. | |
3744 | */ | |
3745 | cfg = irq_cfg(irq); | |
3746 | if (!cfg->vector) | |
3747 | setup_IO_APIC_irq(ioapic, pin, irq, | |
3748 | irq_trigger(irq_entry), | |
3749 | irq_polarity(irq_entry)); | |
54168ed7 IM |
3750 | #ifdef CONFIG_INTR_REMAP |
3751 | else if (intr_remapping_enabled) | |
3752 | set_ir_ioapic_affinity_irq(irq, TARGET_CPUS); | |
3753 | #endif | |
3754 | else | |
497c9a19 | 3755 | set_ioapic_affinity_irq(irq, TARGET_CPUS); |
497c9a19 YL |
3756 | } |
3757 | ||
3758 | } | |
3759 | } | |
3760 | #endif | |
3761 | ||
54168ed7 IM |
3762 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
3763 | ||
3764 | static struct resource *ioapic_resources; | |
3765 | ||
3766 | static struct resource * __init ioapic_setup_resources(void) | |
3767 | { | |
3768 | unsigned long n; | |
3769 | struct resource *res; | |
3770 | char *mem; | |
3771 | int i; | |
3772 | ||
3773 | if (nr_ioapics <= 0) | |
3774 | return NULL; | |
3775 | ||
3776 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); | |
3777 | n *= nr_ioapics; | |
3778 | ||
3779 | mem = alloc_bootmem(n); | |
3780 | res = (void *)mem; | |
3781 | ||
3782 | if (mem != NULL) { | |
3783 | mem += sizeof(struct resource) * nr_ioapics; | |
3784 | ||
3785 | for (i = 0; i < nr_ioapics; i++) { | |
3786 | res[i].name = mem; | |
3787 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; | |
3788 | sprintf(mem, "IOAPIC %u", i); | |
3789 | mem += IOAPIC_RESOURCE_NAME_SIZE; | |
3790 | } | |
3791 | } | |
3792 | ||
3793 | ioapic_resources = res; | |
3794 | ||
3795 | return res; | |
3796 | } | |
54168ed7 | 3797 | |
f3294a33 YL |
3798 | void __init ioapic_init_mappings(void) |
3799 | { | |
3800 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; | |
3801 | int i; | |
54168ed7 | 3802 | struct resource *ioapic_res; |
f3294a33 | 3803 | |
54168ed7 | 3804 | ioapic_res = ioapic_setup_resources(); |
f3294a33 YL |
3805 | for (i = 0; i < nr_ioapics; i++) { |
3806 | if (smp_found_config) { | |
3807 | ioapic_phys = mp_ioapics[i].mp_apicaddr; | |
54168ed7 IM |
3808 | #ifdef CONFIG_X86_32 |
3809 | if (!ioapic_phys) { | |
3810 | printk(KERN_ERR | |
3811 | "WARNING: bogus zero IO-APIC " | |
3812 | "address found in MPTABLE, " | |
3813 | "disabling IO/APIC support!\n"); | |
3814 | smp_found_config = 0; | |
3815 | skip_ioapic_setup = 1; | |
3816 | goto fake_ioapic_page; | |
3817 | } | |
3818 | #endif | |
f3294a33 | 3819 | } else { |
54168ed7 | 3820 | #ifdef CONFIG_X86_32 |
f3294a33 | 3821 | fake_ioapic_page: |
54168ed7 | 3822 | #endif |
f3294a33 | 3823 | ioapic_phys = (unsigned long) |
54168ed7 | 3824 | alloc_bootmem_pages(PAGE_SIZE); |
f3294a33 YL |
3825 | ioapic_phys = __pa(ioapic_phys); |
3826 | } | |
3827 | set_fixmap_nocache(idx, ioapic_phys); | |
54168ed7 IM |
3828 | apic_printk(APIC_VERBOSE, |
3829 | "mapped IOAPIC to %08lx (%08lx)\n", | |
3830 | __fix_to_virt(idx), ioapic_phys); | |
f3294a33 | 3831 | idx++; |
54168ed7 | 3832 | |
54168ed7 IM |
3833 | if (ioapic_res != NULL) { |
3834 | ioapic_res->start = ioapic_phys; | |
3835 | ioapic_res->end = ioapic_phys + (4 * 1024) - 1; | |
3836 | ioapic_res++; | |
3837 | } | |
f3294a33 YL |
3838 | } |
3839 | } | |
3840 | ||
54168ed7 IM |
3841 | static int __init ioapic_insert_resources(void) |
3842 | { | |
3843 | int i; | |
3844 | struct resource *r = ioapic_resources; | |
3845 | ||
3846 | if (!r) { | |
3847 | printk(KERN_ERR | |
3848 | "IO APIC resources could be not be allocated.\n"); | |
3849 | return -1; | |
3850 | } | |
3851 | ||
3852 | for (i = 0; i < nr_ioapics; i++) { | |
3853 | insert_resource(&iomem_resource, r); | |
3854 | r++; | |
3855 | } | |
3856 | ||
3857 | return 0; | |
3858 | } | |
3859 | ||
3860 | /* Insert the IO APIC resources after PCI initialization has occured to handle | |
3861 | * IO APICS that are mapped in on a BAR in PCI space. */ | |
3862 | late_initcall(ioapic_insert_resources); |