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1da177e4 LT |
1 | /* |
2 | * Intel IO-APIC support for multi-Pentium hosts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo | |
5 | * | |
6 | * Many thanks to Stig Venaas for trying out countless experimental | |
7 | * patches and reporting/debugging problems patiently! | |
8 | * | |
9 | * (c) 1999, Multiple IO-APIC support, developed by | |
10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and | |
11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, | |
12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> | |
13 | * and Ingo Molnar <mingo@redhat.com> | |
14 | * | |
15 | * Fixes | |
16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; | |
17 | * thanks to Eric Gilmore | |
18 | * and Rolf G. Tews | |
19 | * for testing these extensively | |
20 | * Paul Diefenbaugh : Added full ACPI support | |
21 | */ | |
22 | ||
23 | #include <linux/mm.h> | |
1da177e4 LT |
24 | #include <linux/interrupt.h> |
25 | #include <linux/init.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/sched.h> | |
1da177e4 LT |
28 | #include <linux/mc146818rtc.h> |
29 | #include <linux/compiler.h> | |
30 | #include <linux/acpi.h> | |
129f6946 | 31 | #include <linux/module.h> |
1da177e4 | 32 | #include <linux/sysdev.h> |
2d3fcc1c | 33 | #include <linux/pci.h> |
3b7d1921 | 34 | #include <linux/msi.h> |
95d77884 | 35 | #include <linux/htirq.h> |
7dfb7103 | 36 | #include <linux/freezer.h> |
f26d6a2b | 37 | #include <linux/kthread.h> |
1d16b53e | 38 | #include <linux/jiffies.h> /* time_after() */ |
54d5d424 | 39 | |
1da177e4 LT |
40 | #include <asm/io.h> |
41 | #include <asm/smp.h> | |
42 | #include <asm/desc.h> | |
43 | #include <asm/timer.h> | |
306e440d | 44 | #include <asm/i8259.h> |
3e4ff115 | 45 | #include <asm/nmi.h> |
2d3fcc1c | 46 | #include <asm/msidef.h> |
8b955b0d | 47 | #include <asm/hypertransport.h> |
1da177e4 LT |
48 | |
49 | #include <mach_apic.h> | |
874c4fe3 | 50 | #include <mach_apicdef.h> |
1da177e4 | 51 | |
1da177e4 LT |
52 | int (*ioapic_renumber_irq)(int ioapic, int irq); |
53 | atomic_t irq_mis_count; | |
54 | ||
fcfd636a EB |
55 | /* Where if anywhere is the i8259 connect in external int mode */ |
56 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; | |
57 | ||
1da177e4 | 58 | static DEFINE_SPINLOCK(ioapic_lock); |
0a1ad60d | 59 | static DEFINE_SPINLOCK(vector_lock); |
1da177e4 | 60 | |
35542c5e | 61 | int timer_through_8259 __initdata; |
f9262c12 | 62 | |
1da177e4 LT |
63 | /* |
64 | * Is the SiS APIC rmw bug present ? | |
65 | * -1 = don't know, 0 = no, 1 = yes | |
66 | */ | |
67 | int sis_apic_bug = -1; | |
68 | ||
69 | /* | |
70 | * # of IRQ routing registers | |
71 | */ | |
72 | int nr_ioapic_registers[MAX_IO_APICS]; | |
73 | ||
9f640ccb | 74 | /* I/O APIC entries */ |
ec2cd0a2 | 75 | struct mp_config_ioapic mp_ioapics[MAX_IO_APICS]; |
9f640ccb AS |
76 | int nr_ioapics; |
77 | ||
584f734d | 78 | /* MP IRQ source entries */ |
2fddb6e2 | 79 | struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
584f734d AS |
80 | |
81 | /* # of MP IRQ source entries */ | |
82 | int mp_irq_entries; | |
83 | ||
8732fc4b AS |
84 | #if defined (CONFIG_MCA) || defined (CONFIG_EISA) |
85 | int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
86 | #endif | |
87 | ||
88 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
89 | ||
1a3f239d | 90 | static int disable_timer_pin_1 __initdata; |
66759a01 | 91 | |
1da177e4 LT |
92 | /* |
93 | * Rough estimation of how many shared IRQs there are, can | |
94 | * be changed anytime. | |
95 | */ | |
96 | #define MAX_PLUS_SHARED_IRQS NR_IRQS | |
97 | #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) | |
98 | ||
99 | /* | |
100 | * This is performance-critical, we want to do it O(1) | |
101 | * | |
102 | * the indexing order of this array favors 1:1 mappings | |
103 | * between pins and IRQs. | |
104 | */ | |
105 | ||
106 | static struct irq_pin_list { | |
107 | int apic, pin, next; | |
108 | } irq_2_pin[PIN_MAP_SIZE]; | |
109 | ||
130fe05d LT |
110 | struct io_apic { |
111 | unsigned int index; | |
112 | unsigned int unused[3]; | |
113 | unsigned int data; | |
114 | }; | |
115 | ||
116 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) | |
117 | { | |
118 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) | |
ec2cd0a2 | 119 | + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK); |
130fe05d LT |
120 | } |
121 | ||
122 | static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) | |
123 | { | |
124 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
125 | writel(reg, &io_apic->index); | |
126 | return readl(&io_apic->data); | |
127 | } | |
128 | ||
129 | static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) | |
130 | { | |
131 | struct io_apic __iomem *io_apic = io_apic_base(apic); | |
132 | writel(reg, &io_apic->index); | |
133 | writel(value, &io_apic->data); | |
134 | } | |
135 | ||
136 | /* | |
137 | * Re-write a value: to be used for read-modify-write | |
138 | * cycles where the read already set up the index register. | |
139 | * | |
140 | * Older SiS APIC requires we rewrite the index register | |
141 | */ | |
142 | static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) | |
143 | { | |
cb468984 | 144 | volatile struct io_apic __iomem *io_apic = io_apic_base(apic); |
130fe05d LT |
145 | if (sis_apic_bug) |
146 | writel(reg, &io_apic->index); | |
147 | writel(value, &io_apic->data); | |
148 | } | |
149 | ||
cf4c6a2f AK |
150 | union entry_union { |
151 | struct { u32 w1, w2; }; | |
152 | struct IO_APIC_route_entry entry; | |
153 | }; | |
154 | ||
155 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | |
156 | { | |
157 | union entry_union eu; | |
158 | unsigned long flags; | |
159 | spin_lock_irqsave(&ioapic_lock, flags); | |
160 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | |
161 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | |
162 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
163 | return eu.entry; | |
164 | } | |
165 | ||
f9dadfa7 LT |
166 | /* |
167 | * When we write a new IO APIC routing entry, we need to write the high | |
168 | * word first! If the mask bit in the low word is clear, we will enable | |
169 | * the interrupt, and we need to make sure the entry is fully populated | |
170 | * before that happens. | |
171 | */ | |
d15512f4 AK |
172 | static void |
173 | __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
cf4c6a2f | 174 | { |
cf4c6a2f AK |
175 | union entry_union eu; |
176 | eu.entry = e; | |
f9dadfa7 LT |
177 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
178 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
d15512f4 AK |
179 | } |
180 | ||
181 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) | |
182 | { | |
183 | unsigned long flags; | |
184 | spin_lock_irqsave(&ioapic_lock, flags); | |
185 | __ioapic_write_entry(apic, pin, e); | |
f9dadfa7 LT |
186 | spin_unlock_irqrestore(&ioapic_lock, flags); |
187 | } | |
188 | ||
189 | /* | |
190 | * When we mask an IO APIC routing entry, we need to write the low | |
191 | * word first, in order to set the mask bit before we change the | |
192 | * high bits! | |
193 | */ | |
194 | static void ioapic_mask_entry(int apic, int pin) | |
195 | { | |
196 | unsigned long flags; | |
197 | union entry_union eu = { .entry.mask = 1 }; | |
198 | ||
cf4c6a2f AK |
199 | spin_lock_irqsave(&ioapic_lock, flags); |
200 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); | |
201 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); | |
202 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
203 | } | |
204 | ||
1da177e4 LT |
205 | /* |
206 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are | |
207 | * shared ISA-space IRQs, so we have to support them. We are super | |
208 | * fast in the common case, and fast for shared ISA-space IRQs. | |
209 | */ | |
210 | static void add_pin_to_irq(unsigned int irq, int apic, int pin) | |
211 | { | |
212 | static int first_free_entry = NR_IRQS; | |
213 | struct irq_pin_list *entry = irq_2_pin + irq; | |
214 | ||
215 | while (entry->next) | |
216 | entry = irq_2_pin + entry->next; | |
217 | ||
218 | if (entry->pin != -1) { | |
219 | entry->next = first_free_entry; | |
220 | entry = irq_2_pin + entry->next; | |
221 | if (++first_free_entry >= PIN_MAP_SIZE) | |
222 | panic("io_apic.c: whoops"); | |
223 | } | |
224 | entry->apic = apic; | |
225 | entry->pin = pin; | |
226 | } | |
227 | ||
228 | /* | |
229 | * Reroute an IRQ to a different pin. | |
230 | */ | |
231 | static void __init replace_pin_at_irq(unsigned int irq, | |
232 | int oldapic, int oldpin, | |
233 | int newapic, int newpin) | |
234 | { | |
235 | struct irq_pin_list *entry = irq_2_pin + irq; | |
236 | ||
237 | while (1) { | |
238 | if (entry->apic == oldapic && entry->pin == oldpin) { | |
239 | entry->apic = newapic; | |
240 | entry->pin = newpin; | |
241 | } | |
242 | if (!entry->next) | |
243 | break; | |
244 | entry = irq_2_pin + entry->next; | |
245 | } | |
246 | } | |
247 | ||
36062448 | 248 | static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable) |
1da177e4 LT |
249 | { |
250 | struct irq_pin_list *entry = irq_2_pin + irq; | |
251 | unsigned int pin, reg; | |
252 | ||
253 | for (;;) { | |
254 | pin = entry->pin; | |
255 | if (pin == -1) | |
256 | break; | |
257 | reg = io_apic_read(entry->apic, 0x10 + pin*2); | |
258 | reg &= ~disable; | |
259 | reg |= enable; | |
260 | io_apic_modify(entry->apic, 0x10 + pin*2, reg); | |
261 | if (!entry->next) | |
262 | break; | |
263 | entry = irq_2_pin + entry->next; | |
264 | } | |
265 | } | |
266 | ||
267 | /* mask = 1 */ | |
36062448 | 268 | static void __mask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 269 | { |
46b3b4ef | 270 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0); |
1da177e4 LT |
271 | } |
272 | ||
273 | /* mask = 0 */ | |
36062448 | 274 | static void __unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 | 275 | { |
46b3b4ef | 276 | __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED); |
1da177e4 LT |
277 | } |
278 | ||
279 | /* mask = 1, trigger = 0 */ | |
36062448 | 280 | static void __mask_and_edge_IO_APIC_irq(unsigned int irq) |
1da177e4 | 281 | { |
46b3b4ef CG |
282 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, |
283 | IO_APIC_REDIR_LEVEL_TRIGGER); | |
1da177e4 LT |
284 | } |
285 | ||
286 | /* mask = 0, trigger = 1 */ | |
36062448 | 287 | static void __unmask_and_level_IO_APIC_irq(unsigned int irq) |
1da177e4 | 288 | { |
46b3b4ef CG |
289 | __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER, |
290 | IO_APIC_REDIR_MASKED); | |
1da177e4 LT |
291 | } |
292 | ||
36062448 | 293 | static void mask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
294 | { |
295 | unsigned long flags; | |
296 | ||
297 | spin_lock_irqsave(&ioapic_lock, flags); | |
298 | __mask_IO_APIC_irq(irq); | |
299 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
300 | } | |
301 | ||
36062448 | 302 | static void unmask_IO_APIC_irq(unsigned int irq) |
1da177e4 LT |
303 | { |
304 | unsigned long flags; | |
305 | ||
306 | spin_lock_irqsave(&ioapic_lock, flags); | |
307 | __unmask_IO_APIC_irq(irq); | |
308 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
309 | } | |
310 | ||
311 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |
312 | { | |
313 | struct IO_APIC_route_entry entry; | |
36062448 | 314 | |
1da177e4 | 315 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
cf4c6a2f | 316 | entry = ioapic_read_entry(apic, pin); |
1da177e4 LT |
317 | if (entry.delivery_mode == dest_SMI) |
318 | return; | |
319 | ||
320 | /* | |
321 | * Disable it in the IO-APIC irq-routing table: | |
322 | */ | |
f9dadfa7 | 323 | ioapic_mask_entry(apic, pin); |
1da177e4 LT |
324 | } |
325 | ||
36062448 | 326 | static void clear_IO_APIC(void) |
1da177e4 LT |
327 | { |
328 | int apic, pin; | |
329 | ||
330 | for (apic = 0; apic < nr_ioapics; apic++) | |
331 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) | |
332 | clear_IO_APIC_pin(apic, pin); | |
333 | } | |
334 | ||
54d5d424 | 335 | #ifdef CONFIG_SMP |
1da177e4 LT |
336 | static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask) |
337 | { | |
338 | unsigned long flags; | |
339 | int pin; | |
340 | struct irq_pin_list *entry = irq_2_pin + irq; | |
341 | unsigned int apicid_value; | |
54d5d424 | 342 | cpumask_t tmp; |
36062448 | 343 | |
54d5d424 AR |
344 | cpus_and(tmp, cpumask, cpu_online_map); |
345 | if (cpus_empty(tmp)) | |
346 | tmp = TARGET_CPUS; | |
347 | ||
348 | cpus_and(cpumask, tmp, CPU_MASK_ALL); | |
349 | ||
1da177e4 LT |
350 | apicid_value = cpu_mask_to_apicid(cpumask); |
351 | /* Prepare to do the io_apic_write */ | |
352 | apicid_value = apicid_value << 24; | |
353 | spin_lock_irqsave(&ioapic_lock, flags); | |
354 | for (;;) { | |
355 | pin = entry->pin; | |
356 | if (pin == -1) | |
357 | break; | |
358 | io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value); | |
359 | if (!entry->next) | |
360 | break; | |
361 | entry = irq_2_pin + entry->next; | |
362 | } | |
9f0a5ba5 | 363 | irq_desc[irq].affinity = cpumask; |
1da177e4 LT |
364 | spin_unlock_irqrestore(&ioapic_lock, flags); |
365 | } | |
366 | ||
367 | #if defined(CONFIG_IRQBALANCE) | |
368 | # include <asm/processor.h> /* kernel_thread() */ | |
369 | # include <linux/kernel_stat.h> /* kstat */ | |
370 | # include <linux/slab.h> /* kmalloc() */ | |
1d16b53e | 371 | # include <linux/timer.h> |
36062448 | 372 | |
1da177e4 | 373 | #define IRQBALANCE_CHECK_ARCH -999 |
1b61b910 ZY |
374 | #define MAX_BALANCED_IRQ_INTERVAL (5*HZ) |
375 | #define MIN_BALANCED_IRQ_INTERVAL (HZ/2) | |
376 | #define BALANCED_IRQ_MORE_DELTA (HZ/10) | |
377 | #define BALANCED_IRQ_LESS_DELTA (HZ) | |
378 | ||
379 | static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH; | |
380 | static int physical_balance __read_mostly; | |
381 | static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL; | |
1da177e4 LT |
382 | |
383 | static struct irq_cpu_info { | |
36062448 PC |
384 | unsigned long *last_irq; |
385 | unsigned long *irq_delta; | |
1da177e4 LT |
386 | unsigned long irq; |
387 | } irq_cpu_data[NR_CPUS]; | |
388 | ||
389 | #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq) | |
36062448 PC |
390 | #define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq]) |
391 | #define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq]) | |
1da177e4 LT |
392 | |
393 | #define IDLE_ENOUGH(cpu,now) \ | |
394 | (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1)) | |
395 | ||
396 | #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask) | |
397 | ||
d5a7430d | 398 | #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i))) |
1da177e4 | 399 | |
1b61b910 ZY |
400 | static cpumask_t balance_irq_affinity[NR_IRQS] = { |
401 | [0 ... NR_IRQS-1] = CPU_MASK_ALL | |
402 | }; | |
1da177e4 | 403 | |
1b61b910 ZY |
404 | void set_balance_irq_affinity(unsigned int irq, cpumask_t mask) |
405 | { | |
406 | balance_irq_affinity[irq] = mask; | |
407 | } | |
1da177e4 LT |
408 | |
409 | static unsigned long move(int curr_cpu, cpumask_t allowed_mask, | |
410 | unsigned long now, int direction) | |
411 | { | |
412 | int search_idle = 1; | |
413 | int cpu = curr_cpu; | |
414 | ||
415 | goto inside; | |
416 | ||
417 | do { | |
418 | if (unlikely(cpu == curr_cpu)) | |
419 | search_idle = 0; | |
420 | inside: | |
421 | if (direction == 1) { | |
422 | cpu++; | |
423 | if (cpu >= NR_CPUS) | |
424 | cpu = 0; | |
425 | } else { | |
426 | cpu--; | |
427 | if (cpu == -1) | |
428 | cpu = NR_CPUS-1; | |
429 | } | |
36062448 PC |
430 | } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) || |
431 | (search_idle && !IDLE_ENOUGH(cpu, now))); | |
1da177e4 LT |
432 | |
433 | return cpu; | |
434 | } | |
435 | ||
436 | static inline void balance_irq(int cpu, int irq) | |
437 | { | |
438 | unsigned long now = jiffies; | |
439 | cpumask_t allowed_mask; | |
440 | unsigned int new_cpu; | |
36062448 | 441 | |
1da177e4 | 442 | if (irqbalance_disabled) |
36062448 | 443 | return; |
1da177e4 | 444 | |
1b61b910 | 445 | cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]); |
1da177e4 | 446 | new_cpu = move(cpu, allowed_mask, now, 1); |
36062448 | 447 | if (cpu != new_cpu) |
54d5d424 | 448 | set_pending_irq(irq, cpumask_of_cpu(new_cpu)); |
1da177e4 LT |
449 | } |
450 | ||
451 | static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold) | |
452 | { | |
453 | int i, j; | |
edc2cbf4 | 454 | |
394e3902 AM |
455 | for_each_online_cpu(i) { |
456 | for (j = 0; j < NR_IRQS; j++) { | |
1da177e4 LT |
457 | if (!irq_desc[j].action) |
458 | continue; | |
459 | /* Is it a significant load ? */ | |
36062448 | 460 | if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) < |
1da177e4 LT |
461 | useful_load_threshold) |
462 | continue; | |
463 | balance_irq(i, j); | |
464 | } | |
465 | } | |
466 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
36062448 | 467 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
1da177e4 LT |
468 | return; |
469 | } | |
470 | ||
471 | static void do_irq_balance(void) | |
472 | { | |
473 | int i, j; | |
474 | unsigned long max_cpu_irq = 0, min_cpu_irq = (~0); | |
475 | unsigned long move_this_load = 0; | |
476 | int max_loaded = 0, min_loaded = 0; | |
477 | int load; | |
478 | unsigned long useful_load_threshold = balanced_irq_interval + 10; | |
479 | int selected_irq; | |
480 | int tmp_loaded, first_attempt = 1; | |
481 | unsigned long tmp_cpu_irq; | |
482 | unsigned long imbalance = 0; | |
483 | cpumask_t allowed_mask, target_cpu_mask, tmp; | |
484 | ||
c8912599 | 485 | for_each_possible_cpu(i) { |
1da177e4 LT |
486 | int package_index; |
487 | CPU_IRQ(i) = 0; | |
488 | if (!cpu_online(i)) | |
489 | continue; | |
490 | package_index = CPU_TO_PACKAGEINDEX(i); | |
491 | for (j = 0; j < NR_IRQS; j++) { | |
492 | unsigned long value_now, delta; | |
950f4427 TG |
493 | /* Is this an active IRQ or balancing disabled ? */ |
494 | if (!irq_desc[j].action || irq_balancing_disabled(j)) | |
1da177e4 | 495 | continue; |
36062448 PC |
496 | if (package_index == i) |
497 | IRQ_DELTA(package_index, j) = 0; | |
1da177e4 LT |
498 | /* Determine the total count per processor per IRQ */ |
499 | value_now = (unsigned long) kstat_cpu(i).irqs[j]; | |
500 | ||
501 | /* Determine the activity per processor per IRQ */ | |
36062448 | 502 | delta = value_now - LAST_CPU_IRQ(i, j); |
1da177e4 LT |
503 | |
504 | /* Update last_cpu_irq[][] for the next time */ | |
36062448 | 505 | LAST_CPU_IRQ(i, j) = value_now; |
1da177e4 LT |
506 | |
507 | /* Ignore IRQs whose rate is less than the clock */ | |
508 | if (delta < useful_load_threshold) | |
509 | continue; | |
510 | /* update the load for the processor or package total */ | |
36062448 | 511 | IRQ_DELTA(package_index, j) += delta; |
1da177e4 LT |
512 | |
513 | /* Keep track of the higher numbered sibling as well */ | |
514 | if (i != package_index) | |
515 | CPU_IRQ(i) += delta; | |
516 | /* | |
517 | * We have sibling A and sibling B in the package | |
518 | * | |
519 | * cpu_irq[A] = load for cpu A + load for cpu B | |
520 | * cpu_irq[B] = load for cpu B | |
521 | */ | |
522 | CPU_IRQ(package_index) += delta; | |
523 | } | |
524 | } | |
525 | /* Find the least loaded processor package */ | |
394e3902 | 526 | for_each_online_cpu(i) { |
1da177e4 LT |
527 | if (i != CPU_TO_PACKAGEINDEX(i)) |
528 | continue; | |
529 | if (min_cpu_irq > CPU_IRQ(i)) { | |
530 | min_cpu_irq = CPU_IRQ(i); | |
531 | min_loaded = i; | |
532 | } | |
533 | } | |
534 | max_cpu_irq = ULONG_MAX; | |
535 | ||
536 | tryanothercpu: | |
36062448 PC |
537 | /* |
538 | * Look for heaviest loaded processor. | |
1da177e4 LT |
539 | * We may come back to get the next heaviest loaded processor. |
540 | * Skip processors with trivial loads. | |
541 | */ | |
542 | tmp_cpu_irq = 0; | |
543 | tmp_loaded = -1; | |
394e3902 | 544 | for_each_online_cpu(i) { |
1da177e4 LT |
545 | if (i != CPU_TO_PACKAGEINDEX(i)) |
546 | continue; | |
36062448 | 547 | if (max_cpu_irq <= CPU_IRQ(i)) |
1da177e4 LT |
548 | continue; |
549 | if (tmp_cpu_irq < CPU_IRQ(i)) { | |
550 | tmp_cpu_irq = CPU_IRQ(i); | |
551 | tmp_loaded = i; | |
552 | } | |
553 | } | |
554 | ||
555 | if (tmp_loaded == -1) { | |
36062448 PC |
556 | /* |
557 | * In the case of small number of heavy interrupt sources, | |
558 | * loading some of the cpus too much. We use Ingo's original | |
1da177e4 LT |
559 | * approach to rotate them around. |
560 | */ | |
561 | if (!first_attempt && imbalance >= useful_load_threshold) { | |
562 | rotate_irqs_among_cpus(useful_load_threshold); | |
563 | return; | |
564 | } | |
565 | goto not_worth_the_effort; | |
566 | } | |
36062448 | 567 | |
1da177e4 LT |
568 | first_attempt = 0; /* heaviest search */ |
569 | max_cpu_irq = tmp_cpu_irq; /* load */ | |
570 | max_loaded = tmp_loaded; /* processor */ | |
571 | imbalance = (max_cpu_irq - min_cpu_irq) / 2; | |
36062448 PC |
572 | |
573 | /* | |
574 | * if imbalance is less than approx 10% of max load, then | |
1da177e4 LT |
575 | * observe diminishing returns action. - quit |
576 | */ | |
edc2cbf4 | 577 | if (imbalance < (max_cpu_irq >> 3)) |
1da177e4 | 578 | goto not_worth_the_effort; |
1da177e4 LT |
579 | |
580 | tryanotherirq: | |
581 | /* if we select an IRQ to move that can't go where we want, then | |
582 | * see if there is another one to try. | |
583 | */ | |
584 | move_this_load = 0; | |
585 | selected_irq = -1; | |
586 | for (j = 0; j < NR_IRQS; j++) { | |
587 | /* Is this an active IRQ? */ | |
588 | if (!irq_desc[j].action) | |
589 | continue; | |
36062448 | 590 | if (imbalance <= IRQ_DELTA(max_loaded, j)) |
1da177e4 LT |
591 | continue; |
592 | /* Try to find the IRQ that is closest to the imbalance | |
593 | * without going over. | |
594 | */ | |
36062448 PC |
595 | if (move_this_load < IRQ_DELTA(max_loaded, j)) { |
596 | move_this_load = IRQ_DELTA(max_loaded, j); | |
1da177e4 LT |
597 | selected_irq = j; |
598 | } | |
599 | } | |
36062448 | 600 | if (selected_irq == -1) |
1da177e4 | 601 | goto tryanothercpu; |
1da177e4 LT |
602 | |
603 | imbalance = move_this_load; | |
36062448 | 604 | |
27b46d76 | 605 | /* For physical_balance case, we accumulated both load |
1da177e4 LT |
606 | * values in the one of the siblings cpu_irq[], |
607 | * to use the same code for physical and logical processors | |
36062448 | 608 | * as much as possible. |
1da177e4 LT |
609 | * |
610 | * NOTE: the cpu_irq[] array holds the sum of the load for | |
611 | * sibling A and sibling B in the slot for the lowest numbered | |
612 | * sibling (A), _AND_ the load for sibling B in the slot for | |
613 | * the higher numbered sibling. | |
614 | * | |
615 | * We seek the least loaded sibling by making the comparison | |
616 | * (A+B)/2 vs B | |
617 | */ | |
618 | load = CPU_IRQ(min_loaded) >> 1; | |
d5a7430d | 619 | for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) { |
1da177e4 LT |
620 | if (load > CPU_IRQ(j)) { |
621 | /* This won't change cpu_sibling_map[min_loaded] */ | |
622 | load = CPU_IRQ(j); | |
623 | min_loaded = j; | |
624 | } | |
625 | } | |
626 | ||
1b61b910 ZY |
627 | cpus_and(allowed_mask, |
628 | cpu_online_map, | |
629 | balance_irq_affinity[selected_irq]); | |
1da177e4 LT |
630 | target_cpu_mask = cpumask_of_cpu(min_loaded); |
631 | cpus_and(tmp, target_cpu_mask, allowed_mask); | |
632 | ||
633 | if (!cpus_empty(tmp)) { | |
1da177e4 | 634 | /* mark for change destination */ |
54d5d424 AR |
635 | set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded)); |
636 | ||
36062448 | 637 | /* Since we made a change, come back sooner to |
1da177e4 LT |
638 | * check for more variation. |
639 | */ | |
640 | balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL, | |
36062448 | 641 | balanced_irq_interval - BALANCED_IRQ_LESS_DELTA); |
1da177e4 LT |
642 | return; |
643 | } | |
644 | goto tryanotherirq; | |
645 | ||
646 | not_worth_the_effort: | |
647 | /* | |
648 | * if we did not find an IRQ to move, then adjust the time interval | |
649 | * upward | |
650 | */ | |
651 | balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL, | |
36062448 | 652 | balanced_irq_interval + BALANCED_IRQ_MORE_DELTA); |
1da177e4 LT |
653 | return; |
654 | } | |
655 | ||
656 | static int balanced_irq(void *unused) | |
657 | { | |
658 | int i; | |
659 | unsigned long prev_balance_time = jiffies; | |
660 | long time_remaining = balanced_irq_interval; | |
661 | ||
1da177e4 LT |
662 | /* push everything to CPU 0 to give us a starting point. */ |
663 | for (i = 0 ; i < NR_IRQS ; i++) { | |
cd916d31 | 664 | irq_desc[i].pending_mask = cpumask_of_cpu(0); |
54d5d424 | 665 | set_pending_irq(i, cpumask_of_cpu(0)); |
1da177e4 LT |
666 | } |
667 | ||
83144186 | 668 | set_freezable(); |
1da177e4 | 669 | for ( ; ; ) { |
52e6e630 | 670 | time_remaining = schedule_timeout_interruptible(time_remaining); |
3e1d1d28 | 671 | try_to_freeze(); |
1da177e4 LT |
672 | if (time_after(jiffies, |
673 | prev_balance_time+balanced_irq_interval)) { | |
f3705136 | 674 | preempt_disable(); |
1da177e4 LT |
675 | do_irq_balance(); |
676 | prev_balance_time = jiffies; | |
677 | time_remaining = balanced_irq_interval; | |
f3705136 | 678 | preempt_enable(); |
1da177e4 LT |
679 | } |
680 | } | |
681 | return 0; | |
682 | } | |
683 | ||
684 | static int __init balanced_irq_init(void) | |
685 | { | |
686 | int i; | |
687 | struct cpuinfo_x86 *c; | |
688 | cpumask_t tmp; | |
689 | ||
690 | cpus_shift_right(tmp, cpu_online_map, 2); | |
36062448 | 691 | c = &boot_cpu_data; |
1da177e4 LT |
692 | /* When not overwritten by the command line ask subarchitecture. */ |
693 | if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH) | |
694 | irqbalance_disabled = NO_BALANCE_IRQ; | |
695 | if (irqbalance_disabled) | |
696 | return 0; | |
36062448 | 697 | |
1da177e4 LT |
698 | /* disable irqbalance completely if there is only one processor online */ |
699 | if (num_online_cpus() < 2) { | |
700 | irqbalance_disabled = 1; | |
701 | return 0; | |
702 | } | |
703 | /* | |
704 | * Enable physical balance only if more than 1 physical processor | |
705 | * is present | |
706 | */ | |
707 | if (smp_num_siblings > 1 && !cpus_empty(tmp)) | |
708 | physical_balance = 1; | |
709 | ||
394e3902 | 710 | for_each_online_cpu(i) { |
25556c16 CJ |
711 | irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); |
712 | irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL); | |
1da177e4 LT |
713 | if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) { |
714 | printk(KERN_ERR "balanced_irq_init: out of memory"); | |
715 | goto failed; | |
716 | } | |
1da177e4 | 717 | } |
36062448 | 718 | |
1da177e4 | 719 | printk(KERN_INFO "Starting balanced_irq\n"); |
f26d6a2b | 720 | if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd"))) |
1da177e4 | 721 | return 0; |
f26d6a2b | 722 | printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq"); |
1da177e4 | 723 | failed: |
c8912599 | 724 | for_each_possible_cpu(i) { |
4ae6673e | 725 | kfree(irq_cpu_data[i].irq_delta); |
394e3902 | 726 | irq_cpu_data[i].irq_delta = NULL; |
4ae6673e | 727 | kfree(irq_cpu_data[i].last_irq); |
394e3902 | 728 | irq_cpu_data[i].last_irq = NULL; |
1da177e4 LT |
729 | } |
730 | return 0; | |
731 | } | |
732 | ||
c2481cc4 | 733 | int __devinit irqbalance_disable(char *str) |
1da177e4 LT |
734 | { |
735 | irqbalance_disabled = 1; | |
9b41046c | 736 | return 1; |
1da177e4 LT |
737 | } |
738 | ||
739 | __setup("noirqbalance", irqbalance_disable); | |
740 | ||
1da177e4 | 741 | late_initcall(balanced_irq_init); |
1da177e4 | 742 | #endif /* CONFIG_IRQBALANCE */ |
54d5d424 | 743 | #endif /* CONFIG_SMP */ |
1da177e4 LT |
744 | |
745 | #ifndef CONFIG_SMP | |
75604d7f | 746 | void send_IPI_self(int vector) |
1da177e4 LT |
747 | { |
748 | unsigned int cfg; | |
749 | ||
750 | /* | |
751 | * Wait for idle. | |
752 | */ | |
753 | apic_wait_icr_idle(); | |
754 | cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL; | |
755 | /* | |
756 | * Send the IPI. The write to APIC_ICR fires this off. | |
757 | */ | |
758 | apic_write_around(APIC_ICR, cfg); | |
759 | } | |
760 | #endif /* !CONFIG_SMP */ | |
761 | ||
762 | ||
763 | /* | |
764 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to | |
765 | * specific CPU-side IRQs. | |
766 | */ | |
767 | ||
768 | #define MAX_PIRQS 8 | |
769 | static int pirq_entries [MAX_PIRQS]; | |
770 | static int pirqs_enabled; | |
771 | int skip_ioapic_setup; | |
772 | ||
1da177e4 LT |
773 | static int __init ioapic_pirq_setup(char *str) |
774 | { | |
775 | int i, max; | |
776 | int ints[MAX_PIRQS+1]; | |
777 | ||
778 | get_options(str, ARRAY_SIZE(ints), ints); | |
779 | ||
780 | for (i = 0; i < MAX_PIRQS; i++) | |
781 | pirq_entries[i] = -1; | |
782 | ||
783 | pirqs_enabled = 1; | |
784 | apic_printk(APIC_VERBOSE, KERN_INFO | |
785 | "PIRQ redirection, working around broken MP-BIOS.\n"); | |
786 | max = MAX_PIRQS; | |
787 | if (ints[0] < MAX_PIRQS) | |
788 | max = ints[0]; | |
789 | ||
790 | for (i = 0; i < max; i++) { | |
791 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
792 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); | |
793 | /* | |
794 | * PIRQs are mapped upside down, usually. | |
795 | */ | |
796 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; | |
797 | } | |
798 | return 1; | |
799 | } | |
800 | ||
801 | __setup("pirq=", ioapic_pirq_setup); | |
802 | ||
803 | /* | |
804 | * Find the IRQ entry number of a certain pin. | |
805 | */ | |
806 | static int find_irq_entry(int apic, int pin, int type) | |
807 | { | |
808 | int i; | |
809 | ||
810 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
811 | if (mp_irqs[i].mp_irqtype == type && |
812 | (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid || | |
813 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) && | |
814 | mp_irqs[i].mp_dstirq == pin) | |
1da177e4 LT |
815 | return i; |
816 | ||
817 | return -1; | |
818 | } | |
819 | ||
820 | /* | |
821 | * Find the pin to which IRQ[irq] (ISA) is connected | |
822 | */ | |
fcfd636a | 823 | static int __init find_isa_irq_pin(int irq, int type) |
1da177e4 LT |
824 | { |
825 | int i; | |
826 | ||
827 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 828 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 | 829 | |
d27e2b8e | 830 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
831 | (mp_irqs[i].mp_irqtype == type) && |
832 | (mp_irqs[i].mp_srcbusirq == irq)) | |
1da177e4 | 833 | |
2fddb6e2 | 834 | return mp_irqs[i].mp_dstirq; |
1da177e4 LT |
835 | } |
836 | return -1; | |
837 | } | |
838 | ||
fcfd636a EB |
839 | static int __init find_isa_irq_apic(int irq, int type) |
840 | { | |
841 | int i; | |
842 | ||
843 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 844 | int lbus = mp_irqs[i].mp_srcbus; |
fcfd636a | 845 | |
73b2961b | 846 | if (test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 AS |
847 | (mp_irqs[i].mp_irqtype == type) && |
848 | (mp_irqs[i].mp_srcbusirq == irq)) | |
fcfd636a EB |
849 | break; |
850 | } | |
851 | if (i < mp_irq_entries) { | |
852 | int apic; | |
36062448 | 853 | for (apic = 0; apic < nr_ioapics; apic++) { |
2fddb6e2 | 854 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic) |
fcfd636a EB |
855 | return apic; |
856 | } | |
857 | } | |
858 | ||
859 | return -1; | |
860 | } | |
861 | ||
1da177e4 LT |
862 | /* |
863 | * Find a specific PCI IRQ entry. | |
864 | * Not an __init, possibly needed by modules | |
865 | */ | |
866 | static int pin_2_irq(int idx, int apic, int pin); | |
867 | ||
868 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) | |
869 | { | |
870 | int apic, i, best_guess = -1; | |
871 | ||
872 | apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, " | |
873 | "slot:%d, pin:%d.\n", bus, slot, pin); | |
ce6444d3 | 874 | if (test_bit(bus, mp_bus_not_pci)) { |
1da177e4 LT |
875 | printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
876 | return -1; | |
877 | } | |
878 | for (i = 0; i < mp_irq_entries; i++) { | |
2fddb6e2 | 879 | int lbus = mp_irqs[i].mp_srcbus; |
1da177e4 LT |
880 | |
881 | for (apic = 0; apic < nr_ioapics; apic++) | |
2fddb6e2 AS |
882 | if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic || |
883 | mp_irqs[i].mp_dstapic == MP_APIC_ALL) | |
1da177e4 LT |
884 | break; |
885 | ||
47cab822 | 886 | if (!test_bit(lbus, mp_bus_not_pci) && |
2fddb6e2 | 887 | !mp_irqs[i].mp_irqtype && |
1da177e4 | 888 | (bus == lbus) && |
2fddb6e2 | 889 | (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) { |
3de352bb | 890 | int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq); |
1da177e4 LT |
891 | |
892 | if (!(apic || IO_APIC_IRQ(irq))) | |
893 | continue; | |
894 | ||
2fddb6e2 | 895 | if (pin == (mp_irqs[i].mp_srcbusirq & 3)) |
1da177e4 LT |
896 | return irq; |
897 | /* | |
898 | * Use the first all-but-pin matching entry as a | |
899 | * best-guess fuzzy result for broken mptables. | |
900 | */ | |
901 | if (best_guess < 0) | |
902 | best_guess = irq; | |
903 | } | |
904 | } | |
905 | return best_guess; | |
906 | } | |
129f6946 | 907 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
1da177e4 LT |
908 | |
909 | /* | |
36062448 | 910 | * This function currently is only a helper for the i386 smp boot process where |
1da177e4 LT |
911 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
912 | * so mask in all cases should simply be TARGET_CPUS | |
913 | */ | |
54d5d424 | 914 | #ifdef CONFIG_SMP |
1da177e4 LT |
915 | void __init setup_ioapic_dest(void) |
916 | { | |
917 | int pin, ioapic, irq, irq_entry; | |
918 | ||
919 | if (skip_ioapic_setup == 1) | |
920 | return; | |
921 | ||
922 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) { | |
923 | for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) { | |
924 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); | |
925 | if (irq_entry == -1) | |
926 | continue; | |
927 | irq = pin_2_irq(irq_entry, ioapic, pin); | |
928 | set_ioapic_affinity_irq(irq, TARGET_CPUS); | |
929 | } | |
930 | ||
931 | } | |
932 | } | |
54d5d424 | 933 | #endif |
1da177e4 | 934 | |
c0a282c2 | 935 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
1da177e4 LT |
936 | /* |
937 | * EISA Edge/Level control register, ELCR | |
938 | */ | |
939 | static int EISA_ELCR(unsigned int irq) | |
940 | { | |
941 | if (irq < 16) { | |
942 | unsigned int port = 0x4d0 + (irq >> 3); | |
943 | return (inb(port) >> (irq & 7)) & 1; | |
944 | } | |
945 | apic_printk(APIC_VERBOSE, KERN_INFO | |
946 | "Broken MPtable reports ISA irq %d\n", irq); | |
947 | return 0; | |
948 | } | |
c0a282c2 | 949 | #endif |
1da177e4 | 950 | |
6728801d AS |
951 | /* ISA interrupts are always polarity zero edge triggered, |
952 | * when listed as conforming in the MP table. */ | |
953 | ||
954 | #define default_ISA_trigger(idx) (0) | |
955 | #define default_ISA_polarity(idx) (0) | |
956 | ||
1da177e4 LT |
957 | /* EISA interrupts are always polarity zero and can be edge or level |
958 | * trigger depending on the ELCR value. If an interrupt is listed as | |
959 | * EISA conforming in the MP table, that means its trigger type must | |
960 | * be read in from the ELCR */ | |
961 | ||
2fddb6e2 | 962 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq)) |
6728801d | 963 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 LT |
964 | |
965 | /* PCI interrupts are always polarity one level triggered, | |
966 | * when listed as conforming in the MP table. */ | |
967 | ||
968 | #define default_PCI_trigger(idx) (1) | |
969 | #define default_PCI_polarity(idx) (1) | |
970 | ||
971 | /* MCA interrupts are always polarity zero level triggered, | |
972 | * when listed as conforming in the MP table. */ | |
973 | ||
974 | #define default_MCA_trigger(idx) (1) | |
6728801d | 975 | #define default_MCA_polarity(idx) default_ISA_polarity(idx) |
1da177e4 | 976 | |
61fd47e0 | 977 | static int MPBIOS_polarity(int idx) |
1da177e4 | 978 | { |
2fddb6e2 | 979 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
980 | int polarity; |
981 | ||
982 | /* | |
983 | * Determine IRQ line polarity (high active or low active): | |
984 | */ | |
3de352bb | 985 | switch (mp_irqs[idx].mp_irqflag & 3) { |
36062448 | 986 | case 0: /* conforms, ie. bus-type dependent polarity */ |
1da177e4 | 987 | { |
36062448 PC |
988 | polarity = test_bit(bus, mp_bus_not_pci)? |
989 | default_ISA_polarity(idx): | |
990 | default_PCI_polarity(idx); | |
991 | break; | |
992 | } | |
993 | case 1: /* high active */ | |
994 | { | |
995 | polarity = 0; | |
996 | break; | |
997 | } | |
998 | case 2: /* reserved */ | |
999 | { | |
1000 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1001 | polarity = 1; | |
1002 | break; | |
1003 | } | |
1004 | case 3: /* low active */ | |
1005 | { | |
1006 | polarity = 1; | |
1007 | break; | |
1008 | } | |
1009 | default: /* invalid */ | |
1010 | { | |
1011 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1012 | polarity = 1; | |
1013 | break; | |
1014 | } | |
1da177e4 LT |
1015 | } |
1016 | return polarity; | |
1017 | } | |
1018 | ||
1019 | static int MPBIOS_trigger(int idx) | |
1020 | { | |
2fddb6e2 | 1021 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1022 | int trigger; |
1023 | ||
1024 | /* | |
1025 | * Determine IRQ trigger mode (edge or level sensitive): | |
1026 | */ | |
3de352bb | 1027 | switch ((mp_irqs[idx].mp_irqflag>>2) & 3) { |
36062448 | 1028 | case 0: /* conforms, ie. bus-type dependent */ |
1da177e4 | 1029 | { |
36062448 PC |
1030 | trigger = test_bit(bus, mp_bus_not_pci)? |
1031 | default_ISA_trigger(idx): | |
1032 | default_PCI_trigger(idx); | |
c0a282c2 | 1033 | #if defined(CONFIG_EISA) || defined(CONFIG_MCA) |
36062448 PC |
1034 | switch (mp_bus_id_to_type[bus]) { |
1035 | case MP_BUS_ISA: /* ISA pin */ | |
1036 | { | |
1037 | /* set before the switch */ | |
1da177e4 LT |
1038 | break; |
1039 | } | |
36062448 | 1040 | case MP_BUS_EISA: /* EISA pin */ |
1da177e4 | 1041 | { |
36062448 | 1042 | trigger = default_EISA_trigger(idx); |
1da177e4 LT |
1043 | break; |
1044 | } | |
36062448 | 1045 | case MP_BUS_PCI: /* PCI pin */ |
1da177e4 | 1046 | { |
36062448 | 1047 | /* set before the switch */ |
1da177e4 LT |
1048 | break; |
1049 | } | |
36062448 | 1050 | case MP_BUS_MCA: /* MCA pin */ |
1da177e4 | 1051 | { |
36062448 | 1052 | trigger = default_MCA_trigger(idx); |
1da177e4 LT |
1053 | break; |
1054 | } | |
36062448 | 1055 | default: |
1da177e4 LT |
1056 | { |
1057 | printk(KERN_WARNING "broken BIOS!!\n"); | |
36062448 | 1058 | trigger = 1; |
1da177e4 LT |
1059 | break; |
1060 | } | |
1061 | } | |
36062448 PC |
1062 | #endif |
1063 | break; | |
1064 | } | |
1065 | case 1: /* edge */ | |
1066 | { | |
1067 | trigger = 0; | |
1068 | break; | |
1069 | } | |
1070 | case 2: /* reserved */ | |
1071 | { | |
1072 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1073 | trigger = 1; | |
1074 | break; | |
1075 | } | |
1076 | case 3: /* level */ | |
1077 | { | |
1078 | trigger = 1; | |
1079 | break; | |
1080 | } | |
1081 | default: /* invalid */ | |
1082 | { | |
1083 | printk(KERN_WARNING "broken BIOS!!\n"); | |
1084 | trigger = 0; | |
1085 | break; | |
1086 | } | |
1087 | } | |
1da177e4 LT |
1088 | return trigger; |
1089 | } | |
1090 | ||
1091 | static inline int irq_polarity(int idx) | |
1092 | { | |
1093 | return MPBIOS_polarity(idx); | |
1094 | } | |
1095 | ||
1096 | static inline int irq_trigger(int idx) | |
1097 | { | |
1098 | return MPBIOS_trigger(idx); | |
1099 | } | |
1100 | ||
1101 | static int pin_2_irq(int idx, int apic, int pin) | |
1102 | { | |
1103 | int irq, i; | |
2fddb6e2 | 1104 | int bus = mp_irqs[idx].mp_srcbus; |
1da177e4 LT |
1105 | |
1106 | /* | |
1107 | * Debugging check, we are in big trouble if this message pops up! | |
1108 | */ | |
2fddb6e2 | 1109 | if (mp_irqs[idx].mp_dstirq != pin) |
1da177e4 LT |
1110 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); |
1111 | ||
643befed | 1112 | if (test_bit(bus, mp_bus_not_pci)) |
2fddb6e2 | 1113 | irq = mp_irqs[idx].mp_srcbusirq; |
643befed AS |
1114 | else { |
1115 | /* | |
1116 | * PCI IRQs are mapped in order | |
1117 | */ | |
1118 | i = irq = 0; | |
1119 | while (i < apic) | |
1120 | irq += nr_ioapic_registers[i++]; | |
1121 | irq += pin; | |
1da177e4 | 1122 | |
643befed AS |
1123 | /* |
1124 | * For MPS mode, so far only needed by ES7000 platform | |
1125 | */ | |
1126 | if (ioapic_renumber_irq) | |
1127 | irq = ioapic_renumber_irq(apic, irq); | |
1da177e4 LT |
1128 | } |
1129 | ||
1130 | /* | |
1131 | * PCI IRQ command line redirection. Yes, limits are hardcoded. | |
1132 | */ | |
1133 | if ((pin >= 16) && (pin <= 23)) { | |
1134 | if (pirq_entries[pin-16] != -1) { | |
1135 | if (!pirq_entries[pin-16]) { | |
1136 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1137 | "disabling PIRQ%d\n", pin-16); | |
1138 | } else { | |
1139 | irq = pirq_entries[pin-16]; | |
1140 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1141 | "using PIRQ%d -> IRQ %d\n", | |
1142 | pin-16, irq); | |
1143 | } | |
1144 | } | |
1145 | } | |
1146 | return irq; | |
1147 | } | |
1148 | ||
1149 | static inline int IO_APIC_irq_trigger(int irq) | |
1150 | { | |
1151 | int apic, idx, pin; | |
1152 | ||
1153 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1154 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
36062448 PC |
1155 | idx = find_irq_entry(apic, pin, mp_INT); |
1156 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) | |
1da177e4 LT |
1157 | return irq_trigger(idx); |
1158 | } | |
1159 | } | |
1160 | /* | |
1161 | * nonexistent IRQs are edge default | |
1162 | */ | |
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */ | |
7e95b593 | 1167 | static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 }; |
1da177e4 | 1168 | |
ace80ab7 | 1169 | static int __assign_irq_vector(int irq) |
1da177e4 | 1170 | { |
36062448 | 1171 | static int current_vector = FIRST_DEVICE_VECTOR, current_offset; |
dbeb2be2 | 1172 | int vector, offset; |
1da177e4 | 1173 | |
ace80ab7 | 1174 | BUG_ON((unsigned)irq >= NR_IRQ_VECTORS); |
0a1ad60d | 1175 | |
b940d22d EB |
1176 | if (irq_vector[irq] > 0) |
1177 | return irq_vector[irq]; | |
ace80ab7 | 1178 | |
0a1ad60d | 1179 | vector = current_vector; |
8339f000 EB |
1180 | offset = current_offset; |
1181 | next: | |
1182 | vector += 8; | |
305b92a2 | 1183 | if (vector >= first_system_vector) { |
8339f000 EB |
1184 | offset = (offset + 1) % 8; |
1185 | vector = FIRST_DEVICE_VECTOR + offset; | |
1186 | } | |
1187 | if (vector == current_vector) | |
1188 | return -ENOSPC; | |
dbeb2be2 | 1189 | if (test_and_set_bit(vector, used_vectors)) |
8339f000 | 1190 | goto next; |
8339f000 EB |
1191 | |
1192 | current_vector = vector; | |
1193 | current_offset = offset; | |
b940d22d | 1194 | irq_vector[irq] = vector; |
ace80ab7 EB |
1195 | |
1196 | return vector; | |
1197 | } | |
0a1ad60d | 1198 | |
ace80ab7 EB |
1199 | static int assign_irq_vector(int irq) |
1200 | { | |
1201 | unsigned long flags; | |
1202 | int vector; | |
1203 | ||
1204 | spin_lock_irqsave(&vector_lock, flags); | |
1205 | vector = __assign_irq_vector(irq); | |
26a3c49c | 1206 | spin_unlock_irqrestore(&vector_lock, flags); |
1da177e4 | 1207 | |
0a1ad60d | 1208 | return vector; |
1da177e4 | 1209 | } |
3fde6900 GC |
1210 | |
1211 | void setup_vector_irq(int cpu) | |
1212 | { | |
1213 | } | |
1214 | ||
f5b9ed7a | 1215 | static struct irq_chip ioapic_chip; |
1da177e4 LT |
1216 | |
1217 | #define IOAPIC_AUTO -1 | |
1218 | #define IOAPIC_EDGE 0 | |
1219 | #define IOAPIC_LEVEL 1 | |
1220 | ||
d1bef4ed | 1221 | static void ioapic_register_intr(int irq, int vector, unsigned long trigger) |
1da177e4 | 1222 | { |
6ebcc00e | 1223 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
cc75b92d TG |
1224 | trigger == IOAPIC_LEVEL) { |
1225 | irq_desc[irq].status |= IRQ_LEVEL; | |
a460e745 IM |
1226 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1227 | handle_fasteoi_irq, "fasteoi"); | |
cc75b92d TG |
1228 | } else { |
1229 | irq_desc[irq].status &= ~IRQ_LEVEL; | |
a460e745 IM |
1230 | set_irq_chip_and_handler_name(irq, &ioapic_chip, |
1231 | handle_edge_irq, "edge"); | |
cc75b92d | 1232 | } |
ace80ab7 | 1233 | set_intr_gate(vector, interrupt[irq]); |
1da177e4 LT |
1234 | } |
1235 | ||
1236 | static void __init setup_IO_APIC_irqs(void) | |
1237 | { | |
1238 | struct IO_APIC_route_entry entry; | |
1239 | int apic, pin, idx, irq, first_notcon = 1, vector; | |
1da177e4 LT |
1240 | |
1241 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); | |
1242 | ||
1243 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1244 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { | |
1245 | ||
1246 | /* | |
1247 | * add it to the IO-APIC irq-routing table: | |
1248 | */ | |
36062448 | 1249 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1250 | |
1251 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1252 | entry.dest_mode = INT_DEST_MODE; | |
1253 | entry.mask = 0; /* enable IRQ */ | |
36062448 | 1254 | entry.dest.logical.logical_dest = |
1da177e4 LT |
1255 | cpu_mask_to_apicid(TARGET_CPUS); |
1256 | ||
36062448 | 1257 | idx = find_irq_entry(apic, pin, mp_INT); |
1da177e4 LT |
1258 | if (idx == -1) { |
1259 | if (first_notcon) { | |
1260 | apic_printk(APIC_VERBOSE, KERN_DEBUG | |
1261 | " IO-APIC (apicid-pin) %d-%d", | |
ec2cd0a2 | 1262 | mp_ioapics[apic].mp_apicid, |
1da177e4 LT |
1263 | pin); |
1264 | first_notcon = 0; | |
1265 | } else | |
1266 | apic_printk(APIC_VERBOSE, ", %d-%d", | |
ec2cd0a2 | 1267 | mp_ioapics[apic].mp_apicid, pin); |
1da177e4 LT |
1268 | continue; |
1269 | } | |
1270 | ||
20d225b9 YL |
1271 | if (!first_notcon) { |
1272 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1273 | first_notcon = 1; | |
1274 | } | |
1275 | ||
1da177e4 LT |
1276 | entry.trigger = irq_trigger(idx); |
1277 | entry.polarity = irq_polarity(idx); | |
1278 | ||
1279 | if (irq_trigger(idx)) { | |
1280 | entry.trigger = 1; | |
1281 | entry.mask = 1; | |
1282 | } | |
1283 | ||
1284 | irq = pin_2_irq(idx, apic, pin); | |
1285 | /* | |
1286 | * skip adding the timer int on secondary nodes, which causes | |
1287 | * a small but painful rift in the time-space continuum | |
1288 | */ | |
1289 | if (multi_timer_check(apic, irq)) | |
1290 | continue; | |
1291 | else | |
1292 | add_pin_to_irq(irq, apic, pin); | |
1293 | ||
1294 | if (!apic && !IO_APIC_IRQ(irq)) | |
1295 | continue; | |
1296 | ||
1297 | if (IO_APIC_IRQ(irq)) { | |
1298 | vector = assign_irq_vector(irq); | |
1299 | entry.vector = vector; | |
1300 | ioapic_register_intr(irq, vector, IOAPIC_AUTO); | |
36062448 | 1301 | |
1da177e4 LT |
1302 | if (!apic && (irq < 16)) |
1303 | disable_8259A_irq(irq); | |
1304 | } | |
a2249cba | 1305 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1306 | } |
1307 | } | |
1308 | ||
1309 | if (!first_notcon) | |
1310 | apic_printk(APIC_VERBOSE, " not connected.\n"); | |
1311 | } | |
1312 | ||
1313 | /* | |
f7633ce5 | 1314 | * Set up the timer pin, possibly with the 8259A-master behind. |
1da177e4 | 1315 | */ |
f7633ce5 MR |
1316 | static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin, |
1317 | int vector) | |
1da177e4 LT |
1318 | { |
1319 | struct IO_APIC_route_entry entry; | |
1da177e4 | 1320 | |
36062448 | 1321 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
1322 | |
1323 | /* | |
1324 | * We use logical delivery to get the timer IRQ | |
1325 | * to the first CPU. | |
1326 | */ | |
1327 | entry.dest_mode = INT_DEST_MODE; | |
03be7505 | 1328 | entry.mask = 1; /* mask IRQ now */ |
1da177e4 LT |
1329 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); |
1330 | entry.delivery_mode = INT_DELIVERY_MODE; | |
1331 | entry.polarity = 0; | |
1332 | entry.trigger = 0; | |
1333 | entry.vector = vector; | |
1334 | ||
1335 | /* | |
1336 | * The timer IRQ doesn't have to know that behind the | |
f7633ce5 | 1337 | * scene we may have a 8259A-master in AEOI mode ... |
1da177e4 | 1338 | */ |
f0825262 | 1339 | ioapic_register_intr(0, vector, IOAPIC_EDGE); |
1da177e4 LT |
1340 | |
1341 | /* | |
1342 | * Add it to the IO-APIC irq-routing table: | |
1343 | */ | |
cf4c6a2f | 1344 | ioapic_write_entry(apic, pin, entry); |
1da177e4 LT |
1345 | } |
1346 | ||
1da177e4 LT |
1347 | void __init print_IO_APIC(void) |
1348 | { | |
1349 | int apic, i; | |
1350 | union IO_APIC_reg_00 reg_00; | |
1351 | union IO_APIC_reg_01 reg_01; | |
1352 | union IO_APIC_reg_02 reg_02; | |
1353 | union IO_APIC_reg_03 reg_03; | |
1354 | unsigned long flags; | |
1355 | ||
1356 | if (apic_verbosity == APIC_QUIET) | |
1357 | return; | |
1358 | ||
36062448 | 1359 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
1da177e4 LT |
1360 | for (i = 0; i < nr_ioapics; i++) |
1361 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", | |
ec2cd0a2 | 1362 | mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]); |
1da177e4 LT |
1363 | |
1364 | /* | |
1365 | * We are a bit conservative about what we expect. We have to | |
1366 | * know about every hardware change ASAP. | |
1367 | */ | |
1368 | printk(KERN_INFO "testing the IO APIC.......................\n"); | |
1369 | ||
1370 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1371 | ||
1372 | spin_lock_irqsave(&ioapic_lock, flags); | |
1373 | reg_00.raw = io_apic_read(apic, 0); | |
1374 | reg_01.raw = io_apic_read(apic, 1); | |
1375 | if (reg_01.bits.version >= 0x10) | |
1376 | reg_02.raw = io_apic_read(apic, 2); | |
1377 | if (reg_01.bits.version >= 0x20) | |
1378 | reg_03.raw = io_apic_read(apic, 3); | |
1379 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1380 | ||
ec2cd0a2 | 1381 | printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1382 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1383 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | |
1384 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); | |
1385 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); | |
1da177e4 LT |
1386 | |
1387 | printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw); | |
1388 | printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries); | |
1da177e4 LT |
1389 | |
1390 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); | |
1391 | printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version); | |
1da177e4 LT |
1392 | |
1393 | /* | |
1394 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, | |
1395 | * but the value of reg_02 is read as the previous read register | |
1396 | * value, so ignore it if reg_02 == reg_01. | |
1397 | */ | |
1398 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { | |
1399 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); | |
1400 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); | |
1da177e4 LT |
1401 | } |
1402 | ||
1403 | /* | |
1404 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 | |
1405 | * or reg_03, but the value of reg_0[23] is read as the previous read | |
1406 | * register value, so ignore it if reg_03 == reg_0[12]. | |
1407 | */ | |
1408 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && | |
1409 | reg_03.raw != reg_01.raw) { | |
1410 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); | |
1411 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); | |
1da177e4 LT |
1412 | } |
1413 | ||
1414 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); | |
1415 | ||
1416 | printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" | |
1417 | " Stat Dest Deli Vect: \n"); | |
1418 | ||
1419 | for (i = 0; i <= reg_01.bits.entries; i++) { | |
1420 | struct IO_APIC_route_entry entry; | |
1421 | ||
cf4c6a2f | 1422 | entry = ioapic_read_entry(apic, i); |
1da177e4 LT |
1423 | |
1424 | printk(KERN_DEBUG " %02x %03X %02X ", | |
1425 | i, | |
1426 | entry.dest.logical.logical_dest, | |
1427 | entry.dest.physical.physical_dest | |
1428 | ); | |
1429 | ||
1430 | printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", | |
1431 | entry.mask, | |
1432 | entry.trigger, | |
1433 | entry.irr, | |
1434 | entry.polarity, | |
1435 | entry.delivery_status, | |
1436 | entry.dest_mode, | |
1437 | entry.delivery_mode, | |
1438 | entry.vector | |
1439 | ); | |
1440 | } | |
1441 | } | |
1da177e4 LT |
1442 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
1443 | for (i = 0; i < NR_IRQS; i++) { | |
1444 | struct irq_pin_list *entry = irq_2_pin + i; | |
1445 | if (entry->pin < 0) | |
1446 | continue; | |
ace80ab7 | 1447 | printk(KERN_DEBUG "IRQ%d ", i); |
1da177e4 LT |
1448 | for (;;) { |
1449 | printk("-> %d:%d", entry->apic, entry->pin); | |
1450 | if (!entry->next) | |
1451 | break; | |
1452 | entry = irq_2_pin + entry->next; | |
1453 | } | |
1454 | printk("\n"); | |
1455 | } | |
1456 | ||
1457 | printk(KERN_INFO ".................................... done.\n"); | |
1458 | ||
1459 | return; | |
1460 | } | |
1461 | ||
1462 | #if 0 | |
1463 | ||
36062448 | 1464 | static void print_APIC_bitfield(int base) |
1da177e4 LT |
1465 | { |
1466 | unsigned int v; | |
1467 | int i, j; | |
1468 | ||
1469 | if (apic_verbosity == APIC_QUIET) | |
1470 | return; | |
1471 | ||
1472 | printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); | |
1473 | for (i = 0; i < 8; i++) { | |
1474 | v = apic_read(base + i*0x10); | |
1475 | for (j = 0; j < 32; j++) { | |
1476 | if (v & (1<<j)) | |
1477 | printk("1"); | |
1478 | else | |
1479 | printk("0"); | |
1480 | } | |
1481 | printk("\n"); | |
1482 | } | |
1483 | } | |
1484 | ||
36062448 | 1485 | void /*__init*/ print_local_APIC(void *dummy) |
1da177e4 LT |
1486 | { |
1487 | unsigned int v, ver, maxlvt; | |
1488 | ||
1489 | if (apic_verbosity == APIC_QUIET) | |
1490 | return; | |
1491 | ||
1492 | printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", | |
1493 | smp_processor_id(), hard_smp_processor_id()); | |
66823114 | 1494 | v = apic_read(APIC_ID); |
05f2d12c JS |
1495 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, |
1496 | GET_APIC_ID(read_apic_id())); | |
1da177e4 LT |
1497 | v = apic_read(APIC_LVR); |
1498 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); | |
1499 | ver = GET_APIC_VERSION(v); | |
e05d723f | 1500 | maxlvt = lapic_get_maxlvt(); |
1da177e4 LT |
1501 | |
1502 | v = apic_read(APIC_TASKPRI); | |
1503 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); | |
1504 | ||
1505 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1506 | v = apic_read(APIC_ARBPRI); | |
1507 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, | |
1508 | v & APIC_ARBPRI_MASK); | |
1509 | v = apic_read(APIC_PROCPRI); | |
1510 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); | |
1511 | } | |
1512 | ||
1513 | v = apic_read(APIC_EOI); | |
1514 | printk(KERN_DEBUG "... APIC EOI: %08x\n", v); | |
1515 | v = apic_read(APIC_RRR); | |
1516 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); | |
1517 | v = apic_read(APIC_LDR); | |
1518 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); | |
1519 | v = apic_read(APIC_DFR); | |
1520 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); | |
1521 | v = apic_read(APIC_SPIV); | |
1522 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); | |
1523 | ||
1524 | printk(KERN_DEBUG "... APIC ISR field:\n"); | |
1525 | print_APIC_bitfield(APIC_ISR); | |
1526 | printk(KERN_DEBUG "... APIC TMR field:\n"); | |
1527 | print_APIC_bitfield(APIC_TMR); | |
1528 | printk(KERN_DEBUG "... APIC IRR field:\n"); | |
1529 | print_APIC_bitfield(APIC_IRR); | |
1530 | ||
1531 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ | |
1532 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
1533 | apic_write(APIC_ESR, 0); | |
1534 | v = apic_read(APIC_ESR); | |
1535 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); | |
1536 | } | |
1537 | ||
1538 | v = apic_read(APIC_ICR); | |
1539 | printk(KERN_DEBUG "... APIC ICR: %08x\n", v); | |
1540 | v = apic_read(APIC_ICR2); | |
1541 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); | |
1542 | ||
1543 | v = apic_read(APIC_LVTT); | |
1544 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); | |
1545 | ||
1546 | if (maxlvt > 3) { /* PC is LVT#4. */ | |
1547 | v = apic_read(APIC_LVTPC); | |
1548 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); | |
1549 | } | |
1550 | v = apic_read(APIC_LVT0); | |
1551 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); | |
1552 | v = apic_read(APIC_LVT1); | |
1553 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); | |
1554 | ||
1555 | if (maxlvt > 2) { /* ERR is LVT#3. */ | |
1556 | v = apic_read(APIC_LVTERR); | |
1557 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); | |
1558 | } | |
1559 | ||
1560 | v = apic_read(APIC_TMICT); | |
1561 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); | |
1562 | v = apic_read(APIC_TMCCT); | |
1563 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); | |
1564 | v = apic_read(APIC_TDCR); | |
1565 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); | |
1566 | printk("\n"); | |
1567 | } | |
1568 | ||
36062448 | 1569 | void print_all_local_APICs(void) |
1da177e4 LT |
1570 | { |
1571 | on_each_cpu(print_local_APIC, NULL, 1, 1); | |
1572 | } | |
1573 | ||
1574 | void /*__init*/ print_PIC(void) | |
1575 | { | |
1da177e4 LT |
1576 | unsigned int v; |
1577 | unsigned long flags; | |
1578 | ||
1579 | if (apic_verbosity == APIC_QUIET) | |
1580 | return; | |
1581 | ||
1582 | printk(KERN_DEBUG "\nprinting PIC contents\n"); | |
1583 | ||
1584 | spin_lock_irqsave(&i8259A_lock, flags); | |
1585 | ||
1586 | v = inb(0xa1) << 8 | inb(0x21); | |
1587 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); | |
1588 | ||
1589 | v = inb(0xa0) << 8 | inb(0x20); | |
1590 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); | |
1591 | ||
36062448 PC |
1592 | outb(0x0b, 0xa0); |
1593 | outb(0x0b, 0x20); | |
1da177e4 | 1594 | v = inb(0xa0) << 8 | inb(0x20); |
36062448 PC |
1595 | outb(0x0a, 0xa0); |
1596 | outb(0x0a, 0x20); | |
1da177e4 LT |
1597 | |
1598 | spin_unlock_irqrestore(&i8259A_lock, flags); | |
1599 | ||
1600 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); | |
1601 | ||
1602 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
1603 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); | |
1604 | } | |
1605 | ||
1606 | #endif /* 0 */ | |
1607 | ||
1608 | static void __init enable_IO_APIC(void) | |
1609 | { | |
1610 | union IO_APIC_reg_01 reg_01; | |
fcfd636a EB |
1611 | int i8259_apic, i8259_pin; |
1612 | int i, apic; | |
1da177e4 LT |
1613 | unsigned long flags; |
1614 | ||
1615 | for (i = 0; i < PIN_MAP_SIZE; i++) { | |
1616 | irq_2_pin[i].pin = -1; | |
1617 | irq_2_pin[i].next = 0; | |
1618 | } | |
1619 | if (!pirqs_enabled) | |
1620 | for (i = 0; i < MAX_PIRQS; i++) | |
1621 | pirq_entries[i] = -1; | |
1622 | ||
1623 | /* | |
1624 | * The number of IO-APIC IRQ registers (== #pins): | |
1625 | */ | |
fcfd636a | 1626 | for (apic = 0; apic < nr_ioapics; apic++) { |
1da177e4 | 1627 | spin_lock_irqsave(&ioapic_lock, flags); |
fcfd636a | 1628 | reg_01.raw = io_apic_read(apic, 1); |
1da177e4 | 1629 | spin_unlock_irqrestore(&ioapic_lock, flags); |
fcfd636a EB |
1630 | nr_ioapic_registers[apic] = reg_01.bits.entries+1; |
1631 | } | |
36062448 | 1632 | for (apic = 0; apic < nr_ioapics; apic++) { |
fcfd636a EB |
1633 | int pin; |
1634 | /* See if any of the pins is in ExtINT mode */ | |
1008fddc | 1635 | for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { |
fcfd636a | 1636 | struct IO_APIC_route_entry entry; |
cf4c6a2f | 1637 | entry = ioapic_read_entry(apic, pin); |
fcfd636a EB |
1638 | |
1639 | ||
1640 | /* If the interrupt line is enabled and in ExtInt mode | |
1641 | * I have found the pin where the i8259 is connected. | |
1642 | */ | |
1643 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { | |
1644 | ioapic_i8259.apic = apic; | |
1645 | ioapic_i8259.pin = pin; | |
1646 | goto found_i8259; | |
1647 | } | |
1648 | } | |
1649 | } | |
1650 | found_i8259: | |
1651 | /* Look to see what if the MP table has reported the ExtINT */ | |
1652 | /* If we could not find the appropriate pin by looking at the ioapic | |
1653 | * the i8259 probably is not connected the ioapic but give the | |
1654 | * mptable a chance anyway. | |
1655 | */ | |
1656 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); | |
1657 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); | |
1658 | /* Trust the MP table if nothing is setup in the hardware */ | |
1659 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { | |
1660 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); | |
1661 | ioapic_i8259.pin = i8259_pin; | |
1662 | ioapic_i8259.apic = i8259_apic; | |
1663 | } | |
1664 | /* Complain if the MP table and the hardware disagree */ | |
1665 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && | |
1666 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) | |
1667 | { | |
1668 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); | |
1da177e4 LT |
1669 | } |
1670 | ||
1671 | /* | |
1672 | * Do not trust the IO-APIC being empty at bootup | |
1673 | */ | |
1674 | clear_IO_APIC(); | |
1675 | } | |
1676 | ||
1677 | /* | |
1678 | * Not an __init, needed by the reboot code | |
1679 | */ | |
1680 | void disable_IO_APIC(void) | |
1681 | { | |
1682 | /* | |
1683 | * Clear the IO-APIC before rebooting: | |
1684 | */ | |
1685 | clear_IO_APIC(); | |
1686 | ||
650927ef | 1687 | /* |
0b968d23 | 1688 | * If the i8259 is routed through an IOAPIC |
650927ef | 1689 | * Put that IOAPIC in virtual wire mode |
0b968d23 | 1690 | * so legacy interrupts can be delivered. |
650927ef | 1691 | */ |
fcfd636a | 1692 | if (ioapic_i8259.pin != -1) { |
650927ef | 1693 | struct IO_APIC_route_entry entry; |
650927ef EB |
1694 | |
1695 | memset(&entry, 0, sizeof(entry)); | |
1696 | entry.mask = 0; /* Enabled */ | |
1697 | entry.trigger = 0; /* Edge */ | |
1698 | entry.irr = 0; | |
1699 | entry.polarity = 0; /* High */ | |
1700 | entry.delivery_status = 0; | |
1701 | entry.dest_mode = 0; /* Physical */ | |
fcfd636a | 1702 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
650927ef | 1703 | entry.vector = 0; |
76865c3f | 1704 | entry.dest.physical.physical_dest = |
05f2d12c | 1705 | GET_APIC_ID(read_apic_id()); |
650927ef EB |
1706 | |
1707 | /* | |
1708 | * Add it to the IO-APIC irq-routing table: | |
1709 | */ | |
cf4c6a2f | 1710 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
650927ef | 1711 | } |
fcfd636a | 1712 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
1da177e4 LT |
1713 | } |
1714 | ||
1715 | /* | |
1716 | * function to set the IO-APIC physical IDs based on the | |
1717 | * values stored in the MPC table. | |
1718 | * | |
1719 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 | |
1720 | */ | |
1721 | ||
1da177e4 LT |
1722 | static void __init setup_ioapic_ids_from_mpc(void) |
1723 | { | |
1724 | union IO_APIC_reg_00 reg_00; | |
1725 | physid_mask_t phys_id_present_map; | |
1726 | int apic; | |
1727 | int i; | |
1728 | unsigned char old_id; | |
1729 | unsigned long flags; | |
1730 | ||
d49c4288 YL |
1731 | #ifdef CONFIG_X86_NUMAQ |
1732 | if (found_numaq) | |
1733 | return; | |
1734 | #endif | |
1735 | ||
ca05fea6 NP |
1736 | /* |
1737 | * Don't check I/O APIC IDs for xAPIC systems. They have | |
1738 | * no meaning without the serial APIC bus. | |
1739 | */ | |
7c5c1e42 SL |
1740 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
1741 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) | |
ca05fea6 | 1742 | return; |
1da177e4 LT |
1743 | /* |
1744 | * This is broken; anything with a real cpu count has to | |
1745 | * circumvent this idiocy regardless. | |
1746 | */ | |
1747 | phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map); | |
1748 | ||
1749 | /* | |
1750 | * Set the IOAPIC ID to the value stored in the MPC table. | |
1751 | */ | |
1752 | for (apic = 0; apic < nr_ioapics; apic++) { | |
1753 | ||
1754 | /* Read the register 0 value */ | |
1755 | spin_lock_irqsave(&ioapic_lock, flags); | |
1756 | reg_00.raw = io_apic_read(apic, 0); | |
1757 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
36062448 | 1758 | |
ec2cd0a2 | 1759 | old_id = mp_ioapics[apic].mp_apicid; |
1da177e4 | 1760 | |
ec2cd0a2 | 1761 | if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) { |
1da177e4 | 1762 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
ec2cd0a2 | 1763 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1764 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
1765 | reg_00.bits.ID); | |
ec2cd0a2 | 1766 | mp_ioapics[apic].mp_apicid = reg_00.bits.ID; |
1da177e4 LT |
1767 | } |
1768 | ||
1da177e4 LT |
1769 | /* |
1770 | * Sanity check, is the ID really free? Every APIC in a | |
1771 | * system must have a unique ID or we get lots of nice | |
1772 | * 'stuck on smp_invalidate_needed IPI wait' messages. | |
1773 | */ | |
1774 | if (check_apicid_used(phys_id_present_map, | |
ec2cd0a2 | 1775 | mp_ioapics[apic].mp_apicid)) { |
1da177e4 | 1776 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
ec2cd0a2 | 1777 | apic, mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1778 | for (i = 0; i < get_physical_broadcast(); i++) |
1779 | if (!physid_isset(i, phys_id_present_map)) | |
1780 | break; | |
1781 | if (i >= get_physical_broadcast()) | |
1782 | panic("Max APIC ID exceeded!\n"); | |
1783 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", | |
1784 | i); | |
1785 | physid_set(i, phys_id_present_map); | |
ec2cd0a2 | 1786 | mp_ioapics[apic].mp_apicid = i; |
1da177e4 LT |
1787 | } else { |
1788 | physid_mask_t tmp; | |
ec2cd0a2 | 1789 | tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1790 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
1791 | "phys_id_present_map\n", | |
ec2cd0a2 | 1792 | mp_ioapics[apic].mp_apicid); |
1da177e4 LT |
1793 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
1794 | } | |
1795 | ||
1796 | ||
1797 | /* | |
1798 | * We need to adjust the IRQ routing table | |
1799 | * if the ID changed. | |
1800 | */ | |
ec2cd0a2 | 1801 | if (old_id != mp_ioapics[apic].mp_apicid) |
1da177e4 | 1802 | for (i = 0; i < mp_irq_entries; i++) |
2fddb6e2 AS |
1803 | if (mp_irqs[i].mp_dstapic == old_id) |
1804 | mp_irqs[i].mp_dstapic | |
ec2cd0a2 | 1805 | = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1806 | |
1807 | /* | |
1808 | * Read the right value from the MPC table and | |
1809 | * write it into the ID register. | |
36062448 | 1810 | */ |
1da177e4 LT |
1811 | apic_printk(APIC_VERBOSE, KERN_INFO |
1812 | "...changing IO-APIC physical APIC ID to %d ...", | |
ec2cd0a2 | 1813 | mp_ioapics[apic].mp_apicid); |
1da177e4 | 1814 | |
ec2cd0a2 | 1815 | reg_00.bits.ID = mp_ioapics[apic].mp_apicid; |
1da177e4 LT |
1816 | spin_lock_irqsave(&ioapic_lock, flags); |
1817 | io_apic_write(apic, 0, reg_00.raw); | |
1818 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1819 | ||
1820 | /* | |
1821 | * Sanity check | |
1822 | */ | |
1823 | spin_lock_irqsave(&ioapic_lock, flags); | |
1824 | reg_00.raw = io_apic_read(apic, 0); | |
1825 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
ec2cd0a2 | 1826 | if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid) |
1da177e4 LT |
1827 | printk("could not set ID!\n"); |
1828 | else | |
1829 | apic_printk(APIC_VERBOSE, " ok.\n"); | |
1830 | } | |
1831 | } | |
1da177e4 | 1832 | |
7ce0bcfd | 1833 | int no_timer_check __initdata; |
8542b200 ZA |
1834 | |
1835 | static int __init notimercheck(char *s) | |
1836 | { | |
1837 | no_timer_check = 1; | |
1838 | return 1; | |
1839 | } | |
1840 | __setup("no_timer_check", notimercheck); | |
1841 | ||
1da177e4 LT |
1842 | /* |
1843 | * There is a nasty bug in some older SMP boards, their mptable lies | |
1844 | * about the timer IRQ. We do the following to work around the situation: | |
1845 | * | |
1846 | * - timer IRQ defaults to IO-APIC IRQ | |
1847 | * - if this function detects that timer IRQs are defunct, then we fall | |
1848 | * back to ISA timer IRQs | |
1849 | */ | |
f0a7a5c9 | 1850 | static int __init timer_irq_works(void) |
1da177e4 LT |
1851 | { |
1852 | unsigned long t1 = jiffies; | |
4aae0702 | 1853 | unsigned long flags; |
1da177e4 | 1854 | |
8542b200 ZA |
1855 | if (no_timer_check) |
1856 | return 1; | |
1857 | ||
4aae0702 | 1858 | local_save_flags(flags); |
1da177e4 LT |
1859 | local_irq_enable(); |
1860 | /* Let ten ticks pass... */ | |
1861 | mdelay((10 * 1000) / HZ); | |
4aae0702 | 1862 | local_irq_restore(flags); |
1da177e4 LT |
1863 | |
1864 | /* | |
1865 | * Expect a few ticks at least, to be sure some possible | |
1866 | * glue logic does not lock up after one or two first | |
1867 | * ticks in a non-ExtINT mode. Also the local APIC | |
1868 | * might have cached one ExtINT interrupt. Finally, at | |
1869 | * least one tick may be lost due to delays. | |
1870 | */ | |
1d16b53e | 1871 | if (time_after(jiffies, t1 + 4)) |
1da177e4 LT |
1872 | return 1; |
1873 | ||
1874 | return 0; | |
1875 | } | |
1876 | ||
1877 | /* | |
1878 | * In the SMP+IOAPIC case it might happen that there are an unspecified | |
1879 | * number of pending IRQ events unhandled. These cases are very rare, | |
1880 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much | |
1881 | * better to do it this way as thus we do not have to be aware of | |
1882 | * 'pending' interrupts in the IRQ path, except at this point. | |
1883 | */ | |
1884 | /* | |
1885 | * Edge triggered needs to resend any interrupt | |
1886 | * that was delayed but this is now handled in the device | |
1887 | * independent code. | |
1888 | */ | |
1889 | ||
1890 | /* | |
f5b9ed7a IM |
1891 | * Startup quirk: |
1892 | * | |
1da177e4 LT |
1893 | * Starting up a edge-triggered IO-APIC interrupt is |
1894 | * nasty - we need to make sure that we get the edge. | |
1895 | * If it is already asserted for some reason, we need | |
1896 | * return 1 to indicate that is was pending. | |
1897 | * | |
1898 | * This is not complete - we should be able to fake | |
1899 | * an edge even if it isn't on the 8259A... | |
f5b9ed7a IM |
1900 | * |
1901 | * (We do this for level-triggered IRQs too - it cannot hurt.) | |
1da177e4 | 1902 | */ |
f5b9ed7a | 1903 | static unsigned int startup_ioapic_irq(unsigned int irq) |
1da177e4 LT |
1904 | { |
1905 | int was_pending = 0; | |
1906 | unsigned long flags; | |
1907 | ||
1908 | spin_lock_irqsave(&ioapic_lock, flags); | |
1909 | if (irq < 16) { | |
1910 | disable_8259A_irq(irq); | |
1911 | if (i8259A_irq_pending(irq)) | |
1912 | was_pending = 1; | |
1913 | } | |
1914 | __unmask_IO_APIC_irq(irq); | |
1915 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
1916 | ||
1917 | return was_pending; | |
1918 | } | |
1919 | ||
f5b9ed7a | 1920 | static void ack_ioapic_irq(unsigned int irq) |
1da177e4 | 1921 | { |
ace80ab7 | 1922 | move_native_irq(irq); |
1da177e4 LT |
1923 | ack_APIC_irq(); |
1924 | } | |
1925 | ||
f5b9ed7a | 1926 | static void ack_ioapic_quirk_irq(unsigned int irq) |
1da177e4 LT |
1927 | { |
1928 | unsigned long v; | |
1929 | int i; | |
1930 | ||
ace80ab7 | 1931 | move_native_irq(irq); |
1da177e4 LT |
1932 | /* |
1933 | * It appears there is an erratum which affects at least version 0x11 | |
1934 | * of I/O APIC (that's the 82093AA and cores integrated into various | |
1935 | * chipsets). Under certain conditions a level-triggered interrupt is | |
1936 | * erroneously delivered as edge-triggered one but the respective IRR | |
1937 | * bit gets set nevertheless. As a result the I/O unit expects an EOI | |
1938 | * message but it will never arrive and further interrupts are blocked | |
1939 | * from the source. The exact reason is so far unknown, but the | |
1940 | * phenomenon was observed when two consecutive interrupt requests | |
1941 | * from a given source get delivered to the same CPU and the source is | |
1942 | * temporarily disabled in between. | |
1943 | * | |
1944 | * A workaround is to simulate an EOI message manually. We achieve it | |
1945 | * by setting the trigger mode to edge and then to level when the edge | |
1946 | * trigger mode gets detected in the TMR of a local APIC for a | |
1947 | * level-triggered interrupt. We mask the source for the time of the | |
1948 | * operation to prevent an edge-triggered interrupt escaping meanwhile. | |
1949 | * The idea is from Manfred Spraul. --macro | |
1950 | */ | |
b940d22d | 1951 | i = irq_vector[irq]; |
1da177e4 LT |
1952 | |
1953 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); | |
1954 | ||
1955 | ack_APIC_irq(); | |
1956 | ||
1957 | if (!(v & (1 << (i & 0x1f)))) { | |
1958 | atomic_inc(&irq_mis_count); | |
1959 | spin_lock(&ioapic_lock); | |
1960 | __mask_and_edge_IO_APIC_irq(irq); | |
1961 | __unmask_and_level_IO_APIC_irq(irq); | |
1962 | spin_unlock(&ioapic_lock); | |
1963 | } | |
1964 | } | |
1965 | ||
ace80ab7 | 1966 | static int ioapic_retrigger_irq(unsigned int irq) |
1da177e4 | 1967 | { |
b940d22d | 1968 | send_IPI_self(irq_vector[irq]); |
c0ad90a3 IM |
1969 | |
1970 | return 1; | |
1971 | } | |
1972 | ||
f5b9ed7a IM |
1973 | static struct irq_chip ioapic_chip __read_mostly = { |
1974 | .name = "IO-APIC", | |
ace80ab7 EB |
1975 | .startup = startup_ioapic_irq, |
1976 | .mask = mask_IO_APIC_irq, | |
1977 | .unmask = unmask_IO_APIC_irq, | |
1978 | .ack = ack_ioapic_irq, | |
1979 | .eoi = ack_ioapic_quirk_irq, | |
54d5d424 | 1980 | #ifdef CONFIG_SMP |
ace80ab7 | 1981 | .set_affinity = set_ioapic_affinity_irq, |
54d5d424 | 1982 | #endif |
ace80ab7 | 1983 | .retrigger = ioapic_retrigger_irq, |
1da177e4 LT |
1984 | }; |
1985 | ||
1da177e4 LT |
1986 | |
1987 | static inline void init_IO_APIC_traps(void) | |
1988 | { | |
1989 | int irq; | |
1990 | ||
1991 | /* | |
1992 | * NOTE! The local APIC isn't very good at handling | |
1993 | * multiple interrupts at the same interrupt level. | |
1994 | * As the interrupt level is determined by taking the | |
1995 | * vector number and shifting that right by 4, we | |
1996 | * want to spread these out a bit so that they don't | |
1997 | * all fall in the same interrupt level. | |
1998 | * | |
1999 | * Also, we've got to be careful not to trash gate | |
2000 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
2001 | */ | |
2002 | for (irq = 0; irq < NR_IRQS ; irq++) { | |
addfc66b | 2003 | if (IO_APIC_IRQ(irq) && !irq_vector[irq]) { |
1da177e4 LT |
2004 | /* |
2005 | * Hmm.. We don't have an entry for this, | |
2006 | * so default to an old-fashioned 8259 | |
2007 | * interrupt if we can.. | |
2008 | */ | |
2009 | if (irq < 16) | |
2010 | make_8259A_irq(irq); | |
2011 | else | |
2012 | /* Strange. Oh, well.. */ | |
f5b9ed7a | 2013 | irq_desc[irq].chip = &no_irq_chip; |
1da177e4 LT |
2014 | } |
2015 | } | |
2016 | } | |
2017 | ||
f5b9ed7a IM |
2018 | /* |
2019 | * The local APIC irq-chip implementation: | |
2020 | */ | |
1da177e4 | 2021 | |
f5b9ed7a IM |
2022 | static void ack_apic(unsigned int irq) |
2023 | { | |
2024 | ack_APIC_irq(); | |
1da177e4 LT |
2025 | } |
2026 | ||
36062448 | 2027 | static void mask_lapic_irq(unsigned int irq) |
1da177e4 LT |
2028 | { |
2029 | unsigned long v; | |
2030 | ||
2031 | v = apic_read(APIC_LVT0); | |
2032 | apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); | |
2033 | } | |
2034 | ||
36062448 | 2035 | static void unmask_lapic_irq(unsigned int irq) |
1da177e4 | 2036 | { |
f5b9ed7a | 2037 | unsigned long v; |
1da177e4 | 2038 | |
f5b9ed7a IM |
2039 | v = apic_read(APIC_LVT0); |
2040 | apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); | |
2041 | } | |
1da177e4 | 2042 | |
f5b9ed7a | 2043 | static struct irq_chip lapic_chip __read_mostly = { |
9a1c6192 | 2044 | .name = "local-APIC", |
f5b9ed7a IM |
2045 | .mask = mask_lapic_irq, |
2046 | .unmask = unmask_lapic_irq, | |
2047 | .eoi = ack_apic, | |
1da177e4 LT |
2048 | }; |
2049 | ||
e9427101 | 2050 | static void __init setup_nmi(void) |
1da177e4 LT |
2051 | { |
2052 | /* | |
36062448 | 2053 | * Dirty trick to enable the NMI watchdog ... |
1da177e4 LT |
2054 | * We put the 8259A master into AEOI mode and |
2055 | * unmask on all local APICs LVT0 as NMI. | |
2056 | * | |
2057 | * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') | |
2058 | * is from Maciej W. Rozycki - so we do not have to EOI from | |
2059 | * the NMI handler or the timer interrupt. | |
36062448 | 2060 | */ |
1da177e4 LT |
2061 | apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ..."); |
2062 | ||
e9427101 | 2063 | enable_NMI_through_LVT0(); |
1da177e4 LT |
2064 | |
2065 | apic_printk(APIC_VERBOSE, " done.\n"); | |
2066 | } | |
2067 | ||
2068 | /* | |
2069 | * This looks a bit hackish but it's about the only one way of sending | |
2070 | * a few INTA cycles to 8259As and any associated glue logic. ICR does | |
2071 | * not support the ExtINT mode, unfortunately. We need to send these | |
2072 | * cycles as some i82489DX-based boards have glue logic that keeps the | |
2073 | * 8259A interrupt line asserted until INTA. --macro | |
2074 | */ | |
28acf285 | 2075 | static inline void __init unlock_ExtINT_logic(void) |
1da177e4 | 2076 | { |
fcfd636a | 2077 | int apic, pin, i; |
1da177e4 LT |
2078 | struct IO_APIC_route_entry entry0, entry1; |
2079 | unsigned char save_control, save_freq_select; | |
1da177e4 | 2080 | |
fcfd636a | 2081 | pin = find_isa_irq_pin(8, mp_INT); |
956fb531 AB |
2082 | if (pin == -1) { |
2083 | WARN_ON_ONCE(1); | |
2084 | return; | |
2085 | } | |
fcfd636a | 2086 | apic = find_isa_irq_apic(8, mp_INT); |
956fb531 AB |
2087 | if (apic == -1) { |
2088 | WARN_ON_ONCE(1); | |
1da177e4 | 2089 | return; |
956fb531 | 2090 | } |
1da177e4 | 2091 | |
cf4c6a2f | 2092 | entry0 = ioapic_read_entry(apic, pin); |
fcfd636a | 2093 | clear_IO_APIC_pin(apic, pin); |
1da177e4 LT |
2094 | |
2095 | memset(&entry1, 0, sizeof(entry1)); | |
2096 | ||
2097 | entry1.dest_mode = 0; /* physical delivery */ | |
2098 | entry1.mask = 0; /* unmask IRQ now */ | |
2099 | entry1.dest.physical.physical_dest = hard_smp_processor_id(); | |
2100 | entry1.delivery_mode = dest_ExtINT; | |
2101 | entry1.polarity = entry0.polarity; | |
2102 | entry1.trigger = 0; | |
2103 | entry1.vector = 0; | |
2104 | ||
cf4c6a2f | 2105 | ioapic_write_entry(apic, pin, entry1); |
1da177e4 LT |
2106 | |
2107 | save_control = CMOS_READ(RTC_CONTROL); | |
2108 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); | |
2109 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, | |
2110 | RTC_FREQ_SELECT); | |
2111 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); | |
2112 | ||
2113 | i = 100; | |
2114 | while (i-- > 0) { | |
2115 | mdelay(10); | |
2116 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) | |
2117 | i -= 10; | |
2118 | } | |
2119 | ||
2120 | CMOS_WRITE(save_control, RTC_CONTROL); | |
2121 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); | |
fcfd636a | 2122 | clear_IO_APIC_pin(apic, pin); |
1da177e4 | 2123 | |
cf4c6a2f | 2124 | ioapic_write_entry(apic, pin, entry0); |
1da177e4 LT |
2125 | } |
2126 | ||
2127 | /* | |
2128 | * This code may look a bit paranoid, but it's supposed to cooperate with | |
2129 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ | |
2130 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast | |
2131 | * fanatically on his truly buggy board. | |
2132 | */ | |
8542b200 | 2133 | static inline void __init check_timer(void) |
1da177e4 | 2134 | { |
fcfd636a | 2135 | int apic1, pin1, apic2, pin2; |
691874fa | 2136 | int no_pin1 = 0; |
1da177e4 | 2137 | int vector; |
6e908947 | 2138 | unsigned int ver; |
4aae0702 IM |
2139 | unsigned long flags; |
2140 | ||
2141 | local_irq_save(flags); | |
d4d25dec | 2142 | |
6e908947 IM |
2143 | ver = apic_read(APIC_LVR); |
2144 | ver = GET_APIC_VERSION(ver); | |
2145 | ||
1da177e4 LT |
2146 | /* |
2147 | * get/set the timer IRQ vector: | |
2148 | */ | |
2149 | disable_8259A_irq(0); | |
2150 | vector = assign_irq_vector(0); | |
2151 | set_intr_gate(vector, interrupt[0]); | |
2152 | ||
2153 | /* | |
d11d5794 MR |
2154 | * As IRQ0 is to be enabled in the 8259A, the virtual |
2155 | * wire has to be disabled in the local APIC. Also | |
2156 | * timer interrupts need to be acknowledged manually in | |
2157 | * the 8259A for the i82489DX when using the NMI | |
2158 | * watchdog as that APIC treats NMIs as level-triggered. | |
2159 | * The AEOI mode will finish them in the 8259A | |
2160 | * automatically. | |
1da177e4 LT |
2161 | */ |
2162 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); | |
2163 | init_8259A(1); | |
d11d5794 | 2164 | timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver)); |
1da177e4 | 2165 | |
fcfd636a EB |
2166 | pin1 = find_isa_irq_pin(0, mp_INT); |
2167 | apic1 = find_isa_irq_apic(0, mp_INT); | |
2168 | pin2 = ioapic_i8259.pin; | |
2169 | apic2 = ioapic_i8259.apic; | |
1da177e4 | 2170 | |
fcfd636a EB |
2171 | printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n", |
2172 | vector, apic1, pin1, apic2, pin2); | |
1da177e4 | 2173 | |
691874fa MR |
2174 | /* |
2175 | * Some BIOS writers are clueless and report the ExtINTA | |
2176 | * I/O APIC input from the cascaded 8259A as the timer | |
2177 | * interrupt input. So just in case, if only one pin | |
2178 | * was found above, try it both directly and through the | |
2179 | * 8259A. | |
2180 | */ | |
2181 | if (pin1 == -1) { | |
2182 | pin1 = pin2; | |
2183 | apic1 = apic2; | |
2184 | no_pin1 = 1; | |
2185 | } else if (pin2 == -1) { | |
2186 | pin2 = pin1; | |
2187 | apic2 = apic1; | |
2188 | } | |
2189 | ||
1da177e4 LT |
2190 | if (pin1 != -1) { |
2191 | /* | |
2192 | * Ok, does IRQ0 through the IOAPIC work? | |
2193 | */ | |
691874fa MR |
2194 | if (no_pin1) { |
2195 | add_pin_to_irq(0, apic1, pin1); | |
2196 | setup_timer_IRQ0_pin(apic1, pin1, vector); | |
2197 | } | |
1da177e4 LT |
2198 | unmask_IO_APIC_irq(0); |
2199 | if (timer_irq_works()) { | |
2200 | if (nmi_watchdog == NMI_IO_APIC) { | |
1da177e4 LT |
2201 | setup_nmi(); |
2202 | enable_8259A_irq(0); | |
1da177e4 | 2203 | } |
66759a01 CE |
2204 | if (disable_timer_pin_1 > 0) |
2205 | clear_IO_APIC_pin(0, pin1); | |
4aae0702 | 2206 | goto out; |
1da177e4 | 2207 | } |
fcfd636a | 2208 | clear_IO_APIC_pin(apic1, pin1); |
691874fa MR |
2209 | if (!no_pin1) |
2210 | printk(KERN_ERR "..MP-BIOS bug: " | |
2211 | "8254 timer not connected to IO-APIC\n"); | |
1da177e4 | 2212 | |
691874fa MR |
2213 | printk(KERN_INFO "...trying to set up timer (IRQ0) " |
2214 | "through the 8259A ... "); | |
1da177e4 LT |
2215 | printk("\n..... (found pin %d) ...", pin2); |
2216 | /* | |
2217 | * legacy devices should be connected to IO APIC #0 | |
2218 | */ | |
691874fa | 2219 | replace_pin_at_irq(0, apic1, pin1, apic2, pin2); |
f7633ce5 | 2220 | setup_timer_IRQ0_pin(apic2, pin2, vector); |
24742ece | 2221 | unmask_IO_APIC_irq(0); |
ecd29476 | 2222 | enable_8259A_irq(0); |
1da177e4 LT |
2223 | if (timer_irq_works()) { |
2224 | printk("works.\n"); | |
35542c5e | 2225 | timer_through_8259 = 1; |
1da177e4 | 2226 | if (nmi_watchdog == NMI_IO_APIC) { |
60134ebe | 2227 | disable_8259A_irq(0); |
1da177e4 | 2228 | setup_nmi(); |
60134ebe | 2229 | enable_8259A_irq(0); |
1da177e4 | 2230 | } |
4aae0702 | 2231 | goto out; |
1da177e4 LT |
2232 | } |
2233 | /* | |
2234 | * Cleanup, just in case ... | |
2235 | */ | |
ecd29476 | 2236 | disable_8259A_irq(0); |
fcfd636a | 2237 | clear_IO_APIC_pin(apic2, pin2); |
691874fa | 2238 | printk(" failed.\n"); |
1da177e4 | 2239 | } |
1da177e4 LT |
2240 | |
2241 | if (nmi_watchdog == NMI_IO_APIC) { | |
2242 | printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); | |
067fa0ff | 2243 | nmi_watchdog = NMI_NONE; |
1da177e4 | 2244 | } |
d11d5794 | 2245 | timer_ack = 0; |
1da177e4 LT |
2246 | |
2247 | printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); | |
2248 | ||
a460e745 | 2249 | set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq, |
2e188938 | 2250 | "fasteoi"); |
1da177e4 LT |
2251 | apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ |
2252 | enable_8259A_irq(0); | |
2253 | ||
2254 | if (timer_irq_works()) { | |
2255 | printk(" works.\n"); | |
4aae0702 | 2256 | goto out; |
1da177e4 | 2257 | } |
e67465f1 | 2258 | disable_8259A_irq(0); |
1da177e4 LT |
2259 | apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); |
2260 | printk(" failed.\n"); | |
2261 | ||
2262 | printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); | |
2263 | ||
1da177e4 LT |
2264 | init_8259A(0); |
2265 | make_8259A_irq(0); | |
2266 | apic_write_around(APIC_LVT0, APIC_DM_EXTINT); | |
2267 | ||
2268 | unlock_ExtINT_logic(); | |
2269 | ||
2270 | if (timer_irq_works()) { | |
2271 | printk(" works.\n"); | |
4aae0702 | 2272 | goto out; |
1da177e4 LT |
2273 | } |
2274 | printk(" failed :(.\n"); | |
2275 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " | |
2276 | "report. Then try booting with the 'noapic' option"); | |
4aae0702 IM |
2277 | out: |
2278 | local_irq_restore(flags); | |
1da177e4 LT |
2279 | } |
2280 | ||
2281 | /* | |
2282 | * | |
2283 | * IRQ's that are handled by the PIC in the MPS IOAPIC case. | |
2284 | * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. | |
2285 | * Linux doesn't really care, as it's not actually used | |
2286 | * for any interrupt handling anyway. | |
2287 | */ | |
2288 | #define PIC_IRQS (1 << PIC_CASCADE_IR) | |
2289 | ||
2290 | void __init setup_IO_APIC(void) | |
2291 | { | |
dbeb2be2 RR |
2292 | int i; |
2293 | ||
2294 | /* Reserve all the system vectors. */ | |
305b92a2 | 2295 | for (i = first_system_vector; i < NR_VECTORS; i++) |
dbeb2be2 RR |
2296 | set_bit(i, used_vectors); |
2297 | ||
1da177e4 LT |
2298 | enable_IO_APIC(); |
2299 | ||
2300 | if (acpi_ioapic) | |
2301 | io_apic_irqs = ~0; /* all IRQs go through IOAPIC */ | |
2302 | else | |
2303 | io_apic_irqs = ~PIC_IRQS; | |
2304 | ||
2305 | printk("ENABLING IO-APIC IRQs\n"); | |
2306 | ||
2307 | /* | |
2308 | * Set up IO-APIC IRQ routing. | |
2309 | */ | |
2310 | if (!acpi_ioapic) | |
2311 | setup_ioapic_ids_from_mpc(); | |
2312 | sync_Arb_IDs(); | |
2313 | setup_IO_APIC_irqs(); | |
2314 | init_IO_APIC_traps(); | |
1e4c85f9 | 2315 | check_timer(); |
1da177e4 LT |
2316 | if (!acpi_ioapic) |
2317 | print_IO_APIC(); | |
2318 | } | |
2319 | ||
2320 | /* | |
2321 | * Called after all the initialization is done. If we didnt find any | |
2322 | * APIC bugs then we can allow the modify fast path | |
2323 | */ | |
36062448 | 2324 | |
1da177e4 LT |
2325 | static int __init io_apic_bug_finalize(void) |
2326 | { | |
36062448 | 2327 | if (sis_apic_bug == -1) |
1da177e4 LT |
2328 | sis_apic_bug = 0; |
2329 | return 0; | |
2330 | } | |
2331 | ||
2332 | late_initcall(io_apic_bug_finalize); | |
2333 | ||
2334 | struct sysfs_ioapic_data { | |
2335 | struct sys_device dev; | |
2336 | struct IO_APIC_route_entry entry[0]; | |
2337 | }; | |
36062448 | 2338 | static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS]; |
1da177e4 | 2339 | |
438510f6 | 2340 | static int ioapic_suspend(struct sys_device *dev, pm_message_t state) |
1da177e4 LT |
2341 | { |
2342 | struct IO_APIC_route_entry *entry; | |
2343 | struct sysfs_ioapic_data *data; | |
1da177e4 | 2344 | int i; |
36062448 | 2345 | |
1da177e4 LT |
2346 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2347 | entry = data->entry; | |
36062448 | 2348 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2349 | entry[i] = ioapic_read_entry(dev->id, i); |
1da177e4 LT |
2350 | |
2351 | return 0; | |
2352 | } | |
2353 | ||
2354 | static int ioapic_resume(struct sys_device *dev) | |
2355 | { | |
2356 | struct IO_APIC_route_entry *entry; | |
2357 | struct sysfs_ioapic_data *data; | |
2358 | unsigned long flags; | |
2359 | union IO_APIC_reg_00 reg_00; | |
2360 | int i; | |
36062448 | 2361 | |
1da177e4 LT |
2362 | data = container_of(dev, struct sysfs_ioapic_data, dev); |
2363 | entry = data->entry; | |
2364 | ||
2365 | spin_lock_irqsave(&ioapic_lock, flags); | |
2366 | reg_00.raw = io_apic_read(dev->id, 0); | |
ec2cd0a2 AS |
2367 | if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) { |
2368 | reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid; | |
1da177e4 LT |
2369 | io_apic_write(dev->id, 0, reg_00.raw); |
2370 | } | |
1da177e4 | 2371 | spin_unlock_irqrestore(&ioapic_lock, flags); |
36062448 | 2372 | for (i = 0; i < nr_ioapic_registers[dev->id]; i++) |
cf4c6a2f | 2373 | ioapic_write_entry(dev->id, i, entry[i]); |
1da177e4 LT |
2374 | |
2375 | return 0; | |
2376 | } | |
2377 | ||
2378 | static struct sysdev_class ioapic_sysdev_class = { | |
af5ca3f4 | 2379 | .name = "ioapic", |
1da177e4 LT |
2380 | .suspend = ioapic_suspend, |
2381 | .resume = ioapic_resume, | |
2382 | }; | |
2383 | ||
2384 | static int __init ioapic_init_sysfs(void) | |
2385 | { | |
36062448 | 2386 | struct sys_device *dev; |
1da177e4 LT |
2387 | int i, size, error = 0; |
2388 | ||
2389 | error = sysdev_class_register(&ioapic_sysdev_class); | |
2390 | if (error) | |
2391 | return error; | |
2392 | ||
36062448 PC |
2393 | for (i = 0; i < nr_ioapics; i++) { |
2394 | size = sizeof(struct sys_device) + nr_ioapic_registers[i] | |
1da177e4 | 2395 | * sizeof(struct IO_APIC_route_entry); |
25556c16 | 2396 | mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL); |
1da177e4 LT |
2397 | if (!mp_ioapic_data[i]) { |
2398 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2399 | continue; | |
2400 | } | |
1da177e4 | 2401 | dev = &mp_ioapic_data[i]->dev; |
36062448 | 2402 | dev->id = i; |
1da177e4 LT |
2403 | dev->cls = &ioapic_sysdev_class; |
2404 | error = sysdev_register(dev); | |
2405 | if (error) { | |
2406 | kfree(mp_ioapic_data[i]); | |
2407 | mp_ioapic_data[i] = NULL; | |
2408 | printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i); | |
2409 | continue; | |
2410 | } | |
2411 | } | |
2412 | ||
2413 | return 0; | |
2414 | } | |
2415 | ||
2416 | device_initcall(ioapic_init_sysfs); | |
2417 | ||
3fc471ed | 2418 | /* |
95d77884 | 2419 | * Dynamic irq allocate and deallocation |
3fc471ed EB |
2420 | */ |
2421 | int create_irq(void) | |
2422 | { | |
ace80ab7 | 2423 | /* Allocate an unused irq */ |
306a22c2 | 2424 | int irq, new, vector = 0; |
3fc471ed | 2425 | unsigned long flags; |
3fc471ed | 2426 | |
ace80ab7 EB |
2427 | irq = -ENOSPC; |
2428 | spin_lock_irqsave(&vector_lock, flags); | |
2429 | for (new = (NR_IRQS - 1); new >= 0; new--) { | |
2430 | if (platform_legacy_irq(new)) | |
2431 | continue; | |
2432 | if (irq_vector[new] != 0) | |
2433 | continue; | |
2434 | vector = __assign_irq_vector(new); | |
2435 | if (likely(vector > 0)) | |
2436 | irq = new; | |
2437 | break; | |
2438 | } | |
2439 | spin_unlock_irqrestore(&vector_lock, flags); | |
3fc471ed | 2440 | |
ace80ab7 | 2441 | if (irq >= 0) { |
3fc471ed | 2442 | set_intr_gate(vector, interrupt[irq]); |
3fc471ed EB |
2443 | dynamic_irq_init(irq); |
2444 | } | |
2445 | return irq; | |
2446 | } | |
2447 | ||
2448 | void destroy_irq(unsigned int irq) | |
2449 | { | |
2450 | unsigned long flags; | |
3fc471ed EB |
2451 | |
2452 | dynamic_irq_cleanup(irq); | |
2453 | ||
2454 | spin_lock_irqsave(&vector_lock, flags); | |
9d9ad4b5 | 2455 | clear_bit(irq_vector[irq], used_vectors); |
3fc471ed EB |
2456 | irq_vector[irq] = 0; |
2457 | spin_unlock_irqrestore(&vector_lock, flags); | |
2458 | } | |
3fc471ed | 2459 | |
2d3fcc1c | 2460 | /* |
27b46d76 | 2461 | * MSI message composition |
2d3fcc1c EB |
2462 | */ |
2463 | #ifdef CONFIG_PCI_MSI | |
3b7d1921 | 2464 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg) |
2d3fcc1c | 2465 | { |
2d3fcc1c EB |
2466 | int vector; |
2467 | unsigned dest; | |
2468 | ||
2469 | vector = assign_irq_vector(irq); | |
2470 | if (vector >= 0) { | |
2471 | dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2472 | ||
2473 | msg->address_hi = MSI_ADDR_BASE_HI; | |
2474 | msg->address_lo = | |
2475 | MSI_ADDR_BASE_LO | | |
2476 | ((INT_DEST_MODE == 0) ? | |
36062448 | 2477 | MSI_ADDR_DEST_MODE_PHYSICAL: |
2d3fcc1c EB |
2478 | MSI_ADDR_DEST_MODE_LOGICAL) | |
2479 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2480 | MSI_ADDR_REDIRECTION_CPU: | |
2481 | MSI_ADDR_REDIRECTION_LOWPRI) | | |
2482 | MSI_ADDR_DEST_ID(dest); | |
2483 | ||
2484 | msg->data = | |
2485 | MSI_DATA_TRIGGER_EDGE | | |
2486 | MSI_DATA_LEVEL_ASSERT | | |
2487 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
36062448 | 2488 | MSI_DATA_DELIVERY_FIXED: |
2d3fcc1c EB |
2489 | MSI_DATA_DELIVERY_LOWPRI) | |
2490 | MSI_DATA_VECTOR(vector); | |
2491 | } | |
2492 | return vector; | |
2493 | } | |
2494 | ||
3b7d1921 EB |
2495 | #ifdef CONFIG_SMP |
2496 | static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask) | |
2d3fcc1c | 2497 | { |
3b7d1921 EB |
2498 | struct msi_msg msg; |
2499 | unsigned int dest; | |
2500 | cpumask_t tmp; | |
2d3fcc1c | 2501 | int vector; |
3b7d1921 EB |
2502 | |
2503 | cpus_and(tmp, mask, cpu_online_map); | |
2504 | if (cpus_empty(tmp)) | |
2505 | tmp = TARGET_CPUS; | |
2d3fcc1c EB |
2506 | |
2507 | vector = assign_irq_vector(irq); | |
3b7d1921 EB |
2508 | if (vector < 0) |
2509 | return; | |
2d3fcc1c | 2510 | |
3b7d1921 EB |
2511 | dest = cpu_mask_to_apicid(mask); |
2512 | ||
2513 | read_msi_msg(irq, &msg); | |
2514 | ||
2515 | msg.data &= ~MSI_DATA_VECTOR_MASK; | |
2516 | msg.data |= MSI_DATA_VECTOR(vector); | |
2517 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; | |
2518 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); | |
2519 | ||
2520 | write_msi_msg(irq, &msg); | |
9f0a5ba5 | 2521 | irq_desc[irq].affinity = mask; |
2d3fcc1c | 2522 | } |
3b7d1921 | 2523 | #endif /* CONFIG_SMP */ |
2d3fcc1c | 2524 | |
3b7d1921 EB |
2525 | /* |
2526 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
2527 | * which implement the MSI or MSI-X Capability Structure. | |
2528 | */ | |
2529 | static struct irq_chip msi_chip = { | |
2530 | .name = "PCI-MSI", | |
2531 | .unmask = unmask_msi_irq, | |
2532 | .mask = mask_msi_irq, | |
2533 | .ack = ack_ioapic_irq, | |
2534 | #ifdef CONFIG_SMP | |
2535 | .set_affinity = set_msi_irq_affinity, | |
2536 | #endif | |
2537 | .retrigger = ioapic_retrigger_irq, | |
2d3fcc1c EB |
2538 | }; |
2539 | ||
f7feaca7 | 2540 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
3b7d1921 EB |
2541 | { |
2542 | struct msi_msg msg; | |
f7feaca7 EB |
2543 | int irq, ret; |
2544 | irq = create_irq(); | |
2545 | if (irq < 0) | |
2546 | return irq; | |
2547 | ||
3b7d1921 | 2548 | ret = msi_compose_msg(dev, irq, &msg); |
f7feaca7 EB |
2549 | if (ret < 0) { |
2550 | destroy_irq(irq); | |
3b7d1921 | 2551 | return ret; |
f7feaca7 | 2552 | } |
3b7d1921 | 2553 | |
7fe3730d | 2554 | set_irq_msi(irq, desc); |
3b7d1921 EB |
2555 | write_msi_msg(irq, &msg); |
2556 | ||
a460e745 IM |
2557 | set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, |
2558 | "edge"); | |
3b7d1921 | 2559 | |
7fe3730d | 2560 | return 0; |
3b7d1921 EB |
2561 | } |
2562 | ||
2563 | void arch_teardown_msi_irq(unsigned int irq) | |
2564 | { | |
f7feaca7 | 2565 | destroy_irq(irq); |
3b7d1921 EB |
2566 | } |
2567 | ||
2d3fcc1c EB |
2568 | #endif /* CONFIG_PCI_MSI */ |
2569 | ||
8b955b0d EB |
2570 | /* |
2571 | * Hypertransport interrupt support | |
2572 | */ | |
2573 | #ifdef CONFIG_HT_IRQ | |
2574 | ||
2575 | #ifdef CONFIG_SMP | |
2576 | ||
2577 | static void target_ht_irq(unsigned int irq, unsigned int dest) | |
2578 | { | |
ec68307c EB |
2579 | struct ht_irq_msg msg; |
2580 | fetch_ht_irq_msg(irq, &msg); | |
8b955b0d | 2581 | |
ec68307c EB |
2582 | msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK); |
2583 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); | |
8b955b0d | 2584 | |
ec68307c EB |
2585 | msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest); |
2586 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); | |
8b955b0d | 2587 | |
ec68307c | 2588 | write_ht_irq_msg(irq, &msg); |
8b955b0d EB |
2589 | } |
2590 | ||
2591 | static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) | |
2592 | { | |
2593 | unsigned int dest; | |
2594 | cpumask_t tmp; | |
2595 | ||
2596 | cpus_and(tmp, mask, cpu_online_map); | |
2597 | if (cpus_empty(tmp)) | |
2598 | tmp = TARGET_CPUS; | |
2599 | ||
2600 | cpus_and(mask, tmp, CPU_MASK_ALL); | |
2601 | ||
2602 | dest = cpu_mask_to_apicid(mask); | |
2603 | ||
2604 | target_ht_irq(irq, dest); | |
9f0a5ba5 | 2605 | irq_desc[irq].affinity = mask; |
8b955b0d EB |
2606 | } |
2607 | #endif | |
2608 | ||
c37e108d | 2609 | static struct irq_chip ht_irq_chip = { |
8b955b0d EB |
2610 | .name = "PCI-HT", |
2611 | .mask = mask_ht_irq, | |
2612 | .unmask = unmask_ht_irq, | |
2613 | .ack = ack_ioapic_irq, | |
2614 | #ifdef CONFIG_SMP | |
2615 | .set_affinity = set_ht_irq_affinity, | |
2616 | #endif | |
2617 | .retrigger = ioapic_retrigger_irq, | |
2618 | }; | |
2619 | ||
2620 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |
2621 | { | |
2622 | int vector; | |
2623 | ||
2624 | vector = assign_irq_vector(irq); | |
2625 | if (vector >= 0) { | |
ec68307c | 2626 | struct ht_irq_msg msg; |
8b955b0d EB |
2627 | unsigned dest; |
2628 | cpumask_t tmp; | |
2629 | ||
2630 | cpus_clear(tmp); | |
2631 | cpu_set(vector >> 8, tmp); | |
2632 | dest = cpu_mask_to_apicid(tmp); | |
2633 | ||
ec68307c | 2634 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
8b955b0d | 2635 | |
ec68307c EB |
2636 | msg.address_lo = |
2637 | HT_IRQ_LOW_BASE | | |
8b955b0d EB |
2638 | HT_IRQ_LOW_DEST_ID(dest) | |
2639 | HT_IRQ_LOW_VECTOR(vector) | | |
2640 | ((INT_DEST_MODE == 0) ? | |
2641 | HT_IRQ_LOW_DM_PHYSICAL : | |
2642 | HT_IRQ_LOW_DM_LOGICAL) | | |
2643 | HT_IRQ_LOW_RQEOI_EDGE | | |
2644 | ((INT_DELIVERY_MODE != dest_LowestPrio) ? | |
2645 | HT_IRQ_LOW_MT_FIXED : | |
2646 | HT_IRQ_LOW_MT_ARBITRATED) | | |
2647 | HT_IRQ_LOW_IRQ_MASKED; | |
2648 | ||
ec68307c | 2649 | write_ht_irq_msg(irq, &msg); |
8b955b0d | 2650 | |
a460e745 IM |
2651 | set_irq_chip_and_handler_name(irq, &ht_irq_chip, |
2652 | handle_edge_irq, "edge"); | |
8b955b0d EB |
2653 | } |
2654 | return vector; | |
2655 | } | |
2656 | #endif /* CONFIG_HT_IRQ */ | |
2657 | ||
1da177e4 | 2658 | /* -------------------------------------------------------------------------- |
36062448 | 2659 | ACPI-based IOAPIC Configuration |
1da177e4 LT |
2660 | -------------------------------------------------------------------------- */ |
2661 | ||
888ba6c6 | 2662 | #ifdef CONFIG_ACPI |
1da177e4 | 2663 | |
36062448 | 2664 | int __init io_apic_get_unique_id(int ioapic, int apic_id) |
1da177e4 LT |
2665 | { |
2666 | union IO_APIC_reg_00 reg_00; | |
2667 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; | |
2668 | physid_mask_t tmp; | |
2669 | unsigned long flags; | |
2670 | int i = 0; | |
2671 | ||
2672 | /* | |
36062448 PC |
2673 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
2674 | * buses (one for LAPICs, one for IOAPICs), where predecessors only | |
1da177e4 | 2675 | * supports up to 16 on one shared APIC bus. |
36062448 | 2676 | * |
1da177e4 LT |
2677 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
2678 | * advantage of new APIC bus architecture. | |
2679 | */ | |
2680 | ||
2681 | if (physids_empty(apic_id_map)) | |
2682 | apic_id_map = ioapic_phys_id_map(phys_cpu_present_map); | |
2683 | ||
2684 | spin_lock_irqsave(&ioapic_lock, flags); | |
2685 | reg_00.raw = io_apic_read(ioapic, 0); | |
2686 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2687 | ||
2688 | if (apic_id >= get_physical_broadcast()) { | |
2689 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " | |
2690 | "%d\n", ioapic, apic_id, reg_00.bits.ID); | |
2691 | apic_id = reg_00.bits.ID; | |
2692 | } | |
2693 | ||
2694 | /* | |
36062448 | 2695 | * Every APIC in a system must have a unique ID or we get lots of nice |
1da177e4 LT |
2696 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
2697 | */ | |
2698 | if (check_apicid_used(apic_id_map, apic_id)) { | |
2699 | ||
2700 | for (i = 0; i < get_physical_broadcast(); i++) { | |
2701 | if (!check_apicid_used(apic_id_map, i)) | |
2702 | break; | |
2703 | } | |
2704 | ||
2705 | if (i == get_physical_broadcast()) | |
2706 | panic("Max apic_id exceeded!\n"); | |
2707 | ||
2708 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " | |
2709 | "trying %d\n", ioapic, apic_id, i); | |
2710 | ||
2711 | apic_id = i; | |
36062448 | 2712 | } |
1da177e4 LT |
2713 | |
2714 | tmp = apicid_to_cpu_present(apic_id); | |
2715 | physids_or(apic_id_map, apic_id_map, tmp); | |
2716 | ||
2717 | if (reg_00.bits.ID != apic_id) { | |
2718 | reg_00.bits.ID = apic_id; | |
2719 | ||
2720 | spin_lock_irqsave(&ioapic_lock, flags); | |
2721 | io_apic_write(ioapic, 0, reg_00.raw); | |
2722 | reg_00.raw = io_apic_read(ioapic, 0); | |
2723 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2724 | ||
2725 | /* Sanity check */ | |
6070f9ec AD |
2726 | if (reg_00.bits.ID != apic_id) { |
2727 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | |
2728 | return -1; | |
2729 | } | |
1da177e4 LT |
2730 | } |
2731 | ||
2732 | apic_printk(APIC_VERBOSE, KERN_INFO | |
2733 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); | |
2734 | ||
2735 | return apic_id; | |
2736 | } | |
2737 | ||
2738 | ||
36062448 | 2739 | int __init io_apic_get_version(int ioapic) |
1da177e4 LT |
2740 | { |
2741 | union IO_APIC_reg_01 reg_01; | |
2742 | unsigned long flags; | |
2743 | ||
2744 | spin_lock_irqsave(&ioapic_lock, flags); | |
2745 | reg_01.raw = io_apic_read(ioapic, 1); | |
2746 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2747 | ||
2748 | return reg_01.bits.version; | |
2749 | } | |
2750 | ||
2751 | ||
36062448 | 2752 | int __init io_apic_get_redir_entries(int ioapic) |
1da177e4 LT |
2753 | { |
2754 | union IO_APIC_reg_01 reg_01; | |
2755 | unsigned long flags; | |
2756 | ||
2757 | spin_lock_irqsave(&ioapic_lock, flags); | |
2758 | reg_01.raw = io_apic_read(ioapic, 1); | |
2759 | spin_unlock_irqrestore(&ioapic_lock, flags); | |
2760 | ||
2761 | return reg_01.bits.entries; | |
2762 | } | |
2763 | ||
2764 | ||
36062448 | 2765 | int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low) |
1da177e4 LT |
2766 | { |
2767 | struct IO_APIC_route_entry entry; | |
1da177e4 LT |
2768 | |
2769 | if (!IO_APIC_IRQ(irq)) { | |
2770 | printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", | |
2771 | ioapic); | |
2772 | return -EINVAL; | |
2773 | } | |
2774 | ||
2775 | /* | |
2776 | * Generate a PCI IRQ routing entry and program the IOAPIC accordingly. | |
2777 | * Note that we mask (disable) IRQs now -- these get enabled when the | |
2778 | * corresponding device driver registers for this IRQ. | |
2779 | */ | |
2780 | ||
36062448 | 2781 | memset(&entry, 0, sizeof(entry)); |
1da177e4 LT |
2782 | |
2783 | entry.delivery_mode = INT_DELIVERY_MODE; | |
2784 | entry.dest_mode = INT_DEST_MODE; | |
2785 | entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS); | |
2786 | entry.trigger = edge_level; | |
2787 | entry.polarity = active_high_low; | |
2788 | entry.mask = 1; | |
2789 | ||
2790 | /* | |
2791 | * IRQs < 16 are already in the irq_2_pin[] map | |
2792 | */ | |
2793 | if (irq >= 16) | |
2794 | add_pin_to_irq(irq, ioapic, pin); | |
2795 | ||
2796 | entry.vector = assign_irq_vector(irq); | |
2797 | ||
2798 | apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry " | |
2799 | "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic, | |
ec2cd0a2 | 2800 | mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq, |
1da177e4 LT |
2801 | edge_level, active_high_low); |
2802 | ||
2803 | ioapic_register_intr(irq, entry.vector, edge_level); | |
2804 | ||
2805 | if (!ioapic && (irq < 16)) | |
2806 | disable_8259A_irq(irq); | |
2807 | ||
a2249cba | 2808 | ioapic_write_entry(ioapic, pin, entry); |
1da177e4 LT |
2809 | |
2810 | return 0; | |
2811 | } | |
2812 | ||
61fd47e0 SL |
2813 | int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity) |
2814 | { | |
2815 | int i; | |
2816 | ||
2817 | if (skip_ioapic_setup) | |
2818 | return -1; | |
2819 | ||
2820 | for (i = 0; i < mp_irq_entries; i++) | |
2fddb6e2 AS |
2821 | if (mp_irqs[i].mp_irqtype == mp_INT && |
2822 | mp_irqs[i].mp_srcbusirq == bus_irq) | |
61fd47e0 SL |
2823 | break; |
2824 | if (i >= mp_irq_entries) | |
2825 | return -1; | |
2826 | ||
2827 | *trigger = irq_trigger(i); | |
2828 | *polarity = irq_polarity(i); | |
2829 | return 0; | |
2830 | } | |
2831 | ||
888ba6c6 | 2832 | #endif /* CONFIG_ACPI */ |
1a3f239d RR |
2833 | |
2834 | static int __init parse_disable_timer_pin_1(char *arg) | |
2835 | { | |
2836 | disable_timer_pin_1 = 1; | |
2837 | return 0; | |
2838 | } | |
2839 | early_param("disable_timer_pin_1", parse_disable_timer_pin_1); | |
2840 | ||
2841 | static int __init parse_enable_timer_pin_1(char *arg) | |
2842 | { | |
2843 | disable_timer_pin_1 = -1; | |
2844 | return 0; | |
2845 | } | |
2846 | early_param("enable_timer_pin_1", parse_enable_timer_pin_1); | |
2847 | ||
2848 | static int __init parse_noapic(char *arg) | |
2849 | { | |
2850 | /* disable IO-APIC */ | |
2851 | disable_ioapic_setup(); | |
2852 | return 0; | |
2853 | } | |
2854 | early_param("noapic", parse_noapic); |