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Commit | Line | Data |
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6b39ba77 TG |
1 | /* |
2 | * Common interrupt code for 32 and 64 bit | |
3 | */ | |
4 | #include <linux/cpu.h> | |
5 | #include <linux/interrupt.h> | |
6 | #include <linux/kernel_stat.h> | |
4722d194 | 7 | #include <linux/of.h> |
6b39ba77 | 8 | #include <linux/seq_file.h> |
6a02e710 | 9 | #include <linux/smp.h> |
7c1d7cdc | 10 | #include <linux/ftrace.h> |
ca444564 | 11 | #include <linux/delay.h> |
69c60c88 | 12 | #include <linux/export.h> |
6b39ba77 | 13 | |
7b6aa335 | 14 | #include <asm/apic.h> |
6b39ba77 | 15 | #include <asm/io_apic.h> |
c3d80000 | 16 | #include <asm/irq.h> |
7c1d7cdc | 17 | #include <asm/idle.h> |
01ca79f1 | 18 | #include <asm/mce.h> |
2c1b284e | 19 | #include <asm/hw_irq.h> |
83ab8514 SRRH |
20 | |
21 | #define CREATE_TRACE_POINTS | |
cf910e83 | 22 | #include <asm/trace/irq_vectors.h> |
6b39ba77 TG |
23 | |
24 | atomic_t irq_err_count; | |
25 | ||
acaabe79 | 26 | /* Function pointer for generic interrupt vector handling */ |
4a4de9c7 | 27 | void (*x86_platform_ipi_callback)(void) = NULL; |
acaabe79 | 28 | |
249f6d9e TG |
29 | /* |
30 | * 'what should we do if we get a hw irq event on an illegal vector'. | |
31 | * each architecture has to answer this themselves. | |
32 | */ | |
33 | void ack_bad_irq(unsigned int irq) | |
34 | { | |
edea7148 CG |
35 | if (printk_ratelimit()) |
36 | pr_err("unexpected IRQ trap at vector %02x\n", irq); | |
249f6d9e | 37 | |
249f6d9e TG |
38 | /* |
39 | * Currently unexpected vectors happen only on SMP and APIC. | |
40 | * We _must_ ack these because every local APIC has only N | |
41 | * irq slots per priority level, and a 'hanging, unacked' IRQ | |
42 | * holds up an irq slot - in excessive cases (when multiple | |
43 | * unexpected vectors occur) that might lock up the APIC | |
44 | * completely. | |
45 | * But only ack when the APIC is enabled -AK | |
46 | */ | |
08306ce6 | 47 | ack_APIC_irq(); |
249f6d9e TG |
48 | } |
49 | ||
1b437c8c | 50 | #define irq_stats(x) (&per_cpu(irq_stat, x)) |
6b39ba77 | 51 | /* |
517e4981 | 52 | * /proc/interrupts printing for arch specific interrupts |
6b39ba77 | 53 | */ |
517e4981 | 54 | int arch_show_interrupts(struct seq_file *p, int prec) |
6b39ba77 TG |
55 | { |
56 | int j; | |
57 | ||
7a81d9a7 | 58 | seq_printf(p, "%*s: ", prec, "NMI"); |
6b39ba77 TG |
59 | for_each_online_cpu(j) |
60 | seq_printf(p, "%10u ", irq_stats(j)->__nmi_count); | |
61 | seq_printf(p, " Non-maskable interrupts\n"); | |
62 | #ifdef CONFIG_X86_LOCAL_APIC | |
7a81d9a7 | 63 | seq_printf(p, "%*s: ", prec, "LOC"); |
6b39ba77 TG |
64 | for_each_online_cpu(j) |
65 | seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs); | |
66 | seq_printf(p, " Local timer interrupts\n"); | |
474e56b8 JSR |
67 | |
68 | seq_printf(p, "%*s: ", prec, "SPU"); | |
69 | for_each_online_cpu(j) | |
70 | seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count); | |
71 | seq_printf(p, " Spurious interrupts\n"); | |
89ccf465 | 72 | seq_printf(p, "%*s: ", prec, "PMI"); |
241771ef IM |
73 | for_each_online_cpu(j) |
74 | seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs); | |
89ccf465 | 75 | seq_printf(p, " Performance monitoring interrupts\n"); |
e360adbe | 76 | seq_printf(p, "%*s: ", prec, "IWI"); |
b6276f35 | 77 | for_each_online_cpu(j) |
e360adbe PZ |
78 | seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs); |
79 | seq_printf(p, " IRQ work interrupts\n"); | |
346b46be FLVC |
80 | seq_printf(p, "%*s: ", prec, "RTR"); |
81 | for_each_online_cpu(j) | |
b49d7d87 | 82 | seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count); |
346b46be | 83 | seq_printf(p, " APIC ICR read retries\n"); |
6b39ba77 | 84 | #endif |
4a4de9c7 | 85 | if (x86_platform_ipi_callback) { |
59d13812 | 86 | seq_printf(p, "%*s: ", prec, "PLT"); |
acaabe79 | 87 | for_each_online_cpu(j) |
4a4de9c7 | 88 | seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis); |
acaabe79 DS |
89 | seq_printf(p, " Platform interrupts\n"); |
90 | } | |
6b39ba77 | 91 | #ifdef CONFIG_SMP |
7a81d9a7 | 92 | seq_printf(p, "%*s: ", prec, "RES"); |
6b39ba77 TG |
93 | for_each_online_cpu(j) |
94 | seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count); | |
95 | seq_printf(p, " Rescheduling interrupts\n"); | |
7a81d9a7 | 96 | seq_printf(p, "%*s: ", prec, "CAL"); |
6b39ba77 | 97 | for_each_online_cpu(j) |
fd0f5869 TS |
98 | seq_printf(p, "%10u ", irq_stats(j)->irq_call_count - |
99 | irq_stats(j)->irq_tlb_count); | |
6b39ba77 | 100 | seq_printf(p, " Function call interrupts\n"); |
7a81d9a7 | 101 | seq_printf(p, "%*s: ", prec, "TLB"); |
6b39ba77 TG |
102 | for_each_online_cpu(j) |
103 | seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count); | |
104 | seq_printf(p, " TLB shootdowns\n"); | |
105 | #endif | |
0444c9bd | 106 | #ifdef CONFIG_X86_THERMAL_VECTOR |
7a81d9a7 | 107 | seq_printf(p, "%*s: ", prec, "TRM"); |
6b39ba77 TG |
108 | for_each_online_cpu(j) |
109 | seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count); | |
110 | seq_printf(p, " Thermal event interrupts\n"); | |
0444c9bd JB |
111 | #endif |
112 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
7a81d9a7 | 113 | seq_printf(p, "%*s: ", prec, "THR"); |
6b39ba77 TG |
114 | for_each_online_cpu(j) |
115 | seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count); | |
116 | seq_printf(p, " Threshold APIC interrupts\n"); | |
01ca79f1 | 117 | #endif |
c1ebf835 | 118 | #ifdef CONFIG_X86_MCE |
01ca79f1 AK |
119 | seq_printf(p, "%*s: ", prec, "MCE"); |
120 | for_each_online_cpu(j) | |
121 | seq_printf(p, "%10u ", per_cpu(mce_exception_count, j)); | |
122 | seq_printf(p, " Machine check exceptions\n"); | |
ca84f696 AK |
123 | seq_printf(p, "%*s: ", prec, "MCP"); |
124 | for_each_online_cpu(j) | |
125 | seq_printf(p, "%10u ", per_cpu(mce_poll_count, j)); | |
126 | seq_printf(p, " Machine check polls\n"); | |
6b39ba77 | 127 | #endif |
7a81d9a7 | 128 | seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count)); |
6b39ba77 | 129 | #if defined(CONFIG_X86_IO_APIC) |
7a81d9a7 | 130 | seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count)); |
6b39ba77 TG |
131 | #endif |
132 | return 0; | |
133 | } | |
134 | ||
6b39ba77 TG |
135 | /* |
136 | * /proc/stat helpers | |
137 | */ | |
138 | u64 arch_irq_stat_cpu(unsigned int cpu) | |
139 | { | |
140 | u64 sum = irq_stats(cpu)->__nmi_count; | |
141 | ||
142 | #ifdef CONFIG_X86_LOCAL_APIC | |
143 | sum += irq_stats(cpu)->apic_timer_irqs; | |
474e56b8 | 144 | sum += irq_stats(cpu)->irq_spurious_count; |
241771ef | 145 | sum += irq_stats(cpu)->apic_perf_irqs; |
e360adbe | 146 | sum += irq_stats(cpu)->apic_irq_work_irqs; |
b49d7d87 | 147 | sum += irq_stats(cpu)->icr_read_retry_count; |
6b39ba77 | 148 | #endif |
4a4de9c7 DS |
149 | if (x86_platform_ipi_callback) |
150 | sum += irq_stats(cpu)->x86_platform_ipis; | |
6b39ba77 TG |
151 | #ifdef CONFIG_SMP |
152 | sum += irq_stats(cpu)->irq_resched_count; | |
153 | sum += irq_stats(cpu)->irq_call_count; | |
6b39ba77 | 154 | #endif |
0444c9bd | 155 | #ifdef CONFIG_X86_THERMAL_VECTOR |
6b39ba77 | 156 | sum += irq_stats(cpu)->irq_thermal_count; |
0444c9bd JB |
157 | #endif |
158 | #ifdef CONFIG_X86_MCE_THRESHOLD | |
6b39ba77 | 159 | sum += irq_stats(cpu)->irq_threshold_count; |
8051dbd2 | 160 | #endif |
c1ebf835 | 161 | #ifdef CONFIG_X86_MCE |
8051dbd2 HS |
162 | sum += per_cpu(mce_exception_count, cpu); |
163 | sum += per_cpu(mce_poll_count, cpu); | |
6b39ba77 TG |
164 | #endif |
165 | return sum; | |
166 | } | |
167 | ||
168 | u64 arch_irq_stat(void) | |
169 | { | |
170 | u64 sum = atomic_read(&irq_err_count); | |
6b39ba77 TG |
171 | return sum; |
172 | } | |
c3d80000 | 173 | |
7c1d7cdc JF |
174 | |
175 | /* | |
176 | * do_IRQ handles all normal device IRQ's (the special | |
177 | * SMP cross-CPU interrupts have their own specific | |
178 | * handlers). | |
179 | */ | |
1d9090e2 | 180 | __visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs) |
7c1d7cdc JF |
181 | { |
182 | struct pt_regs *old_regs = set_irq_regs(regs); | |
183 | ||
184 | /* high bit used in ret_from_ code */ | |
185 | unsigned vector = ~regs->orig_ax; | |
186 | unsigned irq; | |
187 | ||
7c1d7cdc | 188 | irq_enter(); |
98ad1cc1 | 189 | exit_idle(); |
7c1d7cdc | 190 | |
0a3aee0d | 191 | irq = __this_cpu_read(vector_irq[vector]); |
7c1d7cdc JF |
192 | |
193 | if (!handle_irq(irq, regs)) { | |
08306ce6 | 194 | ack_APIC_irq(); |
7c1d7cdc JF |
195 | |
196 | if (printk_ratelimit()) | |
edea7148 CG |
197 | pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n", |
198 | __func__, smp_processor_id(), vector, irq); | |
7c1d7cdc JF |
199 | } |
200 | ||
201 | irq_exit(); | |
202 | ||
203 | set_irq_regs(old_regs); | |
204 | return 1; | |
205 | } | |
206 | ||
acaabe79 | 207 | /* |
4a4de9c7 | 208 | * Handler for X86_PLATFORM_IPI_VECTOR. |
acaabe79 | 209 | */ |
eddc0e92 | 210 | void __smp_x86_platform_ipi(void) |
acaabe79 | 211 | { |
4a4de9c7 | 212 | inc_irq_stat(x86_platform_ipis); |
acaabe79 | 213 | |
4a4de9c7 DS |
214 | if (x86_platform_ipi_callback) |
215 | x86_platform_ipi_callback(); | |
eddc0e92 | 216 | } |
acaabe79 | 217 | |
1d9090e2 | 218 | __visible void smp_x86_platform_ipi(struct pt_regs *regs) |
eddc0e92 SA |
219 | { |
220 | struct pt_regs *old_regs = set_irq_regs(regs); | |
acaabe79 | 221 | |
eddc0e92 SA |
222 | entering_ack_irq(); |
223 | __smp_x86_platform_ipi(); | |
224 | exiting_irq(); | |
acaabe79 DS |
225 | set_irq_regs(old_regs); |
226 | } | |
227 | ||
d78f2664 YZ |
228 | #ifdef CONFIG_HAVE_KVM |
229 | /* | |
230 | * Handler for POSTED_INTERRUPT_VECTOR. | |
231 | */ | |
1d9090e2 | 232 | __visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs) |
d78f2664 YZ |
233 | { |
234 | struct pt_regs *old_regs = set_irq_regs(regs); | |
235 | ||
236 | ack_APIC_irq(); | |
237 | ||
238 | irq_enter(); | |
239 | ||
240 | exit_idle(); | |
241 | ||
242 | inc_irq_stat(kvm_posted_intr_ipis); | |
243 | ||
244 | irq_exit(); | |
245 | ||
246 | set_irq_regs(old_regs); | |
247 | } | |
248 | #endif | |
249 | ||
1d9090e2 | 250 | __visible void smp_trace_x86_platform_ipi(struct pt_regs *regs) |
cf910e83 SA |
251 | { |
252 | struct pt_regs *old_regs = set_irq_regs(regs); | |
253 | ||
254 | entering_ack_irq(); | |
255 | trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR); | |
256 | __smp_x86_platform_ipi(); | |
257 | trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR); | |
258 | exiting_irq(); | |
259 | set_irq_regs(old_regs); | |
260 | } | |
261 | ||
c3d80000 | 262 | EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq); |
7a7732bc SS |
263 | |
264 | #ifdef CONFIG_HOTPLUG_CPU | |
265 | /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */ | |
266 | void fixup_irqs(void) | |
267 | { | |
5231a686 | 268 | unsigned int irq, vector; |
7a7732bc SS |
269 | static int warned; |
270 | struct irq_desc *desc; | |
a3c08e5d | 271 | struct irq_data *data; |
51c43ac6 | 272 | struct irq_chip *chip; |
7a7732bc SS |
273 | |
274 | for_each_irq_desc(irq, desc) { | |
275 | int break_affinity = 0; | |
276 | int set_affinity = 1; | |
277 | const struct cpumask *affinity; | |
278 | ||
279 | if (!desc) | |
280 | continue; | |
281 | if (irq == 2) | |
282 | continue; | |
283 | ||
284 | /* interrupt's are disabled at this point */ | |
239007b8 | 285 | raw_spin_lock(&desc->lock); |
7a7732bc | 286 | |
51c43ac6 | 287 | data = irq_desc_get_irq_data(desc); |
a3c08e5d | 288 | affinity = data->affinity; |
b87ba87c | 289 | if (!irq_has_action(irq) || irqd_is_per_cpu(data) || |
58bff947 | 290 | cpumask_subset(affinity, cpu_online_mask)) { |
239007b8 | 291 | raw_spin_unlock(&desc->lock); |
7a7732bc SS |
292 | continue; |
293 | } | |
294 | ||
a5e74b84 SS |
295 | /* |
296 | * Complete the irq move. This cpu is going down and for | |
297 | * non intr-remapping case, we can't wait till this interrupt | |
298 | * arrives at this cpu before completing the irq move. | |
299 | */ | |
300 | irq_force_complete_move(irq); | |
301 | ||
7a7732bc SS |
302 | if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) { |
303 | break_affinity = 1; | |
2530cd4f | 304 | affinity = cpu_online_mask; |
7a7732bc SS |
305 | } |
306 | ||
51c43ac6 TG |
307 | chip = irq_data_get_irq_chip(data); |
308 | if (!irqd_can_move_in_process_context(data) && chip->irq_mask) | |
309 | chip->irq_mask(data); | |
7a7732bc | 310 | |
51c43ac6 TG |
311 | if (chip->irq_set_affinity) |
312 | chip->irq_set_affinity(data, affinity, true); | |
7a7732bc SS |
313 | else if (!(warned++)) |
314 | set_affinity = 0; | |
315 | ||
99dd5497 LC |
316 | /* |
317 | * We unmask if the irq was not marked masked by the | |
318 | * core code. That respects the lazy irq disable | |
319 | * behaviour. | |
320 | */ | |
983bbf1a | 321 | if (!irqd_can_move_in_process_context(data) && |
99dd5497 | 322 | !irqd_irq_masked(data) && chip->irq_unmask) |
51c43ac6 | 323 | chip->irq_unmask(data); |
7a7732bc | 324 | |
239007b8 | 325 | raw_spin_unlock(&desc->lock); |
7a7732bc SS |
326 | |
327 | if (break_affinity && set_affinity) | |
c767a54b | 328 | pr_notice("Broke affinity for irq %i\n", irq); |
7a7732bc | 329 | else if (!set_affinity) |
c767a54b | 330 | pr_notice("Cannot set affinity for irq %i\n", irq); |
7a7732bc SS |
331 | } |
332 | ||
5231a686 SS |
333 | /* |
334 | * We can remove mdelay() and then send spuriuous interrupts to | |
335 | * new cpu targets for all the irqs that were handled previously by | |
336 | * this cpu. While it works, I have seen spurious interrupt messages | |
337 | * (nothing wrong but still...). | |
338 | * | |
339 | * So for now, retain mdelay(1) and check the IRR and then send those | |
340 | * interrupts to new targets as this cpu is already offlined... | |
341 | */ | |
7a7732bc | 342 | mdelay(1); |
5231a686 SS |
343 | |
344 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
345 | unsigned int irr; | |
346 | ||
0a3aee0d | 347 | if (__this_cpu_read(vector_irq[vector]) < 0) |
5231a686 SS |
348 | continue; |
349 | ||
350 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
351 | if (irr & (1 << (vector % 32))) { | |
0a3aee0d | 352 | irq = __this_cpu_read(vector_irq[vector]); |
5231a686 | 353 | |
5117348d | 354 | desc = irq_to_desc(irq); |
51c43ac6 TG |
355 | data = irq_desc_get_irq_data(desc); |
356 | chip = irq_data_get_irq_chip(data); | |
239007b8 | 357 | raw_spin_lock(&desc->lock); |
51c43ac6 TG |
358 | if (chip->irq_retrigger) |
359 | chip->irq_retrigger(data); | |
239007b8 | 360 | raw_spin_unlock(&desc->lock); |
5231a686 | 361 | } |
1d44b30f | 362 | __this_cpu_write(vector_irq[vector], -1); |
5231a686 | 363 | } |
7a7732bc SS |
364 | } |
365 | #endif |